AD6649BCPZRL7

IF Diversity Receiver AD6649 FEATURES SNR = 73.0 dBFS in a 95 MHz bandwidth at 185 MHz AIN and 245.76 MSPS SFDR = 85 dBc at 185 MHz AIN and 250 MSPS Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 dBFS AIN and 250 MSPS Total power consumption: 1 W with fixed-frequency NCO, 95 MHz FIR filter 1.8 V supply voltages LVDS (ANSI-644 levels) outputs Integer 1-to-8 input clock divider (625 MHz maximum input) Integrated dual-channel ADC Sample rates of up to 250 MSPS IF sampling frequencies to 400 MHz Internal ADC voltage reference Flexible input range 1.4 V p-p to 2.1 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Integrated wideband digital processor 32-bit complex numerically controlled oscillator (NCO) FIR filter with 2 modes Real output from an fS/4 output NCO Amplitude detect bits for efficient AGC implementation Energy saving power-down modes Decimated, interleaved real LVDS data outputs AVDD FDA APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE General-purpose software radios Broadband data applications GENERAL DESCRIPTION The AD6649 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital downconverter (DDC). The AD6649 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. FUNCTIONAL BLOCK DIAGRAM DRVDD THRESHOLD DETECT I DDR LVDS OUTPUT BUFFER SELECTABLE FIR FILTER AD6649 OR+ OR– D13+/D13– D0+/D0– VIN+A ADC VIN–A Q DC CORRECTION REFERENCE 32-BIT TUNING NCO SELECTABLE FIR FILTER DIGITAL INTERLEAVING fS/4 NCO Q DIVIDE 1 TO 8 DUTY CYCLE STABILIZER DCO GENERATION MULTICHIP SYNC PROGRAMMING DATA CLK+ CLK– DCO+ DCO– SYNC DC CORRECTION VIN–B ADC VIN+B SELECTABLE FIR FILTER I THRESHOLD DETECT SELECTABLE FIR FILTER SPI 09635-001 AGND FDB PDWN OEB SDIO SCLK CSB Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD6649 TABLE OF CONTENTS Features .............................................................................................. 1  Applications....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Product Highlights ........................................................................... 3  Specifications..................................................................................... 4  ADC DC Specifications................................................................. 4  ADC AC Specifications ................................................................. 5  Digital Specifications ..................................................................... 6  Switching Specifications ................................................................ 8  Timing Specifications .................................................................. 9  Absolute Maximum Ratings.......................................................... 10  Thermal Characteristics ............................................................ 10  ESD Caution................................................................................ 10  Pin Configuration and Function Descriptions........................... 11  Typical Performance Characteristics ........................................... 13  Equivalent Circuits ......................................................................... 16  Theory of Operation ...................................................................... 17  ADC Architecture ...................................................................... 17  Analog Input Considerations.................................................... 17  Voltage Reference ....................................................................... 19  Clock Input Considerations ...................................................... 19  Power Dissipation and Standby Mode..................................... 20  Digital Outputs ........................................................................... 21  Digital Processing ........................................................................... 22  Numerically Controlled Oscillator (NCO) ............................. 22  NCO and FIR Filter Modes....................................................... 22  fS/4 Fixed-Frequency NCO ....................................................... 22  Numerically Controlled Oscillator (NCO) ................................. 23  Frequency Translation ............................................................... 23  NCO Synchronization ............................................................... 23  NCO Amplitude and Phase Dither.......................................... 23  FIR Filters ........................................................................................ 24  FIR Synchronization .................................................................. 24  Filter Performance...................................................................... 24  Output NCO ............................................................................... 25  ADC Overrange and Gain Control.............................................. 26  ADC Overrange (OR)................................................................ 26  Gain Switching............................................................................ 26  DC Correction ................................................................................ 27  Channel/Chip Synchronization.................................................... 28  Serial Port Interface (SPI).............................................................. 29  Configuration Using the SPI..................................................... 29  Hardware Interface..................................................................... 29  SPI Accessible Features.............................................................. 30  Memory Map .................................................................................. 31  Reading the Memory Map Register Table............................... 31  Memory Map Register Table..................................................... 32  Memory Map Register Description ......................................... 36  Applications Information .............................................................. 39  Design Guidelines ...................................................................... 39  Outline Dimensions ....................................................................... 40  Ordering Guide .......................................................................... 40  REVISION HISTORY 4/11—Revision 0: Initial Version Rev. 0 | Page 2 of 40 AD6649 ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO)), an optional sample rate converter, a fixed FIR filter, and an fS/4 fixed-frequency NCO. In addition to the receiver DDC, the AD6649 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. After digital processing, data is routed directly to the 14-bit output port. These outputs operate at ANSI or reduced swing LVDS signal levels. The AD6649 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. In diversity applications, the output data format is real due to the final NCO, which shifts the output center frequency to fS/4. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-pin SPI-compatible serial interface. The AD6649 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. 2. 3. 4. Integrated dual, 14-bit, 250 MSPS ADCs. Integrated wideband filter and 32-bit complex NCO. Fast overrange and threshold detect. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. 5. SYNC input allows synchronization of multiple devices. 6. 3-pin, 1.8 V SPI port for register programming and register readback. Rev. 0 | Page 3 of 40 AD6649 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1 1.75 V p-p full-scale input range, duty cycle stabilizer (DCS) enabled, NCO enabled, FIR filter enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span Input Capacitance 2 Input Resistance 3 Input Common-Mode Voltage POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD4 IDRVDD4 (Fixed-Frequency NCO, 95 MHz FIR Filter) IDRVDD 4 ( Tunable-Frequency NCO, 100 MHz FIR Filter) POWER CONSUMPTION Sine Wave Input (Fixed-Frequency NCO, 95 MHz FIR Filter) Sine Wave Input (Tunable-Frequency NCO, 100 MHz FIR Filter) Standby Power 5 Power-Down Power 1 Temperature Full Full Full Full Full Full Full Full 25°C Full Full Full Full Min 14 Typ Max Unit Bits −5.5 Guaranteed ±10 +2.5 ±13 ±2.5 ±15 ±50 1.32 1.75 2.5 20 0.9 mV %FSR mV %FSR ppm/°C ppm/°C LSB rms V p-p pF kΩ V Full Full Full Full Full Full Full Full Full 1.7 1.7 1.8 1.8 271 283 375 997 1163 104 10 1.9 1.9 275 300 V V mA mA mA mW mW mW mW 1035 A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters section for more details. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Measured with a 185 MHz, full-scale sine wave input on both channels and an NCO frequency of 62.5 MHz (fS/4). 5 Standby power is measured with a dc input and the CLK pin inactive (set to AVDD or AGND). Rev. 0 | Page 4 of 40 AD6649 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1 1.75 V p-p full-scale input range, DCS enabled, NCO enabled, FIR filter enabled, unless otherwise noted. Table 2. Parameter 2 SIGNAL-TO-NOISE RATIO (SNR) 3 fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz WORST SECOND OR THIRD HARMONIC fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz WORST OTHER HARMONIC OR SPUR fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz T WO-TONE SFDR fIN = 184.12 MHz, 187.12 MHz (−7 dBFS) CROSSTALK 4 ANALOG INPUT BANDWIDTH 1 Temperature 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C Full 25°C Min Typ 74.5 74.2 73.9 73.4 Max Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB MHz 70.9 72.9 73.4 73.0 72.3 71.7 68.7 71.0 −92 −88 −85 −85 −80 −89 92 88 85 85 80 84 −95 −94 −93 −93 −80 −84 88 95 1000 A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters section for more details. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 3 SNR specifications are for filtered 95 MHz bandwidth. 4 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel. Rev. 0 | Page 5 of 40 AD6649 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Current Low Level Input Current Input Capacitance Input Resistance SYNC INPUT Logic Compliance Internal Bias Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance LOGIC INPUT (CSB) 2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SCLK) 3 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT/OUTPUT (SDIO)2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (OEB, PDWN)3 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Temperature Min Typ Max Unit Full Full Full Full Full Full Full Full CMOS/LVDS/LVPECL 0.9 0.3 3.6 AGND AVDD 0.9 1.4 +10 +22 −22 −10 4 8 10 12 CMOS/LVDS 0.9 AGND AVDD 1.2 AVDD AGND 0.6 −5 +5 −5 +5 1 12 16 20 1.22 0 −5 −80 26 2 1.22 0 45 −5 26 2 1.22 0 45 −5 26 5 1.22 0 45 −5 2.1 0.6 70 +5 2.1 0.6 70 +5 2.1 0.6 70 +5 2.1 0.6 +5 −45 V V p-p V V μA μA pF kΩ Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full V V V V μA μA pF kΩ V V μA μA kΩ pF V V μA μA kΩ pF V V μA μA kΩ pF V V μA μA Rev. 0 | Page 6 of 40 AD6649 Parameter Input Resistance Input Capacitance DIGITAL OUTPUTS FDA and FDB High Level Output Voltage IOH = 50 μA IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 μA LVDS Data and OR Outputs Differential Output Voltage (VOD), ANSI Mode Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode 1 Temperature Full Full Min Typ 26 5 Max Unit kΩ pF Full Full Full Full Full Full Full Full 1.79 1.75 0.2 0.05 250 1.15 150 1.15 350 1.25 200 1.25 450 1.35 280 1.35 V V V V mV V mV V A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters section for more details. 2 Pull-up. 3 Pull-down. Rev. 0 | Page 7 of 40 AD6649 SWITCHING SPECIFICATIONS Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate 1 CLK Period—Divide-by-1 Mode (tCLK) CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-3 Through Divide-by-8 Modes, DCS Enabled DATA OUTPUT PARAMETERS (DATA, OR) Data Propagation Delay (tPD) DCO Propagation Delay (tDCO) DCO-to-Data Skew (tSKEW) Pipeline Delay—Fixed-Frequency NCO, 95 MHz FIR Filter (Latency) Pipeline Delay—Tunable-Frequency NCO, 100 MHz FIR Filter (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time (from Standby) Wake-Up Time (from Power-Down) OUT-OF-RANGE RECOVERY TIME 1 Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Min Typ Max 625 250 Unit MHz MSPS ns ns ns ns ns ns ns Cycles Cycles ns ps rms μs μs Cycles 40 4.0 1.8 1.9 0.8 2.0 2.0 2.2 2.1 0.1 4.8 5.5 0.7 23 43 1.0 0.1 10 250 3 1.3 Conversion rate is the clock rate after the divider. Rev. 0 | Page 8 of 40 AD6649 TIMING SPECIFICATIONS Table 5. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Conditions SYNC to the rising edge of CLK setup time SYNC to the rising edge of CLK hold time Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 2 2 40 2 2 10 10 10 10 Min Typ 0.3 0.4 Max Unit ns ns ns ns ns ns ns ns ns ns ns Timing Diagrams tCH CLK+ CLK– tCLK tDCO DCO+ DCO– tPD D0+ TO D13+ CHA0 D0– TO D13– CHB0 CHA1 CHB1 CHA2 CHB2 tSKEW 09635-002 CHA3 CHB3 CHA4 CHB4 CHA5 CHB5 CHA6 CHB6 Figure 2. Interleaved LVDS Mode Data Output Timing CLK+ tSSYNC SYNC tHSYNC 09635-016 Figure 3. SYNC Timing Inputs Rev. 0 | Page 9 of 40 AD6649 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND OEB to AGND PDWN to AGND D0−/D0+ through D13−/D13+ to AGND FDA/FDB to AGND OR+/OR− to AGND DCO+/DCO− to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −40°C to +85°C 150°C −65°C to +125°C THERMAL CHARACTERISTICS The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 7. Thermal Resistance Package Type 64-Lead LFCSP 9 mm × 9 mm (CP-64-4) 1 2 Airflow Velocity (m/sec) 0 1.0 2.0 θJA1, 2 26.8 21.6 20.2 θJC1, 3 1.14 θJB1, 4 10.4 Unit °C/W °C/W °C/W Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Typical θJA is specified for a 4-layer PCB with solid ground plane. As shown in Table 7, airflow increases heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θJA. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 10 of 40 AD6649 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR CLK+ CLK– SYNC FDA FDB DNC DNC D0– (LSB) D0+ (LSB) DRVDD D1– D1+ D2– D2+ D3– D3+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD DNC VCM DNC DNC AVDD AVDD VIN–A VIN+A AVDD AVDD AD6649 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK SDIO OR+ OR– D13+ (MSB) D13– (MSB) D12+ D21– DRVDD D11+ D11– D10+ D10– Figure 4. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View) Table 8. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. ADC Power Supplies 10, 19, 28, 37 49, 50, 53, 54, 59, 60, 63, 64 6, 7, 55, 56, 58 0 Mnemonic DRVDD AVDD DNC AGND, Exposed Paddle Type Supply Supply Ground Description Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). Do Not Connect. Do not connect to this pin. Analog Ground. The exposed thermal paddle on the bottom of the package provides the analog ground for the part. This exposed paddle must be connected to ground for proper operation. Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (−) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (−) for Channel B. Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. ADC Clock Input—True. ADC Clock Input—Complement. Channel A Fast Detect Indicator (CMOS Levels). Channel B Fast Detect Indicator (CMOS Levels). Digital Synchronization Pin. Slave mode only. Channel A/Channel B LVDS Output Data 0—True. Channel A/Channel B LVDS Output Data 0—Complement. Channel A/Channel B LVDS Output Data 1—True. Channel A/Channel B LVDS Output Data 1—Complement. Channel A/Channel B LVDS Output Data 2—True. Channel A/Channel B LVDS Output Data 2—Complement. Channel A/Channel B LVDS Output Data 3—True. ADC Analog 51 52 62 61 57 1 2 ADC Fast Detect Outputs 4 5 Digital Input 3 Digital Outputs 9 8 12 11 14 13 16 VIN+A VIN−A VIN+B VIN−B VCM CLK+ CLK− FDA FDB SYNC D0+ (LSB) D0− (LSB) D1+ D1− D2+ D2− D3+ Input Input Input Input Output Input Input Output Output Input Output Output Output Output Output Output Output Rev. 0 | Page 11 of 40 09635-004 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. D4– D4+ DRVDD D5– D5+ D6– D6+ DCO– DCO+ D7– D7+ DRVDD D8– D8+ D9– D9+ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AD6649 Pin No. 15 18 17 21 20 23 22 27 26 30 29 32 31 34 33 36 35 39 38 41 40 43 42 25 24 SPI Control 45 44 46 Output Enable and Power-Down 47 48 Mnemonic D3− D4+ D4− D5+ D5− D6+ D6− D7+ D7− D8+ D8− D9+ D9− D10+ D10− D11+ D11− D12+ D12− D13+ (MSB) D13− (MSB) OR+ OR− DCO+ DCO− SCLK SDIO CSB OEB PDWN Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/Output Input Input/Output Input/Output Description Channel A/Channel B LVDS Output Data 3—Complement. Channel A/Channel B LVDS Output Data 4—True. Channel A/Channel B LVDS Output Data 4—Complement. Channel A/Channel B LVDS Output Data 5—True. Channel A/Channel B LVDS Output Data 5—Complement. Channel A/Channel B LVDS Output Data 6—True. Channel A/Channel B LVDS Output Data 6—Complement. Channel A/Channel B LVDS Output Data 7—True. Channel A/Channel B LVDS Output Data 7—Complement. Channel A/Channel B LVDS Output Data 8—True. Channel A/Channel B LVDS Output Data 8—Complement. Channel A/Channel B LVDS Output Data 9—True. Channel A/Channel B LVDS Output Data 9—Complement. Channel A/Channel B LVDS Output Data 10—True. Channel A/Channel B LVDS Output Data 10—Complement. Channel A/Channel B LVDS Output Data 11—True. Channel A/Channel B LVDS Output Data 11—Complement. Channel A/Channel B LVDS Output Data 12—True. Channel A/Channel B LVDS Output Data 12—Complement. Channel A/Channel B LVDS Output Data 13—True. Channel A/Channel B LVDS Output Data 13—Complement. Channel A/Channel B LVDS Overrange—True. Channel A/Channel B LVDS Overrange—Complement. Channel A/Channel B LVDS Data Clock Output—True. Channel A/Channel B LVDS Data Clock Output—Complement. SPI Serial Clock. SPI Serial Data Input/Output. SPI Chip Select (Active Low). Output Enable Input (Active Low). Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby (see Table 14). Rev. 0 | Page 12 of 40 AD6649 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample, TA = 25°C, fixed-frequency NCO, 95 MHz BW FIR filter, unless otherwise noted. In the FFT plots that follow, the location of the second and third harmonics is noted when they fall in the pass band of the filter. A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters section for more details. 0 –20 –40 –60 –80 –100 –120 –140 SECOND HARMONIC THIRD HARMONIC fS = 250MSPS fIN = 30.1MHz @ –1.0dBFS SNR = 72dB (74.5dBFS) SFDR = 92dBc (IN-BAND) 0 –20 –40 –60 –80 –100 –120 –140 THIRD HARMONIC fS = 250MSPS fIN = 185.1MHz @ –1.0dBFS SNR = 70.5dB (73.0dBFS) SFDR = 84.5dBc (IN-BAND) AMPLITUDE (dBFS) 09635-112 AMPLITUDE (dBFS) 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) 90 100 110 120 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) 90 100 110 120 Figure 5. AD6649 Single-Tone FFT with fIN = 30.1 MHz 0 –20 –40 –60 –80 –100 –120 –140 THIRD HARMONIC SECOND HARMONIC Figure 8. AD6649 Single-Tone FFT with fIN = 185.1 MHz 0 –20 –40 –60 SECOND HARMONIC –80 –100 –120 –140 THIRD HARMONIC fS = 250MSPS fIN = 90.1MHz @ –1.0dBFS SNR = 71.6dB (74.1dBFS) SFDR = 87.5dBc (IN-BAND) AMPLITUDE (dBFS) fS = 250MSPS fIN = 220.1MHz @ –1.0dBFS SNR = 69.8dB (72.3dBFS) SFDR = 84dBc (IN-BAND) AMPLITUDE (dBFS) 09635-113 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) 90 100 110 120 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) 90 100 110 120 Figure 6. AD6649 Single-Tone FFT with fIN = 90.1 MHz 0 –20 –40 –60 SECOND HARMONIC –80 –100 –120 –140 THIRD HARMONIC Figure 9. AD6649 Single-Tone FFT with fIN = 220.1 MHz 0 fS = 250MSPS fIN = 140.1MHz @ –1.0dBFS SNR = 71.1dB (73.6dBFS) SFDR = 85dBc (IN-BAND) –20 –40 –60 –80 –100 –120 –140 fS = 250MSPS fIN = 305.1MHz @ –1.0dBFS SNR = 68.5dB (71.0dBFS) SFDR = 83.5dBc (IN-BAND) AMPLITUDE (dBFS) AMPLITUDE (dBFS) SECOND HARMONIC THIRD HARMONIC 09635-114 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) 90 100 110 120 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) 90 100 110 120 Figure 7. AD6649 Single-Tone FFT with fIN = 140.1 MHz Rev. 0 | Page 13 of 40 Figure 10. AD6649 Single-Tone FFT with fIN = 305.1 MHz 09635-117 09635-216 09635-215 AD6649 120 SFDR (dBFS) 100 SNR/SFDR (dBc AND dBFS) 0 –20 SNR (dBFS) SFDR/IMD3 (dBc AND dBFS) SFDR (dBc) 80 –40 IMD3 (dBc) –60 60 40 SFDR (dBc) 20 SNR (dBc) 0 –100 –10 –5 –95 –90 –85 –80 –75 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 0 09635-118 –80 SFDR (dBFS) –100 IMD3 (dBFS) –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –9.5 09635-121 09635-123 09635-122 –120 –90.0 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 11. AD6649 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 90.1 MHz Figure 14. AD6649 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS 100 95 0 –20 SFDR (dBc) AMPLITUDE (dBFS) SNR/SFDR (dBFS and dBc) 250MSPS 89.12MHz @ –7.0dBFS 92.12MHz @ –7.0dBFS SFDR = 88dBc (96.5dBFS) 90 85 80 75 70 65 50 SNR (dBFS) –40 –60 –80 –100 –120 –140 100 150 200 250 300 350 400 450 09635-119 0 10 20 30 40 50 60 70 80 90 100 110 120 INPUT FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. AD6649 Single-Tone SNR/SFDR vs. Input Frequency (fIN) Figure 15. AD6649 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS 0 –20 250MSPS 184.12MHz @ –7.0dBFS 187.12MHz @ –7.0dBFS SFDR = 85dBc (93.5dBFS) 0 –20 SFDR/IMD3 (dBc AND dBFS) SFDR (dBc) AMPLITUDE (dBFS) 09635-120 –40 –60 –80 –100 –120 –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –140 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –9.5 0 10 20 30 40 50 60 70 80 90 100 110 120 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 13. AD6649 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS Figure 16. AD6649 Two-Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS Rev. 0 | Page 14 of 40 AD6649 100 6000 1.32 LSB rms 16,378 TOTAL HITS 95 SNR/SFDR (dBFS/dBc) 5000 85 80 SFDR CHANNEL A (dBc) SFDR CHANNEL B (dBc) SNR CHANNEL A (dBFS) SNR CHANNEL B (dBFS) NUMBER OF HITS 90 4000 3000 2000 75 1000 70 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 SAMPLE RATE (MSPS) 09635-124 OUTPUT CODE Figure 17. AD6649 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 90.1 MHz Figure 18. AD6649 Grounded Input Histogram Rev. 0 | Page 15 of 40 09635-125 0 N+1 N+2 N+3 N+4 N+5 N–5 N–4 N–3 N–2 N–1 N AD6649 EQUIVALENT CIRCUITS AVDD SCLK OR PDWN 350 Ω 26kΩ VIN 09635-008 Figure 19. Equivalent Analog Input Circuit Figure 23. Equivalent SCLK or PDWN Input Circuit AVDD AVDD AVDD 0.9V CLK+ 15kΩ 15kΩ AVDD 26kΩ CSB CLK– 350 Ω Figure 20. Equivalent Clock Input Circuit 09635-009 Figure 24. Equivalent CSB Input Circuit DRVDD AVDD AVDD V+ DATAOUT– V– V– DATAOUT+ V+ 16kΩ 09635-010 SYNC 0.9V 0.9V Figure 21. Equivalent LVDS Output Circuit Figure 25. Equivalent SYNC Input Circuit DRVDD SDIO 350Ω 26kΩ Figure 22. Equivalent SDIO Circuit 09635-011 Rev. 0 | Page 16 of 40 09635-025 09635-014 09635-012 AD6649 THEORY OF OPERATION The AD6649 has two analog input channels, two filter channels, and two digital output channels. The intermediate frequency (IF) input signal passes through several stages before appearing at the output port(s) as a filtered and optionally decimated digital signal. The dual ADC design can be used for diversity reception of signals, where the ADCs operate identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample frequencies from dc to 300 MHz using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 400 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion. Synchronization capability is provided to allow synchronized timing between multiple devices. Programming and control of the AD6649 are accomplished using a 3-pin SPI-compatible serial interface. must be capable of charging the sampling capacitors and settling within 1/2 clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In intermediate frequency (IF) undersampling applications, the shunt capacitors should be reduced. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. Refer to the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, “Transformer-Coupled Front-End for Wideband A/D Converters,” for more information on this subject. BIAS S CS VIN+ CPAR1 CPAR2 H CS VIN– S 09635-034 ADC ARCHITECTURE The AD6649 architecture consists of a dual front-end sampleand-hold circuit, followed by a pipelined switched-capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage of each channel contains a differential sampling circuit that can be ac- or dc-coupled in differential or singleended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. During power-down, the output buffers go into a high impedance state. S CFB S S CPAR1 CPAR2 BIAS S CFB Figure 26. Switched-Capacitor Input For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched, and the inputs should be differentially balanced. Input Common Mode The analog inputs of the AD6649 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.5 × AVDD (or 0.9 V) is recommended for optimum performance. An on-board common-mode voltage reference is included in the design and is available from the VCM pin. Using the VCM output to set the input common mode is recommended. Optimum performance is achieved when the common-mode voltage of the analog input is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. This decoupling capacitor should be placed close to the pin to minimize the series resistance and inductance between the part and this capacitor. ANALOG INPUT CONSIDERATIONS The analog input to the AD6649 is a differential switchedcapacitor circuit that has been designed for optimum performance while processing a differential input signal. The clock signal alternatively switches the input between sample mode and hold mode (see the configuration shown in Figure 26). When the input is switched into sample mode, the signal source Rev. 0 | Page 17 of 40 AD6649 Differential Input Configurations Optimum performance is achieved while driving the AD6649 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, ADA4938-2, and ADA4930-2 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4930-2 is easily set with the VCM pin of the AD6649 (see Figure 27), and the driver can be configured in a Sallen-Key filter topology to provide band-limiting of the input signal. 15pF 200Ω VIN 76.8Ω 90Ω 33Ω 5pF 15Ω VIN– ADC 15Ω VIN+ VCM At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD6649. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 30). In this configuration, the input is ac-coupled and the CML is provided to each input through a 33 Ω resistor. These resistors compensate for losses in the input baluns to provide a 50 Ω impedance to the driver. In the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance. Based on these parameters the value of the input resistors and capacitors may need to be adjusted or some components may need to be removed. Table 9 displays recommended values to set the RC network for different input frequency ranges. However, these values are dependent on the input signal and bandwidth and should be used only as a starting guide. Note that the values given in Table 9 are for each R1, R2, C2, and R3 component shown in Figure 28 and Figure 30. Table 9. Example RC Network Frequency Range (MHz) 0 to 100 100 to 250 R1 Series (Ω) 33 15 C1 Differential (pF) 8.2 3.9 R2 Series (Ω) 0 0 C2 Shunt (pF) 15 8.2 R3 Shunt (Ω) 49.9 49.9 ADA4930-2 0.1µF 120Ω 200Ω 15pF 33Ω 33Ω 0.1µF Figure 27. Differential Input Configuration Using the ADA4930-2 For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 28. To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. C2 R3 R1 2V p-p 49.9Ω C1 R1 R2 33Ω 0.1µF R3 C2 0.1µF 09635-040 09635-039 R2 VIN+ ADC VIN– VCM An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use an amplifier with variable gain. The AD8375 or AD8376 digital variable gain amplifier (DVGAs) provides good performance for driving the AD6649. Figure 29 shows an example of the AD8376 driving the AD6649 through a band-pass antialiasing filter. 1000pF 180nH 220nH 1µH VPOS 165Ω 301Ω 5.1pF 3.9pF 165Ω AD8376 1µH 1nF 15pF VCM 1nF 68nH 2.5kΩ║2pF Figure 28. Differential Transformer-Coupled Configuration Figure 29. Differential Input Configuration Using the AD8376 C2 R3 0.1µF 2V p-p PA S S P 0.1µF 33Ω 0.1µF 33Ω 0.1µF C1 R1 R2 33Ω C2 09635-041 R1 R2 VIN+ ADC VIN– VCM R3 0.1µF Figure 30. Differential Double Balun Input Configuration Rev. 0 | Page 18 of 40 09635-115 The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz. Excessive signal power can also cause core saturation, which leads to distortion. AD6649 1000pF 180nH 220nH NOTES 1. ALL INDUCTORS ARE COILCRAFT® 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (COILCRAFT 0603LS). 2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz. AD6649 VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD6649. The full-scale input range can be adjusted by varying the reference voltage via SPI. The input span of the ADC tracks reference voltage changes linearly. CLOCK INPUT 390pF 25Ω 390pF CLK+ 390pF CLK– 25Ω SCHOTTKY DIODES: HSMS2822 09635-049 ADC CLOCK INPUT CONSIDERATIONS For optimum performance, the AD6649 sample clock inputs, CLK+ and CLK−, should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or via capacitors. These pins are biased internally (see Figure 31) and require no external bias. If the inputs are floated, the CLK− pin is pulled low to prevent spurious clocking. AVDD Figure 33. Balun-Coupled Differential Clock (Up to 625 MHz) If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins as shown in Figure 34. The AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/ADCLK925 clock drivers offer excellent jitter performance. 0.1µF 0.1µF CLK+ 0.9V CLK+ 4pF 4pF 09635-044 CLK– CLOCK INPUT AD95xx CLOCK INPUT 0.1µF 50kΩ 50kΩ PECL DRIVER 240Ω 100Ω 0.1µF ADC CLK– 240Ω Figure 31. Simplified Equivalent Clock Input Circuit Figure 34. Differential PECL Sample Clock (Up to 625 MHz) Clock Input Options The AD6649 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 32 and Figure 33 show two preferable methods for clocking the AD6649 (at clock rates of up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using an RF balun or RF transformer. The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD6649 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD6649 while preserving the fast rise and fall times of the signal, which are critical to low jitter performance. Mini-Circuits® ADT1-1WT, 1:1Z 390pF XFMR 100Ω 390pF CLK– 09635-048 A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as shown in Figure 35. The AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers offer excellent jitter performance. 0.1µF CLOCK INPUT 0.1µF CLK+ AD95xx 0.1µF CLOCK INPUT 50kΩ 50kΩ LVDS DRIVER 100Ω 0.1µF ADC CLK– 09635-051 Figure 35. Differential LVDS Sample Clock (Up to 625 MHz) Input Clock Divider The AD6649 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. The duty cycle stabilizer (DCS) is enabled by default on power-up. The AD6649 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. ADC CLK+ CLOCK INPUT 390pF 50Ω SCHOTTKY DIODES: HSMS2822 Figure 32. Transformer-Coupled Differential Clock (Up to 200 MHz) Rev. 0 | Page 19 of 40 09635-050 AD6649 Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD6649 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD6649. Jitter on the rising edge of the input clock is still of paramount concern and is not reduced by the duty cycle stabilizer. The duty cycle control loop does not function for clock rates less than 40 MHz nominally. The loop has a time constant associated with it that must be considered when the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time period that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. Refer to the AN-501 Application Note, Aperture Uncertainty and ADC System Performance, and the AN-756 Application Note, Sampled Systems and the Effects of Clock Phase Noise and Jitter, for more information about jitter performance as it relates to ADCs. POWER DISSIPATION AND STANDBY MODE As shown in Figure 37, the power dissipated by the AD6649 is proportional to its sample rate. The data in Figure 37 was taken using the same operating conditions as those used for the Typical Performance Characteristics. 1.0 0.9 0.8 0.4 TOTAL POWER 0.3 IAVDD IDRVDD 0.1 0.5 TOTAL POWER (W) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.2 Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fIN) due to jitter (tJ) can be calculated by SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 ( − SNRLF /10) ] In the equation, the rms aperture jitter represents the rootmean-square of all jitter sources, which include the clock input, the analog input signal, and the ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, as shown in Figure 36. 80 40 60 80 100 120 140 160 180 200 220 250 ENCODE FREQUENCY (MSPS) Figure 37. AD6649 Power and Current vs. Sample Rate 75 By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD6649 is placed in power-down mode. In this state, the ADC typically dissipates 10 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD6649 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. 70 SNR (dBFS) 0.05ps 0.20ps 0.50ps 1.00ps 1.50ps MEASURED 65 60 55 1 10 100 1000 INPUT FREQUENCY (MHz) Figure 36. SNR (95 MHz BW) vs. Input Frequency and Jitter The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD6649. Power supplies for clock drivers should be separated from the 09635-140 50 When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map Register Description section and the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, for additional details. Rev. 0 | Page 20 of 40 09635-037 0 0 SUPPLY CURRENT (A) AD6649 DIGITAL OUTPUTS The AD6649 output drivers can be configured for either ANSI LVDS or reduced drive LVDS using a 1.8 V DRVDD supply. As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. output enable bar bit (Bit 4) in Register 0x14. Because the output data is interleaved, if only one of the two channels is disabled, the data of the remaining channel is repeated in both the rising and falling output clock cycles. Timing The AD6649 provides latched data with a pipeline delay of 23 or 43 input sample clock cycles, depending on the mode of operation. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD6649. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD6649 is 40 MSPS. At clock rates below 40 MSPS, dynamic performance may degrade. Digital Output Enable Function (OEB) The AD6649 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the OEB pin or through the SPI interface. If the OEB pin is low, the output data drivers are enabled. If the OEB pin is high, the output data drivers are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. When using the SPI interface, the data and fast detect outputs of each channel can be independently three-stated by using the Data Clock Output (DCO) The AD6649 also provides data clock output (DCO) intended for capturing the data in an external register. Figure 2 shows a graphical timing diagram of the AD6649 output modes. Table 10. Output Data Format Input (V) VIN+ − VIN– VIN+ − VIN– VIN+ − VIN– VIN+ − VIN– VIN+ − VIN– VIN+ − VIN−, Input Span = 1.75 V p-p (V) +0.875 Offset Binary Output Mode 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1111 Twos Complement Mode (Default) 10 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1111 OR 1 0 0 0 1 Rev. 0 | Page 21 of 40 AD6649 DIGITAL PROCESSING The AD6649 includes a digital processing section that provides filtering. This digital processing section includes a numerically controlled oscillator (NCO), a selectable FIR filter (high performance or low latency), and a second coarse NCO (fS/4 fixed value) for output frequency translation (complex to real). These blocks can be configured in several modes to implement a signal processing function. Refer to Figure 1 for the functional block diagram of the AD6649. Two fixed-coefficient FIR filters provide filtering capability. A low latency FIR or a high performance FIR can be selected. It removes the negative frequency images to avoid aliasing negative frequencies for real outputs. Figure 38, Figure 39, and Figure 40 show the progression of a 95 MHz bandwidth signal through the filter stages when using the fixed-frequency NCO and 95 MHz FIR filter with a sample rate of 245.76 MSPS. The tunable-frequency NCO can be used instead and operates in a similar fashion. In these modes, the output is centered at 61.44 MHz, assuming a 245.76 MSPS sample rate. NUMERICALLY CONTROLLED OSCILLATOR (NCO) Frequency translation is accomplished with an NCO shared between the two channels. Amplitude and phase dither can be enabled on chip to improve the noise and spurious performance of the NCO. Because the filtering prevents usage of part of the Nyquist spectrum, a means is needed to translate the sampled input spectrum into the usable range of the decimation filter. To achieve this, a 32-bit, tuning, complex NCO is provided. This NCO/mixer allows the input spectrum to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing. When using the low latency FIR, the NCO must be tuned to fS/4 (0x40000000). This prevents unwanted aliases from falling back into the band of interest. fS/4 FIXED-FREQUENCY NCO A fixed-frequency fS/4 NCO is provided to translate the filtered, decimated signal from dc to fS/4 to allow a real output. The fS/4 NCO is required in all operation modes because complex output from the part is not supported. REAL ADC INPUT –108.94 –61.44 –13.94 0 13.94 61.44 108.94 122.88 Figure 38. Example AD6649 Real 95 MHz Bandwidth Input Signal Centered at 61.44 MHz (fADC = 245.76 MHz) COMPLEX ADC OUTPUT/NCO OUTPUT NCO AND FIR FILTER MODES The NCO and FIR blocks can be used in two modes depending on the bandwidth and latency requirement of the application. The two modes of operation of these blocks are summarized in Table 11. –122.88 –75.38 –47.5 0 47.5 75.38 122.88 09635-042 09635-043 Table 11. Signal Path Modes Output Bandwidth at 245.76 MSPS 95 MHz 99.5 MHz Figure 39. Example AD6649 95 MHz Bandwidth Input Signal Tuned to DC Using the NCO (NCO Frequency = 61.44 MHz) TUNED NCO OUTPUT 0 13.94 61.44 108.94 122.88 Figure 40. Example AD6649 95 MHz Bandwidth Output Signal Tuned to fS/4 (NCO Frequency = 61.44 MHz) Rev. 0 | Page 22 of 40 09635-247 Mode Fixed-Frequency NCO, 95 MHz FIR Filter Tunable-Frequency NCO, 100 MHz FIR Filter FIR Low latency (default) High performance AD6649 NUMERICALLY CONTROLLED OSCILLATOR (NCO) FREQUENCY TRANSLATION This processing stage comprises a digital tuner consisting of a 32-bit complex numerically controlled oscillator (NCO). The NCO is always enabled. This NCO block accepts a real input from the ADC stage and outputs a frequency translated complex (I and Q) output. The NCO frequency is programmed in Register 0x52 through Register 0x55. These four 8-bit registers make up a 32-bit unsigned frequency programming word. Frequencies between −CLK/2 and +CLK/2 are represented using the following frequency words: • • • 0x80000000 represents a frequency given by −CLK/2. 0x00000000 represents dc (frequency = 0 Hz). 0x7FFFFFFF represents CLK/2 − CLK/232. NCO SYNCHRONIZATION The AD6649 NCOs within a single part or across multiple parts can be synchronized using the external SYNC input. Bit 0 and Bit 1 of Register 0x58 allow the NCO to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the NCO to restart at the programmed phase offset value. NCO AMPLITUDE AND PHASE DITHER The NCO block contains amplitude and phase dither to improve the spurious performance. Amplitude dither improves performance by randomizing the amplitude quantization errors within the angular-to-Cartesian conversion of the NCO. This option reduces spurs at the expense of a slightly raised noise floor. With amplitude dither enabled, the NCO has an SNR of greater than 93 dB and an SFDR of greater than 115 dB. With amplitude dither disabled, the SNR is increased to greater than 96 dB at the cost of SFDR performance, which is reduced to 100 dB. The NCO amplitude and phase dither are recommended and can be enabled by setting Bit 1 and Bit 2 in Register 0x51. Use the following equation to calculate the NCO frequency: NCO_FREQ = 2 32 × Mod( f , f CLK ) f CLK where: NCO_FREQ is a 32-bit twos complement number representing the NCO frequency register. f is the desired carrier frequency in hertz. fCLK is the AD6649 ADC clock rate in hertz. Rev. 0 | Page 23 of 40 AD6649 FIR FILTERS The two FIR filters that can be used are either a 47-tap, high performance, fixed-coefficient FIR filter or a 21-tap, low latency, fixed-coefficient FIR filter. These filters are useful in providing alias protection at the device output. The high performance FIR is a simple sum-of-products FIR filter with 47 filter taps and 21-bit fixed coefficients. Note that this filter does not decimate. The normalized coefficients used in the implementation and the decimal equivalent value of the coefficients are listed in Table 12. Table 12. High Performance FIR Filter Coefficients Coefficient Number C0, C46 C1, C45 C2, C44 C3, C43 C4, C42 C5, C41 C6, C40 C7, C39 C8, C38 C9, C37 C10, C36 C11, C35 C12, C34 C13, C33 C14, C32 C15, C31 C16, C30 C17, C29 C18, C28 C19, C27 C20, C26 C21, C25 C22, C24 C23 Normalized Coefficient −0.0001335 −0.0009689 −0.0024185 −0.0019341 0.0023584 0.0051260 −0.0009680 −0.0086231 −0.0011368 0.0142097 0.0064697 −0.0207596 −0.0161047 0.0274601 0.0310631 −0.0348339 −0.0557785 0.0415993 0.0986786 −0.0463982 −0.1893501 0.0505829 0.6113434 0.9171314 Decimal Coefficient (21-Bit) −140 −1016 −2536 −2028 2473 5375 −1015 −9042 −1192 14900 6784 −21768 −16887 28794 32572 −36526 −58488 43620 103472 −48652 −198548 53040 641040 961682 part in this mode, set SPI Register 0x50 to 0xB0. When operating in this mode, the NCO must be placed at fS/4, and the low latency NCO select bit (Bit 0) in Register 0x5A must be set. It is important to note that a −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the low latency FIR filter. This output level reduction is a result of the −1.5 dB passband attenuation in the FIR filter in this mode and does not result in loss in the dynamic range of the converter. 0 –1 AMPLITUDE (dBc) –2 –3 09635-144 –4 0 30.72 61.44 92.16 122.88 FILTER RESPONSE (MHz) Figure 41. Low Latency FIR Filter Composite Response at 245.76 MSPS (Fixed-Frequency NCO, 95 MHz FIR Filter Mode) –1.000 –1.125 AMPLITUDE (dBc) –1.250 –1.375 09635-145 –1.500 FIR SYNCHRONIZATION The AD6649 filters within a single part or across multiple parts can be synchronized using the external SYNC input. The filters can be configured to be resynchronized on every SYNC signal or only on the first SYNC signal after the SPI control register is written. A valid SYNC causes the FIR filter to restart at the programmed decimation phase value. Bit 4 and Bit 5 of Register 0x58 allow the FIR to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. 0 30.72 61.44 92.16 122.88 FILTER RESPONSE (MHz) Figure 42. Low Latency FIR Filter Pass-Band Response at 245.76 MSPS (Fixed-Frequency NCO, 95 MHz FIR Filter Mode) FILTER PERFORMANCE When using the fixed-frequency NCO and a 95 MHz FIR filter, the output rate is equal to the sample clock rate. The composite response of this mode is shown in Figure 41. The detailed passband response for this mode is shown in Figure 42. To place the When using the tunable-frequency NCO and 100 MHz FIR filter, the output rate is equal to the sample clock rate. The response of the high performance FIR filter is shown in Figure 43. The detailed pass-band response for this mode is shown in Figure 44. To place the part into this mode, set SPI Register 0x50 to 0xA0. When using the high performance FIR filter, the output level is −1.3 dBFS for a corresponding input level of −1.0 dBFS at the analog inputs. This is a result of the −0.3 dB pass-band attenuation of the FIR filter in this mode and does not result in loss in the dynamic range of the converter. Rev. 0 | Page 24 of 40 AD6649 0 –10 –20 –30 OUTPUT NCO The output of the 32-bit fine-tuning NCO is complex and typically centered in frequency around dc. This complex output is carried through the stages of either the 95 MHz or 100 MHz FIR filter to provide proper antialiasing filtering. The final NCO provides a means to move this complex output signal away from dc so that a real output can be provided from the AD6649. The output NCO translates the output from dc to a frequency equal to the output frequency divided by 4 (fS/4). This provides the user with an output signal centered at fS/4 in frequency. 09635-146 AMPLITUDE (dBc) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 30.72 61.44 92.16 122.88 FILTER RESPONSE (MHz) Figure 43. High Performance FIR Filter Pass-Band Response at 245.76 MSPS (Tunable-Frequency NCO, 100 MHz FIR Filter) 0 –0.1 –0.2 The AD6649 output NCOs within a single part or across multiple parts can be synchronized using the external SYNC input. Bit 7 and Bit 6 of Register 0x58 allow the output NCO to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. AMPLITUDE (dBc) –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –1.0 0 15.36 30.72 46.08 09635-147 61.44 FILTER RESPONSE (MHz) Figure 44. High Performance FIR Filter Pass-Band Response at 245.76 MSPS (Tunable-Frequency NCO, 100 MHz FIR Filter) Rev. 0 | Page 25 of 40 AD6649 ADC OVERRANGE AND GAIN CONTROL In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides delayed information on the state of the analog input that is of limited value in preventing clipping. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip occurs. In addition, because input signals can have significant slew rates, latency of this function is of concern. Using the SPI port, the user can provide a threshold above which the FD output is active. Bit 0 of SPI Register 0x45 allows the user to select the threshold level. As long as the signal is below the selected threshold, the FD output remains low. In this mode, the magnitude of the data is considered in the calculation of the condition, but the sign of the data is not considered. The threshold detection responds identically to positive and negative signals outside the desired range (magnitude). an indicator that can be used to quickly insert an attenuator that prevents ADC overdrive. Fast Threshold Detection (FDA and FDB) The FD indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold register, located in Register 0x47 and Register 0x48. The selected threshold register is compared with the signal magnitude at the output of the ADC. The fast upper threshold detection has a latency of 4 clock cycles. The upper threshold magnitude is defined by the following equation: Upper Threshold Magnitude (dBFS) = 20 log(Threshold Magnitude/213) The FD indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. The lower threshold is programmed in the fast detect lower threshold register, located at Register 0x49 and Register 0x4A. The fast detect lower threshold register is a 15-bit register that is compared with the signal magnitude at the output of the ADC. This comparison is subject to the ADC pipeline latency but is accurate in terms of converter resolution. The lower threshold magnitude is defined by the following equation: Lower Threshold Magnitude (dBFS) = 20 log(Threshold Magnitude/213) The dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time register, located in Register 0x4B and Register 0x4C. The operation of the upper threshold and lower threshold registers, along with the dwell time, is shown in Figure 45. ADC OVERRANGE (OR) The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange condition is determined at the output of the ADC pipeline and, therefore, is subject to a latency of 7 ADC clock cycles. An overrange at the input is indicated by this bit 7 clock cycles after it occurs. GAIN SWITCHING The AD6649 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging amplifiers are employed. This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed. One such use is to detect when an ADC is about to reach full scale with a particular input condition. The result is to provide UPPER THRESHOLD DWELL TIME TIMER RESET BY RISE ABOVE LT LOWER THRESHOLD MIDSCALE FDA OR FDB TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LT Figure 45. Threshold Settings for FDA and FDB Signals Rev. 0 | Page 26 of 40 09635-148 DWELL TIME AD6649 DC CORRECTION Because the dc offset of the ADC may be significantly larger than the signal being measured, a dc correction circuit is included to null the dc offset before measuring the power. The dc correction circuit can also be switched into the main signal path, but this may not be appropriate if the ADC is digitizing a time-varying signal with significant dc content, such as GSM. DC Correction Readback The current dc correction value can be read back in Register 0x41 and Register 0x42 for each channel. The dc correction value is a 16-bit value that can span the entire input range of the ADC. DC Correction Freeze Setting Bit 6 of Register 0x40 freezes the DC correction at its current state and continues to use the last updated value as the dc correction value. Clearing this bit restarts dc correction and adds the currently calculated value to the data. DC Correction Bandwidth The dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.29 Hz and 2.387 kHz at 245.76 MSPS). The bandwidth is controlled by writing the 4-bit dc correction bandwidth select register, located at Register 0x40, Bits[5:2]. The following equation can be used to compute the bandwidth value for the dc correction circuit: DC _ Corr _ BW = 2 − k − 14 × f CLK 2× π DC Correction Enable Bits Setting Bit 1 of Register 0x40 enables dc correction for use in the output data signal path. where: k is the 4-bit value programmed in Bits[5:2] of Register 0x40 (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). fCLK is the AD6649 ADC sample rate in hertz. Rev. 0 | Page 27 of 40 AD6649 CHANNEL/CHIP SYNCHRONIZATION The AD6649 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The SYNC feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider, NCO, FIR filters, and the output fS/4 NCO can be synchronized using the SYNC input. Each of these blocks can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence by setting the appropriate bits in Register 0x58. The SYNC input is internally synchronized to the sample clock. However, to ensure that there is no timing uncertainty between multiple parts, the SYNC input signal should be synchronized to the input clock signal. The SYNC input should be driven using a single-ended CMOS type signal. If Bit 1 in Register 0x59 is used, the SYNC input can be set to either level or edge sensitive mode. If the SYNC input is set to edge sensitive mode, Bit 0 of Register 0x59 can be used to determine whether the rising or falling edge is used. Rev. 0 | Page 28 of 40 AD6649 SERIAL PORT INTERFACE (SPI) The AD6649 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first mode or in LSB first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 13). The SCLK (serial clock) pin is used to synchronize the read and write data presented from/to the ADC. The SDIO (serial data input/output) pin is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 13. Serial Port Interface Pins Pin SCLK SDIO Function Serial Clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial Data Input/Output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip Select Bar. An active low control that gates the read and write cycles. HARDWARE INTERFACE The pins described in Table 13 comprise the physical interface between the user programming device and the serial port of the AD6649. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6649 to prevent these signals from transitioning at the converter inputs during critical sampling periods. CSB The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 46 and Table 5. Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. Rev. 0 | Page 29 of 40 AD6649 SPI ACCESSIBLE FEATURES Table 14 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD6649 part-specific features are described in the Memory Map Register Description section. Table 14. Features Accessible Using the SPI Feature Name Mode Clock Offset Test I/O Output Mode Output Phase Output Delay VREF Digital Processing Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS via the SPI Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set up outputs Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the reference voltage Allows the user to enable the NCOs, FIR filters, and synchronization features tDS tS CSB tHIGH tDH tLOW tCLK tH SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 46. Serial Port Interface Timing Diagram Rev. 0 | Page 30 of 40 09635-079 AD6649 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x3A); and the digital feature control registers (Address 0x40 to Address 0x5A). The memory map register table (see Table 15) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x14, the output mode register, has a hexadecimal default value of 0x05. This means that Bit 0 = 1 and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0x25. The remaining registers, from Register 0x3A to Register 0x5A, are documented in the Memory Map Register Description section. Logic Levels An explanation of logic level terminology follows: • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Transfer Register Map Address 0x08 to Address 0x20, Address 0x3A, Address 0x40 to Address 0x42, Address 0x45 to 0x4C, and Address 0x50 to Address 0x5A are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and then the bit autoclears. Channel-Specific Registers Some channel setup functions, such as the signal monitor thresholds, can be programmed to a different value for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 15 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 15 affect the entire part and the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Open and Reserved Locations All address and bit locations that are not included in Table 15 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD6649 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 15. Rev. 0 | Page 31 of 40 AD6649 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 15 are not currently supported for this device. Table 15. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Chip Configuration Registers 0x00 0 SPI port configuration (global) 1 Bit 6 LSB first Bit 5 Soft reset Bit 4 1 Bit 3 1 Bit 2 Soft reset Bit 1 LSB first Bit 0 (LSB) 0 Default Value (Hex) 0x18 Default Notes/ Comments The nibbles are mirrored so that LSB first mode or MSB first mode registers correctly, regardless of shift mode. Read only. 0x01 Chip ID (global) Chip grade (global) Open Open 0x02 8-bit chip ID[7:0] (AD6649 = 0xA1) (default) Speed grade ID Open 00 = 250 MSPS 0xA1 Open Open Open Speed grade ID used to differentiate devices; read only. 0x03 Bits are set to determine which device on the chip receives the next write command; applies to local registers only. Synchronously transfers data from the master shift register to the slave. Determines various generic modes of chip operation. Channel Index and Transfer Registers 0x05 Channel index Open (global) Open Open Open Open Open ADC B (default) ADC A (default) 0xFF Transfer (global) Open Open Open Open Open Open Open Transfer 0x00 ADC Functions 0x08 Power modes (local) Open Open 0x09 Global clock (global) Clock divide (global) Open Open External powerdown pin function (local) 0 = powerdown 1 = standby Open Open Open Open Internal power-down mode (local) 00 = normal operation 01 = full power-down 10 = standby 11 = reserved 0x00 Open Open Open Open Duty cycle stabilizer (default) 0x01 0x0B Open Open Input clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles Rev. 0 | Page 32 of 40 Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 Clock divide values other than 000 automatically cause the duty cycle stabilizer to become active. AD6649 Addr (Hex) 0x0D Register Name Test mode (local) Bit 7 (MSB) User test mode control 0 = continuous/ repeat pattern 1 = single pattern, then 0s Bit 6 Open Bit 5 Reset PN long gen Bit 2 Bit 1 Output test mode 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN long sequence 0110 = PN short sequence 0111 = one/zero word toggle 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output Open Open Open BIST enable Reset BIST sequence Offset adjust in LSBs from +31 to −32 (twos complement format) Open Output format Output Output enable bar invert (local) 00 = offset binary (local) 1 = normal 01 = twos complement (default) (default) 0 = inverted 10 = gray code 11 = reserved (local) Open LVDS output drive current adjust 0000 = 3.72 mA output drive current 0001 = 3.5 mA output drive current (default) 0010 = 3.30 mA output drive current 0011 = 2.96 mA output drive current 0100 = 2.82 mA output drive current 0101 = 2.57 mA output drive current 0110 = 2.27 mA output drive current 0111 = 2.0 mA output drive current (reduced range) 1000 to 1111 = reserved Open Open Open Open Open Bit 4 Reset PN short gen Bit 3 Bit 0 (LSB) Default Value (Hex) 0x00 Default Notes/ Comments When this register is set, the test data is placed on the output pins in place of normal data. 0x0E 0x10 0x14 BIST enable (local) Offset adjust (local) Output mode Open Open Open Open Open Open Open 0x00 0x00 0x05 Configures the outputs and the format of the data. Open 0x15 Output adjust (global) Open Open Open 0x01 0x16 0x17 Clock phase control (global) DCO output delay (global) Invert DCO clock Enable DCO clock delay Open Open 0x00 Open Open 0x18 Input span select (global) Open Open Open 0x19 0x1A 0x1B 0x1C 0x1D 0x1E User Test Pattern 1 LSB (global) User Test Pattern 1 MSB (global) User Test Pattern 2 LSB (global) User Test Pattern 2 MSB (global) User Test Pattern 3 LSB (global) User Test Pattern 3 MSB (global) DCO clock delay [delay = (3100 ps × register value/31 +100)] 00000 = 100 ps 00001 = 200 ps 00010 = 300 ps … 11110 = 3100 ps 11111 = 3200 ps Full-scale input voltage selection 01111 = 2.087 V p-p … 00001 = 1.772 V p-p 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p … 10000 = 1.383 V p-p User Test Pattern 1[7:0] 0x00 0x00 Full-scale input adjustment in 0.022 V steps. 0x00 User Test Pattern 1[15:8] 0x00 User Test Pattern 2[7:0] 0x00 User Test Pattern 2[15:8] 0x00 User Test Pattern 3[7:0] 0x00 User Test Pattern 3[15:8] 0x00 Rev. 0 | Page 33 of 40 AD6649 Addr (Hex) 0x1F Register Name User Test Pattern 4 LSB (global) User Test Pattern 4 MSB (global) BIST signature LSB (local) BIST signature MSB (local) Sync control (global) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 User Test Pattern 4[7:0] Bit 1 Bit 0 (LSB) Default Value (Hex) 0x00 Default Notes/ Comments 0x20 User Test Pattern 4[15:8] 0x00 0x24 0x25 0x3A BIST signature[7:0] BIST signature[15:8] Open Open Open Open Open Clock divider next sync only Clock divider sync enable DC correction enable Master sync buffer enable 0x00 0x00 0x00 Read only. Read only. Digital Feature Control Registers 0x40 Open DC correction control (local) DC correction freeze 0x41 0x42 0x45 DC Correction Value 0 (local) DC Correction Value 1 (local) Fast detect control (local) Fast Detect Upper Threshold 0 (local) Fast Detect Upper Threshold 1 (local) Fast Detect Lower Threshold 0 (local) Fast Detect Lower Threshold 1 (local) Fast Detect Dwell Time 0 (local) Fast Detect Dwell Time 1 (local) Filter control (local) DC correction bandwidth select 0000 = 2387.32 Hz 0001 = 1193.66 Hz 0010 = 596.83 Hz 0011 = 298.42 Hz 0100 = 149.21 Hz 0101 = 74.60 Hz 0110 = 37.30 Hz 0111 = 18.65 Hz 1000 = 9.33 Hz 1001 = 4.66 Hz 1010 = 2.33 Hz 1011 = 1.17 Hz 1100 = 0.58 Hz 1101 = 0.29 Hz 1110 = reserved 1111 = reserved DC correction value[7:0] DC correction value[15:8] Open 0x00 Read only. Read only. Reserved Enable fast detect output 0x00 Open Open Open 0x47 Force FD Force FD output output enable value Fast detect upper threshold[7:0] Open 0x00 0x48 Open Open Open Fast detect upper threshold[12:8] 0x00 0x49 Fast detect lower threshold[7:0] 0x00 0x4A Open Open Open Fast detect lower threshold[12:8] 0x00 0x4B Fast detect dwell time[7:0] 0x00 0x4C Fast detect dwell time[15:8] 0x00 0x50 1 Reserved 1 FIR mode 0 = high performance 1 = low latency Output gain 0 = 0 dB 1 = −6 dB 9-bit output mode enable Datapath gain 00 = 0 dB 01 = −6 dB 10 = −12 dB 11 = −18 dB 0xB0 Rev. 0 | Page 34 of 40 AD6649 Addr (Hex) 0x51 Register Name NCO control (local) Bit 7 (MSB) Reserved Bit 6 NCO32 to fS/4 NCO sync enable Bit 5 Spectral reversal Bit 2 NCO32 amplitude dither enable NCO frequency value[31:24] Bit 4 1 Bit 3 Reserved Bit 1 NCO32 phase dither enable Bit 0 (LSB) 1 Default Value (Hex) 0x51 Default Notes/ Comments 0x52 0x53 0x54 0x55 0x56 0x57 0x58 NCO Frequency 3 (local) NCO Frequency 2 (local) NCO Frequency 1 (local) NCO Frequency 0 (local) NCO Phase Offset 1 (local) NCO Phase Offset 0 (local) Sync control (local) Sync pin control (local) 0x40 NCO frequency value[23:16] 0x00 NCO frequency value[15:8] 0x00 NCO frequency value[7:0] 0x00 NCO phase value[15:8] NCO phase value[7:0] fS/4 NCO next sync only Open fS/4 NCO sync enable Open FIR next sync only Open FIR Sync Enable Open Reserved Reserved NCO32 next sync only SYNC pin sensitivity 0 = sync on high level 1 = sync on edge Open NCO32 sync enable SYNC pin edge sensitivity 0 = sync on falling edge 1 = sync on rising edge Low latency NCO select 0x00 0x00 0x00 0x59 Open Open 0x00 0x5A NCO Control 2 (local) Open Open Open Open Open Open 0x01 1 The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00. Rev. 0 | Page 35 of 40 AD6649 MEMORY MAP REGISTER DESCRIPTION For more information on functions controlled in Register 0x00 to Register 0x25, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Bit 2—Force FD Output Value The value written to Bit 2 is forced on the FD output pin when Bit 3 is written high. Bit 1—Reserved Bit 0—Enable Fast Detect Output Setting this bit high enables the output of the upper threshold FD comparator to drive the FD output pin. Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only If the master sync buffer enable bit (Address 0x3A, Bit 0) and the clock divider sync enable bit (Address 0x3A, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse that it receives and to ignore the rest. The clock divider sync enable bit (Address 0x3A, Bit 1) resets after it syncs. Fast Detect Upper Threshold (Register 0x47 and Register 0x48) Register 0x48, Bits[7:5]—Reserved Register 0x48, Bits[4:0]—Fast Detect Upper Threshold[12:8] Register 0x47, Bits[7:0]—Fast Detect Upper Threshold[7:0] These registers provide an upper limit threshold. The 13-bit value is compared with the output magnitude from the ADC block. If the ADC magnitude exceeds this threshold value, the FD output pin is set if Bit 0 in Register 0x45 is set. Bit 1—Clock Divider Sync Enable Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high and Bit 0 is high. This is continuous sync mode. Bit 0—Master Sync Buffer Enable Bit 0 must be set high to enable any of the sync functions. If the sync capability is not used, this bit should remain low to conserve power. Fast Detect Lower Threshold (Register 0x49 and Register 0x4A) Register 0x4A, Bits[7:5]—Reserved Register 0x4A, Bits[4:0]—Fast Detect Lower Threshold[12:8] Register 0x49, Bits[7:0]—Fast Detect Lower Threshold[7:0] These registers provide a lower limit threshold. The 13-bit value is compared with the output magnitude from the ADC block. If the ADC magnitude is less than this threshold value for the number of cycles programmed in the dwell time register, the FD output bit is cleared. DC Correction Control (Register 0x40) Bit 7—Reserved Bit 6—DC Correction Freeze When Bit 6 is set high, the dc correction is no longer updated to the signal monitor block, which holds the last dc value calculated. Bits[5:2]—DC Correction Bandwidth Select Bits[5:2] set the averaging time of the signal monitor dc correction function. This 4-bit word sets the bandwidth of the correction block, according to the following equation: DC _ Corr _ BW = 2 − k − 14 × f CLK 2× π Fast Detect Dwell Time (Register 0x4B and Register 0x4C) Register 0x4C, Bits[7:0]—Fast Detect Dwell Time[15:8] Register 0x4B, Bits[7:0]—Fast Detect Dwell Time[7:0] These register values set the minimum time in ADC sample clock cycles (after clock divider) that a signal needs to stay below the lower threshold limit before the FD output bits are cleared. where: k is the 4-bit value programmed in Bits[5:2] of Register 0x40 (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). fCLK is the AD6649 ADC sample rate in hertz. Filter Control (Register 0x50) Bit 7—Reserved (Reads Back as 1) Bit 6—Reserved Bit 5—Reserved (Reads Back as 1) Bit 4—FIR Mode Setting this bit low enables the high performance FIR filter. Setting this bit high enables the low latency FIR. Bit 1—DC Correction Enable Setting this bit high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path. Bit 0—Reserved Fast Detect Control (Register 0x45) Bits[7:4]—Reserved Bit 3—Force FD Output Enable Setting this bit high forces the FD output pin to the value written to Bit 2 of this register (Register 0x45). This enables the user to force a known value on the FD pin for debugging. Bit 3—Output Gain Setting this bit high sets the output gain to −6 dB. A 0 value on this bit sets the gain at 0 dB. Rev. 0 | Page 36 of 40 AD6649 Bit 2—9-bit Output Mode Enable If this bit is set, the NCOs and filters are bypassed and the part outputs nine bits of data. These nine bits are presented on the nine MSBs of the output bus (that is, Bit D13 through Bit D5). NCO Phase Offset (Register 0x56 and Register 0x57) Register 0x56, Bits[7:0]—NCO Phase Value[15:8] Register 0x57, Bits[7:0]—NCO Phase Value[7:0] The 16-bit value programmed into the NCO phase value register is loaded into the NCO block each time the NCO is started or when an NCO SYNC signal is received. This process allows the NCO to be started with a known nonzero phase. Use the following equation to calculate the NCO phase offset value: NCO_PHASE = 216 × PHASE/360 where NCO_PHASE is a decimal number equal to the 16-bit binary number to be programmed at Register 0x56 and Register 0x57, and PHASE is the desired NCO phase in degrees. Bits[1:0]—Datapath Gain These bits set the datapath gain as follows: 00 = 0 dB gain 01 = −6 dB gain 10 = −12 dB gain 11 = −18 dB gain NCO Control (Register 0x51) Bit 7—Reserved Bit 6—NCO32 to fS/4 NCO Sync Enable This bit should be set high when NCO32 is set to fS/4 using the fixed-frequency NCO and the 95 MHz FIR filter. It should be disabled when using the tunable-frequency NCO and 100 MHz FIR filter. SYNC Control (Register 0x58) Bit 7—fS/4 NCO Next Sync Only If the master sync buffer enable bit (Register 0x3A, Bit 0) and the fS/4 NCO sync enable bit (Register 0x58, Bit 6) are high, Bit 7 allows the fS/4 NCO to synchronize following the first sync pulse that it receives and ignore the rest. If Bit 7 is set, Bit 6 of Register 0x58 resets after this sync occurs. Bit 5—Spectral Reversal This bit should be set high to reverse the output frequency spectrum. Bit 6—fS/4 NCO Sync Enable Bit 6 gates the sync pulse to the fS/4 NCO. When Bit 6 is set high, the sync signal causes the fS/4 NCO to synchronize. This sync is active only when the master sync buffer enable bit (Register 0x3A, Bit 0) is high. This is continuous sync mode. Bit 4—Reserved (Reads Back as 1) Bit 3—Reserved Bit 2—NCO32 Amplitude Dither Enable When Bit 2 is set, amplitude dither in the NCO is enabled. When Bit 2 is cleared, amplitude dither is disabled. Bit 5—FIR Next Sync Only If the master sync buffer enable bit (Register 0x3A, Bit 0) and the FIR sync enable bit (Register 0x58, Bit 4) are high, Bit 5 allows the FIR to synchronize following the first sync pulse that it receives and to ignore the rest. If Bit 5 is set, Bit 4 of Register 0x3A resets after this sync occurs. Bit 1—NCO32 Phase Dither Enable When Bit 2 is set, phase dither in the NCO is enabled. When Bit 2 is cleared, phase dither is disabled. Bit 0—Reserved (Reads Back as 1) NCO Frequency (Register 0x52 to Register 0x55) Register 0x52, Bits[7:0]—NCO Frequency Value[31:24] Register 0x53, Bits[7:0]—NCO Frequency Value[23:16] Register 0x54, Bits[7:0]—NCO Frequency Value[15:8] Register 0x55, Bits[7:0]—NCO Frequency Value[7:0] This 32-bit value is used to program the NCO tuning frequency. The frequency value to be programmed is given by the following equation: NCO_FREQ = 2 32 × Mod( f , f CLK ) f CLK Bit 4—FIR Sync Enable Bit 4 gates the sync pulse to the FIR filter. When Bit 4 is set high, the sync signal causes the half-band to resynchronize. This sync is active only when the master sync buffer enable bit (Register 0x3A, Bit 0) is high. This is continuous sync mode. Bits[3:2]—Reserved Bit 1—NCO32 Next Sync Only If the master sync buffer enable bit (Register 0x3A, Bit 0) and the NCO32 sync enable bit (Register 0x58, Bit 0) are high, Bit 1 allows the NCO32 to synchronize following the first sync pulse that it receives and to ignore the rest. Bit 0 of Register 0x58 resets after a sync occurs if Bit 1 is set. where: NCO_FREQ is a 32-bit twos complement number representing the NCO frequency register. f is the desired carrier frequency in hertz. fCLK is the AD6649 ADC clock rate in hertz. Bit 0—NCO32 Sync Enable Bit 0 gates the sync pulse to the 32-bit NCO. When this bit is set high, the sync signal causes the NCO to resynchronize, starting at the NCO phase offset value. This sync is active only when the master sync buffer enable bit (Register 0x3A, Bit 0) is high. This is continuous sync mode. Rev. 0 | Page 37 of 40 AD6649 SYNC Pin Control (Register 0x59) Bits[7:2]—Reserved Bit 1—SYNC Pin Sensitivity If Bit 1 is set to a 0, the SYNC input responds to a level. If this bit is set low, the SYNC input responds to the edge (rising or falling) set in Bit 0 of Address 0x59. NCO Control 2 (Register 0x5A) Bits[7:1]—Reserved Bit 0—Low Latency NCO Select If Bit 0 is set to a 1, the low latency NCO is selected. This bit should be selected for the fixed-frequency NCO, 95 MHz FIR filter mode of operation. When this bit is set, the NCO value must be set to either 0x40000000 or 0xC0000000. Bit 0—SYNC Pin Edge Sensitivity If Bit 1 is set high, setting Bit 0 to a 0 causes the SYNC input to respond to a falling edge. If this bit is set, the SYNC input respond to a rising edge. Rev. 0 | Page 38 of 40 AD6649 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system level design and layout of the AD6649, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. VCM The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 28. For optimal channel-to-channel isolation, a 33 Ω resistor should be included between the AD6649 VCM pin and the Channel A analog input network connection and between the AD6649 VCM pin and the Channel B analog input network connection. Power and Ground Recommendations When connecting power to the AD6649, it is recommended that two separate 1.8 V supplies be used: one supply should be used for analog (AVDD), and a separate supply should be used for the digital outputs (DRVDD). The designer can employ several different decoupling capacitors to cover both high and low frequencies. These capacitors should be located close to the point of entry at the PC board level and close to the pins of the part with minimal trace length. A single PCB ground plane should be sufficient when using the AD6649. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6649 to keep these signals from transitioning at the converter inputs during critical sampling periods. Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD6649 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. See the evaluation board for a PCB layout example. For detailed information about packaging and PCB layout of chip scale packages, refer to the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). Rev. 0 | Page 39 of 40 AD6649 OUTLINE DIMENSIONS 9.00 BSC SQ 0.60 MAX 0.60 MAX 48 49 64 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 8.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 6.35 6.20 SQ 6.05 0.50 0.40 0.30 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF 33 32 16 17 7.50 REF 0.25 MIN 1.00 0.85 0.80 SEATING PLANE FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 47. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD6649BCPZ AD6649BCPZRL7 AD6649EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board with AD6649 Package Option CP-64-4 CP-64-4 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09635-0-4/11(0) Rev. 0 | Page 40 of 40 091707-C