AD6650 Diversity IF-to-Baseband
GSM/EDGE Narrow-Band Receiver
AD6650
FEATURES
Smart antenna systems
Software radios
In-building wireless telephony
116 dB dynamic range
Digital VGA
I/Q demodulators
Active low-pass filters
Dual wideband ADC
Programmable decimation and channel filters
VCO and phase-locked loop circuitry
Serial data output ports
Intermediate frequencies of 70 MHz to 260 MHz
10 dB noise figure
+43 dBm input IP2 at 70 MHz IF
−9.5 dBm input IP3 at 70 MHz IF
3.3 V I/O and CMOS core
Microprocessor interface
JTAG boundary scan
PRODUCT DESCRIPTION
The AD6650 is a diversity intermediate frequency-to-baseband
(IF-to-baseband) receiver for GSM/EDGE. This narrow-band
receiver consists of an integrated DVGA, IF-to-baseband I/Q
demodulators, low-pass filtering, and a dual wideband ADC.
The chip can accommodate IF input from 70 MHz to 260 MHz.
The receiver architecture is designed such that only one external
surface acoustic wave (SAW) filter for main and one for diversity
are required in the entire receive signal path to meet GSM/EDGE
blocking requirements.
Digital decimation and filtering circuitry provided on-chip
remove unwanted signals and noise outside the channel of
interest. Programmable RAM coefficient filters allow antialiasing,
matched filtering, and static equalization functions to be combined
in a single cost-effective filter. The output of the channel filters
is provided to the user via serial output I/Q data streams.
APPLICATIONS
PHS or GSM/EDGE single carrier, diversity receivers
Microcell and picocell systems
Wireless local loop
FUNCTIONAL BLOCK DIAGRAM
TWEAK GAIN
DAC
AD6650 GSM/
EDGE IF RECEIVER
AGC
RELIN
CTRL
LP
FILTER
I
LPF
AIN
12-BIT
ADC
MUX
VGA
AIN
4TH
ORDER
CIC
COARSE
DCC
7TH
ORDER
IIR
PROG.
FIR
(RCF)
FINE
DCC
BIST
LPF
Q
SCLK
CPOUT
LF
SDFS
0
PLL/
VCO
/4
SERIAL
PORT
REF
90
VLDO
SDO0
SDO1
DR
Q
LPF
BIN
12-BIT
ADC
MUX
VGA
BIN
4TH
ORDER
CIC
COARSE
DCC
7TH
ORDER
IIR
PROG.
FIR
(RCF)
FINE
DCC
BIST
LPF
I
AGC
RELIN
CTRL
DAC
LP
FILTER
TWEAK GAIN
03683-001
D[7:0]
DTACK
A[2:0]
MODE [2:0]
DS
CS
R/W
RESET
DVDD
DGND
AVDD
MICRO
AGND
CLK
SYNC
TMS
TDI
TDO
TRST
TCLK
CLK
CLK
DIVIDER
JTAG
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved.
AD6650
TABLE OF CONTENTS
Features .............................................................................................. 1
LO Synthesis................................................................................ 22
Applications....................................................................................... 1
LDO.............................................................................................. 23
Product Description......................................................................... 1
AGC Loop/Relinearization ....................................................... 23
Functional Block Diagram .............................................................. 1
Serial Output Data Port............................................................. 24
Revision History ............................................................................... 2
Application Information................................................................ 26
Specifications..................................................................................... 3
Explanation of Test Levels ........................................................... 3
Required Settings and Start-up Sequence for DC Correction
....................................................................................................... 26
AC Specifications.......................................................................... 3
Clocking the AD6650 ................................................................ 26
Digital Specifications ................................................................... 4
Driving the Analog Inputs ........................................................ 27
Electrical Characteristics............................................................. 5
External Reference ..................................................................... 27
General Timing Characteristics ................................................. 5
Power Supplies ............................................................................ 27
Microprocessor Port Timing Characteristics ........................... 6
Digital Outputs ........................................................................... 28
Timing Diagrams.......................................................................... 7
Grounding ................................................................................... 28
Absolute Maximum Ratings.......................................................... 10
Layout Information.................................................................... 28
Thermal Characteristics ............................................................ 10
Chip Synchronization ................................................................ 29
ESD Caution................................................................................ 10
Microport Control.......................................................................... 30
Pin Configuration and Function Descriptions........................... 11
External Memory Map .............................................................. 30
Typical Performance Characteristics ........................................... 13
Access Control Register (ACR) ................................................ 30
Terminology .................................................................................... 14
Channel Address Register (CAR) ............................................ 30
Equivalent Circuits ......................................................................... 15
Special Function Registers ........................................................ 30
Theory of Operation ...................................................................... 16
Data Address Registers .............................................................. 31
Analog Front End ....................................................................... 16
Write Sequencing ....................................................................... 31
Digital Back End......................................................................... 16
Read Sequencing ........................................................................ 31
DC Correction ............................................................................ 16
Read/Write Chaining ................................................................. 31
Fourth-Order Cascaded Integrator Comb Filter (CIC4) ...... 17
Programming Modes ................................................................. 31
Infinite Impulse Response (IIR) Filter..................................... 18
JTAG Boundary Scan................................................................. 32
RAM Coefficient Filter .............................................................. 18
Register Map ................................................................................... 33
Composite Filter ......................................................................... 19
Register Details ........................................................................... 39
Fine DC Correction ................................................................... 20
Outline Dimensions ....................................................................... 44
Peak Detector DC Correction Ranging................................... 20
Ordering Guide .......................................................................... 44
User-Configurable Built-In Self-Test (BIST) .......................... 21
REVISION HISTORY
1/07—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Specifications ................................................................ 3
Changes to Figure 18...................................................................... 13
Changes to Power Supplies Section.............................................. 27
Changes to Ordering Guide .......................................................... 44
3/06—Revision 0: Initial Version
Rev. A | Page 2 of 44
AD6650
SPECIFICATIONS
EXPLANATION OF TEST LEVELS
I.
II.
III.
IV.
V.
VI.
VII.
100% production tested.
100% production tested at 25°C; sample tested at specified temperatures.
Sample tested only.
Parameter guaranteed by design and analysis.
Parameter is typical value only.
100% production tested at 25°C; sample tested at temperature extreme.
100% production tested at +85°C.
CLOAD = 40 pF on all outputs, unless otherwise specified. All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO
range of 3.0 V to 3.45 V.
AC SPECIFICATIONS
AVDD and DVDD = 3.3 V, CLK = 52 MSPS (driven differentially), 50% duty cycle, unless otherwise noted. All minimum ac
specifications are guaranteed from −25°C to +85°C. AC minimum specifications degrade slightly from −25°C to −40°C.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
GAIN CONTROL
Gain Step Size
Gain Step Accuracy
AGC Range
BASEBAND FILTERS
Bandwidth
Alias Rejection at 25.9 MHz
LO PHASE NOISE
At 10 kHz Offset
At 20 kHz Offset
At 50 kHz Offset
At 100 kHz Offset
At 200 kHz Offset
At 400 kHz Offset
At 600 kHz Offset
At 800 kHz Offset
At 1600 kHz Offset
At 3000 kHz Offset
GAIN ERROR
PSRR (AVDD with 20 mV RMS Ripple) 1
At 5 kHz
At 10 kHz
At 50 kHz
At 100 kHz
At 150 kHz
f = 70 MHz
Coarse DC Correction
Noise Figure 2
Input IP22
Input IP32
Image Rejection
Full-Scale Input Power
Input Impedance
Temp
Test Level
Min
Full
V
70
25°C
25°C
25°C
V
V
V
Full
25°C
IV
V
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
V
V
V
V
V
V
V
V
V
V
V
−79
−87
−103
−112
−119
−125
−130
−133
−138
−143
−0.7
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dB
25°C
25°C
25°C
25°C
25°C
V
V
V
V
V
−13.4
−17
−34
−39.8
−45.7
dBc
dBc
dBc
dBc
dBc
Full
Full
Full
V
V
IV
IV
IV
V
V
−70
10
43
−9.5
−49
4
189.6 − j33.6
dB
dB
dBm
dBm
dBc
dBm
Ω
Rev. A | Page 3 of 44
Typ
Max
Unit
260
MHz
0.094
±0.047
36
3.36
24
−15
3.5
77
dB
dB
dB
3.64
−33
MHz
dB
AD6650
Parameter
f = 150 MHz
Coarse DC Correction
Noise Figure2
Input IP22
Input IP32
Image Rejection
Full-Scale Input Power
Input Impedance
f = 200 MHz
Coarse DC Correction
Noise Figure2
Input IP22
Input IP32
Image Rejection
Full-Scale Input Power
Input Impedance
f = 250 MHz
Coarse DC Correction
Noise Figure2
Input IP22
Input IP32
Image Rejection
Full-Scale Input Power
Input Impedance
1
2
Temp
Test Level
Full
Full
Full
V
V
IV
IV
IV
V
V
Full
Full
Full
V
V
IV
IV
IV
V
V
Full
Full
Full
V
V
VII
VII
VII
V
V
Min
24
−15
24
−16
24
−16
Typ
Max
−70
10
37
−11.5
−46.5
4
169.3 − j59.2
−70
10
35
−12
−46.5
4
159.3 − j66.9
−70
10
33
−13
−45
4
137.1 − j72.7
−33
−33
−33
Unit
dB
dB
dBm
dBm
dBc
dBm
Ω
dB
dB
dBm
dBm
dBc
dBm
Ω
dB
dB
dBm
dBm
dBc
dBm
Ω
See Figure 40 and Figure 41 for additional PSRR specifications.
This measurement applies for maximum gain (36 dB).
DIGITAL SPECIFICATIONS
AVDD and DVDD = 3.3 V, CLK = 52 MSPS, unless otherwise noted.
Table 2.
Parameter
DVDD
AVDD
TAMBIENT1
1
Temp
Full
Full
Test Level
IV
IV
IV
Min
3.0
3.0
−25
Typ
3.3
3.3
+25
Max
3.45
3.45
+85
Unit
V
V
°C
The AD6650 is guaranteed fully functional from −40°C to +85°C. All ac minimum specifications are guaranteed from −25°C to +85°C, but degrade slightly from −25°C
to −40°C.
Rev. A | Page 4 of 44
AD6650
ELECTRICAL CHARACTERISTICS
Table 3.
Parameter (Conditions)
LOGIC INPUTS
Logic Compatibility
Digital Logic
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CLOCK INPUTS
Differential Input Voltage 1
Common-Mode Input Voltage
Differential Input Resistance
Differential Input Capacitance
LOGIC OUTPUTS
Logic Compatibility
Logic 1 Voltage (IOH = 0.25 mA)
Logic 0 Voltage (IOL = 0.25 mA)
IDD SUPPLY CURRENT
CLK = 52 MHz (GSM Example)
IDVDD
IAVDD
POWER DISSIPATION
CLK = 52 MHz (GSM/EDGE Example)
1
Temp
Test Level
Min
Typ
Full
IV
Full
Full
25°C
25°C
25°C
IV
IV
V
V
V
2.0
0
25°C
25°C
25°C
25°C
V
V
V
V
0.4
Full
Full
Full
IV
IV
2.4
Full
Full
VII
VII
155
360
Full
VII
1.7
Max
Unit
VDD
0.8
V
V
μA
μA
pF
3.6
V p-p
V
kΩ
pF
3.3 V CMOS
60
7
5
DVDD/2
7.5
5
3.3 V CMOS/TTL
VDD − 0.2
0.2
0.8
V
V
mA
mA
2.1
W
All ac specifications are tested by driving CLK and CLK differentially.
GENERAL TIMING CHARACTERISTICS
Table 4.
Parameter (Conditions)
CLK TIMING REQUIREMENTS
CLK Period 1
CLK Width Low
CLK Width High
RESET TIMING REQUIREMENTS
RESET Width Low
PIN_SYNC TIMING REQUIREMENTS
SYNC to ↑ CLK Setup Time
SYNC to ↑ CLK Hold Time
SERIAL PORT TIMING REQUIREMENTS: SWITCHING CHARACTERISTICS 2
↑ CLK to ↑ SCLK Delay (Divide-by-1)
↑ CLK to ↑ SCLK Delay (For Any Other Divisor)
↑ CLK to ↓ SCLK Delay (Divide-by-2 or Even Number)
↓ CLK to ↓ SCLK Delay (Divide-by-3 or Odd Number)
↑ SCLK to SDFS Delay
↑ SCLK to SDO0 Delay
↑ SCLK to SDO1 Delay
↑ SCLK to DR Delay
Symbol
Temp
Test Level
Min
tCLK
tCLKL
tCLKH
Full
Full
Full
I
IV
IV
9.6
tSSF
Full
IV
30
ns
tSS
tHS
Full
Full
IV
IV
−3
6
ns
ns
tDSCLK1
tDSCLKH
tDSCLKL
tDSCLKLL
tDSDFS
tDSDO0
tDSDO1
tDSDR
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
3.2
4.4
4.7
4
1
0.5
0.5
1
1
Typ
Max
Unit
19.2
ns
ns
ns
0.5 × tCLK
0.5 × tCLK
12.5
16
16
14
2.6
3.5
3.5
3.5
Minimum specification is based on a 104 MSPS clock rate (an internal divide-by-2 must be used with a 104 MSPS clock rate); maximum specification is based on a
52 MSPS clock rate. This device is optimized to operate at a clock rate of 52 MSPS or 104 MSPS.
2
The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both Channel 0 and Channel 1.
Rev. A | Page 5 of 44
ns
ns
ns
ns
ns
ns
ns
ns
AD6650
MICROPROCESSOR PORT TIMING CHARACTERISTICS
All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO range of 3.0 V to 3.45 V.
Table 5. Microprocessor Port, Mode INM (MODE = 0); Asynchronous Operation
Parameter
WRITE TIMING
WR (R/W) to RDY (DTACK) Hold Time 1
Address/Data to WR (R/W) Setup Time1
Address/Data to RDY (DTACK) Hold Time1
WR (R/W) to RDY (DTACK) Delay
WR (R/W) to RDY (DTACK) High Delay1
READ TIMING
Address to RD (DS) Setup Time1
Address to Data Hold Time1
Data Three-state Delay1
RDY (DTACK) to Data Delay1
RD (DS) to RDY (DTACK) Delay
RD (DS) to RDY (DTACK) High Delay1
1
2
Symbol
Temp
Test Level
Min
tHWR
tSAM
tHAM
tDRDY 2
tACC
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
0.0
0.0
0.0
9.0
4 × tCLK
tSAM
tHAM
tZD
tDD
tDRDY2
tACC
Full
Full
Full
Full
Full
Full
IV
IV
V
IV
IV
IV
0.0
0.0
Typ
Max
Unit
15.0
13 × tCLK
ns
ns
ns
ns
ns
0.0
15.0
13 × tCLK
ns
ns
ns
ns
ns
ns
12
9.0
4 × tCLK
Timing is guaranteed by design.
Specification pertains to control signals R/W, WR, DS, RD, and CS such that the minimum specification is valid after the last control signal has reached a valid logic level.
Table 6. Microprocessor Port, Mode MNM (MODE = 1)
Parameter
WRITE TIMING
DS (RD) to DTACK (RDY) Hold Time
R/W (WR) to DTACK (RDY) Hold Time
Address/Data to R/W (WR) Setup Time 1
Address/Data to R/W (WR) Hold Time1
DS (RD) to DTACK (RDY) Delay 2
R/W (WR) to DTACK (RDY) Low Delay1
READ TIMING
DS (RD) to DTACK (RDY) Hold Time
Address to DS (RD) Setup Time1
Address to Data Hold Time1
Data Three-State Delay
DTACK (RDY) to Data Delay1
DS (RD) to DTACK (RDY) Delay2
DS (RD) to DTACK (RDY) Low Delay1
1
2
Symbol
Temp
Test Level
Min
tHDS
tHRW
tSAM
tHAM
tDDTACK
tACC
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
V
IV
15.0
15.0
0.0
0.0
tHDS
tSAM
tHAM
tZD
tDD
tDDTACK
tACC
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
V
IV
V
IV
Timing is guaranteed by design.
DTACK is an open-drain device and must be pulled up with a 1 kΩ resistor.
Rev. A | Page 6 of 44
Typ
Max
Unit
13 × tCLK
ns
ns
ns
ns
ns
ns
16
4 × tCLK
15.0
0.0
0.0
13
0.0
16
4 × tCLK
13 × tCLK
ns
ns
ns
ns
ns
ns
ns
AD6650
TIMING DIAGRAMS
03683-002
RESET
tSSF
Figure 2. RESET Timing Requirements
CLK
03683-003
tDSCLKH
SCLK
Figure 3. SCLK Switching Characteristics (Divide-by-1)
CLK
tDSCLKL
03683-004
tDSCLKH
SCLK
Figure 4. SCLK Switching Characteristics (Divide-by-2 or Even Integer)
CLK
tDSCLKLL
03683-005
tDSCLKH
SCLK
Figure 5. SCLK Switching Characteristics (Divide-by-3 or Odd Integer)
SCLK
03683-006
tDSDR
DR
Figure 6. SCLK, DR Switching Characteristics
SCLK
03683-007
tDSDFS
SDFS
Figure 7. SCLK, SDFS Switching Characteristics
SCLK
03683-008
tDSD0/ tDSD1
SDO0/SDO1
Figure 8. SCLK, SDO0/SDO1 Switching Characteristics
Rev. A | Page 7 of 44
AD6650
CLK
tHS
03683-009
tSS
SYNC
Figure 9. SYNC Timing Inputs
RD (DS)
tHWR
WR (R/W)
CS
tHAM
tSAM
A[2:0]
VALID ADDRESS
tHAM
tSAM
VALID DATA
D[7:0]
tDRDY
RDY
(DTACK)
NOTES
1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED
FROM FALLING EDGE OF WR TO RISING EDGE OF RDY.
2. tACC REQUIRES A MAXIMUM OF NINE CLK PERIODS.
03683-010
tACC
Figure 10. INM Microport Write Timing Requirements
RD (DS)
WR (R/W)
CS
tSAM
VALID ADDRESS
A[2:0]
tZD
tDD
D[7:0]
tHAM
tZD
VALID DATA
tDRDY
RDY
(DTACK)
Figure 11. INM Microport Read Timing Requirements
Rev. A | Page 8 of 44
03683-011
tACC
NOTES
1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED
FROM FALLING EDGE OF RD TO RISING EDGE OF RDY.
2. tACC REQUIRES A MAXIMUM OF 13 CLK PERIODS.
AD6650
tHDS
DS (RD)
tHRW
R/W (WR)
CS
tSAM
A[2:0]
tHAM
VALID ADDRESS
tSAM
D[7:0]
tHAM
VALID DATA
tDDTACK
DTACK
(RDY)
tACC
03683-012
NOTES
1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED
FROM FALLING EDGE OF DS TO FALLING EDGE OF DTACK.
2. tACC REQUIRES A MAXIMUM OF NINE CLK PERIODS.
Figure 12. MNM Microport Write Timing Requirements
tHDS
DS (RD)
R/W (WR)
CS
t SAM
A[2:0]
VALID ADDRESS
tZD
tDD
tHAM
D[7:0]
tZD
VALID DATA
tDDTACK
tACC
NOTES
1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED
FROM FALLING EDGE OF DS TO THE FALLING EDGE OF DTACK.
2. tACC REQUIRES A MAXIMUM OF 13 CLK PERIODS.
Figure 13. MNM Microport Read Timing Requirements
Rev. A | Page 9 of 44
03683-013
DTACK
(RDY)
AD6650
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 7.
Parameter
Supply Voltage
Input Voltage
Output Voltage Swing
Load Capacitance
Junction Temperature Under Bias
Storage Temperature Range
Lead Temperature (5 sec)
Rating
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to VDDIO + 0.3 V
200 pF
125°C
−65°C to +150°C
280°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
121-lead chip scale package ball grid array:
θJA = 22.8°C/W, no airflow, measurements made in the
horizontal position on a 4-layer board.
θJA = 20.2°C/W, 200 LFPM airflow, measurements made in the
horizontal position on a 4-layer board.
θJA = 20.7°C/W, no airflow, soldered on an 8-layer board with
two layers dedicated as ground planes.
ESD CAUTION
Rev. A | Page 10 of 44
AD6650
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A1 CORNER
INDEX AREA
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
J
K
L
03683-042
AD6650
TOP VIEW
(Not to Scale)
Figure 14. Pin Configuration
Table 8. Pin Configuration
A
B
C
D
E
F
G
H
J
K
L
1
DGND
SDFS
SDO1
D7
D5
D3
D1
DS (RD)
R/W (WR)
A2
DGND
1
2
TDI
SCLK
SDO0
DR
D6
D4
D2
D0
DTACK (RDY)
A1
A0
2
3
TMS
TDO
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
CS
MODE2
3
4
TRST
TCLK
DVDD
DGND
DGND
DGND
DGND
DGND
DVDD
MODE1
MODE0
4
5
RESET
SYNC
DVDD
DGND
DGND
DGND
DGND
DGND
DVDD
CHIP_ID1
CHIP_ID0
5
6
DNC
DNC
DVDD
DGND
DGND
DGND
DGND
DGND
DVDD
DNC
DNC
6
7
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
7
8
CLK
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
REFGND
VREF
8
9
CLK
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
REFT
REFB
9
10
AGND
AGND
AGND
AGND
AGND
DNC
AGND
AGND
AGND
AGND
AGND
10
11
AGND
BIN
BIN
AGND
LF
VLDO
CPOUT
AGND
AIN
AIN
AGND
11
A
B
C
D
E
F
G
H
J
K
L
Table 9. Pin Function Descriptions
Mnemonic
POWER SUPPLY
DVDD
AVDD
DGND
AGND
DIGITAL INPUTS
RESET
SYNC
CHIP_ID[1:0]
SERIAL DATA PORT
SCLK
SDFS
SDO[1:0]
DR
MICROPORTCONTROL
D[7:0]
A[2:0]
CS
DS (RD)
Type
Description
No. of Pins
Power
Power
Ground
Ground
3.3 V Digital Supply.
3.3 V Analog Supply.
Digital Ground.
Analog Ground.
13
19
17
22
Input
Input
Input
Active Low Reset Pin.
Synchronizes Digital Filters.
Chip ID.
1
1
2
Bidirectional
Bidirectional
Output
Output
Serial Clock.
Serial Data Frame Sync.
Serial Data Outputs. Three-stated when inactive.
Output Data Ready Indicator.
1
1
2
1
Bidirectional
Input
Input
Input
Microport Data.
Microport Address Bits.
Chip Select.
Active Low Data Strobe (Active Low Read).
8
3
1
1
Rev. A | Page 11 of 44
AD6650
Mnemonic
DTACK (RDY)
Type
Output
R/W (WR)
MODE [2:0]
JTAG
TRST
TCLK
TMS
TDO
TDI
ANALOG INPUTS
AIN
AIN
BIN
BIN
PLL INPUTS
CPOUT
LF
VLDO
No. of Pins
1
Input
Input
Description
Active Low Data Acknowledge (Microport Status Bit). Open-drain output, requires
external pull-up resistor of 1 kΩ.
Read Write (Active Low Write).
Selects Control Port Mode.
Input
Input
Input
Output
Input
Test Reset Pin.
Test Clock Input.
Test Mode Select Input.
Test Data Output. Three-stated when JTAG is in reset.
Test Data input.
1
1
1
1
1
Input
Input
Input
Input
Main Analog Input.
Complement of AIN. Differential analog input.
Diversity Analog Input.
Complement of BIN. Differential analog input.
1
1
1
1
Output
Input
Output
Charge-Pump Output.
Loop Filter.
Compensation for Internal Low Dropout Regulator. Bypass to ground with a 220
nF chip capacitor.
Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39
for recommended connection.
Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39
for recommended connection.
Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39
for recommended connection.
ADC Ground Reference. See Figure 39 for recommended connection.
1
1
1
REFT
Output
REFB
Output
VREF
Output
REFGND
CLOCK INPUTS
CLK
CLK
DNC
Ground
Input
Input
Encode Input. Conversion initiated on rising edge.
Complement of Encode.
Do Not Connect.
Rev. A | Page 12 of 44
1
3
1
1
1
1
1
1
5
AD6650
TYPICAL PERFORMANCE CHARACTERISTICS
–44
44
–45
–25°C
42
+25°C
+25°C
–46
–25°C
38
IMAGE (dBc)
+85°C
36
–48
–49
34
–50
03683-016
32
30
70
+85°C
–47
90
110
130
150
170
190
IF FREQUENCY (MHz)
210
230
–51
70
250
03683-018
IIP2 (dBm)
40
90
110
130
150
170
190
IF FREQUENCY (MHz)
210
230
250
210
230
250
Figure 17. Image vs. Frequency
Figure 15. Input IP2 vs. Frequency
–6
0.2
–7
0
–8
–0.2
GAIN ERROR (dB)
–25°C
–10
+25°C
–11
–25°C
–0.6
+25°C
–0.8
–1.0
–13
+85°C
+85°C
–14
–15
70
–0.4
90
110
130
150
170
190
IF FREQUENCY (MHz)
210
230
250
Figure 16. Input IP3 vs. Frequency
–1.2
–1.4
70
03683-019
–12
03683-017
IIP3 (dBm)
–9
90
110
130
150
170
190
IF FREQUENCY (MHz)
Figure 18. Gain Error vs. Frequency
Rev. A | Page 13 of 44
AD6650
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Noise Figure (NF)
The degradation in SNR performance (in dB) of an IF input
signal after it passes through a component or system.
The AD6650 noise figure is determined by the equation
⎛
⎛ V 2 rms Z in
NF = ⎜10 log⎜
⎜ 0.001
⎜
⎝
⎝
⎞
⎞
⎟ − SNR FS ⎟ − 10 log⎛⎜ kTB ⎞⎟ (1)
⎟
⎟
⎝ 0.001 ⎠
⎠
⎠
where:
k is the Boltzmann constant = 1.38 × 10−23.
T is the temperature in kelvin.
B is the channel bandwidth in hertz (200 kHz typical).
V2rms is the full-scale input voltage.
Zin is the input impedance.
SNRFS is the computed signal-to-noise ratio referred to full scale
with a small input signal and the AD6650 in maximum gain.
Input Second-Order Intercept (IIP2)
A figure of merit used to determine a component’s or system’s
susceptibility to intermodulation distortion (IMD) from its
second-order nonlinearities. Two unmodulated carriers at a
specified frequency relationship (f1 and f2) are injected into a
nonlinear system exhibiting second-order nonlinearities
producing IMD components at f1 − f2 and f2 − f1. IIP2
graphically represents the extrapolated intersection of the
carrier’s input power with the second-order IMD component
when plotted in decibels.
Input Third-Order Intercept (IIP3)
A figure of merit used to determine a component’s or system’s
susceptibility to intermodulation distortion (IMD) from its
third-order nonlinearities. Two unmodulated carriers at a
specified frequency relationship (f1 and f2) are injected into a
nonlinear system exhibiting third-order nonlinearities
producing IMD components at (2 × f1) – f2 and (2 × f2) – f1.
IIP3 graphically represents the extrapolated intersection of the
carrier’s input power with the third-order IMD component
when plotted in decibels.
Image
The AD6650 incorporates a quadrature demodulator that mixes
the IF frequency to a baseband frequency. The phase and amplitude
imbalance of this quadrature demodulator is observed in a complex
FFT as an image of the fundamental frequency. The term image
arises from the mirror-like symmetry of signal and image
frequencies about the beating-oscillator frequency (in this
case, this is dc).
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically, and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. The peak-to-peak differential voltage is computed
by rotating the phases of the inputs 180° and taking the peak
measurement again. Then the difference is computed between
both peak measurements.
Full-Scale Input Power
Expressed in dBm. It is computed using the following equation:
PowerFull scale
⎛ V 2 Full scalerms
⎜
⎜ Z Input
= 10 log ⎜
⎜ 0.001
⎜
⎝
⎞
⎟
⎟
⎟
⎟
⎟
⎠
(2)
where ZInput is the input impedance.
Noise
The noise, including both thermal and quantization noise, for
any range within the ADC is computed as
⎛ FSdBm − SNRdBc − SignaldBFS ⎞
⎜⎜
⎟⎟
10
⎠
Vnoise = Z × 0.001 × 10 ⎝
(3)
where:
Z is the input impedance.
FSdBm is the full scale of the device for the frequency in question.
SNRdBc is the value for the particular input level.
SignaldBFS is the signal level within the ADC reported in decibels
below full scale.
Rev. A | Page 14 of 44
AD6650
EQUIVALENT CIRCUITS
1nH
AIN/BIN
25Ω
75Ω
CLAMP
1pF
1.3V
2pF
75Ω
25Ω
03683-014
1nH
AIN/BIN
Figure 19. Analog Input
AVDD
20kΩ
CLK
5kΩ
20kΩ
2.5kΩ
5pF
5kΩ
2.5kΩ
20kΩ
20kΩ
Figure 20. Clock Input
Rev. A | Page 15 of 44
03683-015
CLK
AD6650
THEORY OF OPERATION
The AD6650 is a mixed-signal front-end (MxFE®) component
intended for direct IF sampling radios requiring high dynamic
range. It is optimized for the demanding performance requirements of GSM and EDGE.
The AD6650 has five signal processing stages: a digital VGA,
I/Q demodulators, seventh-order low-pass filters, dual ADCs,
and digital filtering. Programming and control are accomplished via a microprocessor interface.
DVGA
A gain-ranging digital VGA is used to extend the dynamic
range of the ADC and minimize signal clipping at the ADC
input. The VGA has a maximum gain of 36 dB with a nominal
step size of 0.094 dB. The amplifier serves as the input stage to
the AD6650 and has a nominal input impedance of 200 Ω and a
4 dBm maximum input.
that the total AD6650 response is unchanged. The 19-bit output of
the AGC block is then decimated and filtered using the CIC4 filter,
the IIR filter, and the programmable RAM coefficient filter (RCF).
Either 16-bit or 24-bit data is output through the serial port.
With the 36 dB VGA gain, 12-bit ADC performance, and
approximately 21 dB of processing gain, the AD6650 is capable
of delivering approximately 116 dB of dynamic range or 19 bits
of performance. For this reason, it is recommended that the
24-bit serial output be used so that dynamic range is not lost.
A block diagram of the digital signal path is shown in Figure 21.
DITHER
GEN.
AGC
RELIN
CTRL
LP
FILTER
4TH
ORDER
CIC
COARSE
DCC
7TH
ORDER
IIR
PROG.
FIR
(RCF)
FINE
DCC
BIST
SPORT
03683-020
ANALOG FRONT END
Figure 21. Channel Digital Signal Path
I/Q Demodulators
DC CORRECTION
Frequency translation is accomplished with I/Q demodulators.
Real data entering this stage is separated into in-phase (I) and
quadrature (Q) components. This stage translates the input
signal from an intermediate frequency (IF) of 70 MHz to
260 MHz to a baseband frequency.
The dc offset in the analog path of the AD6650 comes from
three sources: the analog baseband filters, the ADCs, and the
LO leakage of the mixers. The dc offsets of the analog filters and
the ADCs dominate that of the LO leakage. The dc offsets on
the I and Q data for both Channel A and Channel B are
different because they use different analog paths. Each path is
corrected independently.
Rev. A | Page 16 of 44
FREQUENCY (MHz)
Figure 22. Uncorrected DC Offset
0.124
0.099
0.074
0.049
0.024
–0.001
03683-021
DC OFFSET
–0.026
The 12-bit ADC data goes through the coarse dc correction
block, which performs a one-time calibration of the dc offsets in
the I and Q paths. The output of this block drives the automatic
gain control (AGC) loop block, which adjusts the digitally
controlled VGA in the analog path. The AGC adjusts the amplitude
of the incoming signal of interest to a programmable level and
prevents the ADC from clipping. The gain of the VGA is subtracted
in the relinearization block so that externally the AD6650 appears
to have constant gain. For example, if the VGA must increase the
gain from 20 dB to 30 dB due to a decrease in the signal power,
the relinearization word changes from a −20 dB to a −30 dB gain so
(dB)
DIGITAL BACK END
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–0.051
The AD6650 has two ADCs. Each is implemented with an
AD9238 core preceded by dual track-and-holds that multiplex
in the I and Q signals at 26 MSPS each. The full-scale input
power into the ADC is 4 dBm.
–0.076
Dual ADCs
The typical uncorrected dc offset is between −32 dB and −35 dB
relative to full scale (dBFS) of the ADC. When the AGC range is
considered along with this offset, the dc is effectively slid down by
the gain setting so that it is approximately −68 dBFS to −71 dBFS
or smaller when the AD6650 is in maximum gain.
–0.101
In each I/Q signal path is a seventh-order low-pass active filter
with 3.5 MHz bandwidth and automatic resistance-capacitance
calibration to ±4%. This filter typically offers greater than 70 dB
of alias rejection at 25.9 MHz.
–0.126
Low-Pass Filters
AD6650
Coarse DC Correction
The coarse dc correction block is a simple integrate-and-dump
that integrates the data for 16,384 cycles at the ADC clock rate
(typically 26 MSPS) and then updates an estimate of the dc. This
estimate is then subtracted from the signal path. The signal is
clipped after the subtraction to avoid numerical wrap around
with large signals.
The −32 dBFS to −35 dBFS uncorrected offset is sufficient to
demodulate large signals, but it does not leave any margin if
30 dB of signal-to-dc is desired. It is essential to consider the dc
offset of the signal at the point where the AGC of the AD6650
begins to range. This is important because once the signal or a
blocker is in the range of the AGC loop, the dc signal that appears
at the output of the AD6650 is modulated by the change in gain
of the loop. If the gain decreases, the signal at the output remains
at the same power level due to the digital relinearization, but the
dc signal at the output is gained up by the relinearization process.
For this reason, the coarse dc correction is used to provide additional correction before relinearizing the data to provide additional
margin. This block gains another 5 dB to 8 dB (sometimes up to
25 dB) of dc rejection that provides additional margin.
The coarse dc correction is provided for two reasons:
•
•
To provide additional margin on the carrier-to-dc term for
large input signals.
To provide more range for the fine dc correction upper
threshold by decreasing the total input power to the block
for small input signals. (This is described in more detail in
the Fine DC Correction section.)
FOURTH-ORDER CASCADED INTEGRATOR COMB
FILTER (CIC4)
The CIC4 processing stage implements a fixed-coefficient
decimating filter. It reduces the sample rate of the signal and
allows subsequent filtering stages to be implemented more
efficiently. The input of the CIC4 is driven by the 19-bit relinearized
data at a maximum input rate of 26 MHz (52 MHz clock rate).
The CIC4 decimation ratio, MCIC4, can be programmed from
8 to 32 (all integer values). The CIC4 scale factor, SCIC4, is a
programmable unsigned integer between 0 and 8. It serves to
control the attenuation of the data into the CIC4 stage in 6 dB
increments such that the CIC4 does not overflow. Because this
scale factor is in 6 dB steps, the CIC4 filter has a gain between
0 dB and −6.02 dB when properly scaled. For the best dynamic
range, SCIC4 should be set to the smallest value possible (lowest
attenuation) without creating an overflow condition.
SCIC 4 = Ceil (4 × log 2 (MCIC 4 )) − 12
CIC _ Gain =
M CIC 4 4
2 SCIC 4
+ 12
(4)
(5)
The value of 12 that is subtracted in Equation 4 comes from the
amount of scaling needed to compensate for the minimum
decimation of 8. The frequency response of the CIC4 filter is
given by Equation 6 and Equation 7. The gain and pass-band
droop of the CIC4 can be calculated using these equations. If the
gain and/or droop of the CIC4 filter are not acceptable, they can
be compensated for in the programmable RCF filter stage.
⎛ 1
1 − Z − MCIC 4
CIC 4(Z ) = ⎜
×
⎜M
1 − Z −1
⎝ CIC 4
4
⎞
⎟ × CIC _ Gain
⎟
⎠
⎛
f × M CIC 4
⎛
⎜
sin⎜⎜ π ×
⎜ 1
f ADC
⎝
CIC 4( f ) = ⎜
×
⎛
f ⎞
⎜ M CIC 4
⎟
sin⎜⎜ π ×
⎜
f ADC ⎟⎠
⎝
⎝
(6)
4
⎞⎞
⎟⎟
⎟⎟
⎠
⎟ × CIC _ Gain
⎟
⎟
⎠
(7)
The output rate of this stage is given by Equation 8.
f SAMP 4 ≤
f ADC
M CIC 4
(8)
CIC4 Rejection
Table 10 shows the amount of bandwidth as a percentage of the
input sample rate (ADC sample rate) that can be protected with
various decimation rates and alias rejection specifications. The
maximum input rate into the CIC4 is 26 MHz. Table 10 shows
the half-bandwidth characteristics of the CIC4.
Table 10. SSB CIC4 Alias Rejection Table
dB
Rate
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
−50
2.494
2.224
2.006
1.827
1.676
1.549
1.439
1.344
1.261
1.187
1.122
1.063
1.010
0.962
0.919
0.879
0.842
0.809
0.778
0.749
0.722
0.697
0.674
0.653
0.632
−60
1.921
1.713
1.546
1.408
1.292
1.194
1.110
1.037
0.972
0.916
0.865
0.820
0.779
0.742
0.709
0.678
0.650
0.624
0.600
0.578
0.557
0.538
0.520
0.503
0.488
−70
1.473
1.315
1.187
1.081
0.992
0.917
0.852
0.796
0.747
0.703
0.665
0.630
0.599
0.570
0.544
0.521
0.499
0.479
0.461
0.444
0.428
0.413
0.400
0.387
0.375
−80
1.128
1.007
0.909
0.828
0.760
0.703
0.653
0.610
0.572
0.539
0.509
0.483
0.459
0.437
0.417
0.399
0.383
0.367
0.353
0.340
0.328
0.317
0.306
0.297
0.287
−90
0.860
0.768
0.693
0.632
0.580
0.536
0.499
0.466
0.437
0.411
0.389
0.369
0.350
0.334
0.319
0.305
0.292
0.281
0.270
0.260
0.251
0.242
0.234
0.226
0.219
−100
0.651
0.581
0.525
0.478
0.439
0.406
0.378
0.353
0.331
0.312
0.295
0.279
0.265
0.253
0.241
0.231
0.221
0.212
0.204
0.197
0.190
0.183
0.177
0.171
0.166
Table 10 enables the calculation of an upper bound on the
decimation ratio (MCIC4), given the desired filter characteristics
and input sample rate.
Rev. A | Page 17 of 44
AD6650
(n × z 7 + n2 × z 5 + n3 × z 3 + n1 × z + n1 × z 6 + n3 × z 4 + n2 × z 2 + n0 )
IIR( z ) = 0
(d7 × z 7 + d5 × z 5 + d3 × z 3 + d1 × z ) × 2
(9)
where:
n0 = 0.046227
n1 = 0.278961
n2 = 0.76021
n3 = 1.208472
d0 = 0
d1 = 0.12895
d2 = 0
d3 = 0.254698
d4 = 0
d5 = 1.026276
d6 = 0
d7 = 1
0.001
6 × 10–4
2 × 10–4
IIR PHASE RESPONSE
–2 × 10–4
–6 × 10–4
–0.001
–100
03683-023
The IIR filter of the AD6650 is a seventh-order low-pass filter
with an infinite impulse response. This filter cannot be bypassed
and always performs a decimation of 2. As can be seen from the
Z-transform, the IIR filter has a gain of −6.02 dB to accommodate
signal peaking within the structure. It is designed to be free of
limit cycles and is unconditionally stable. The IIR filter is
described by the Z-transform and coefficients shown in the
following equation:
the band of interest is essentially perfect. From −100 kHz to
+100 kHz, the phase distortion is ~0.056° rms. This phase
response is several orders of magnitude below the analog LO
and analog filter phase distortions.
PHASE RESPONSE (Degrees)
INFINITE IMPULSE RESPONSE (IIR) FILTER
–50
0
CHANNEL BW (kHz)
RAM COEFFICIENT FILTER
0
The final signal processing stage is a sum-of-products decimating
filter with programmable coefficients (see Figure 25). The I-RAM
and Q-RAM data memories store the most recent complex
samples from the IIR filter with 23-bit resolution. The number
of samples stored in these memories is equal to the coefficient
length (Ntaps), up to 48 taps. The coefficient memory, CMEM,
stores up to 48 coefficients with 20-bit resolution. On every
CLK (up to 52 MHz) cycle, one tap for I and one tap for Q are
calculated using the same coefficients. The RCF output consists
of 16-bit or 24-bit data.
I IN
–10
28
48 × 23
I-RAM
–20
COARSE
SCALE
48 × 20
C-RAM
–30
25
24
–50
Q IN
–60
–70
28
48 × 23
Q-RAM
RND
WORD
03683-024
IIR RESPONSE
–40
Figure 25. Block Diagram of the RCF
–80
RCF Decimation Register
–90
–110
1000
800
600
400
200
0
–200
–400
–600
–800
–1000
–120
1200
03683-022
–100
–1200
100
Figure 24. IIR Phase Response
Figure 23 shows the magnitude response of the IIR filter in a
typical GSM/EDGE case where the ADCs are sampling at
26 MHz and the CIC filter is decimating by 12 to generate a
2.16 MHz (8× symbol rate) input rate to the IIR.
(dB)
50
Each RCF channel can decimate the data rate by a factor of 1 to
8. The decimation register is a 3-bit register. The RCF decimation is
stored in Address 0x18 in the form of MRCF − 1. The input rate
to the RCF is fSAMPIIR.
RCF Decimation Phase Register
FREQUENCY (MHz)
Figure 23. IIR Frequency Response
Figure 24 shows the phase response of the IIR filter over the
range of ±100 kHz after a time delay during which ~13.449 input
samples of the filter have been removed. The input rate is the
same 2.16 MHz from the above GSM/EDGE configuration.
Examining the plot shows that the IIR filter is not exactly phase
linear. (Linear phase would be flat after the time delay has been
removed). It can be seen, however, that the phase response over
The AD6650 uses the value stored in this register to preload the
RCF counter. Therefore, instead of starting from 0, the counter
is loaded with this value, thus creating a time offset in the
output data. This data is stored in Address 0x19 as a 3-bit
number. Time delays can be achieved in even units of the RCF
input rate, which is typically ¼ of the symbol time for GSM.
Rev. A | Page 18 of 44
AD6650
RCF Filter Length
The maximum number of taps this filter can calculate, Ntaps, is
given by Equation 10. The value Ntaps − 1 is written to the
channel register within the AD6650 at Address 0x1B.
⎛ f CLK × M RCF
⎞
N taps ≤ min ⎜⎜
, 48 ⎟⎟
⎝ f SAMPIIR
⎠
(10)
f SAMPIIR
M RCF
(11)
where:
RCF Output Scale Factor and Control Register
fCLK is the external frequency oscillator.
MRCF is the RCF filter decimation rate.
fSAMPIIR is the input rate to the RCF.
The RCF coefficients are located in Address 0x40 to Address 0x6F,
and are interpreted as 20-bit twos complement numbers. When
writing the coefficient RAM, the lower addresses are multiplied
by relatively older data from the IIR, and the higher coefficient
addresses are multiplied by relatively newer data from the IIR.
The coefficients need not be symmetric, and the coefficient
length, Ntaps, can be even or odd. If the coefficients are
symmetric, both sides of the impulse response must be written
into the coefficient RAM.
The RCF stores the data from the IIR into a 46 × 48 RAM. A
RAM of 23 × 48 is assigned to I data, and a RAM of 23 × 48 is
assigned to Q data.
When the RCF is triggered to calculate a filter output, it starts
by multiplying the oldest value in the data RAM by the first
coefficient, which is pointed to by the RCF coefficient offset
register (Address 0x1A). This value is accumulated with the
products of newer data-words multiplied by the subsequent
locations in the coefficient RAM until the coefficient address
RCFOFF + Ntaps − 1 is reached.
Table 11. Three-Tap Filter
Impulse Response
h(0)
h(1)
h(2)
f SAMPR =
fSAMPIIR is the input rate to the RCF.
MRCF is the RCF filter decimation rate.
where:
Coefficient Address
0
1
2 = (Ntaps − 1)
The output rate of this filter (fSAMPR) is determined by the output
rate of the IIR stage and MRCF.
Data
N(0) oldest
N(1)
N(2) newest
The RCF coefficient offset register can be used for two purposes.
The main purpose is to allow multiple filters to be loaded into
memory and selected simply by changing the offset. The other
is to contribute to the symbol timing adjustment. If the desired
filter length is padded with 0s on the ends, the starting point
can be adjusted to form slight delays in the time the filter is
computed with reference to the high speed clock. This allows
for vernier adjustment of the symbol timing. Coarse adjustments
can be made with the RCF decimation phase.
Address 0x1C is used to configure the scale factor for the RCF
filter. This 2-bit register is used to scale the output data in 6 dB
increments. The possible output scales range from 0 dB to −18 dB.
The AD6650 RCF uses a recirculating multiply accumulator
(MAC) to compute the filter. This accumulator has three bits of
growth, allowing the output of the accumulator to be up to eight
times as large as the input signal. To achieve the best filter
performance, the coefficients should be as large as possible
without overflowing the accumulator. The gain of a filter is
merely the sum of the coefficients; therefore, for normal steady
state signals, the sum of the coefficients must be less than 8. If
the sum of the coefficients is 8 or slightly less, very rare
transient events can overflow the accumulator. To prevent this,
the sum of the absolute values of the coefficients should be less
than 8. It is then impossible for the RCF filter to overflow.
The RCF filter has a 4-position mux at the output of the
accumulator. This mux chooses which 24 bits are propagated to
the output and adjusts the rounding appropriately. This can be
viewed as a gain block that can be varied in 6 dB steps and is
controlled by the 2-bit RCF scale register.
The resulting gain of the RCF (RCFgain) is then represented by
the following equation:
RCFgain = ∑ Coef ×
1
2 3 − RCFScale
(12)
where RCFScale is the value in the RCF scale register.
COMPOSITE FILTER
The total gain of the digital filters can be calculated with
Equation 13 and must be less than or equal to 1 (0 dB).
Typically, the RCF coefficient gain is scaled to compensate for
the gain of the CIC and IIR, and the RCF scale factor is set to 3.
Gain =
M CIC 4 4
2 SCIC 4 + 12
×
1 ⎛
1
⎞
× ⎜ ∑ Coef × 3 − RCFScale ⎟
2 ⎝
2
⎠
(13)
where:
Gain is the gain of the digital filters.
MCIC4 is the CIC4 decimation ratio.
SCIC4 is the CIC4 scale factor.
RCFScale is the value in the RCF scale register.
The individual responses of the CIC4 and IIR filters, along with
the composite response of all the filters, are shown in Figure 26.
Rev. A | Page 19 of 44
AD6650
0
⎛ f
PG = 10 × log ⎜⎜ BW
⎝ f HPF
–10
–20
–30
AD6650 DIGITAL
COMPOSITE
RESPONSE
(dB)
–50
fBW is the channel filter bandwidth.
fHPF is the HPF bandwidth.
–60
IIR FILTER
RESPONSE
–70
–80
–90
03683-025
–100
–110
–120
–1.98
–1.46
–0.94
(14)
where:
CIC4 RESPONSE
–40
⎞
⎟
⎟
⎠
–0.43 0 17
0.61
FREQUENCY (MHz)
1.13
1.65
2.17
Figure 26. Composite Digital Response with 8× Rate
FINE DC CORRECTION
The fine dc correction block in the AD6650 lies between the
RCF and serial output port. While the coarse dc correction
block at the front of the channel is included to provide a onetime correction at startup or at rare intervals when commanded
by the user, the fine dc correction block is intended to run
continuously and track any changes in the dc offsets of the
analog front end. To achieve this efficiently under varying
signal conditions, this dc estimation process is adaptive.
Adaptive DC Correction Filter
In typical applications where dc offsets are to be corrected, a
high-pass filter (HPF) is used to remove the dc and some small
percentage of the input signal power. This approach is
straightforward and works well when the input signal has a
relatively constant power or when the bandwidth of the HPF is
extremely small (in the μHz or nHz range) and the dc content
does not vary. In general, the more the input signal power can
vary, the narrower the bandwidth of the high-pass filter must be
to avoid low frequency transients in the filter that are larger
than the smallest expected signals. A fundamental trade-off
exists because if the high-pass filter has a very low bandwidth, it
can only track very slow changes (over hours, days, or weeks) in
the dc offsets of the device. On the other hand, if it has a higher
bandwidth, it may not be able to estimate the dc properly in the
presence of a large baseband signal.
Given the assumption that the signal of interest is uniformly
distributed across frequency, the processing gain equation can
be used to provide a starting point for system optimization.
Enough processing gain must be guaranteed for the dc estimate
to be valid for a minimum signal case. This is typically 20 dB to
30 dB but depends on the baseband signal processing of a
particular system. For GSM/EDGE, which is distributed over
~100 kHz single sideband (SSB), this implies that the HPF
bandwidth must be between 100 Hz to 1 kHz SSB. For every
6 dB that the signal power increases, 6 dB more processing gain
is required; therefore, the HPF bandwidth needs to decrease by
a factor of 4 or more.
(14)
In the case of GSM, a simple HPF is not well suited to this
problem because the signal power can vary 50 dB or more from
time slot to time slot and has a total dynamic range of 91 dB or
more. A large time slot would excite the impulse response of the
HPF, possibly resulting in a peak occurring later when a small
time slot is present. To provide a more optimal dc correction,
the AD6650 adaptively adjusts the bandwidth of the HPF based
on the signal power. As the signal level decreases, the HPF
bandwidth increases. Conversely, as the signal level increases,
the HPF bandwidth decreases.
The AD6650 implements this high-pass filter in the form of an
accumulator that integrates a number of samples of the output
of the RCF and produces an estimate after the samples are
accumulated. The estimated dc is then removed from the signal
path by a simple subtraction. The subtraction is clamped to
avoid overflow problems. The HPF bandwidth is varied by
changing the integration time (equivalent to a SYNC 1 filter
decimation of the integrator). The integration time is varied based
on the output of a peak detector circuit according to the process
described in the Peak Detector DC Correction Ranging section.
PEAK DETECTOR DC CORRECTION RANGING
The peak detector of the AD6650 always looks at the maximum
signal power present in the I or Q data path. The I and Q paths
are treated totally independently in the dc correction circuitry
because the analog paths are not guaranteed to match. The first
sample that arrives is rectified and preloaded into the peak
detector. A control counter is set to the minimum period
control register setting. On every input sample, the peak
detector determines if the new sample is larger than the
currently held sample, and if so, the peak detector is updated.
The contents of the peak detector are then examined. If they are
below the lower threshold, the control counter counts down and
when it reaches 0, it updates the dc estimate, resets the dc
accumulator, and reloads the peak detector with the newest
input sample magnitude. If the peak detector value is above the
upper threshold of the dc correction, the estimate currently
being calculated is discarded. When the signal drops below the
upper threshold, the calculation of a new dc estimate begins.
The current estimate is held, so the last known dc content
continues to be removed.
The AI, AQ, BI, and BQ paths of the AD6650 are each treated
independently in the dc correction circuitry because the analog
paths are not guaranteed to match, and separate dc estimates
need to be kept for each. Separate peak detectors, dc estimate
accumulators, dc estimate subtractors, and control counters are
implemented for each of these paths.
Rev. A | Page 20 of 44
AD6650
Peak Detector
The peak detector always stores the input sample with the
largest magnitude. The absolute value of every input sample is
compared to what is currently in the peak detector’s holding
register. The only exception is when the control counter reaches
0; at this point, the dc offset estimate is updated and the peak
detector is set to the current input magnitude. The output of
each of the peak detectors is then encoded into a digital word
that represents the signal power in 6 dB steps relative to full
scale (FS).
⎛ Desired _ Signal _ Power − Lower _ Threshold
I _ P = 2 Min _ Period + Ceil ⎜
⎜
6.02
⎝
⎞
⎟×2
⎟
⎠
(16)
where Min_Period, Upper_Threshold, and Lower_Threshold are
register-programmable values.
To calculate the time required for the fine dc correction to
converge, use the following equation:
Fine _ DC _ Converge =
I _ P × TSYM
60
(17)
DC Accumulator
where:
The dc accumulator accumulates the 24-bit samples input from
the RCF filter until the control counter reaches 0. At this time,
the dc estimate in the holding register is updated, and the
accumulator is directly loaded with the new input sample to
begin work on the next estimate.
TSYM is the output symbol rate of the AD6650.
Fine_DC_Converge is expressed in minutes, and for a GSM
application with 1× oversampling, it is 3.69 × 10−6.
Control Counter
The AD6650 includes a BIST to assess digital functionality. This
feature verifies the integrity of the main digital signal paths of
the AD6650. Each BIST register is independent, meaning that
each channel can be tested independently at the same time.
This counter controls the update of the dc correction block
based on the peak detector value and the input control registers.
The following three conditions are possible:
•
•
•
If the digital word from the peak detector indicates that the
desired signal is below the lower threshold, the counter
merely cycles through at the minimum period.
If the digital word from the peak detector indicates that the
desired signal is above the upper threshold, the control
counter is held at the minimum period value and does
not count down; therefore, no update is made. When the
signal returns below the upper threshold, this counter
resumes counting.
If the digital word from the peak detector indicates that the
desired signal is between the lower threshold and the upper
threshold, the fine dc correction circuit is in its normal mode
of operation. In this mode, the control counter starts with the
minimum period but is reloaded with 4× minimum period
every time the peak detector output words increment by
6 dB. This errs on the side of caution and ensures that the
dc correction integrates long enough to obtain a valid
estimate. If smaller integrations are preferred, the minimum
period can be decreased or the lower threshold can be raised.
The integration period is given by Equation 15 and Equation 16.
The factor of 2 in the exponent shows that as peak signal power
increases, the integration time is increased by a factor of 4. This
decreases the bandwidth of the estimation filter, thus providing
the additional processing gain in the dc estimation term.
USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the selected AD6650 digital
signal path. With this test mode, it is possible to use the internal
pseudorandom generator to produce known test data. A
signature register follows the fine dc correction block. This
register can be read back and compared to a known good
signature. If the known good signature matches the register
value, the channel is fully operational.
If an error is detected, each internal block can be bypassed and
another test can be run to debug the fault. The I and Q paths are
tested independently. Use the following steps to perform this test:
1.
2.
3.
4.
5.
6.
7.
When the desired signal power equals the upper threshold,
⎛ Upper _ Threshold − Lower _ Threshold
I _ P = 2 Min _ Period + Ceil ⎜
⎜
6.02
⎝
⎞
⎟×2
⎟
⎠
(15)
When the desired signal power is less than the upper threshold,
Rev. A | Page 21 of 44
Reset the AD6650.
Program the desired AD6650 channel parameters for the
desired application (these parameters include decimation
rates, scalars, and RCF coefficients). Also, ensure that the
start holdoff counter is set to a nonzero value.
Set Register 0xA, Bit 1, to 1 (PN_EN).
Set Register 0x21, Bit 8, to 0 (fine DCC to BIST).
Start the A and/or B channels with a microprocessor write
(Soft_SYNC) or a pulse on the SYNC pin (Pin_SYNC).
Wait at least 300 μs.
Read the four BIST registers and compare the values to a
known good device. This ensures that the AD6650 is
programmed correctly and that each channel is
functioning correctly.
AD6650
LO SYNTHESIS
The AD6650 has a fully integrated quadrature LO synthesizer
consisting of a voltage-controlled oscillator (VCO) and a phaselocked loop (PLL). Together these blocks generate quadrature
IF LO signals for the demodulators.
Figure 27 shows a block diagram of the LO synthesis block.
Besides the usual PLL and VCO, there is also a programmable
half-rate divider (Div-X and a fixed divide-by-4 quadrature
divider that produces the final I and Q LO signals).
therefore, the PFD reference frequency should be set for
optimal placement of spurs.
Prescaler and Feedback Dividers
The dual modulus prescaler, P/(P + 1), and the A and B
feedback dividers (5 bits and 13 bits, respectively) combine to
provide a wide ranging N-divider in the PLL feedback loop. The
feedback division is N = 8B + A. Including the final quadrature
divider (divide-by-4), the LO frequency is given by
f LO =
VCO
Immediately following the VCO is a programmable half-rate
divider that has settings of divide-by-2, -2.5, -3, -3.5, and so on,
up to divide-by-8. This function divides the VCO frequency
down to four times the LO frequency and effectively extends
the tuning range of the VCO. The VCO and the half-rate
divider can be thought of as a single lower frequency VCO with
a frequency range of 280 MHz to 1040 MHz.
Autocalibration selects both the VCO operating band and the
oscillator amplitude to ensure peak operating performance
across the entire frequency range. The half-rate divide setting is
also selected as part of the VCO calibration. Autocalibration is
performed whenever PLL Register 3 (the test mode latch) is
written; therefore, all other PLL registers should be set first, and
Register 3 should be written to last. This is true whenever
programming any portion of the LO synthesizer because the
VCO may need to recalibrate itself, depending on the changes
made to the registers.
(18)
4R
where:
fLO is the local oscillator frequency.
fCLK is the external frequency oscillator.
B is the 13-bit divider (3 to 8191).
A is the 5-bit swallow divider (0 to 31).
R is the input reference divider (1 to 16,384).
The fCLK/4R term combines the effects of the reference divider
and the final quadrature divider, and determines the frequency
spacing for the LO synthesizer. For a typical GSM application,
fCLK = 52 MHz and R = 65 result in a 200 kHz PFD update rate,
which sets the frequency spacing at a desired 200 kHz. However,
this also places LO spurs at offsets of 200 kHz multiples, which
might degrade the interferer/blocker performance.
CAL
fCLK
R-DIV
14-BIT
fREF
EXTERNAL
LOOP FILTER
UP
CHARGE
PUMP
PFD
DIV-X
DN
VCO
DIV-4
IOUT
QOUT
N-COUNTER
B-DIV
13-BIT
A-DIV
5-BIT
PRESCALER
P/(P + 1)
03683-027
The VCO generates an on-chip RF signal in the range of
2.2 GHz to 2.8 GHz. The only external component required is a
bypass capacitor for the low dropout (LDO) voltage regulator
used to power the VCO tank core. The VCO uses overlapping
bands to achieve the wide tuning range while maintaining
excellent phase noise and spurious performance. During band
selection, which takes 5 PFD cycles, the VCO VTUNE is disconnected
from the output of the loop filter and connected to an internal
reference voltage. After band select, normal PLL action
resumes. The nominal value of KV is 65 MHz/V, where KV is the
VCO sensitivity.
f CLK × (B × 8 + A )
Figure 27. PLL Circuit
PFD and Charge Pump
The integer-N type PLL consists of a programmable reference
divider (R-divider), a prescaler and feedback divider (N-divider),
a phase-frequency detector (PFD), and a charge pump. The
output of the charge pump drives an external loop filter, which
in turn drives the input of the VCO.
The phase-frequency detector (PFD) takes inputs from the
R-divider and N-divider and produces an output proportional
to the phase and frequency difference between them. The PFD
includes a programmable delay element that controls the width
of the antibacklash pulse. This pulse ensures that there is no
dead zone in the PFD transfer function and minimizes
reference spurs.
R-Divider
Loop Filter
The 14-bit R-divider divides down the input clock frequency to
produce the reference frequency for the phase-frequency
detector. Although division ratios from 1 to 16,383 are allowed,
the maximum update rate for the PFD is 1 MHz. The selected
update rate of the PFD and the subsequent charge pump
determines the spurious performance of the LO synthesizer;
The final element in the LO synthesizer is the external loop
filter, which is generally a first-order or second-order RC lowpass filter. A filter like the one shown in Figure 28 is recommended
to provide a good balance of stability, spurs, and phase noise.
This partiular filter is optimized for an update rate of 1 MHz.
PLL
Rev. A | Page 22 of 44
AD6650
Slow Loop
LF
867Ω
CP
The slow loop is the main loop and is associated with a loop
gain parameter. This parameter controls the rate of change of
the gain and should always be less than 1. To determine the
loop gain, Equation 19 should be used.
200Ω
AD6650
56000pF
3900pF
1.0µF
⎛K
⎞
AGCLoopGai n = ⎜ Mantissa ⎟ × 2 − K Exponent
⎝ 256 ⎠
03683-028
VLDO
Figure 28. Loop Filter Circuit
VP
HI
D1
Q1
(19)
where:
CHARGE
PUMP
KMantissa is the loop gain mantissa. Values can range from 0 to 63.
KExponent is the loop gain exponent. Values can range from 0 to 7.
UP
U1
R-DIVIDER
PROGRAMMABLE
DELAY
CLR1
CP
U3
ADP2
ADP1
HI
CLR2
D2
Q2
DOWN
U2
N-DIVIDER
CPGND
R-DIVIDER
03683-029
N-DIVIDER
CP OUTPUT
Figure 29. PFD Simplified Schematic and Timing (Locked)
As the loop gain value increases, the speed of the response of
the AGC loop increases; as the loop gain value decreases, so
does the speed of the response of the AGC loop. The slow loop
attempts to maintain the signal entering the ADC at a given
level, referred to as the requested level. This level is specified in
dBFS and can be between 0 dBFS and −24 dBFS (in 0.094 dB
steps) of the converter resolution. The default value is −6.02 dBFS.
The slow loop has a peak detection function, the period of
which can be set by the user. This period should be set to ¼ of
the symbol period, or greater, to prevent the AGC loop from
gaining off the envelope of the EDGE signal. This detection
period works because the peak detector’s operation is based on
dB (max(|I|, |Q|)); therefore, all of the I/Q samples are reflected
back into one quadrant of the I/Q plane. At a 26 MHz sampling
frequency, one symbol period is 96 clock cycles. Therefore, to
obtain a peak detector period that is ¼ of the symbol period,
the peak detector period should be set to a minimum of 24
samples. The following equation can also be used:
SPB Peak Samples ≥ 1 4 × ( f SAMP / f SYM )
LDO
The AD6650 includes an on-chip 2.6 V low dropout (LDO)
voltage regulator that supplies the VCO and other sections of
the PLL. A 0.22 μF bypass capacitor is required on the VLDO
output to ensure stability. This LDO employs the same technology
used in the anyCAP® line of regulators from Analog Devices, Inc.,
making it insensitive to the type of capacitor used. Driving an
external load from the VLDO output is not supported.
where:
fSYM = 270.833 kHz (GSM symbol rate).
fSAMP = 26 MHz.
Fast Attack (FA) Loop
AGC LOOP/RELINEARIZATION
UPPER
THRESHOLD
POWER DETECTOR
DECIMATION FILTERS
RE-LINEARIZTION FORMATTER
The AGC consists of three gain control loops: a slow loop, a fast
attack (FA) loop, and a fast decay (FD) loop.
ADC
FAST LOOP DETECTORS
SLOW LOOP, SIGNAL LEVEL
SIGNAL PLUS BLOCKER LEVEL
03683-030
ADC
AGC
STATE
MACHINE
(20)
The FA loop utilizes an analog threshold detector that prevents
overdrive of the analog signal path. In a situation that could
potentially overdrive the ADC, the FA loop takes over from the
slow loop and decreases the gain to the VGA in the front end.
The step size used for the FA loop is programmable between
0 dB and 1.504 dB in 0.094 dB steps. The FA loop also has a
counter that is programmable between 1 and 16. When
initialized to count + 1, the FA loop decreases the gain for
count + 1 clock cycles when the threshold is crossed.
Fast Decay (FD) Loop
The FD loop is a fast loop that increases the gain when the
signal falls below a threshold during a deep channel fade or on
the ramp down. The fast loop accomplishes this task by
comparing the peak signal-plus-blocker level at the ADC output
(which includes the signal and any blockers that pass through
the SAW filter) with a programmable level (SPB_level) that
determines when this loop is activated. The SBP_level default
Figure 30. AGC Loop Block Diagram
Rev. A | Page 23 of 44
AD6650
value is −40 dBFS. When the wideband signal is below the SPB
level, the FD loop is activated. This loop overrides the slow loop
and has a programmable step size (default 0.094 dB) and a
programmable peak detect period (defaults four samples at
1.08 MHz).
UPPER THRESHOLD1
(OVER LOAD PROTECTION)
~–1dBFS
OPERATIONAL
RANGE
–6dBFS
REQUESTED LEVEL2
–46dBFS
LOWER THRESHOLD3
(DEEP FADE PROTECTION)
The SDIV for Serial Port 0 and Serial Port 1 can be programmed
via Internal Control Register 0x21. Valid SDIV values are between
0 and 7, corresponding to divide ratios between 1 and 8.
Serial Output Frame Timing
The SDFS signal transitions high to signal the start of a data
frame. On the next rising edge of SCLK, the port drives the first
bit of the serial data on the SDO pin. The falling edge of SCLK
or the subsequent rising edge can then be used by the DSP to
sample the data until the required number of bits is received
(determined by the serial output port word length). If the DSP
has the ability to count bits, it can identify when the complete
frame is received.
03683-031
Serial Port Timing Specifications
NOTES
1 ADJUSTABLE LEVEL, WITH PROGRAMMABLE STEP SIZE AND ADJUSTABLE PERIOD.
2 ADJUSTABLE LEVEL, LOOP GAIN (
