AD6653BCPZ-150

IF Diversity Receiver AD6653 FEATURES SNR = 70.8 dBc (71.8 dBFS) in a 32.7 MHz BW at 70 MHz @ 150 MSPS SFDR = 83 dBc to 70 MHz @ 150 MSPS 1.8 V analog supply operation 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS output supply Integer 1-to-8 input clock divider Integrated dual-channel ADC Sample rates up to 150 MSPS IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Integrated wideband digital downconverter (DDC) 32-bit, complex, numerically controlled oscillator (NCO) Decimating half-band filter and FIR filter Supports real and complex output modes Fast attack/threshold detect bits Composite signal monitor Energy-saving power-down modes APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 7. Integrated dual, 12-bit, 125 MSPS/150 MSPS ADC. Integrated wideband decimation filter and 32-bit complex NCO. Fast overrange detect and signal monitor with serial output. Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz. Flexible output modes, including independent CMOS, interleaved CMOS, IQ mode CMOS, and interleaved LVDS. SYNC input allows synchronization of multiple devices. 3-bit SPI port for register programming and register readback. FUNCTIONAL BLOCK DIAGRAM AVDD FD[0:3]A FD BITS/THRESHOLD DETECT I VIN+A SHA VIN–A ADC Q LP/HP DECIMATING HB FILTER + FIR DVDD DRVDD AD6653 CMOS/LVDS OUTPUT BUFFER D11A D0A VREF SENSE CML RBIAS VIN–B SHA VIN+B ADC I MULTI-CHIP SYNC FD BITS/THRESHOLD DETECT REF SELECT Q LP/HP DECIMATING HB FILTER + FIR SIGNAL MONITOR 32-BIT TUNING NCO fADC /8 NCO DIVIDE 1 TO 8 DUTY CYCLE STABILIZER DCO GENERATION CMOS OUTPUT BUFFER CLK+ CLK– DCOA DCOB D11B D0B PROGRAMMING DATA SIGNAL MONITOR DATA SIGNAL MONITOR INTERFACE SPI AGND SYNC FD[0:3]B NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 10 FOR LVDS PIN NAMES. Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. 06708-001 SMI SMI SMI SDFS SCLK/ SDO/ PDWN OEB SDIO/ SCLK/ CSB DCS DFS DRGND AD6653 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 ADC DC Specifications ............................................................... 5 ADC AC Specifications ............................................................... 6 Digital Specifications ................................................................... 7 Switching Specifications .............................................................. 9 Timing Specifications ................................................................ 10 Absolute Maximum Ratings.......................................................... 13 Thermal Characteristics ............................................................ 13 ESD Caution................................................................................ 13 Pin Configurations and Function Descriptions ......................... 14 Equivalent Circuits ......................................................................... 18 Typical Performance Characteristics ........................................... 19 Theory of Operation ...................................................................... 24 ADC Architecture ...................................................................... 24 Analog Input Considerations.................................................... 24 Voltage Reference ....................................................................... 26 Clock Input Considerations ...................................................... 27 Power Dissipation and Standby Mode..................................... 29 Digital Outputs ........................................................................... 30 Digital Downconverter .................................................................. 31 Downconverter Modes .............................................................. 31 Numerically Controlled Oscillator (NCO) ............................. 31 Half-Band Decimating Filter and FIR Filter........................... 31 fADC/8 Fixed-Frequency NCO ................................................... 31 Numerically Controlled Oscillator (NCO) ................................. 32 Frequency Translation ............................................................... 32 NCO Synchronization ............................................................... 32 Phase Offset................................................................................. 32 NCO Amplitude and Phase Dither .......................................... 32 Decimating Half-Band Filter and FIR Filter ............................... 33 Half-Band Filter Coefficients.................................................... 33 Half-Band Filter Features .......................................................... 33 Fixed-Coefficient FIR Filter ...................................................... 33 Synchronization.......................................................................... 34 Combined Filter Performance.................................................. 34 Final NCO ................................................................................... 34 ADC Overrange and Gain Control.............................................. 35 Fast Detect Overview................................................................. 35 ADC Fast Magnitude ................................................................. 35 ADC Overrange (OR)................................................................ 36 Gain Switching............................................................................ 36 Signal Monitor ................................................................................ 38 Peak Detector Mode................................................................... 38 RMS/MS Magnitude Mode....................................................... 38 Threshold Crossing Mode......................................................... 39 Additional Control Bits ............................................................. 39 DC Correction ............................................................................ 39 Signal Monitor SPORT Output ................................................ 40 Channel/Chip Synchronization.................................................... 41 Serial Port Interface (SPI).............................................................. 42 Configuration Using the SPI..................................................... 42 Hardware Interface..................................................................... 42 Configuration Without the SPI ................................................ 43 SPI Accessible Features.............................................................. 43 Memory Map .................................................................................. 44 Reading the Memory Map Register Table............................... 44 Memory Map Register Table..................................................... 45 Memory Map Register Description ......................................... 49 Applications Information .............................................................. 53 Design Guidelines ...................................................................... 53 Evaluation Board ............................................................................ 55 Power Supplies ............................................................................ 55 Input Signals................................................................................ 55 Output Signals ............................................................................ 55 Default Operation and Jumper Selection Settings................. 56 Alternative Clock Configurations............................................ 56 Alternative Analog Input Drive Configuration...................... 57 Schematics................................................................................... 58 Evaluation Board Layouts ......................................................... 68 Bill of Materials........................................................................... 76 Outline Dimensions ....................................................................... 78 Ordering Guide .......................................................................... 78 Rev. 0 | Page 2 of 80 AD6653 REVISION HISTORY 11/07—Revision 0: Initial Version Rev. 0 | Page 3 of 80 AD6653 GENERAL DESCRIPTION The AD6653 is a mixed-signal intermediate frequency (IF) receiver consisting of dual, 12-bit, 125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6653 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver, simplifying layout and reducing interconnection parasitics. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO)), a decimating half-band filter, a fixed FIR filter, and an fADC/8 fixed-frequency NCO. In addition to the receiver, DDC, the AD6653 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with short latency. In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition. The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system. After digital processing, data can be routed directly to the two external 12-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or as 1.8 V LVDS. The CMOS data can also be output in an interleaved configuration at a double data rate, using only Port A. The AD6653 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD6653 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. Rev. 0 | Page 4 of 80 AD6653 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance 1 VREF INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD, DVDD DRVDD (CMOS Mode) DRVDD (LVDS Mode) Supply Current IAVDD 2 , 3 IDVDD2, 3 IDRVDD2 (3.3 V CMOS) IDRVDD2 (1.8 V CMOS) IDRVDD2 (1.8 V LVDS) POWER CONSUMPTION DC Input Sine Wave Input2 (DRVDD = 1.8 V) Sine Wave Input2 (DRVDD = 3.3 V) Standby Power 4 Power-Down Power 1 2 Temperature Full Full Full Full 25°C 25°C Full Full Full Full 25°C Full Full Full Min 12 AD6653BCPZ-125 Typ Max Min 12 AD6653BCPZ-150 Typ Max Unit Bits −3.9 Guaranteed ±0.3 −2.7 ±0.3 ±0.1 ±19 ±38 ±5 7 0.21 2 8 6 ±0.6 −0.7 ±0.6 ±0.7 −5.2 Guaranteed ±0.2 ±0.6 −3.2 −0.9 ±0.2 ±0.2 ±17 ±49 ±0.7 ±0.7 % FSR % FSR % FSR % FSR ppm/°C ppm/°C ±18 ±5 7 0.21 2 8 6 ±18 mV mV LSB rms V p-p pF kΩ Full Full Full Full Full Full Full Full Full Full Full Full Full 1.7 1.7 1.7 1.8 3.3 1.8 390 270 20 12 57 770 1215 1275 77 2.5 1.9 3.6 1.9 689 1.7 1.7 1.7 1.8 3.3 1.8 440 320 24 15 57 870 1395 1450 77 2.5 1.9 3.6 1.9 785 V V V mA mA mA mA mA mW mW mW mW mW 800 905 8 8 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 11 for the equivalent analog input structure. Measured with a 9.7 MHz, full-scale sine wave input, NCO enabled with a frequency of 13 MHz, FIR filter enabled and the fS/8 output mix enabled with approximately 5 pF loading on each output bit. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pin inactive (set to AVDD or AGND). Rev. 0 | Page 5 of 80 AD6653 ADC AC SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, NCO enabled, half-band filter enabled, FIR filter enabled, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE-RATIO (SNR) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz WORST SECOND OR THIRD HARMONIC fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz WORST OTHER HARMONIC OR SPUR 2 fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz T WO-TONE SFDR fIN = 29.12 MHz, 32.12 MHz (−7 dBFS) fIN = 169.12 MHz, 172.12 MHz (−7 dBFS) CROSSTALK 3 ANALOG INPUT BANDWIDTH 1 2 3 Temperature 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C Min AD6653BCPZ-125 Typ Max 71.0 70.8 Min AD6653BCPZ-150 Typ Max 70.9 70.8 Unit dB dB dB dB dB dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB MHz 69.8 70.6 70.2 −85 −84 −74 −83 −81 85 84 74 83 81 −92 −90 −82 −88 −84 85 81 95 650 69.4 70.6 70.0 −84 −83 −73 −82 −77 84 83 73 82 77 −90 −87 −80 −83 −78 85 81 95 650 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. See the Applications Information section for more information about the worst other specifications for the AD6653. Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel. Rev. 0 | Page 6 of 80 AD6653 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance SYNC INPUT Logic Compliance Internal Bias Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance LOGIC INPUT (CSB) 1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SCLK/DFS) 2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SDIO/DCS, SMI SDFS)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance Temp Min AD6653BCPZ-125 Typ Max Min AD6653BCPZ-150 Typ Max Unit Full Full Full Full Full Full Full Full Full Full CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − 0.3 AVDD + 1.6 1.1 V AVDD 1.2 3.6 0 0.8 −10 +10 −10 +10 4 8 10 12 CMOS 1.2 AVDD − 0.3 1.2 0 −10 −10 8 1.22 0 −10 40 26 2 1.22 0 −92 −10 26 2 1.22 0 −10 38 26 5 3.6 0.6 +10 128 3.6 0.6 −135 +10 4 10 AVDD + 1.6 3.6 0.8 +10 +10 12 3.6 0.6 +10 132 CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − 0.3 AVDD + 1.6 1.1 V AVDD 1.2 3.6 0 0.8 −10 +10 −10 +10 4 8 10 12 CMOS 1.2 AVDD − 0.3 1.2 0 −10 −10 8 1.22 0 −10 40 26 2 1.22 0 −92 −10 26 2 1.22 0 −10 38 26 5 3.6 0.6 +10 128 3.6 0.6 −135 +10 4 10 AVDD + 1.6 3.6 0.8 +10 +10 12 3.6 0.6 +10 132 V V p-p V V V V μA μA pF kΩ Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full V V V V μA μA pF kΩ V V μA μA kΩ pF V V μA μA kΩ pF V V μA μA kΩ pF Rev. 0 | Page 7 of 80 AD6653 Parameter LOGIC INPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage IOH = 50 μA IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 μA CMOS Mode—DRVDD = 1.8 V High Level Output Voltage IOH = 50 μA IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 μA LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode 1 2 Temp Full Full Full Full Full Full Min 1.22 0 −90 −10 AD6653BCPZ-125 Typ Max 3.6 0.6 −134 +10 26 5 Min 1.22 0 −90 −10 AD6653BCPZ-150 Typ Max 3.6 0.6 −134 +10 26 5 Unit V V μA μA kΩ pF Full Full Full Full 3.29 3.25 0.2 0.05 3.29 3.25 0.2 0.05 V V V V Full Full Full Full Full Full Full Full 1.79 1.75 0.2 0.05 250 1.15 150 1.15 350 1.25 200 1.25 450 1.35 280 1.35 1.79 1.75 0.2 0.05 250 1.15 150 1.15 350 1.25 200 1.25 450 1.35 280 1.35 V V V V mV V mV V Pull up. Pull down. Rev. 0 | Page 8 of 80 AD6653 SWITCHING SPECIFICATIONS Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate1 DCS Enabled DCS Disabled CLK Period—Divide-by-1 Mode (tCLK) CLK Pulse Width High (tCLKH) Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Mode, DCS Enabled Divide-by-3 Through Divide-by-8 Modes, DCS Enabled DATA OUTPUT PARAMETERS (DATA, FD) CMOS Noninterleaved Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Noninterleaved Mode—DRVDD = 3.3 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Interleaved and IQ Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Interleaved and IQ Mode—DRVDD = 3.3 V Data Propagation Delay (tPD) 2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) LVDS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Pipeline Delay (Latency) NCO, FIR, fS/8 Mix Disabled Pipeline Delay (Latency) NCO Enabled; FIR and fS/8 Mix Disabled (Complex Output Mode) Pipeline Delay (Latency) NCO, FIR Filter, and fS/8 Mix Enabled Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time3 OUT-OF-RANGE RECOVERY TIME 1 2 Temperature Full Full Full Full Full Full Full Full AD6653BCPZ-125 Min Typ Max 625 20 10 8 2.4 3.6 1.6 0.8 4 4 125 125 AD6653BCPZ-150 Min Typ Max 625 20 10 6.66 2.0 3.0 1.6 0.8 3.33 3.33 150 150 Unit MHz MSPS MSPS ns ns ns ns ns 5.6 4.4 4.66 3.66 Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 1.6 4.0 3.9 5.4 9.5 6.5 4.1 5.8 9.7 6.3 3.9 4.8 4.9 3.1 4.1 5.2 5.1 2.9 4.8 5.3 38 38 109 1.0 0.1 350 44 6.2 7.3 1.6 4.0 3.9 5.4 8.16 5.16 4.1 5.8 8.36 4.96 3.9 4.8 4.23 2.43 4.1 5.2 4.43 2.23 4.8 5.3 38 38 109 1.0 0.1 350 44 6.2 7.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cycles Cycles Cycles ns ps rms μs Cycles 1.9 4.4 6.4 7.7 1.9 4.4 6.4 7.7 1.6 3.4 6.2 6.7 1.6 3.4 6.2 6.7 1.9 3.8 6.4 7.1 1.9 3.8 6.4 7.1 2.5 3.7 7.0 7.3 2.5 3.7 7.0 7.3 Conversion rate is the clock rate after the divider. Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with a 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors. Rev. 0 | Page 9 of 80 AD6653 TIMING SPECIFICATIONS Table 5. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO SPORT TIMING REQUIREMENTS tCSSCLK tSSLKSDO tSSCLKSDFS Conditions SYNC to the rising edge of CLK setup time SYNC to the rising edge of CLK hold time Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge Delay from rising edge of CLK+ to rising edge of SMI SCLK Delay from rising edge of SMI SCLK to SMI SDO Delay from rising edge of SMI SCLK to SMI SDFS 2 2 40 2 2 10 10 10 10 Min Typ 0.24 0.4 Max Unit ns ns ns ns ns ns ns ns ns ns ns 3.2 −0.4 −0.4 4.5 0 0 6.2 +0.4 +0.4 ns ns ns Timing Diagrams CLK+ tPD DECIMATED CMOS DATA CHANNEL A/B DATA BITS tDCO CHANNEL A/B DATA BITS CHANNEL A/B DATA BITS DECIMATED FD DATA CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS tS tH 06708-109 DECIMATED DCOA/DCOB Figure 2. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000) CLK+ tPD tDCO DECIMATED CMOS DATA CHANNEL A/B DATA BITS CHANNEL A/B DATA BITS CHANNEL A/B DATA BITS DECIMATED FD DATA CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS tS DECIMATED DCOA/DCOB tH Figure 3. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100) Rev. 0 | Page 10 of 80 06708-002 AD6653 CLK+ tPD DECIMATED INTERLEAVED CMOS DATA DECIMATED INTERLEAVED FD DATA DECIMATED DCO CHANNEL A: DATA CHANNEL B: DATA CHANNEL A: DATA CHANNEL B: DATA tDCO CHANNEL A: DATA CHANNEL B: DATA CHANNEL A: FD BITS CHANNEL B: FD BITS CHANNEL A: FD BITS CHANNEL B: FD BITS CHANNEL A: FD BITS CHANNEL B: FD BITS tS tH 06708-003 Figure 4. Decimated Interleaved CMOS Mode Data and Fast Detect Output Timing CLK+ tPD DECIMATED CMOS IQ OUTPUT DATA CHANNEL A/B: Q DATA CHANNEL A/B: I DATA CHANNEL A/B: Q DATA tDCO CHANNEL A/B: I DATA CHANNEL A/B: Q DATA CHANNEL A/B: I DATA CMOS FD DATA CHANNEL A/B: FD BITS CHANNEL A/B: FD BITS CHANNEL A/B: FD BITS CHANNEL A/B: FD BITS CHANNEL A/B: FD BITS CHANNEL A/B: FD BITS tS DECIMATED DCOA/DCOB tH Figure 5. Decimated IQ Mode CMOS Data and Fast Detect Output Timing CLK– CLK+ tPD LVDS DATA CHANNEL A: DATA CHANNEL B: DATA CHANNEL A: DATA CHANNEL B: DATA CHANNEL A: DATA LVDS FAST DET DCO– DCO+ CHANNEL A: FD CHANNEL B: FD CHANNEL A: FD CHANNEL B: FD CHANNEL A: FD tDCO 06708-005 Figure 6. Decimated Interleaved LVDS Mode Data and Fast Detect Output Timing CLK+ tSSYNC SYNC tHSYNC 06708-006 Figure 7. SYNC Timing Inputs Rev. 0 | Page 11 of 80 06708-004 AD6653 CLK+ CLK– tCSSCLK SMI SCLK tSSCLKSDFS SMI SDFS tSSCLKSDFS SMI SDO DATA DATA Figure 8. Signal Monitor SPORT Output Timing Rev. 0 | Page 12 of 80 06708-007 AD6653 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND CML to AGND RBIAS to AGND CSB to AGND SCLK/DFS to DRGND SDIO/DCS to DRGND SMI SDO/OEB to DRGND SMI SCLK/PDWN to DRGND SMI SDFS to DRGND D0A/D0B through D11A/D11B to DRGND FD0A/FD0B through FD3A/FD3B to DRGND DCOA/DCOB to DRGND ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to AVDD + 0.2 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −40°C to +85°C 150°C −65°C to +125°C THERMAL CHARACTERISTICS The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints and maximizes the thermal capability of the package. Table 7. Thermal Resistance Package Type 64-Lead LFCSP 9 mm × 9 mm (CP-64-3) 1 2 Airflow Velocity (m/s) 0 1.0 2.0 θJA1, 2 18.8 16.5 15.8 θJC1, 3 0.6 θJB1, 4 6.0 Unit °C/W °C/W °C/W Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown, airflow increases heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θJA. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 13 of 80 AD6653 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PIN 1 INDICATOR DRGND D3B D2B D1B D0B (LSB) DNC DNC DVDD FD3B FD2B FD1B FD0B SYNC CSB CLK– CLK+ DRVDD D4B D5B D6B D7B D8B D9B D10B D11B (MSB) DCOB DCOA DNC DNC D0A (LSB) D1A D2A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD6653 PARALLEL CMOS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK/DFS SDIO/DCS AVDD AVDD VIN+B VIN–B RBIAS CML SENSE VREF VIN–A VIN+A AVDD SMI SDFS SMI SCLK/PDWN SMI SDO/OEB DNC = DO NOT CONNECT D3A D4A D5A DRGND DRVDD D6A D7A DVDD D8A D9A D10A D11A (MSB) FD0A FD1A FD2A FD3A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 9. LFCSP Parallel CMOS Pin Configuration (Top View) Table 8. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic ADC Power Supplies 20, 64 DRGND 1, 21 DRVDD 24, 57 DVDD 36, 45, 46 AVDD 0 AGND 12, 13, 58, 59 DNC ADC Analog 37 VIN+A 38 VIN−A 44 VIN+B 43 VIN−B 39 VREF 40 SENSE 42 RBIAS 41 CML 49 CLK+ 50 CLK− ADC Fast Detect Outputs 29 FD0A 30 FD1A 31 FD2A 32 FD3A 53 FD0B 54 FD1B 55 FD2B 56 FD3B Type Ground Supply Supply Supply Ground Description Digital Output Ground. Digital Output Driver Supply (1.8 V to 3.3 V). Digital Power Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. Do Not Connect. Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (−) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Voltage Reference Mode Select. See Table 11 for details. External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. Channel A Fast Detect Indicator. See Table 17 for details. Channel A Fast Detect Indicator. See Table 17 for details. Channel A Fast Detect Indicator. See Table 17 for details. Channel A Fast Detect Indicator. See Table 17 for details. Channel B Fast Detect Indicator. See Table 17 for details. Channel B Fast Detect Indicator. See Table 17 for details. Channel B Fast Detect Indicator. See Table 17 for details. Channel B Fast Detect Indicator. See Table 17 for details. Input Input Input Input Input/Output Input Input/Output Output Input Input Output Output Output Output Output Output Output Output Rev. 0 | Page 14 of 80 06708-008 AD6653 Pin No. Mnemonic Digital Inputs 52 SYNC Digital Outputs 14 D0A (LSB) 15 D1A 16 D2A 17 D3A 18 D4A 19 D5A 22 D6A 23 D7A 25 D8A 26 D9A 27 D10A 28 D11A (MSB) 60 D0B (LSB) 61 D1B 62 D2B 63 D3B 2 D4B 3 D5B 4 D6B 5 D7B 6 D8B 7 D9B 8 D10B 9 D11B (MSB) 11 DCOA 10 DCOB SPI Control 48 SCLK/DFS 47 SDIO/DCS 51 CSB Signal Monitor Port 33 SMI SDO/OEB 35 SMI SDFS 34 SMI SCLK/PDWN Type Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/Output Input Input/Output Output Input/Output Description Digital Synchronization Pin. Slave mode only. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel A Data Clock Output. Channel B Data Clock Output. SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select. Active low. Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. Signal Monitor Serial Data Frame Sync. Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode. Rev. 0 | Page 15 of 80 AD6653 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PIN 1 INDICATOR DRGND DNC DNC FD3+ FD3– FD2+ FD2– DVDD FD1+ FD1– FD0+ FD0– SYNC CSB CLK– CLK+ DRVDD DNC DNC D0– (LSB) D0+ (LSB) D1– D1+ D2– D2+ DCO– DCO+ D3– D3+ D4– D4+ D5– 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD6653 PARALLEL LVDS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK/DFS SDIO/DCS AVDD AVDD VIN+B VIN–B RBIAS CML SENSE VREF VIN–A VIN+A AVDD SMI SDFS SMI SCLK/PDWN SMI SDO/OEB DNC = DO NOT CONNECT D5+ D6– D6+ DRGND DRVDD D7– D7+ DVDD D8– D8+ D9– D9+ D10– D10+ D11– (MSB) D11+ (MSB) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 10. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View) Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic ADC Power Supplies 20, 64 DRGND 1, 21 DRVDD 24, 57 DVDD 36, 45, 46 AVDD 0 AGND 2, 3, 62, 63 DNC ADC Analog 37 VIN+A 38 VIN−A 44 VIN+B 43 VIN−B 39 VREF 40 SENSE 42 RBIAS 41 CML 49 CLK+ 50 CLK− ADC Fast Detect Outputs 54 FD0+ 53 FD0− 56 55 59 58 61 60 FD1+ FD1− FD2+ FD2− FD3+ FD3− Type Ground Supply Supply Supply Ground Description Digital Output Ground. Digital Output Driver Supply (1.8 V to 3.3 V). Digital Power Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. Do Not Connect. Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (−) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Voltage Reference Mode Select. See Table 11 for details. External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 17 for details. Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 17 for details. Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 17 for details. Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 17 for details. Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 17 for details. Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 17 for details. Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 17 for details. Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 17 for details. Rev. 0 | Page 16 of 80 Input Input Input Input Input/Output Input Input/Output Output Input Input Output Output Output Output Output Output Output Output 06708-009 AD6653 Pin No. Mnemonic Digital Inputs 52 SYNC Digital Outputs 5 D0+ (LSB) 4 D0− (LSB) 7 D1+ 6 D1− 9 D2+ 8 D2− 13 D3+ 12 D3− 15 D4+ 14 D4− 17 D5+ 16 D5− 19 D6+ 18 D6− 23 D7+ 22 D7− 26 D8+ 25 D8− 28 D9+ 27 D9− 30 D10+ 29 D10− 32 D11+ (MSB) 31 D11− (MSB) 11 DCO+ 10 DCO− SPI Control 48 SCLK/DFS 47 SDIO/DCS 51 CSB Signal Monitor Port 33 SMI SDO/OEB 35 34 SMI SDFS SMI SCLK/PDWN Type Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/Output Input Input/Output Output Input/Output Description Digital Synchronization Pin. Slave mode only. Channel A/Channel B LVDS Output Data 0—True. Channel A/Channel B LVDS Output Data 0—Complement. Channel A/Channel B LVDS Output Data 1—True. Channel A/Channel B LVDS Output Data 1—Complement. Channel A/Channel B LVDS Output Data 2—True. Channel A/Channel B LVDS Output Data 2—Complement. Channel A/Channel B LVDS Output Data 3—True. Channel A/Channel B LVDS Output Data 3—Complement. Channel A/Channel B LVDS Output Data 4 —True. Channel A/Channel B LVDS Output Data 4—Complement. Channel A/Channel B LVDS Output Data 5—True. Channel A/Channel B LVDS Output Data 5—Complement. Channel A/Channel B LVDS Output Data 6—True. Channel A/Channel B LVDS Output Data 6—Complement. Channel A/Channel B LVDS Output Data 7—True. Channel A/Channel B LVDS Output Data 7—Complement. Channel A/Channel B LVDS Output Data 8—True. Channel A/Channel B LVDS Output Data 8—Complement. Channel A/Channel B LVDS Output Data 9—True. Channel A/Channel B LVDS Output Data 9—Complement. Channel A/Channel B LVDS Output Data 10—True. Channel A/Channel B LVDS Output Data 10—Complement. Channel A/Channel B LVDS Output Data 11—True. Channel A/Channel B LVDS Output Data 11—Complement. Channel A/Channel B LVDS Data Clock Output—True. Channel A/Channel B LVDS Data Clock Output—Complement. SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data Input/Output/Duty Cycle Stabilizer in External Pin Mode. SPI Chip Select. Active low. Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. Signal Monitor Serial Data Frame Sync. Signal Monitor Serial Clock Output/Power-Down Input (Active High) in External Pin Mode. Rev. 0 | Page 17 of 80 AD6653 EQUIVALENT CIRCUITS VIN SCLK/DFS 1kΩ 26kΩ 06708-010 Figure 11. Equivalent Analog Input Circuit Figure 15. Equivalent SCLK/DFS Input Circuit AVDD 1.2V CLK+ 10kΩ 10kΩ CLK– SENSE 1kΩ Figure 12. Equivalent Clock lnput Circuit 06708-011 Figure 16. Equivalent SENSE Circuit DRVDD AVDD 26kΩ CSB 1kΩ DRGND 06708-012 Figure 13. Equivalent Digital Output Circuit Figure 17. Equivalent CSB Input Circuit AVDD DRVDD DRVDD 26kΩ 1kΩ SDIO/DCS 06708-013 VREF 6kΩ Figure 14. Equivalent SDIO/DCS Circuit or SMI SDFS Circuit Figure 18. Equivalent VREF Circuit Rev. 0 | Page 18 of 80 06708-017 06708-016 06708-015 06708-014 AD6653 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 150 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, 64k sample, TA = 25°C, NCO enabled, FIR filter enabled, unless otherwise noted. In the FFT plots that follow, the location of the second and third harmonics is noted when they fall in the pass band of the filter. 0 –20 –40 –60 –80 –100 –120 –140 0 5 10 15 20 25 30 35 FREQUENCY (MHz) SECOND HARMONIC 150MSPS 2.4MHz @ –1dBFS SNR = 70.9dBc (71.9dBFS) SFDR = 83.2dBc fNCO = 18.75MHz AMPLITUDE (dBFS) 0 –20 –40 –60 150MSPS 140.1MHz @ –1dBFS SNR = 70.6dBc (71.6dBFS) SFDR = 82.9dBc fNCO = 126MHz AMPLITUDE (dBFS) THIRD HARMONIC THIRD HARMONIC –80 –100 –120 –140 0 5 10 15 SECOND HARMONIC 06708-018 20 25 30 35 FREQUENCY (MHz) Figure 19. AD6653-150 Single-Tone FFT with fIN = 2.4 MHz, fNCO = 18.75 MHz 0 –20 –40 –60 –80 –100 –120 –140 0 5 10 15 20 25 30 35 FREQUENCY (MHz) Figure 22. AD6653-150 Single-Tone FFT with fIN = 140.1 MHz, fNCO = 126 MHz 0 –20 –40 –60 THIRD HARMONIC –80 –100 –120 –140 0 5 10 15 20 25 30 35 FREQUENCY (MHz) 150MSPS 30.3MHz @ –1dBFS SNR = 71.0dBc (72.0dBFS) SFDR = 92.3dBc fNCO = 24MHz AMPLITUDE (dBFS) 150MSPS 220.1MHz @ –1dBFS SNR = 70.0dBc (71.0dBFS) SFDR = 80.9dBc fNCO = 205MHz AMPLITUDE (dBFS) 06708-019 Figure 20. AD6653-150 Single-Tone FFT with fIN = 30.3 MHz, fNCO = 24 MHz 0 –20 –40 –60 THIRD HARMONIC –80 –100 –120 –140 0 5 10 15 20 25 30 35 FREQUENCY (MHz) 150MSPS 70.1MHz @ –1dBFS SNR = 70.8dBc (71.8dBFS) SFDR = 82.9dBc fNCO = 56MHz Figure 23. AD6653-150 Single-Tone FFT with fIN = 220.1 MHz, fNCO = 205 MHz 0 –20 –40 –60 –80 –100 –120 –140 0 5 10 15 20 25 30 35 FREQUENCY (MHz) 150MSPS 332.1MHz @ –1dBFS SNR = 69.4dBc (70.4dBFS) SFDR = 91.2dBc fNCO = 321.5MHz AMPLITUDE (dBFS) 06708-020 AMPLITUDE (dBFS) Figure 21. AD6653-150 Single-Tone FFT with fIN = 70.1 MHz, fNCO = 56 MHz Figure 24. AD6653-150 Single-Tone FFT with fIN = 332.1 MHz, fNCO = 321.5 MHz Rev. 0 | Page 19 of 80 06708-023 06708-022 06708-021 AD6653 0 –20 –40 –60 THIRD HARMONIC –80 –100 –120 –140 0 5 10 15 20 25 30 35 FREQUENCY (MHz) 150MSPS 445.1MHz @ –1dBFS SNR = 69.1dBc (70.1dBFS) SFDR = 73.7dBc fNCO = 429MHz SECOND HARMONIC AMPLITUDE (dBFS) 0 –20 –40 –60 125MSPS 70.3MHz @ –1dBFS SNR = 70.9dBc (71.9dBFS) SFDR = 85.9dBc fNCO = 78MHz AMPLITUDE (dBFS) THIRD HARMONIC –80 –100 –120 –140 0 5 10 15 20 25 30 FREQUENCY (MHz) 06708-024 Figure 25. AD6653-150 Single-Tone FFT with fIN = 445.1 MHz, fNCO = 429 MHz 0 –20 –40 –60 –80 –100 –120 –140 0 5 10 15 20 25 30 FREQUENCY (MHz) 125MSPS 2.4MHz @ –1dBFS SNR = 71.0dBc (72.0dBFS) SFDR = 84.6dBc fNCO = 15.75MHz Figure 28. AD6653-125 Single-Tone FFT with fIN = 70.3 MHz, fNCO = 78 MHz 0 –20 –40 –60 –80 –100 –120 –140 0 5 10 15 20 25 30 FREQUENCY (MHz) THIRD HARMONIC 125MSPS 140.1MHz @ –1dBFS SNR = 70.6dBc (71.6dBFS) SFDR = 86.1dBc fNCO = 142MHz AMPLITUDE (dBFS) SECOND HARMONIC THIRD HARMONIC 06708-025 AMPLITUDE (dBFS) Figure 26. AD6653-125 Single-Tone FFT with fIN = 2.4 MHz, fNCO = 15.75 MHz 0 –20 –40 –60 THIRD HARMONIC –80 –100 –120 –140 0 5 10 15 20 25 30 FREQUENCY (MHz) Figure 29. AD6653-125 Single-Tone FFT with fIN = 140.1 MHz, fNCO = 142 MHz 0 –20 –40 –60 –80 –100 –120 –140 0 5 10 15 20 25 30 FREQUENCY (MHz) 125MSPS 30.3MHz @ –1dBFS SNR = 70.9dBc (71.9dBFS) SFDR = 90.7dBc fNCO = 21MHz AMPLITUDE (dBFS) 125MSPS 220.1MHz @ –1dBFS SNR = 70.2dBc (71.2dBFS) SFDR = 87.9dBc fNCO = 231MHz AMPLITUDE (dBFS) 06708-026 Figure 27. AD6653-125 Single-Tone FFT with fIN = 30.3 MHz, fNCO = 21 MHz Figure 30. AD6653-125 Single-Tone FFT with fIN = 220.1 MHz, fNCO = 231 MHz Rev. 0 | Page 20 of 80 06708-029 06708-028 06708-027 AD6653 120 95 90 SFDR = +85°C 85 SNR/SFDR (dBc) 100 SNR/SFDR (dBc AND dBFS) SFDR (dBFS) 80 SNR (dBFS) SFDR = +25°C 80 SFDR = –40°C 75 70 65 SNR = +25°C SNR = +85°C SNR = –40°C 60 40 SFDR (dBc) 20 SNR (dBc) 06708-030 85dB REFERENCE LINE –80 –70 –60 –50 –40 –30 –20 –10 0 0 50 100 150 200 250 300 350 400 450 INPUT AMPLITUDE (dBFS) INPUT FREQUENCY (MHz) Figure 31. AD6653-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 2.4 MHz, fNCO = 18.75 MHz 120 Figure 34. AD6653-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with DRVDD = 3.3 V –1.5 0.5 100 SNR/SFDR (dBc AND dBFS) SFDR (dBFS) –2.0 GAIN ERROR (%FSR) 0.4 OFFSET OFFSET ERROR (%FSR) 06708-035 06708-034 80 SNR (dBFS) –2.5 0.3 60 –3.0 GAIN –3.5 0.2 40 SFDR (dBc) 20 SNR (dBc) –80 –70 –60 –50 –40 –30 –20 –10 0 06708-031 85dB REFERENCE LINE 0.1 0 –90 –4.0 –40 0 –20 0 20 40 60 80 TEMPERATURE (°C) INPUT AMPLITUDE (dBFS) Figure 32. AD6653-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 98.12 MHz, fNCO = 100.49 MHz 95 90 SFDR/IMD3 (dBc AND dBFS) Figure 35. AD6653-150 Gain and Offset vs. Temperature 0 SFDR = +85°C 85 SNR/SFDR (dBc) –20 SFDR (dBc) –40 IMD3 (dBc) –60 SFDR = +25°C 80 SFDR = –40°C 75 70 65 60 0 50 100 150 200 250 300 350 400 450 INPUT FREQUENCY (MHz) SNR = +25°C SNR = +85°C SNR = –40°C –80 SFDR (dBFS) –100 IMD3 (dBFS) 06708-032 –120 –90 –78 –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) Figure 33. AD6653-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with DRVDD = 1.8 V Figure 36. AD6653-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29.12 MHz, fIN2 = 32.12 MHz, fS = 150 MSPS, fNCO = 22 MHz Rev. 0 | Page 21 of 80 06708-033 0 –90 60 AD6653 0 0 –20 150MSPS 169.12MHz @ –7dBFS 172.12MHz @ –7dBFS SFDR = 83.6dBc (90.6dBFS) fNCO = 177MHz –20 SFDR/IMD3 (dBc AND dBFS) SFDR (dBc) –40 IMD3 (dBc) –60 AMPLITUDE (dBFS) 06708-036 –40 –60 –80 –100 –120 –140 0 5 10 15 –80 SFDR (dBFS) –100 IMD3 (dBFS) –78 –66 –54 –42 –30 –18 –6 20 25 30 35 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 37. AD6653-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 169.12 MHz, fIN2 = 172.12 MHz, fS = 150 MSPS, fNCO = 177 MHz 0 –20 –40 –60 –80 –100 –120 –140 Figure 40. AD6653-150 Two-Tone FFT with fIN1 = 169.12 MHz, fIN2 = 172.12 MHz, fS = 150 MSPS, fNCO = 177 MHz 0 –20 NPR = 61.9dBc NOTCH @ 18.5MHz NOTCH WIDTH = 3MHz AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –60 –80 –100 06708-037 0 5 10 15 20 25 30 0 7.5 15.0 22.5 30.0 37.5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 38. AD6653-125, Two 64k WCDMA Carriers with fIN = 170 MHz, fS = 122.88 MHz, fNCO = 168.96 MHz 0 –20 –40 –60 –80 –100 –120 –140 0 5 10 15 20 25 30 35 FREQUENCY (MHz) 95 90 85 SNR/SFDR (dBc) Figure 41. AD6653-150 Noise Power Ratio (NPR) 150MSPS 29.12MHz @ –7dBFS 32.12MHz @ –7dBFS SFDR = 91.1dBc (98.1dBFS) fNCO = 22MHz SFDR AMPLITUDE (dBFS) 80 75 SNR 70 65 60 0 25 50 75 100 125 150 SAMPLE RATE (MSPS) 06708-038 Figure 39. AD6653-150 Two-Tone FFT with fIN1 = 29.12 MHz, fIN2 = 32.12 MHz, fS = 150 MSPS, fNCO = 22 MHz Figure 42. AD6653-150 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 2.3 MHz Rev. 0 | Page 22 of 80 06708-041 06708-040 –120 06708-039 –120 –90 AD6653 12 0.21 LSB rms 90 10 NUMBER OF HITS (1M) 85 SFDR SNR/SFDR (dBc) 8 80 6 75 SNR 4 2 70 06708-042 N–3 N–2 N–1 N N+1 N+2 N+3 0.4 OUTPUT CODE 0.6 0.8 1.0 1.2 1.4 INPUT COMMON-MODE VOLTAGE (V) 1.6 Figure 43. AD6653 Grounded Input Histogram 90 Figure 45. AD6653-150 SNR/SFDR vs. Input Common Mode (VCM) with fIN = 30.3 MHz, fNCO = 45 MHz 85 SFDR DCS ON SNR/SFDR (dBc) 80 SFDR DCS OFF 75 SNR DCS ON 70 SNR DCS OFF 65 20 30 40 50 60 DUTY CYCLE (%) 70 80 Figure 44. AD6653-150 SNR/SFDR vs. Duty Cycle with fIN = 30.3 MHz, fNCO = 45 MHz 06708-043 Rev. 0 | Page 23 of 80 06708-044 0 65 0.2 AD6653 THEORY OF OPERATION The AD6653 has two analog input channels, two decimating channels, and two digital output channels. The intermediate frequency (IF) input signal passes through several stages before appearing at the output port(s) as a filtered, decimated digital signal. The dual ADC design can be used for diversity reception of signals, where the ADCs operate identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency segment from dc to 150 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 450 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD6653 can be used as a baseband receiver, where one ADC is used for I input data, and the other is used for Q input data. Synchronization capability is provided to allow synchronized timing between multiple channels or multiple devices. The NCO phase can be set to produce a known offset relative to another channel or device. Programming and control of the AD6653 are accomplished using a 3-bit SPI-compatible serial interface. The clock signal alternatively switches the SHA between sample mode and hold mode (see Figure 46). When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within 1/2 of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In IF undersampling applications, any shunt capacitors should be reduced. In combination with the driving source impedance, the shunt capacitors limit input bandwidth. Refer to Application Note AN-742, Frequency Domain Response of SwitchedCapacitor ADCs; Application Note AN-827, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, “Transformer-Coupled Front-End for Wideband A/D Converters,” for more information on this subject (see www.analog.com). In general, the precise values are dependent on the application. S CH S CS VIN+ CPIN, PAR VIN– CPIN, PAR CH S H ADC ARCHITECTURE AD6653 architecture consists of a front-end sample-and-hold amplifier (SHA), followed by a pipelined switched-capacitor ADC. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage of each channel contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. CS S Figure 46. Switched-Capacitor SHA Input For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core. The output common mode of the reference buffer is set to VCMREF (approximately 1.6 V). Input Common Mode The analog inputs of the AD6653 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.55 × AVDD is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 45). An on-board common-mode voltage reference is included in the design and is available from the CML pin. Optimum performance is achieved when the common-mode voltage of the analog input is set by the CML pin voltage (typically 0.55 × AVDD). ANALOG INPUT CONSIDERATIONS The analog input to the AD6653 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. Rev. 0 | Page 24 of 80 06708-048 AD6653 Differential Input Configurations Optimum performance is achieved while driving the AD6653 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD6653 (see Figure 47), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 499Ω 1V p-p 49.9Ω 499Ω R VIN+ C R 499Ω AVDD The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD6653. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 49). An alternative to using a transformer coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver, as shown in Figure 50. See the AD8352 data sheet for more information. In addition, if the application requires an amplifier with variable gain, the AD8375 or AD8376 digital variable gain amplifiers (DVGAs) provide good performance driving the AD6653. In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 10 displays recommended values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide. Table 10. Example RC Network Frequency Range (MHz) 0 to 70 70 to 200 200 to 300 >300 R Series (Ω Each) 33 33 15 15 C Differential (pF) 15 5 5 Open AD8138 0.1µF 523Ω AD6653 06708-049 VIN– CML Figure 47. Differential Input Configuration Using the AD8138 For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 48. To bias the analog input, the CML voltage can be connected to the center tap of the secondary winding of the transformer. R 2V p-p 49.9Ω R C VIN+ AD6653 VIN– CML 0.1µF Figure 48. Differential Transformer-Coupled Configuration 0.1µF 2V p-p 06708-050 0.1µF 25Ω R VIN+ C PA S S P 0.1µF 25Ω 0.1µF R AD6653 VIN– CML 06708-051 06708-052 Figure 49. Differential Double Balun Input Configuration VCC 0.1µF ANALOG INPUT 0Ω 16 1 2 8, 13 11 0.1µF 0.1µF 200Ω R VIN+ C R CD RD RG 3 4 5 AD8352 10 14 0.1µF 0.1µF 200Ω AD6653 VIN– CML ANALOG INPUT 0.1µF 0Ω 0.1µF Figure 50. Differential Input Configuration Using the AD8352 Rev. 0 | Page 25 of 80 AD6653 Single-Ended Input Configuration A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 51 shows a typical single-ended input configuration. 10µF AVDD 1kΩ R 2V p-p 49.9Ω 0.1µF 1kΩ C R VIN+ VIN+A/VIN+B VIN–A/VIN–B ADC CORE VREF 1.0µF 0.1µF SELECT LOGIC SENSE 0.5V 06708-054 AVDD 1kΩ 10µF 0.1µF 1kΩ AD6653 AD6653 VIN– 06708-053 Figure 52. Internal Reference Configuration Figure 51. Single-Ended Input Configuration VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD6653. The input range can be adjusted by varying the reference voltage applied to the AD6653, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference. If a resistor divider is connected externally to the chip, as shown in Figure 53, the switch again sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as follows: R2 ⎞ VREF = 0.5 × ⎛1 + ⎜ ⎟ ⎝ R1 ⎠ The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. VIN+A/VIN+B VIN–A/VIN–B Internal Reference Connection A comparator within the AD6653 detects the potential at the SENSE pin and configures the reference into four possible modes, which are summarized in Table 11. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 52), setting VREF to 1.0 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. ADC CORE VREF 1.0µF 0.1µF R2 SENSE SELECT LOGIC R1 0.5V 06708-055 AD6653 Figure 53. Programmable Reference Configuration Table 11. Reference Configuration Summary Selected Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD VREF 0.2 V to VREF AGND to 0.2 V Resulting VREF (V) N/A 0.5 R2 ⎞ (see Figure 53) ⎛ 0 .5 × ⎜ 1 + ⎟ R1 ⎠ ⎝ Resulting Differential Span (V p-p) 2 × external reference 1.0 2 × VREF 2.0 1.0 Rev. 0 | Page 26 of 80 AD6653 If the internal reference of the AD6653 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 54 depicts how the internal reference voltage is affected by loading. 0 VREF = 0.5V CLOCK INPUT CONSIDERATIONS For optimum performance, the AD6653 sample clock inputs, CLK+ and CLK−, should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 56) and require no external bias. AVDD REFERENCE VOLTAGE ERROR (%) –0.25 VREF = 1.0V –0.50 1.2V CLK+ CLK– –0.75 2pF 2pF 06708-058 –1.00 Figure 56. Equivalent Clock Input Circuit 0 0.5 1.0 LOAD CURRENT (mA) 1.5 2.0 06708-056 –1.25 Clock Input Options The AD6653 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, the clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 57 and Figure 58 show two preferred methods for clocking the AD6653 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal, using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD6653 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD6653 while preserving the fast rise and fall times of the signal, which are critical to low jitter performance. Mini-Circuits® ADT1–1WT, 1:1Z 0.1µF XFMR 100Ω 0.1µF 0.1µF SCHOTTKY DIODES: HSMS2822 Figure 54. VREF Accuracy vs. Load External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 55 shows the typical drift characteristics of the internal reference in both 1.0 V and 0.5 V modes. 2.5 2.0 REFERENCE VOLTAGE ERROR (mV) 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –20 0 20 40 60 80 06708-057 0.1µF CLOCK INPUT 50Ω CLK+ ADC AD6653 06708-059 CLK– –2.5 –40 TEMPERATURE (°C) Figure 57. Transformer-Coupled Differential Clock (Up to 200 MHz) Figure 55. Typical VREF Drift When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 6 kΩ load (see Figure 18). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V. 1nF CLOCK INPUT 50Ω 1nF 0.1µF CLK+ 0.1µF SCHOTTKY DIODES: HSMS2822 ADC AD6653 06708-157 CLK– Figure 58. Balun-Coupled Differential Clock (Up to 625 MHz) Rev. 0 | Page 27 of 80 AD6653 If a low jitter clock source is not available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 59. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent jitter performance. 0.1µF 0.1µF CLK+ Input Clock Divider The AD6653 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. If a divide ratio other than 1 is selected, the duty cycle stabilizer is automatically enabled. The AD6653 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. CLOCK INPUT AD951x CLOCK INPUT 0.1µF 50kΩ 50kΩ PECL DRIVER 240Ω 240Ω 100Ω 0.1µF ADC AD6653 CLK– 06708-060 Figure 59. Differential PECL Sample Clock (Up to 625 MHz) This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as shown in Figure 60. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent jitter performance. Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD6653 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting performance of the AD6653. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on, as shown in Figure 44. Jitter on the rising edge of the input clock is still of paramount concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz nominally. The loop has a time constant associated with it that must be considered when the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time period that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. CLOCK INPUT 0.1µF 0.1µF CLK+ LVDS DRIVER AD951x 100Ω 0.1µF 50kΩ 50kΩ Figure 60. Differential LVDS Sample Clock (Up to 625 MHz) In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, the CLK+ pin should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 61). CLK+ can be driven directly from a CMOS gate. Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.6 V, making the selection of the drive logic voltage very flexible. VCC 0.1µF CLOCK INPUT 50Ω 1kΩ 1kΩ CMOS DRIVER AD951x OPTIONAL 0.1µF 100Ω CLK+ ADC AD6653 CLK– 06708-062 06708-061 CLOCK INPUT 0.1µF ADC AD6653 CLK– Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fIN) due to jitter (tJ) can be calculated by SNR = −20 log 2πf IN × t J 0.1µF 39kΩ Figure 61. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS) VCC CLOCK INPUT 0.1µF 50Ω 1kΩ 1kΩ 0.1µF [ ] CMOS DRIVER AD951x OPTIONAL 0.1µF 100Ω CLK+ ADC AD6653 CLK– 06708-063 In the equation, the rms aperture jitter represents the root mean square of all jitter sources, which include the clock input, the analog input signal, and the ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, as shown in Figure 63. Figure 62. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS) Rev. 0 | Page 28 of 80 AD6653 75 1.50 TOTAL POWER 70 MEASURED 65 SNR (dBc) TOTAL POWER (W) 0.6 0.05ps 0.20ps 1.25 IAVDD 0.5 SUPPLY CURRENT (A) SUPPLY CURRENT (A) 06708-066 06708-065 1.00 0.4 60 0.50ps 0.75 IDVDD 0.3 55 1.00ps 1.50ps 2.00ps 2.50ps 3.00ps 1 10 100 1000 06708-064 0.50 0.2 50 0.25 IDRVDD 0 0 25 50 75 100 125 0.1 45 0 150 INPUT FREQUENCY (MHz) SAMPLE RATE (MSPS) Figure 63. SNR vs. Input Frequency and Jitter Figure 64. AD6653-150 Power and Current vs. Sample Rate 1.50 0.6 TOTAL POWER (W) The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD6653. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. Refer to Application Note AN-501 and Application Note AN-756 for more information about jitter performance as it relates to ADCs (see www.analog.com). 1.25 TOTAL POWER 1.00 IAVDD 0.75 0.5 0.4 0.3 0.50 IDVDD 0.25 IDRVDD 0 25 50 75 100 SAMPLE RATE (MSPS) 0.2 0.1 POWER DISSIPATION AND STANDBY MODE As shown in Figure 64 and Figure 65, the power dissipated by the AD6653 is proportional to its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (IDRVDD) can be calculated by IDRVDD = VDRVDD × fCLK × N where N is the number of output bits (26, in the case of the AD6653, assuming the FD bits are inactive). This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 64 and Figure 65 was taken using the same operating conditions as those used for the Typical Performance Characteristics, with a 5 pF load on each output driver. 0 0 125 Figure 65. AD6653-125 Power and Current vs. Sample Rate By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD6653 is placed in power-down mode. In this state, the ADC typically dissipates 2.5 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD6653 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage level. PDWN can be driven with 1.8 V logic, even when DRVDD is at 3.3 V. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. Rev. 0 | Page 29 of 80 AD6653 When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map Register Description section and Application Note AN-877, Interfacing to High Speed ADCs via SPI at www.analog.com for additional details. If the SMI SDO/OEB pin is low, the output data drivers are enabled. If the SMI SDO/OEB pin is high, the output data drivers are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. When using the SPI interface, the data and fast detect outputs of each channel can be independently three-stated by using the output enable bar bit, Bit 4 in Register 0x14. DIGITAL OUTPUTS The AD6653 output drivers can be configured to interface with 1.8 V to 3.3 V CMOS logic families by matching DRVDD to the digital supply of the interfaced logic. Alternatively, the AD6653 outputs can be configured for either ANSI LVDS or reduced drive LVDS using a 1.8 V DRVDD supply. In CMOS output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. The output data format can be selected for either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 12). As detailed in Application Note AN-877, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. Table 12. SCLK/DFS Mode Selection (External Pin Mode) Voltage at Pin AGND (default) AVDD SCLK/DFS Offset binary Twos complement SDIO/DCS DCS disabled DCS enabled Interleaved CMOS Mode Setting Bit 5 in Register 0x14 enables interleaved CMOS output mode. In this mode, output data is routed through Port A with the ADC Channel A output data present on the rising edge of DCO and the ADC Channel B output data present on the falling edge of DCO. Timing The AD6653 provides latched data with a pipeline delay that is dependent on which of the digital back end features are enabled. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD6653. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD6653 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance may degrade. Data Clock Output (DCO) The AD6653 also provides data clock output (DCO) intended for capturing the data in an external register. Figure 2 through Figure 6 show a graphical timing description of the AD6653 output modes. Digital Output Enable Function (OEB) The AD6653 has a flexible, three-state ability for the digital output pins. The three-state modeis enabled using the SMI SDO/OEB pin or through the SPI interface. Table 13. Output Data Format Input (V) VIN+ – VIN− VIN+ – VIN− VIN+ – VIN− VIN+ – VIN− VIN+ − VIN− Condition (V) < −VREF − 0.5 LSB = −VREF =0 = +VREF − 1.0 LSB > +VREF − 0.5 LSB Offset Binary Output Mode 0000 0000 0000 0000 0000 0000 1000 0000 0000 1111 1111 1111 1111 1111 1111 Twos Complement Mode 1000 0000 0000 1000 0000 0000 0000 0000 0000 0111 1111 1111 0111 1111 1111 OR 1 0 0 0 1 Rev. 0 | Page 30 of 80 AD6653 DIGITAL DOWNCONVERTER The AD6653 includes a digital processing section that provides filtering and reduces the output data rate. This digital processing section includes a numerically controlled oscillator (NCO), a half-band decimating filter, an FIR filter, and a second coarse NCO (fADC/8 fixed value) for output frequency translation. Each of these processing blocks (except the decimating half-band filter) has control lines that allow it to be independently enabled and disabled to provide the desired processing function. The digital downconverter can be configured to output either real data or complex output data. These blocks can be configured in five recommended combinations to implement different signal processing functions. a maximum usable bandwidth of 16.5 MHz when using the filter in real mode (NCO bypassed) or a maximum usable bandwidth of 33.0 MHz when using the filter in the complex mode (NCO enabled). The optional fixed-coefficient FIR filter provides additional filtering capability to sharpen the half-band roll-off to enhance the alias protection. It removes the negative frequency images to avoid aliasing negative frequencies for real outputs. fADC/8 FIXED-FREQUENCY NCO A fixed fADC/8 NCO is provided to translate the filtered, decimated signal from dc to fADC/8 to allow a real output. Figure 66 to Figure 69 show an example of a 20 MHz input as it is processed by the blocks of the AD6653. DOWNCONVERTER MODES Table 14 details the recommended downconverter modes of operation in the AD6653. Mode 1 2 3 4 5 NCO/Filter Half-band filter only Half-band filter and FIR filter NCO and half-band filter NCO, half-band filter, and FIR filter NCO, half-band filter, FIR filter, and fADC/8 NCO Output Type Real Real Complex Complex Real –50 –24 –14 –4 0 4 14 24 50 Figure 66. Example AD6653 Real 20 MHz Bandwidth Input Signal Centered at 14 MHz (fADC = 100 MHz) NUMERICALLY CONTROLLED OSCILLATOR (NCO) Frequency translation is accomplished with an NCO. Each of the two processing channels shares a common NCO. Amplitude and phase dither can be enabled on chip to improve the noise and spurious performance of the NCO. A phase offset word is available to create a known phase relationship between multiple AD6653s. Because the decimation filter prevents usage of half the Nyquist spectrum, a means is needed to translate the sampled input spectrum into the usable range of the decimation filter. To achieve this, a 32-bit, fine tuning, complex NCO is provided. This NCO/mixer allows the input spectrum to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing. –50 –38 –28 –18 –10 0 10 50 Figure 67. Example AD6653 20 MHz Bandwidth Input Signal Tuned to DC Using the NCO (NCO Frequency = 14 MHz) –50 –38 –28 –18 –10 0 10 50 Figure 68. Example AD6653 20 MHz Bandwidth Input Signal with the Negative Image Filtered by the Half-Band and FIR Filters HALF-BAND DECIMATING FILTER AND FIR FILTER The goal of the AD6653 digital filter block is to allow the sample rate to be reduced by a factor of 2 while rejecting aliases that fall into the band of interest. The half-band filter is designed to operate as either a low-pass or high-pass filter and to provide greater than 100 dB of alias protection for 22% of the input rate of the structure. For an ADC sample rate of 150 MSPS, this provides 06708-070 –50 0.25 12.5 22.5 50 Figure 69. Example AD6653 20 MHz Bandwidth Input Signal Tuned to fADC/8 for Real Output Rev. 0 | Page 31 of 80 06708-069 06708-068 06708-067 Table 14. Downconverter Modes AD6653 NUMERICALLY CONTROLLED OSCILLATOR (NCO) FREQUENCY TRANSLATION This processing stage comprises a digital tuner consisting of a 32-bit complex numerically controlled oscillator (NCO). The two channels of the AD6653 share a single NCO. The NCO is optional and can be bypassed by clearing Bit 0 of Register 0x11D. This NCO block accepts a real input from the ADC stage and outputs a frequency translated complex (I and Q) output. The NCO frequency is programmed in Register 0x11E, Register 0x11F, Register 0x120, and Register 0x121. These four 8-bit registers make up a 32-bit unsigned frequency programming word. Frequencies between −CLK/2 and +CLK/2 are represented using the following frequency words: • • • PHASE OFFSET The NCO phase offset register at Address 0x122 and Address 0x123 adds a programmable offset to the phase accumulator of the NCO. This 16-bit register is interpreted as a 16-bit unsigned integer. A 0x00 in this register corresponds to no offset, and a 0xFFFF corresponds to an offset of 359.995°. Each bit represents a phase change of 0.005°. This register allows multiple NCOs to be synchronized to produce outputs with predictable phase differences. Use the following equation to calculate the NCO phase offset value: NCO_PHASE = 216 × PHASE/360 where: NCO_PHASE is a decimal number equal to the 16-bit binary number to be programmed at Register 0x122 and Register 0x123. PHASE is the desired NCO phase in degrees. 0x8000 0000 represents a frequency given by −CLK/2. 0x0000 0000 represents dc (frequency = 0 Hz). 0x7FFF FFFF represents CLK/2 − CLK/232. Use the following equation to calculate the NCO frequency: NCO AMPLITUDE AND PHASE DITHER The NCO block contains amplitude and phase dither to improve the spurious performance. Amplitude dither improves performance by randomizing the amplitude quantization errors within the angular-to-Cartesian conversion of the NCO. This option reduces spurs at the expense of a slightly raised noise floor. With amplitude dither enabled, the NCO has an SNR of >93 dB and an SFDR of >115 dB. With amplitude dither disabled, the SNR is increased to >96 dB at the cost of SFDR performance, which is reduced to 100 dB. The NCO amplitude dither is recommended and is enabled by setting Bit 1 of Register 0x11D. NCO_FREQ = 2 × 32 Mod( f , f CLK ) f CLK where: NCO_FREQ is a 32-bit twos complement number representing the NCO frequency register. f is the desired carrier frequency in hertz (Hz). fCLK is the AD6653 ADC clock rate in hertz (Hz). NCO SYNCHRONIZATION The AD6653 NCOs within a single part or across multiple parts can be synchronized using the external SYNC input. Bit 3 and Bit 4 of Register 0x100 allow the NCO to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the NCO to restart at the programmed phase offset value. Rev. 0 | Page 32 of 80 AD6653 DECIMATING HALF-BAND FILTER AND FIR FILTER The goal of the AD6653 half-band digital filter is to allow the sample rate to be reduced by a factor of 2 while rejecting aliases that fall into the band of interest. This filter is designed to operate as either a low-pass or a high-pass filter and to provide >100 dB of alias protection for 11% of the input rate of the structure. Used in conjunction with the NCO and the FIR filter, the halfband filter can provide an effective band-pass. For an ADC sample rate of 150 MSPS, this provides a maximum usable bandwidth of 33 MHz. 0 –10 –20 –30 AMPLITUDE (dBc) –40 –50 –60 –70 –80 –90 –100 0 0.1 0.2 0.3 0.4 06708-072 HALF-BAND FILTER COEFFICIENTS The 19-tap, symmetrical, fixed-coefficient half-band filter has low power consumption due to its polyphase implementation. Table 15 lists the coefficients of the half-band filter. The normalized coefficients used in the implementation and the decimal equivalent value of the coefficients are also listed. Coefficients not listed in Table 15 are 0s. Table 15. Fixed Coefficients for Half-Band Filter Coefficient Number C0, C18 C2, C16 C4, C14 C6, C12 C8, C10 C9 Normalized Coefficient 0.0008049 −0.0059023 0.0239182 −0.0755024 0.3066864 0.5 Decimal Coefficient (20-Bit) 844 −6189 25080 −79170 321584 524287 –110 FRACTION OF INPUT SAMPLE RATE Figure 71. Half-Band Filter, High-Pass Response The half-band filter has a ripple of 0.000182 dB and a rejection of 100 dB. For an alias rejection of 100 dB, the alias protected bandwidth is 11% of the input sample rate. If both the I and the Q paths are used, a complex bandwidth of 22% of the input rate is available. In the event of even Nyquist zone sampling, the half-band filter can be configured to provide a spectral reversal. Setting Bit 2 high in Address 0x103 enables the spectral reversal feature. The half-band decimation phase can be selected such that the half-band filter starts on the first or second sample following synchronization. This shifts the output from the half-band between the two input sample clocks. The decimation phase can be set to 0 or 1, using Bit 3 of Register 0x103. HALF-BAND FILTER FEATURES In the AD6653, the half-band filter cannot be disabled. The filter can be set for a low-pass or high-pass response. For a highpass filter, Bit 1 of Register 0x103 should be set; for a low-pass response, this bit should be cleared. The low-pass response of the filter with respect to the normalized output rate is shown in Figure 70, and the high-pass response is shown in Figure 71. 0 –10 –20 –30 AMPLITUDE (dBc) –40 –50 –60 –70 –80 –90 –100 0 0.1 0.2 0.3 0.4 06708-071 FIXED-COEFFICIENT FIR FILTER Following the half-band filters is a 66-tap, fixed-coefficient FIR filter. This filter is useful in providing extra alias protection for the decimating half-band filter. It is a simple sum-of-products FIR filter with 66 filter taps and 21-bit fixed coefficients. Note that this filter does not decimate. The normalized coefficients used in the implementation and the decimal equivalent value of the coefficients are listed in Table 16. The user can either select or bypass this filter, but the FIR filter can be enabled only when the half-band filter is enabled. Writing Logic 0 to the enable FIR filter bit (Bit 0) in Register 0x102 bypasses this fixed-coefficient filter. The filter is necessary when using the final NCO with a real output; bypassing it when using other configurations results in power savings. –110 FRACTION OF INPUT SAMPLE RATE Figure 70. Half-Band Filter, Low-Pass Response Rev. 0 | Page 33 of 80 AD6653 Table 16. FIR Filter Coefficients Coefficient Number C0, C65 C1, C64 C2, C63 C3, C62 C4, C61 C5, C60 C6, C59 C7, C58 C8, C57 C9, C56 C10, C55 C11, C54 C12, C53 C13, C52 C14, C51 C15, C50 C16, C49 C17, C48 C18, C47 C19, C46 C20, C45 C21, C44 C22, C43 C23, C42 C24, C41 C25, C40 C26, C39 C27, C38 C28, C37 C29, C36 C30, C35 C31, C34 C32, C33 Normalized Coefficient 0.0001826 0.0006824 0.0009298 0.0000458 −0.0012689 −0.0008345 0.0011806 0.0011387 −0.0018439 −0.0024557 0.0018063 0.0035825 −0.0021510 −0.0056810 0.0017405 0.0078602 −0.0013437 −0.0110626 −0.0000229 0.0146618 0.0018959 −0.0195594 −0.0053153 0.0255623 0.0104036 −0.0341468 −0.0192165 0.0471258 0.0354118 −0.0728111 −0.0768890 0.1607208 0.4396725 Decimal Coefficient (21-Bit) 383 1431 1950 96 −2661 −1750 2476 2388 −3867 −5150 3788 7513 −4511 −11914 3650 16484 −2818 −23200 −48 30748 3976 −41019 −11147 53608 21818 −71611 −40300 98830 74264 −152696 −161248 337056 922060 COMBINED FILTER PERFORMANCE The combined response of the half-band filter and the FIR filter is shown in Figure 72. The act of bandlimiting the ADC data with the half-band filter ideally provides a 3 dB improvement in the SNR at the expense of the sample rate and available bandwidth of the output data. As a consequence of finite math, additional quantization noise is added to the system due to truncation in the NCO and half-band. As a consequence of the digital filter rejection of out-of-band noise (assuming no quantization in the filters and with a white noise floor from the ADC), there should be a 3.16 dB improvement in the ADC SNR. However, the added quantization lessens improvement to about 2.66 dB. 0 –10 –20 –30 AMPLITUDE (dBc) –40 –50 –60 –70 –80 –90 –100 0 0.1 0.2 0.3 0.4 06708-073 –110 FRACTION OF INPUT SAMPLE RATE Figure 72. Half-Band Filter and FIR Filter Composite Response FINAL NCO The output of the 32-bit fine tuning NCO is complex and typically centered in frequency around dc. This complex output is carried through the stages of the half-band and FIR filters to provide proper antialiasing filtering. The final NCO provides a means to move this complex output signal away from dc so that a real output can be provided from the AD6653. The final NCO, if enabled, translates the output from dc to a frequency equal to the ADC sampling frequency divided by 8 (fADC/8). This provides the user a decimated output signal centered at fADC/8 in frequency. Optionally, this final NCO can be bypassed, and the dc-centered I and Q values can be output in an interleaved fashion. SYNCHRONIZATION The AD6653 half-band filters within a single part or across multiple parts can be synchronized using the external SYNC input. Bit 5 and Bit 6 of Register 0x100 allow the half-bands to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the half-band filter to restart at the programmed decimation phase value. Rev. 0 | Page 34 of 80 AD6653 ADC OVERRANGE AND GAIN CONTROL In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides after-the-fact information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, latency of this function is of major concern. Highly pipelined converters can have significant latency. A good compromise is to use the output bits from the first stage of the ADC for this function. Latency for these output bits is very low, and overall resolution is not highly significant. Peak input signals are typically between full scale and 6 dB to 10 dB below full scale. A 3-bit or 4-bit output provides adequate range and resolution for this function. Using the SPI port, the user can provide a threshold above which an overrange output is active. As long as the signal is below that threshold, the output should remain low. The fast detect outputs can also be programmed via the SPI port so that one of the pins functions as a traditional overrange pin for customers who currently use this feature. In this mode, all 14 bits of the converter are examined in the traditional manner, and the output is high for the condition normally defined as overflow. In either mode, the magnitude of the data is considered in the calculation of the condition (but the sign of the data is not considered). The threshold detection responds identically to positive and negative signals outside the desired range (magnitude). Table 17. Fast Detect Mode Select Bit Settings Fast Detect Mode Select Bits (Register 0x104[3:1]) 000 001 010 Information Presented on Fast Detect (FD) Pins of Each ADC1, 2 FD[3] FD[2] FD[1] FD[0] ADC fast magnitude (see Table 18) OR ADC fast magnitude (see Table 19) OR F_LT ADC fast magnitude (see Table 20) C_UT F_LT ADC fast magnitude (see Table 20) OR C_UT F_UT F_LT OR F_UT IG DG 011 100 101 1 The fast detect pins are FD0A/FD0B to FD3A/FD3B for the CMOS mode configuration and FD0+/FD0− to FD3+/FD3− for the LVDS mode configuration. 2 See the ADC Overrange (OR) and Gain Switching sections for more information about OR, C_UT, F_UT, F_LT, IG, and DG. ADC FAST MAGNITUDE When the fast detect output pins are configured to output the ADC fast magnitude (that is, when the fast detect mode select bits are set to 0b000), the information presented is the ADC level from an early converter stage with a latency of only two clock cycles in CMOS output modes. In LVDS output mode, the fast detect bits have a latency of six cycles in all fast detect modes. Using the fast detect output pins in this configuration provides the earliest possible level indication information. Because this information is provided early in the datapath, there is significant uncertainty in the level indicated. The nominal levels, along with the uncertainty indicated by the ADC fast magnitude, are shown in Table 18. Because the DCO is at one-half the sample rate, the user can obtain the fast detect information by sampling the fast detect outputs on both the rising and falling edges of DCO (see Figure 2 for timing information). Table 18. ADC Fast Magnitude Nomimal Levels with Fast Detect Mode Select Bits = 000 ADC Fast Magitude on FD[3:0] Pins 0000 0001 0010 0011 0100 0101 0110 0111 1000 Nominal Input Magnitude Below FS (dB)