AD679AD

a FEATURES AC and DC Characterized and Specified (K, B, T Grades) 128k Conversions per Second 1 MHz Full Power Bandwidth 500 kHz Full Linear Bandwidth 78 dB S/N+D (K, B, T Grades) Twos Complement Data Format (Bipolar Mode) Straight Binary Data Format (Unipolar Mode) 10 M
Input Impedance 8-Bit Bus Interface On-Board Reference and Clock 10 V Unipolar or Bipolar Input Range Pin Compatible with AD678 12-Bit, 200 kSPS ADC MIL-STD-883 Compliant Versions Available 14-Bit 128 kSPS Complete Sampling ADC AD679 FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD679 is a complete, multipurpose 14-bit monolithic analog-to-digital converter, consisting of a sample-and-hold amplifier (SHA), a microprocessor-compatible bus interface, a voltage reference, and clock generation circuitry. 1. COMPLETE INTEGRATION: The AD679 minimizes external component requirements by combining a high speed sample-and-hold amplifier (SHA), ADC, 5 V reference, clock, and digital interface on a single chip. This provides a fully specified sampling A/D function unattainable with discrete designs. The AD679 is specified for ac (or dynamic) parameters such as S/N+D ratio, THD, and IMD, which are important in signal processing applications. In addition, the AD679K, B, and T grades are fully specified for dc parameters that are important in measurement applications. The 14 data bits are accessed in two read operations (8 + 6), with left justification. Data format is straight binary for unipolar mode and twos complement binary for bipolar mode. The input has a full-scale range of 10 V with a full power bandwidth of 1 MHz and a full linear bandwidth of 500 kHz. High input impedance (10 MΩ) allows direct connection to unbuffered sources without signal degradation. Conversions can be initiated either under microprocessor control or by an external clock asynchronous to the system clock. 2. SPECIFICATIONS: The AD679K, B, and T grades provide fully specified and tested ac and dc parameters. The AD679J, A, and S grades are specified and tested for ac parameters; dc accuracy specifications are shown as typicals. DC specifications (such as INL, gain, and offset) are important in control and measurement applications. AC specifications (such as S/N+D ratio, THD, and IMD) are of value in signal processing applications. 3. EASE OF USE: The pinout is designed for easy board layout, and the two-read output provides compatibility with 8-bit buses. Factory trimming eliminates the need for calibration modes or external trimming to achieve rated performance. This product is fabricated on Analog Devices’ BiMOS process, combining low power CMOS logic with high precision, low noise bipolar circuits; laser-trimmed thin-film resistors provide high accuracy. The converter utilizes a recursive subranging algorithm that includes error correction and flash converter circuitry to achieve high speed and resolution. 4. RELIABILITY: The AD679 utilizes Analog Devices’ monolithic BiMOS technology. This ensures long-term reliability compared to multichip and hybrid designs. The AD679 operates from +5 V and ±12 V supplies and dissipates 560 mW (typ). The part is available in 28-lead plastic DIP, ceramic DIP, and 44 J-leaded ceramic surface-mount packages. 6. The AD679 is available in versions compliant with MILSTD-883. Refer to the Analog Devices Military Products Databook or current AD679/883B data sheet for detailed specifications. 5. UPGRADE PATH: The AD679 provides the same pinout as the 12-bit, 200 kSPS AD678 ADC. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. AD679–SPECIFICATIONS (T to T , V = +12 V  5%, V MIN MAX CC AC SPECIFICATIONS unless otherwise noted) EE 1 Parameter = –12 V  5%, VDD = +5 V  10%, fSAMPLE = 128 kSPS, fIN = 10.009 kHz, Min AD679J/A/S Typ Max Min AD679K/B/T Typ Max Unit 2 SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO –0.5 dB Input (Referred to –0 dB Input) –20 dB Input (Referred to –20 dB Input) –60 dB Input (Referred to –60 dB Input) 76 58 18 TOTAL HARMONIC DISTORTION (THD)3 @ 25°C 79 59 19 78 60 20 81 61 21 dB dB dB –90 0.003 –88 0.004 –82 0.006 –82 0.008 –90 0.003 –88 0.004 –82 0.006 –82 0.008 dB % dB % PEAK SPURIOUS OR PEAK HARMONIC COMPONENT –90 –82 –90 –82 dB FULL POWER BANDWIDTH 1 TMIN to TMAX FULL LINEAR BANDWIDTH 1 500 MHz 500 kHz 4 INTERMODULATION DISTORTION (IMD) 2nd Order Products 3rd Order Products –90 –90 –82 –82 –90 –90 –82 –82 dB dB NOTES 1 flN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal unless otherwise noted. 2 See TPC 3 for higher frequencies and other input amplitudes. 3 See TPCs 1 and 2 for higher frequencies and other input amplitudes. 4 fA = 9.08 kHz, fB = 9.58 kHz, with fSAMPLE 100 kSPS. See Definition of Specifications section. Specifications subject to change without notice. DIGITAL SPECIFICATIONS (All device types T Parameter LOGIC INPUTS VIH High Level Input Voltage Low Level Input Voltage VIL High Level Input Current IIH IIL Low Level Input Current CIN Input Capacitance LOGIC OUTPUTS VOH High Level Output Voltage VOL IOZ COZ Low Level Output Voltage High Z Leakage Current High Z Output Capacitance MIN to TMAX, VCC = +12 V  5%, VEE = –12 V  5%, VDD = +5 V  10%) Test Conditions Min Max Unit VIN = 5 V VIN = 0 V 2.0 0 –10 –10 VDD 0.8 +10 +10 10 V V µA µA pF 0.4 +10 10 V V V µA pF IOH = 0.1 mA IOH = 0.5 mA IOL = 1.6 mA VIN = 0 or 5 V 4.0 2.4 –10 NOTES 1 flN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal unless otherwise noted. 2 See TPC 3 for higher frequencies and other input amplitudes. 3 See TPCs 1 and 2 for higher frequencies and other input amplitudes. 4 fA = 9.08 kHz, fB = 9.58 kHz, with fSAMPLE 100 kSPS. See Definition of Specifications section. Specifications subject to change without notice. –2– REV. D AD679 DC SPECIFICATIONS (TMIN to TMAX, VCC = +12 V  5%, VEE = –12 V  5%, VDD = +5 V  10%, unless otherwise noted) Parameter Min TEMPERATURE RANGE J, K Grades A, B Grades S, T Grades 0 –40 –55 ACCURACY Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Unipolar Zero Error1 (@ 25°C) Bipolar Zero Error1 (@ 25°C) Gain Error1, 3 (@ 25°C) Temperature Drift Unipolar Zero4 J, K Grades A, B Grades S, T Grades Bipolar Zero4 J, K Grades A, B Grades S, T Grades Gain4 J, K Grades A, B Grades S, T Grades Gain5 J, K Grades A, B Grades S, T Grades ANALOG INPUT Input Ranges Unipolar Mode Bipolar Mode Input Resistance Input Capacitance Input Settling Time Aperture Delay Aperture Jitter INTERNAL VOLTAGE REFERENCE Output Voltage6 External Load Unipolar Mode Bipolar Mode POWER SUPPLIES Power Supply Rejection VCC = +12 V ± 5% VEE = –12 V ± 5% VDD = +5 V ± 10% Operating Current ICC IEE IDD Power Consumption AD679J/A/S Typ Max Min 70 +85 +125 0 –40 –55 14 AD679K/B/T Typ Max Unit 70 +85 +125 °C °C °C 14 1 2.5 0.08 0.08 0.12 0.05 0.05 0.09 0.07 0.07 0.11 Bits LSB Bits % FSR2 % FSR % FSR 0.04 0.05 0.09 0.04 0.05 0.09 0.05 0.07 0.10 % FSR % FSR % FSR 0.02 0.04 0.08 0.02 0.04 0.08 0.04 0.05 0.09 % FSR % FSR % FSR 0.09 0.10 0.20 0.09 0.10 0.20 0.11 0.16 0.25 % FSR % FSR % FSR 0.04 0.05 0.09 0.04 0.05 0.09 0.05 0.07 0.10 % FSR % FSR % FSR +10 +5 V V MΩ pF µs ns ps 2 14 14 0 –5 +10 +5 0 –5 10 10 10 10 1.5 1.5 10 150 10 150 4.98 5.02 4.98 1.5 0.5 6 6 6 18 25 8 560 20 34 12 745 18 25 8 560 5.02 V 1.5 0.5 mA mA 6 6 6 LSB LSB LSB 20 34 12 745 mA mA mA mW NOTES 1 Adjustable to zero. See Figures 5 and 6. 2 % FSR = percent of full-scale range. 3 Includes internal voltage reference error. 4 Includes internal voltage reference drift. 5 Excludes internal voltage reference drift. 6 With maximum external load applied. Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at T MIN, 25°C and TMAX. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested. Specifications subject to change without notice. REV. D –3– AD679 TIMING SPECIFICATIONS (All device types TMIN to TMAX, VCC = +12 V  5%, VEE = –12 V  5%, VDD = +5 V  10%) Parameter Symbol Min SC Delay Conversion Time Conversion Rate1 Convert Pulse Width Aperture Delay Status Delay Access Time2, 3 tSC tC tCR tCP tAD tSD tBA 50 Float Delay5 Output Delay Format Setup OE Delay Read Pulse Width Conversion Delay EOCEN Delay tFD tOD tFS tOE tRP tCD tEO Max Unit ns µs µs µs ns ns ns ns ns ns ns ns ns ns ns 6.3 7.8 3.0 20 400 100 574 80 0 0.097 5 0 10 10 10 100 20 195 400 50 NOTES 1 Includes acquisition time. 2 Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the data lines/EOC cross 2.0 V or 0.8 V. See Figure 4. 3 COUT = 100 pF. 4 COUT = 50 pF. 5 Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the output voltage changes by 0.5. See Figure 4; COUT = 10 pF. Specifications subject to change without notice. NOTE 1EOC IS A THREE-STATE OUTPUT IN SYNCHRONOUS MODE AND AN OPEN DRAIN OUTPUT IN ASYNCHRONOUS. ACCESS (tBA) AND FLOAT (tFD) TIMING SPECIFICATIONS DO NOT APPLY IN ASYNCHRONOUS MODE WHERE THEY ARE A FUNCTION OF THE TIME CONSTANT FORMED BY THE 10pF OUTPUT CAPACITANCE AND THE PULL-UP RESISTOR. Figure 3. EOC Timing NOTES 1IN ASYNCHRONOUS MODE, STATE OF CS DOES NOT AFFECT OPERATION. SEE THE START CONVERSION TRUTH TABLE FOR DETAILS. 2EOCEN = LOW (SEE FIGURE 3). IN SYNCHRONOUS MODE, EOC IS A THREESTATE OUTPUT. IN ASYNCHRONOUS MODE, EOC IS AN OPEN DRAIN OUTPUT. 3DATA SHOULD NOT BE ENABLED DURING A CONVERSION. TEST VCP COUT ACCESS TIME HIGH Z TO LOGIC LOW 5V FLOAT TIME LOGIC HIGH TO HIGH Z ACCESS TIME HIGH Z TO LOGIC HIGH FLOAT TIME LOGIC LOW TO HIGH Z 100pF 0V 0V 5V 10pF 100pF 10pF Figure 1. Conversion Timing IOL DOUT VCP COUT IOH Figure 4. Load Circuit for Bus Timing Specifications Figure 2. Output Timing –4– REV. D AD679 ABSOLUTE MAXIMUM RATINGS 1 Specification VCC VEE VCC2 VDD AGND AIN, REFIN Digital Inputs Digital Outputs Max Junction Temperature With Respect To Min Max Unit Specification AGND AGND VEE DGND DGND AGND DGND DGND –0.3 –18 –0.3 0 –1 VEE –0.5 –0.5 +18 +0.3 +26.4 +7 +1 VCC +7 VDD + 0.3 V V V V V V V V Operating Temperature J and K Grades A and B Grades S and T Grades Storage Temperature Lead Temperature (10 sec max) 175 With Respect To Min Max Unit 0 –40 –55 –65 70 +85 +125 +150 °C °C °C °C 300 °C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 The AD679 is not designed to operate from ⫾15 V supplies. °C ORDERING GUIDE1 Model Package Temperature Range Tested and Specified Package Option2 AD679JN AD679KN AD679JD AD679KD AD679AD AD679BD AD679SD AD679TD AD679AJ AD679BJ AD679SD/883B3 28-Pin Plastic DIP 28-Pin Plastic DIP 28-Pin Ceramic DIP 28-Pin Ceramic DIP 28-Pin Ceramic DIP 28-Pin Ceramic DIP 28-Pin Ceramic DIP 28-Pin Ceramic DIP 44-Lead Ceramic JLCC 44-Lead Ceramic JLCC 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –55°C to +125°C –40°C to +85°C –40°C to +85°C AC AC + DC AC AC + DC AC AC + DC AC AC + DC AC AC + DC N-28 N-28 D-28 D-28 D-28 D-28 D-28 D-28 J-44 J-44 NOTES 1 For parallel read (14-bits) interface to 16-bit buses, see AD779. 2 N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier. 3 For details, grade, and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or the current AD679/883B data sheet. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD679 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. D –5– AD679 PIN CONFIGURATIONS EOC SC 3 26 DB7 CS 4 25 DB6 VEE 6 5 4 2 44 43 42 41 40 3 1 EOC NC DB7 VDD 27 NC VDD 28 2 NC EOCEN 1 OE CS SC EOCEN NC OE JLCC Package DIP Package PIN 1 IDENTIFIER NC 7 VEE 8 39 38 5 24 DB5 NC 9 37 AIN 6 23 DB4 AIN 10 36 TOP VIEW 22 DB3 REFOUT 8 (Not to Scale) 21 DB2 AGND 11 REFOUT 12 NC 13 REFIN 14 18 DGND DGND 12 17 DGND SYNC 13 16 DGND DGND 14 15 HBE DB1 NC BIPOFF 15 31 DB0 NC 16 VCC 17 30 NC NC 33 29 18 19 20 21 22 23 24 25 26 27 28 NC VCC 11 32 NC DB0 34 HBE NC NC DB1 19 35 DGND 20 NC NC REFIN 9 BIPOFF 10 AD679 TOP VIEW (Not to Scale) NC SYNC NC AD679 AGND 7 DB6 NC DB5 DB4 DB3 DB2 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS 28-Lead DIP Mnemonic Pin No. 44-Lead JLCC Pin No. Type Name and Function AGND AIN BIPOFF 7 6 10 11 10 15 P AI AI CS DGND DB7–DB0 4 12, 14 26–19 DI P DO EOC 27 6 23 40, 39, 37, 36, 35, 34, 33, 31 42 Analog Ground. This is the ground return for AIN only. Analog Signal Input. Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight binary output coding. Connect to REFOUT for ⫾5 V input bipolar mode and twos complement binary output coding. Chip Select. Active LOW. Digital Ground. Data Bits. These pins provide all 14 bits in two bytes (8 + 6 bits). Active HIGH. EOCEN HBE 1 15 1 25 DI DI OE with REFIN REFOUT SC SYNC 2 3 DI 9 8 3 13 14 12 5 21 AI AO DI DI VCC VEE VDD — — 11 5 28 16 17–18 17 8 43 P P P U U 2, 4, 7, 9, 13, 16, 18, 19, 20, 22, 24, 26, 27, 28, 29, 30, 32, 38, 41, 44 DO End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the conversion finishes. In asynchronous mode, EOC is an open-drain output and requires an external 3 kΩ pull-up resistor. See EOCEN and SYNC pins for information on EOC gating. End-of-Convert Enable. Enables EOC pin. Active LOW. High Byte Enable. If LOW, output contains high byte. If HIGH, output contains low byte (corresponding to the most recently read high byte). Output Enable. A down-going transition on OE enables DB7 to DB0. Gated CS. Active LOW. Reference Input. 5 V input gives 10 V full-scale range. 5 V Reference Output. Tied to REFIN for normal operation. Start Convert. Active LOW. See SYNC pin for gating. SYNC Control. If tied to VDD (synchronous mode), SC and EOCEN are gated by CS. If tied to DGND (asynchronous mode), SC and EOCEN are independent of CS, and EOC is an open-drain output. EOC requires an external 3 kΩ pull-up resistor in asynchronous mode. 12 V Analog Power. –12 V Analog Power. 5 V Digital Power. Tie to DGND. These pins are unused and should be connected to DGND or VDD. Type: AI = Analog Input. AO = Analog Output. DI = Digital Input (TTL and 5 V CMOS compatible). DO = Digital Output (TTL and 5 V CMOS compatible). All DO pins are three-state drivers. P = Power. U = Unused. –6– REV. D AD679 DEFINITIONS OF SPECIFICATIONS Nyquist Frequency Aperture Jitter Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. An implication of the Nyquist sampling theorem, the Nyquist frequency of a converter is the input frequency that is one-half the sampling frequency of the converter. Input Setting Time Settling time is a function of the SHA’s ability to track fast slewing signals. This is specified as the maximum time required in track mode after a full-scale step input to guarantee rated conversion accuracy. Signal-to-Noise and Distortion (S/N+D) Ratio S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Differential Nonlinearity (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential linearity is the deviation from this ideal value. It is often specified in terms of resolution for which no missing codes (NMC) are guaranteed. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of a full-scale input signal and is expressed as a percentage or in decibels. For input signals or harmonics above the Nyquist frequency, the aliased component is used. Integral Nonlinearity (INL) The ideal transfer function for a linear ADC is a straight line drawn between zero and full scale. The point used as zero occcurs 1/2 LSB before the first code transition. Full scale is defined as a level 1 1/2 LSB beyond the last code transition. Integral linearity error is the worst case deviation of a code from the straight line. The deviation of each code is measured from the middle of that code. Peak Spurious or Peak Harmonic Component The peak spurious or peak harmonic component is the largest spectral component excluding the input signal and dc. This value is expressed in decibels relative to the rms value of a fullscale input signal. Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m + n) at sum and difference frequencies of mfa ⫾ nfb, where m, n = 0, 1, 2, 3.... Intermodulation terms are those for which m or n is not equal to zero. For example, the second order terms are (fa + fb) and (fa – fb) and the third order terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distortion terms. The two signals applied to the converter are of equal amplitude, and the peak value of their sum is –0.5 dB from fullscale (9.44 V p-p). The IMD products are normalized to a 0 dB input signal. Note that the linearity error is not user adjustable. Power Supply Rejection Variations in power supply will affect the full-scale transition, but not the converter’s linearity. Power Supply Rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. Temperature Drift This is the maximum change in the parameter from the initial value (@ 25°C) to the value at TMIN or TMAX. Unipolar Zero Error In unipolar mode, the first transition should occur at a level 1/2 LSB above analog ground. Unipolar zero error is the deviation of the actual transition from that point. This error can be adjusted as discussed in the Input Connections and Calibration section. Bandwidth The full-power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input. Bipolar Zero Error The full-linear bandwidth is the input frequency at which the slew rate limit of the sample-and-hold amplifier (SHA) is reached. At this point, the amplitude of the reconstructed fundamental has degraded by less than –0.1 dB. Beyond this frequency, distortion of the sampled input signal increases significantly. In the bipolar mode, the major carry transition (11 1111 1111 1111 to 00 0000 0000 0000 ) should occur at an analog value 1/2 LSB below analog ground. Bipolar zero error is the deviation of the actual transition from that point. This error can be adjusted as discussed in the Input Connections and Calibration section. The AD679 has been designed to optimize input bandwidth, allowing it to undersample input signals with frequencies significantly above the converter’s Nyquist frequency. Gain Error The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale (9.9991 V for a 0 V to 10 V range, 4.9991 V for a ⫾5 V range). The gain error is the deviation of the actual level at the last transition from the ideal level with the zero error trimmed out. This error can be adjusted as shown in the Input Connections and Calibration section. Aperture Delay Aperture delay is a measure of the SHA’s performance and is measured from the falling edge of start convert (SC) to when the input signal is held for conversion. In synchronous mode, chip select (CS) should be LOW before SC to minimize aperture delay. REV. D –7– AMPLITUDE (dB) AMPLITUDE (dB) AD679 –Typical Performance Characteristics FREQUENCY (kHz) INPUT FREQUENCY (Hz) TPC 1. Harmonic Distortion vs. Input Frequency (–0.5 dB Input) THD (dB) AMPLITUDE (dB) TPC 4. 5-Plot Averaged 2048 Point FFT at 128 kSPS, fIN = 10.009 kHz INPUT FREQUENCY (Hz) FREQUENCY (kHz) TPC 2. Total Harmonic Distortion vs. Input Frequency and Amplitude S/(N+D) (dB) S/(N+D) (dB) TPC 5. Nonaveraged IMD Plot for fIN = 9.08 kHz (fa), 9.58 kHz (fb) at 128 kSPS INPUT FREQUENCY (Hz) RIPPLE FREQUENCY (kHz) TPC 3. S/(N+D) vs. Input Frequency and Amplitude TPC 6. Power Supply Rejection (fIN = 10 kHz, fSAMPLE = 128 kSPS, VRIPPLE = 0.1 V p-p) –8– REV. D AD679 CONVERSION CONTROL END-OF-CONVERT In synchronous mode (SYNC = HIGH), both chip select (CS) and start convert (SC) must be brought LOW to start a conversion. CS should be LOW tSC before SC is brought LOW. In asynchronous mode (SYNC = LOW), a conversion is started by bringing SC low, regardless of the state of CS. In asynchronous mode, end-of-convert (EOC) is an open-drain output (requiring a minimum 3 kΩ pull-up resistor) enabled by end-of-convert enable (EOCEN). In synchronous mode, EOC is a three-state output that is enabled by EOCEN and CS. See Table III. Access (tBA) and float (tFD) timing specifications do not apply in asynchronous mode where they are a function of the time constant formed by the external load capacitance and the pull-up resistor. Before a conversion is started, end-of-convert (EOC) is HIGH and the sample-and-hold is in track mode. After a conversion is started, the sample-and-hold goes into hold mode and EOC goes LOW, signifying that a conversion is in progress. During the conversion, the sample-and-hold will go back into track mode and start acquiring the next sample. OUTPUT ENABLE OPERATION The data bits (DB7–DB0) are three-state outputs that are enabled by chip select (CS) and output enable (OE). CS should be LOW tOE before OE is brought LOW. In track mode, the sample-and-hold will settle to ⫾0.003% (14 bits) in 1.5 µs maximum. The acquisition time does not affect the throughput rate as the AD679 goes back into track mode more than 2 µs before the next conversion. In multichannel systems, the input channel can be switched as soon as EOC goes LOW. When EOC goes HIGH, the conversion is completed and the output data may be read. The output is read in two steps as a 16-bit word, with the high byte read first, followed by the low byte. High byte enable (HBE) controls the output sequence. The 14-bit result is left justified within the 16-bit field. Bringing OE LOW tOE after CS goes LOW makes the output register contents available on the output data bits (DB7–DB0). A period of time, tCD, is required after OE is brought HIGH before the next SC instruction is issued. In unipolar mode (BIPOFF tied to AGND), the output coding is straight binary. In bipolar mode (BIPOFF tied to REFOUT), output coding is twos complement binary. If SC is held LOW, conversion accuracy may deteriorate. For this reason, SC should not be held low in an attempt to operate in a continuously converting mode. POWER-UP The AD679 typically requires 10 µs after power-up to reset internal logic. Table I. Start Conversion Truth Table SYNC Synchronous Mode Asynchronous Mode Inputs CS SC Table III. Conversion Status Truth Table Inputs Output SYNC CS EOCEN EOC Status 1 1 1 0 X f No Conversion Start Conversion Synchronous Mode 1 f 0 0 0 1 X 0 0 X 1 0 1 High Z High Z Converting Not Converting Either Either 1 0 0 Start Conversion (Not Recommended) Continuous Conversion (Not Recommended) 1 1 1 1 Asynchronous Mode* 0 0 0 X X X 1 f 0 No Conversion Start Conversion Continuous Conversion (Not Recommended) 0 0 0 X X X 0 0 1 0 High Z High Z Converting Not Converting Either 1 = HIGH voltage level. 0 = LOW voltage level. X = Don’t care. *EOC requires a pull-up resistor in asynchronous mode. 1 = HIGH voltage level. 0 = LOW voltage level. X = Don’t care. f = HIGH to LOW transition. Must stay low for t = t CP. Table IV. Output Enable Truth Table HBE Table II. 14-Bit Mode Coding Format (1 LSB = 0.61 mV) Unipolar Coding (Straight Binary) Bipolar Coding (Twos Complement) VIN* Output Code VIN* (V) Output Code 0.00000 V 5.00000 V 9.99939 V 000 . . . 0 100 . . . 0 111 . . . 1 –5.00000 –0.00061 0.00000 +2.50000 +4.99939 100 . . . 0 111 . . . 1 000 . . . 0 010 . . . 0 011 . . . 1 Unipolar or Bipolar Inputs (CS U OE) X 1 0 1 0 0 Outputs DB7 . . . DB0 ← High Z → a b c d e f g h i j k l m n 0 0 1 = HIGH voltage level. a = MSB. 0 = LOW voltage level. n = LSB. X = Don’t care. U = Logical OR. Data coding is binary for unipolar mode and twos complement binary for bipolar mode. *Code center. REV. D Status –9– AD679 INPUT CONNECTIONS AND CALIBRATION Unipolar Range Inputs The high (10 MΩ) input impedance of the AD679 eases the task of interfacing to high source impedances or multiplexer channel-to-channel mismatches of up to 300 Ω. The 10 V p-p full-scale input range accepts the majority of signal voltages without the need for voltage divider networks that could deteriorate the accuracy of the ADC. Offset and gain errors can be trimmed out by using the configuration shown in Figure 6. This circuit allows approximately ⫾25 mV of offset trim range (⫾40 LSB) and ⫾0.5% of gain trim range (⫾80 LSB). The AD679 is factory trimmed to minimize offset, gain, and linearity errors. In unipolar mode, the only external component that is required is a 50 Ω ⫾1% resistor. Two resistors are required in bipolar mode. If offset and gain are not critical (as in some ac applications), even these components can be eliminated. In some applications, offset and gain errors need to be trimmed out completely. The following sections describe the correct procedure for these various situations. The nominal offset is 1/2 LSB so that the analog range that corresponds to each code is centered in the middle of that code (halfway between the transitions to the codes above and below it). Thus the first transition (from 00 0000 0000 0000 to 00 0000 0000 0001) should nominally occur for an input level of +1/2 LSB (0.305 mV above ground for a 10 V range). To trim unipolar zero to this nominal value, apply a 0.305 mV signal to AIN and adjust R1 until the first transition is located. The gain trim is done by adjusting R2. If the nominal value is required, apply a signal 1 1/2 LSB below full scale (9.9997 V for a 10 V range) and adjust R2 until the last transition is located (11 1111 1111 1110 to 11 1111 1111 1111). Bipolar Range Inputs The connections for the bipolar mode are shown in Figure 5. In this mode, data output coding is twos complement binary. This circuit allows approximately ⫾25 mV of offset trim range (⫾40 LSB) and ⫾0.5% of gain trim range (⫾80 LSB). Either or both of the trim pots can be replaced with 50 Ω ⫾1% fixed resistors if the AD679 accuracy limits are sufficient for application. If the pins are shorted together, the additional offset and gain error is approximately 80 LSB. If offset adjustment is not required, BIPOFF should be connected directly to AGND. If gain adjustment is not required, R2 should be replaced with a fixed 50 Ω ⫾1% metal film resistor. If REFOUT is connected directly to REFIN, the additional gain error is approximately 1%. To trim bipolar zero to its nominal value, apply a signal 1/2 LSB below midrange (–0.305 mV for a ⫾5 V range) and adjust R1 until the major carry transition is located (11 1111 1111 1111 to 00 0000 0000 0000). To trim the gain, apply a signal 1 1/2 LSB below full scale (+4.9991 V for a ⫾5 V range) and adjust R2 to give the last positive transition (01 1111 1111 1110 to 01 1111 1111 1111). These trims are interactive so several iterations may be necessary for convergence. A single pass calibration can be done by substituting a bipolar offset trim (error at minus full scale) for the bipolar zero trim (error at midscale) using the same circuit. First, apply a signal 1/2 LSB above minus full scale (–4.9997 V for a ⫾5 V range) and adjust R1 until the minus full-scale transition is located (10 0000 0000 0000 to 10 000 000 0001). Then perform the gain error trim as outlined above. Figure 6. Unipolar Input Connections with Gain and Offset Trims REFERENCE DECOUPLING It is recommended that a 10 µF tantalum capacitor be connected between REFIN (Pin 9) and ground. This has the effect of improving the S/N+D ratio through filtering possible broadband noise contributions from the voltage reference. BOARD LAYOUT Figure 5. Bipolar Input Connections with Gain and Offset Trims Designing with high resolution data converters requires careful attention to board layout. Trace impedance is a significant issue. A 1.22 mA current through a 0.5 Ω trace will develop a voltage drop of 0.6 mV, which is 1 LSB at the 14-bit level for a 10 V full-scale span. In addition to ground drops, inductive and capacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital signals. Finally, power supplies need to be decoupled in order to filter out ac noise. Analog and digital signals should not share a common path. Each signal should have an appropriate analog or digital return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Separate analog –10– REV. D AD679 and digital ground planes are also desirable, with a single interconnection point to minimize ground loops. Analog signals should be routed as far as possible from digital signals and should cross them at right angles. The AD679 incorporates several features to help the user’s layout. Analog pins (VEE, AIN, AGND, REFOUT, REFIN, BIPOFF, VCC) are adjacent to help isolate analog from digital signals. In addition, the 10 MΩ input impedance of AIN minimizes input trace impedance errors. Finally, ground currents have been minimized by careful circuit architecture. Current through AGND is 200 µA, with no code dependent variation. The current through DGND is dominated by the return current for DB7–DB0 and EOC. Figure 7 shows the use of the AD586 with the AD679 in a bipolar input mode. Over the 0°C to 70°C range, the AD586 L-grade exhibits less than a 2.25 mV output change from its initial value at 25°C. REFIN (Pin 9) scales its input by a factor of two; thus, this change becomes effectively 4.5 mV. When applied to the AD679, this results in a total gain drift of 0.09% FSR, which is an improvement over the on-chip reference performance of 0.11% FSR. A noise-reduction capacitor, CN, has been shown. This capacitor reduces the broadband noise of the AD586 output, thereby optimizing the overall ac and dc performance of the AD679. SUPPLY DECOUPLING The AD679 power supplies should be well filtered, well regulated, and free from high frequency noise. Switching power supplies are not recommended due to their tendency to generate spikes that can induce noise in the analog system. Decoupling capacitors should be used in very close layout proximity between all power supply pins and analog ground. A 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor provides adequate decoupling. An effort should be made to minimize the trace length between the capacitor leads and the respective converter power supply and common pins. The circuit layout should attempt to locate the AD679, associated analog input circuitry, and interconnections as far as possible from logic circuitry. A solid analog ground plane around the AD679 isolates large switching ground currents. For these reasons, the use of wire wrap circuit construction is not recommended; careful printed circuit construction is preferred. GROUNDING If a single AD679 is used with separate analog and digital ground planes, connect the analog ground plane to AGND and the digital ground plane to DGND, keeping lead lengths as short as possible. Then connect AGND and DGND together at the AD679. If multiple AD679s are used or if the AD679 shares analog supplies with other components, connect the analog and digital returns together once at the power supplies rather than at each chip. This prevents large ground loops, which inductively couple noise and allow digital currents to flow through the analog system. Figure 7. Bipolar Input with Gain and Offset Trims Figure 8 shows the AD679 in unipolar input mode with the AD588 reference. The AD588 output is accurate to 0.65 mV from its value at 25°C over the 0°C to 70°C range. This results in a 0.06% FSR total gain drift for the AD679, a substantial improvement over the on-chip reference performance of 0.11% FSR. A noise-reduction network on Pins 4, 6, and 7 has been shown. The 1 µF capacitors form low-pass filters with the internal resistance of the AD588 Zener and amplifier cells and external resistance. This reduces the high frequency (to 1 MHz) noise of the AD588, providing optimum ac and dc performance of the AD679. REFIN USE OF EXTERNAL VOLTAGE REFERENCE The AD679 features an on-chip voltage reference. For improved gain accuracy over temperature, a high performance external voltage reference may be used in place of the on-chip reference. The AD586 and AD588 are popular references appropriate for use with high resolution converters. The AD586 is a low cost reference that utilizes a buried Zener architecture to provide low noise and drift. The AD588 is a higher performance reference that uses a proprietary implanted buried Zener diode in conjunction with laser-trimmed thin-film resistors for low offset and low drift. REV. D –11– Figure 8. Unipolar Input with Gain and Offset Trims AD679 INTERFACING THE AD679 TO MICROPROCESSORS The I/O capabilities of the AD679 allow direct interfacing to general-purpose and DSP microprocessor buses. The asynchronous conversion control feature allows complete flexibility and control with minimal external hardware. The following examples illustrate typical AD679 interface configurations. AD679 to TMS320C25 In Figure 9, the AD679 is mapped into the TMS320C25 I/O space. AD679 conversions are initiated by issuing an OUT instruction to Port 1. EOC status and the conversion result are read in with an IN instruction to Port 1. A single wait state is inserted by generating the processor READY input from IS, Port 1, and MSC. Address line A0 provides HBE decoding to select between the high and low bytes of data. This configuration supports processor clock speeds of 20 MHz and is capable of supporting processor clock speeds of 40 MHz if a NOP instruction follows each AD679 read instruction. Figure 10. AD679 to 80186 DMA Interface AD679 to Analog Devices ADSP-2101 Figure 11 demonstrates the AD679 interfaced to an ADSP-2101. With a clock frequency of 12.5 MHz, and instruction execution in one 80 ns cycle, the digital signal processor supports the AD679 interface with one wait state. The converter is configured to run asynchronously using a sampling clock. The EOC output of the AD679 gets asserted at the end of each conversion and causes an interrupt. Upon interrupt, the ADSP-2101 immediately asserts its FO pin LOW. In the following cycle, the processor starts a data memory read by providing an address on the DMA bus. The decoded address generates OE for the converter, and the high byte of the conversion result is read over the data bus. The read operation is extended with one wait state and thus started and completed within two processor cycles (160 ns). Next, the ADSP-2101 asserts its FO HIGH. This allows the processor to start reading the lower byte of data. This read operation executes in a similar manner to the first and is completed during the next 160 ns. Figure 9. AD679 to TMS320C25 Interface AD679 to 80186 Figure 10 shows the AD679 interfaced to the 80186 microprocessor. This interface allows the 80186’s built-in DMA controller to transfer the AD679 output into a RAM based FIFO buffer of any length, with no microprocessor intervention. In this application the AD679 is configured in the asynchronous mode, which allows conversions to be initiated by an external trigger source independent of the microprocessor clock. After each conversion, the AD679 EOC signal generates a DMA request to Channel 1 (DRQ1). The subsequent DMA READ sequences the high and low byte AD679 data and resets the interrupt latch. The system designer must assign a sufficient priority to the DMA channel to ensure that the DMA request is serviced before the next conversion is completed. This configuration can be used with 6 MHz and 8 MHz 80186 processors. Figure 11. AD679 to ADSP-2101 Interface –12– REV. D AD679 AD679 to Analog Devices ADSP-2100A Figure 12 demonstrates the AD679 interfaced to an ADSP-2100A. With a clock frequency of 12.5 MHz, and instruction execution in one 80 ns cycle, the digital signal processor supports the AD679 data memory interface with three hardware wait states. The converter is configured to run asynchronously using a sampling clock. The EOC output of the AD679 gets asserted at the end of each conversion and causes an interrupt. Upon interrupt, the ADSP-2100A immediately executes a data memory write instruction, which asserts HBE. In the following cycle, the processor starts a data memory read (high byte read) by providing an address on the DMA bus. The decoded address generates OE for the converter. OE, together with logic and latch, is used to force the ADSP-2100A into a one cycle wait state by generating DMACK. The read operation is thus started and completed within two processor cycles (160 ns). HBE is released during high byte read. This allows the processor to read the lower byte of data as soon as high byte read is complete. The low byte read operation executes in a similar manner to the first and is completed during the next 160 ns. REV. D –13– Figure 12. AD679 to ADSP-2100A Interface AD679 OUTLINE DIMENSIONS 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-28) Dimensions shown in inches and (millimeters) 0.005 (0.13) MIN 0.100 (2.54) MAX 28 15 0.610 (15.49) 0.580 (12.73) PIN 1 1 1.490 (37.85) MAX 0.085 (2.16) MAX 0.200 (5.08) 0.125 (3.18) 14 0.026 (0.66) 0.014 (0.36) 0.100 (2.54) 0.060 (1.52) 0.015 (0.38) 0.070 (1.78) 0.030 (0.76) 0.620 (15.75) 0.590 (14.99) 0.150 (3.81) MIN SEATING PLANE 0.018 (0.46) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 28-Lead Plastic Dual In-Line Package [PDIP] Wide Body (N-28) Dimensions shown in inches and (millimeters) 0.005 (0.13) MIN 0.100 (2.54) MAX 28 15 0.610 (15.49) 0.580 (12.73) PIN 1 0.085 (2.16) MAX 0.200 (5.08) 0.125 (3.18) 1 14 1.490 (37.85) MAX 0.026 (0.66) 0.014 (0.36) 0.100 (2.54) 0.060 (1.52) 0.015 (0.38) 0.070 (1.78) 0.030 (0.76) 0.620 (15.75) 0.590 (14.99) 0.150 (3.81) MIN SEATING PLANE 0.018 (0.46) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN –14– REV. D AD679 OUTLINE DIMENSIONS 44-Lead Ceramic Leaded Chip Carrier, J-Formed Leads [JLCC] (J-44) Dimensions shown in inches and (millimeters) 0.078 (1.98) 0.054 (1.37) 0.040 (1.02) REF x 45 3 PLACES 0.662 (16.82) SQ 0.628 (15.95) 0.025 (0.64) MIN 39 29 40 0.020 (0.51) REF x 45 28 0.032 (0.81) 0.020 (0.51) PIN 1 INDEX 0.065 (1.65) 0.050 (1.27) BSC 0.650 (16.51) 0.610 (15.49) PIN 1 0.500 (12.70) 0.492 (12.50) TOP VIEW BOTTOM VIEW 0.023 (0.58) 0.013 (0.33) 18 6 7 0.135 (3.43) 0.100 (2.54) 17 0.700 (17.78) SQ 0.680 (17.27) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location Page 6/04—Data Sheet changed from REV. C to REV. D. Updated Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to AC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 REV. D –15– –16– C00812–0–6/04(D)