AD698

a FEATURES Single Chip Solution, Contains Internal Oscillator and Voltage Reference No Adjustments Required Interfaces to Half-Bridge, 4-Wire LVDT DC Output Proportional to Position 20 Hz to 20 kHz Frequency Range Unipolar or Bipolar Output Will Also Decode AC Bridge Signals Outstanding Performance Linearity: 0.05% Output Voltage: 11 V Gain Drift: 20 ppm/ C (typ) Offset Drift: 5 ppm/ C (typ) Universal LVDT Signal Conditioner AD698 FUNCTIONAL BLOCK DIAGRAM AMP OSCILLATOR VOLTAGE REFERENCE AD698 B A B FILTER A AMP PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD698 is a complete, monolithic Linear Variable Differential Transformer (LVDT) signal conditioning subsystem. It is used in conjunction with LVDTs to convert transducer mechanical position to a unipolar or bipolar dc voltage with a high degree of accuracy and repeatability. All circuit functions are included on the chip. With the addition of a few external passive components to set frequency and gain, the AD698 converts the raw LVDT output to a scaled dc signal. The device will operate with half-bridge LVDTs, LVDTs connected in the series opposed configuration (4-wire), and RVDTs. The AD698 contains a low distortion sine wave oscillator to drive the LVDT primary. Two synchronous demodulation channels of the AD698 are used to detect primary and secondary amplitude. The part divides the output of the secondary by the amplitude of the primary and multiplies by a scale factor. This eliminates scale factor errors due to drift in the amplitude of the primary drive, improving temperature performance and stability. The AD698 uses a unique ratiometric architecture to eliminate several of the disadvantages associated with traditional approaches to LVDT interfacing. The benefits of this new circuit are: no adjustments are necessary; temperature stability is improved; and transducer interchangeability is improved. The AD698 is available in two performance grades: Grade AD698AP AD698SQ Temperature Range –40°C to +85°C –55°C to +125°C Package 28-Pin PLCC 24-Pin Cerdip 1. The AD698 offers a single chip solution to LVDT signal conditioning problems. All active circuits are on the monolithic chip with only passive components required to complete the conversion from mechanical position to dc voltage. 2. The AD698 can be used with many different types of position sensors. The circuit is optimized for use with any LVDT, including half-bridge and series opposed, (4 wire) configurations. The AD698 accommodates a wide range of input and output voltages and frequencies. 3. The 20 Hz to 20 kHz excitation frequency is determined by a single external capacitor. The AD698 provides up to 24 volts rms to differentially drive the LVDT primary, and the AD698 meets its specifications with input levels as low as 100 millivolts rms. 4. Changes in oscillator amplitude with temperature will not affect overall circuit performance. The AD698 computes the ratio of the secondary voltage to the primary voltage to determine position and direction. No adjustments are required. 5. Multiple LVDTs can be driven by a single AD698 either in series or parallel as long as power dissipation limits are not exceeded. The excitation output is thermally protected. 6. The AD698 may be used as a loop integrator in the design of simple electromechanical servo loops. 7. The sum of the transducer secondary voltages do not need to be constant. R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD698–SPECIFICATIONS (@ T = +25 C, V A CM = 0 V, and V+, V– = AD698SQ Typ Max 15 V dc, unless otherwise noted) Min AD698AP Typ Max Unit V 1.65 % of FS V mA mA ppm of FS % of FS ppm/°C of FS % of FS ppm/°C of FS ppm/dB ppm/V ppm/V ppm/V ppm/V mV rms V rms V rms V rms V rms ppm/°C mA rms mA rms mA mV Hz ppm/°C dB Parameter TRANSFER FUNCTION1 OVERALL ERROR TMIN to TMAX SIGNAL OUTPUT CHARACTERISTICS Output Voltage Range Output Current, TMIN to TMAX Short Circuit Current Nonlinearity2 TMIN to TMAX Gain Error3 Gain Drift Output Offset Offset Drift Excitation Voltage Rejection4 Power Supply Rejection (± 12 V to ± 18 V) PSRR Gain PSRR Offset Common-Mode Rejection (± 3 V) CMRR Gain CMRR Offset Output Ripple5 EXCITATION OUTPUT CHARACTERISTICS (@ 2.5 kHz) Excitation Voltage Range Excitation Voltage (Resistors Are 1% Absolute Values) (R1 = Open)6 (R1 = 12.7 kΩ) (R1 = 487 Ω) Excitation Voltage TC7 Output Current TMIN to TMAX Short Circuit Current DC Offset Voltage (Differential, R1 = 12.7 kΩ) TMIN to TMAX Frequency Frequency TC Total Harmonic Distortion SIGNAL INPUT CHARACTERISTICS A/B Ratio Usable Full-Scale Range Signal Voltage B Channel Signal Voltage A Channel Input Impedance Input Bias Current (BIN, AIN) Signal Reference Bias Current Excitation Frequency POWER SUPPLY REQUIREMENTS Operating Range Dual Supply Operation (± 10 V Output) Single Supply Operation 0 V to +10 V Output 0 V to 10 V Output Current (No Load at Signal and Excitation Outputs) TMIN to TMAX OPERATING TEMPERATURE RANGE Min VOUT = A × 500 µA × R 2 B 0.4 11 11 20 75 0.1 20 0.02 5 100 50 15 25 2 4 2.1 1.2 2.6 14 30 100 50 40 60 30 20 200 –50 0.1 0.1 0.0 200 1 2 0 13 ± 13 17.5 17.5 12 –55 15 18 +125 –40 0.9 3.5 3.5 5 10 20 k 36 0.l 0.1 0.0 200 1 2 0 13 ± 13 17.5 17.5 12 15 18 +85 100 20 k 1.65 11 11 20 75 0.1 20 0.02 5 100 50 15 25 2 4 2.1 1.2 2.6 14 30 100 50 40 60 30 20 200 –50 0.9 3.5 3.5 5 10 20 k 36 100 20 k 0.4 500 1.0 100 1 25 500 1.0 100 1 25 300 100 100 100 300 100 100 100 24 2.15 4.35 21.2 24 2.15 4.35 21.2 V rms V rms kΩ µA µA Hz V V V V mA mA °C –2– REV. B AD698 NOTES 1 A and B represent the Mean Average Deviation (MAD) of the detected sine waves V A and VB. The polarity of VOUT is affected by the sign of the A comparator, i.e., multiply VOUT × +1 for ACOMP+ > ACOMP–, and VOUT × –1 for ACOMP– > ACOMP+. 2 Nonlinearity of the AD698 only in units of ppm of full scale. Nonlinearity is defined as the maximum measured deviation of the AD698 output voltage from a straight line. The straight line is determined by connecting the maximum produced full-scale negative voltage with the maximum produced full-scale positive voltage. 3 See Transfer Function. 4 For example, if the excitation to the primary changes by 1 dB, the gain of the system will change by typically 100 ppm. 5 Output ripple is a function of the AD698 bandwidth determined by C1 and C2. A 1000 pF capacitor should be connected in parallel with R2 to reduce the output ripple. See Figures 7, 8 and 13. 6 R1 is shown in Figures 7, 8 and 13. 7 Excitation voltage drift is not an important specification because of the ratiometric operation of the AD698. 8 From TMIN to TMAX the overall error due to the AD698 alone is determined by combining gain error, gain drift and offset drift. For example, the typical overall error for the AD698AP from T MIN to TMAX is calculated as follows: Overall Error = Gain Error at +25 °C (± 0.2% Full Scale) + Gain Drift from –40 °C to +25°C (20 ppm/°C × 65°C) + Offset Drift from –40 °C to +25°C (5 ppm/°C × 65°C) = ± 0.36% of full scale. Note that 1000 ppm of full scale equals 0.1% of full scale. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tested are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS 28-Pin PLCC EXC2 EXC1 OFF1 +VS OFF2 25 NC 24 SIG REF 23 SIG OUT 22 FEEDBACK 21 OUT FILT 20 AFILT1 19 AFILT2 12 13 14 15 16 17 18 Total Supply Voltage (+VS to –VS) . . . . . . . . . . . . . . . . . 36 V Storage Temperature Range P Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Q Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range AD698SQ . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C AD698AP . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C Power Dissipation Derates above +65°C P Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mW/°C Q Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mW/°C THERMAL CHARACTERISTICS NC 4 LEV1 5 LEV2 6 FREQ1 7 FREQ2 8 NC 9 BFILT1 10 BFILT2 11 3 2 –VS 1 28 27 26 AD698 TOP VIEW (Not to Scale) +ACOMP –BIN +BIN +AIN –AIN NC = NO CONNECT ORDERING GUIDE Model AD698AP AD698SQ Package Description 28-Pin PLCC 24-Pin Double Cerdip Package Option P-28A Q-24A 24-Pin Cerdip –VS 1 EXC1 2 EXC2 3 LEV1 4 LEV2 5 FREQ1 6 24 +VS 23 OFFSET1 22 OFFSET2 21 SIG REF AD698 20 SIG OUT TOP VIEW 19 FEEDBACK FREQ2 7 (Not to Scale) 18 OUT FILT BFILT1 8 BFILT2 9 –BIN 10 +BIN 11 –AIN 12 17 AFILT1 16 AFILT2 15 –ACOMP 14 +ACOMP 13 +AIN CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD698 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. B –3– –ACOMP θJC P Package 30°C/W Q Package 26°C/W θJA 60°C/W 62°C/W NC AD698 Typical Characteristics (at +25°C and V = ±15 V unless otherwise noted) S 240 200 GAIN AND OFFSET PSRR – ppm/V TYPICAL GAIN DRIFT – ppm/°C 120 80 GAIN PSRR 15–18V 160 120 80 40 20 0 40 20 0 –20 –40 –60 GAIN PSRR 12–15V OFFSET PSRR 12–15V OFFSET PSRR 15–18V –20 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE – °C –80 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE – °C Figure 1. Gain and Offset PSRR vs. Temperature Figure 3. Typical Gain Drift vs. Temperature 0 –05 OFFSET CMRR ± 3V TYPICAL OFFSET DRIFT – ppm/°C 20 15 10 5 0 –5 –10 –15 –20 –60 GAIN AND OFFSET CMRR – ppm/V –10 –15 –20 –25 –30 –35 –40 –45 –60 GAIN CMRR ± 3V –40 –20 0 20 40 60 80 TEMPERATURE – °C 100 120 140 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE – °C Figure 2. Gain and Offset CMRR vs. Temperature Figure 4. Typical Offset Drift vs. Temperature –4– REV. B AD698 THEORY OF OPERATION gain error in the output. The AD698, eliminates these errors by calculating the ratio of the LVDT output to its input excitation in order to cancel out any drift effects. This device differs from the AD598 LVDT signal conditioner in that it implements a different circuit transfer function and does not require the sum of the LVDT secondaries (A + B) to be constant with stroke length. A block diagram of the AD698 along with an LVDT (linear variable differential transformer) connected to its input is shown in Figure 5 below. The LVDT is an electromechanical transducer—its input is the mechanical displacement of a core, and its output is an ac voltage proportional to core position. Two popular types of LVDTs are the half-bridge type and the series opposed or four-wire LVDT. In both types the moveable core couples flux between the windings. The series-opposed connected LVDT transducer consists of a primary winding energized by an external sine wave reference source and two secondary windings connected in the series opposed configuration. The output voltage across the series secondary increases as the core is moved from the center. The direction of movement is detected by measuring the phase of the output. Half-bridge LVDTs have a single coil with a center tap and work like an autotransformer. The excitation voltage is applied across the coil; the voltage at the center tap is proportional to position. The device behaves similarly to a resistive voltage divider. The AD698 block diagram is shown below. The inputs consist of two independent synchronous demodulation channels. The B channel is designed to monitor the drive excitation to the LVDT. The full wave rectified output is filtered by C2 and sent to the computational circuit. Channel A is identical except that the comparator is pinned out separately. Since the A channel may reach 0 V output at LVDT null, the A channel demodulator is usually triggered by the primary voltage (B Channel). In addition, a phase compensation network may be required to add a phase lead or lag to the A Channel to compensate for the LVDT primary to secondary phase shift. For half-bridge circuits the phase shift is noncritical, and the A channel voltage is large enough to trigger the demodulator. C2 AMP OSCILLATOR VOLTAGE REFERENCE BFILT1 BFILT2 +VS AD698 B B CHANNEL –BIN V/I ±1 FILTER C5 R2 OUT FILTER A B FILTER A AMP +BIN C4 FB VOUT COMP DUTY CYCLE DIVIDER A/B = 1 = 100% DUTY COMP +ACOMP –AIN V/I +AIN ±1 FILTER IREF 500µA OFF 2 OFF 1 V A B –ACOMP Figure 5. Functional Block Diagram The AD698 energizes the LVDT coil, senses the LVDT output voltages and produces a dc output voltage proportional to core position. The AD698 has a sine wave oscillator and power amplifier to drive the LVDT. Two synchronous demodulation stages are available for decoding the primary and secondary voltages. A decoder determines the ratio of the output signal voltage to the input drive voltage (A/B). A filter stage and output amplifier are used to scale the resulting output. The oscillator comprises a multivibrator that produces a triwave output. The triwave drives a sine shaper that produces a low distortion sine wave. Frequency and amplitude are determined by a single resistor and capacitor. Output frequency can range from 20 Hz to 20 kHz and amplitude from 2 V to 24 V rms. Total harmonic distortion is typically –50 dB. The AD698 decodes LVDTs by synchronously demodulating the amplitude modulated input (secondaries), A, and a fixed input reference (primary or sum of secondaries or fixed input), B. A common problem with earlier solutions was that any drift in the amplitude of the drive oscillator corresponded directly to a DEMODULATOR A CHANNEL AFILT1 C3 AFILT2 AD698 –VS Figure 6. AD698 Block Diagram Once both channels are demodulated and filtered a division circuit, implemented with a duty cycle multiplier, is used to calculate the ratio A/B. The output of the divider is a duty cycle. When A/B is equal to 1, the duty cycle will be equal to 100%. (This signal can be used as is if a pulse width modulated output is required.) The duty cycle drives a circuit that modulates and filters a reference current proportional to the duty cycle. The output amplifier scales the 500 µA reference current converting it to a voltage. The output transfer function is thus: VOUT = IREF × A/B × R 2, where IREF = 500 µA REV. B –5– AD698 CONNECTING THE AD698 The AD698 can easily be connected for dual or single supply operation as shown in Figures 7, 8 and 13. The following general design procedures demonstrate how external component values are selected and can be used for any LVDT that meets AD698 input/output criteria. The connections for the A and B channels and the A channel comparators will depend on which transducer is used. In general follow the guidelines below. Parameters set with external passive components include: excitation frequency and amplitude, AD698 input signal frequency, and the scale factor (V/inch). Additionally, there are optional features; offset null adjustment, filtering, and signal integration, which can be implemented by adding external components. +15V –15V 6.8µF 100nF 1 –VS 2 EXC1 3 EXC2 4 LEV1 R1 5 LEV2 C1 15nF SIG OUT 20 R2 33kΩ C4 7 FREQ2 8 BFILT1 C2 9 BFILT2 10 –BIN 11 +BIN 12 –AIN AFILT2 16 –ACOMP 15 +ACOMP 14 +AIN 13 OUT FILT 18 AFILT1 17 C3 1000pF VOUT 6.8µF 100nF 3. Select a suitable LVDT that will operate with an excitation frequency of 2.5 kHz. The Schaevitz E100, for instance, will operate over a range of 50 Hz to 10 kHz and is an eligible candidate for this example. 4. Select excitation frequency determining component C1. C1 = 35 µF Hz / f EXCITATION +15V –15V 6.8µF 100nF 1 –VS 2 EXC1 3 EXC2 4 LEV1 R1 5 LEV2 SIG OUT 20 R2 6.8µF 100nF AD698 +VS 24 R4 R3 OFFSET1 23 OFFSET2 22 SIG REF 21 RL VOUT SIGNAL REFERENCE AD698 +VS 24 R4 R3 C1 6 FREQ1 FEEDBACK 19 C4 1000pF 7 FREQ2 OUT FILT 18 AFILT1 17 C3 9 BFILT2 10 –BIN 11 +BIN 12 –AIN AFILT2 16 –ACOMP 15 +ACOMP 14 A +AIN 13 PHASE LAG/LEAD NETWORK C D B OFFSET1 23 OFFSET2 22 SIG REF 21 RL SIGNAL REFERENCE 8 BFILT1 C2 6 FREQ1 FEEDBACK 19 1M PHASE LAG A B C RT C D PHASE LEAD A B RT RS C D PHASE LAG = Arc Tan (Hz RC); PHASE LEAD = Arc Tan 1/(Hz RC) WHERE R = RS// (RS + RT) RS RS C C Figure 7. Interconnection Diagram for Half-Bridge LVDT and Dual Supply Operation DESIGN PROCEDURE DUAL SUPPLY OPERATION Figure 8. AD698 Interconnection Diagram for Series Opposed LVDT and Dual Supply Operation B. Determine the Oscillator Amplitude Figure 7 shows the connection method for half-bridge LVDTs. Figure 8 demonstrates the connections for 3- and 4-wire LVDTs connected in the series opposed configuration. Both examples use dual ± 15 volt power supplies. A. Determine the Oscillator Frequency Frequency is often determined by the required BW of the system. However, in some systems the frequency is set to match the LVDT zero phase frequency as recommended by the manufacturer; in this case skip to Step 4. 1. Determine the mechanical bandwidth required for LVDT position measurement subsystem, fSUBSYSTEM. For this example, assume fSUBSYSTEM = 250 Hz. 2. Select minimum LVDT excitation frequency approximately 10 × fSUBSYSTEM. Therefore, let excitation frequency = 2.5 kHz. Amplitude is set such that the primary signal is in the 1.0 V to 3.5 V rms range and the secondary signal is in the 0.25 V to 3.5 V rms range when the LVDT is at its mechanical full-scale position. This optimizes linearity and minimizes noise susceptibility. Since the part is ratiometric, the exact value of the excitation is relatively unimportant. 5. Determine optimum LVDT excitation voltage, VEXC. For a 4-wire LVDT determine the voltage transformation ratio, VTR, of the LVDT at its mechanical full scale. VTR = LVDT sensitivity × Maximum Stroke Length from null. LVDT sensitivity is listed in the LVDT manufacturer’s catalog and has units of volts output per volts input per inch displacement. The E100 has a sensitivity of 2.4 mV/V/mil. In the event that LVDT sensitivity is not given by the manufacturer, it can be computed. See section on determining LVDT sensitivity. –6– REV. B AD698 Multiply the primary excitation voltage by the VTR to get the expected secondary voltage at mechanical full scale. For example, for an LVDT with a sensitivity of 2.4 mV/V/mil and a full scale of ± 0.1 inch, the VTR = 0.0024 V/V/Mil × 100 mil = 0.24. Assuming the maximum excitation of 3.5 V rms, the maximum secondary voltage will be 3.5 V rms × 0.24 = 0.84 V rms, which is in the acceptable range. Conversely the VTR may be measured explicitly. With the LVDT energized at its typical drive level VPRI, as indicated by the manufacturer, set the core displacement to its mechanical full-scale position and measure the output VSEC of the secondary. Compute the LVDT voltage transformation ratio, VTR. VTR = VSEC//VPRI. For the E100, VSEC = 0.72 V for VPRI = 3 V. VTR = 0.24. For situations where LVDT sensitivity is low, or the mechanical FS is a small fraction of the total stroke length, an input excitation of more than 3.5 V rms may be needed. In this case a voltage divider network may be placed across the LVDT primary to provide smaller voltage for the +BIN and –BIN input. If, for example, a network was added to divide the B Channel input by 1/2, then the VTR should also be reduced by 1/2 for the purpose of component selection. Check the power supply voltages by verifying that the peak values of VA and VB are at least 2.5 volts less than the voltages at +VS and –VS. 6. Referring to Figure 9, for VS = ± 15 V, select the value of the amplitude determining component R1 as shown by the curve in Figure 9. 30 b. Full-scale core displacement from null, d S × d = VTR and also equals the ratio A/B at mechanical full scale. The VTR should be converted to units of V/V. For a full-scale displacement of d inches, voltage out of the AD698 is computed as VOUT = S × d × 500 µA × R2 VOUT is measured with respect to the signal reference, Pin 21, shown in Figure 7. Solving for R2, R2 = VOUT S × d × 500 µA (1) For VOUT = ± 10 V full-scale range (20 V span) and d = ± 0.1 inch full-scale displacement (0.2 inch span) R2 = 20 V = 83. 3 k Ω 2.4 × 0.2 × 500 µA VOUT as a function of displacement for the above example is shown in Figure 10. VOUT (VOLTS) +10 –0.1 +0.1d (INCHES) –10 Figure 10. VOUT (± 10 V Full Scale) vs. Core Displacement (± 0.1 Inch) E. Optional Offset of Output Voltage Swing 25 9. Selections of R3 and R4 permit a positive or negative output voltage offset adjustment.  1 1 VOS = 1.2 V × R 2 ×  –  R 3 + 2 kΩ R 4 + 2 kΩ  V rms VEXC – V rms 20 (2) 15 For no offset adjustment R3 and R4 should be open circuit. To design a circuit producing a 0 V to +10 V output for a displacement of +0.1 inch, set VOUT to +10 V, d = 0.2 inch and solve Equation (1) for R2. VOUT (VOLTS) 10 5 0 0.01 0.1 1 R1 – kΩ 10 100 1k –0.1 +5 +0.1d (INCHES) Figure 9. Excitation Voltage VEXC vs. R1 7. C2, C3 and C4 are a function of the desired bandwidth of the AD698 position measurement subsystem. They should be nominally equal values. C2 = C3 = C4 = 10 Farad Hz/f5UBSYSTEM (Hz) If the desired system bandwidth is 250 Hz, then C2 = C3 = C4 = 10-4 Farad Hz/250 Hz = 0.4 µF See Figures 14, 15 and 16 for more information about AD698 bandwidth and phase characterization. D. Set the Full-Scale Output Voltage –4 –5 Figure 11. VOUT (± 5 V Full Scale) vs. Core Displacement (± 0.1 Inch) This will produce a response shown in Figure 11. In Equation (2) set VOS = 5 V and solve for R3 and R4. Since a positive offset is desired, let R4 be open circuit. Rearranging Equation (2) and solving for R3 R 3 = 1.2 × R 2 – 2 kΩ = 7.02 kΩ VOS 8. To compute R2, which sets the AD698 gain or full-scale output range, several pieces of information are needed: a. LVDT sensitivity, S REV. B –7– AD698 Note that VOS should be chosen so that R3 cannot have negative value . 11. The voltage drop across R5 must be greater than 1.2V V 2 + 10 kΩ  + 250 µA + OUT  Volts  R4 + 2 kΩ 4 × R2  Figure 12 shows the desired response. VOUT (VOLTS) +10 –0.1 +5 +0.1d (INCHES) Therefore 1.2V V + 250 µA + OUT  2 + 10 k Ω   R4 + 2 kΩ 4 × R 2  Ohms R5 ≥ 100 µA Figure 12. VOUT (0 V–10 V Full Scale) vs. Displacement (± 0.1 Inch) DESIGN PROCEDURE SINGLE SUPPLY OPERATION Based upon the constraints of R5 + R6 (Step 10) and R5 (Step 11), select an interim value of R6. 12. Load current through RL returns to the junction of R5 and R6, and flows back to VPS. Under maximum load conditions, make sure the voltage drop across R5 is met as defined in Step 11. As a final check on the power supply voltages, verify that the peak values of VA and VB are at least 2.5 volts less than the voltage between +VS and –VS. 13. C5 is a bypass capacitor in the range of 0.1 µF to 1 µF. Gain Phase Characteristics Figure 13 shows the single supply connection method. +30V Vps 6.8µF 0.1µF C5 R6 1 –VS 2 EXC1 3 EXC2 4 LEV1 R1 5 LEV2 SIG OUT 20 R2 6 FREQ1 FEEDBACK 19 C1 7 FREQ2 8 BFILT1 C2 9 BFILT2 10 –BIN 11 +BIN 12 –AIN AFILT2 16 OUT FILT 18 AFILT1 17 C3 C4 1000pF R5 AD698 +VS 24 R4 R3 OFFSET1 23 OFFSET2 22 SIG REF 21 RL VOUT SIGNAL REFERENCE To use an LVDT in a closed-loop mechanical servo application, it is necessary to know the dynamic characteristics of the transducer and interface elements. The transducer itself is very quick to respond once the core is moved. The dynamics arise primarily from the interface electronics. Figures 14, 15 and 16 show the frequency response of the AD698 LVDT Signal Conditioner. Note that Figures 15 and 16 are basically the same; the difference is frequency range covered. Figure 15 shows a wider range of mechanical input frequencies at the expense of accuracy. 10 0 –ACOMP 15 +ACOMP 14 A +AIN 13 GAIN – dB –10 2.0µF –20 –30 –40 –50 0.33µF 0.1µF B 1M PHASE LAG/LEAD NETWORK C D PHASE LAG A B C RT C D PHASE LEAD A B RT RS C D PHASE SHIFT – Degrees –60 –70 R2 = 81kΩ fEXC = 2.5kHz PHASE LAG = Arc Tan (Hz RC); PHASE LEAD = Arc Tan 1/(Hz RC) WHERE R = RS// (RS + RT) RS RS C C 0 –60 –120 –180 –240 –300 –360 –420 0 100 1k FREQUENCY – Hz 10k R2 = 81kΩ fEXC = 2.5kHz 2.0µF 0.33µF 0.1µF Figure 13. Interconnection Diagram for Single Supply Operation For single supply operation, repeat Steps 1 through 10 of the design procedure for dual supply operation. R5, R6 and C5 are additional component values to be determined. VOUT is measured with respect to SIGNAL REFERENCE. 10. Compute a maximum value of R5 and R6 based upon the relationship R5 + R6 ≤ VPS/100 µA Figure 14. Gain and Phase Characteristics vs. Frequency (0 kHz–10 kHz) –8– REV. B AD698 10 0 –10 –20 GAIN – dB –30 –40 –50 –60 –70 0 0.033µF –60 PHASE SHIFT – Degrees –120 0.01µF –180 0.1µF –240 –300 –360 R2 = 81kΩ fEXC = 10kHz R2 = 81kΩ fEXC = 10kHz 0.1µF 0.01µF 0.033µF Figure 16 shows a more limited frequency range with enhanced accuracy. The figures are transfer functions with the input to be considered as a sinusoidally varying mechanical position and the output as the voltage from the AD698; the units of the transfer function are volts per inch. The value of C2, C3, and C4, from Figure 7, are all equal and designated as a parameter in the figures. The response is approximately that of two real poles. However, there is appreciable excess phase at higher frequencies. An additional pole of filtering can be introduced with a shunt capacitor across R2, Figure 7; this will also increase phase lag. When selecting values of C2, C3 and C4 to set the bandwidth of the system, a trade-off is involved. There is ripple on the “dc” position output voltage, and the magnitude is determined by the filter capacitors. Generally, smaller capacitors will give higher system bandwidth and larger ripple. Figures 17 and 18 show the magnitude of ripple as a function of C2, C3 and C4, again all equal in value. Note also a shunt capacitor across R2, Figure 7, is shown as a parameter. The value of R2 used was 81 kΩ with a Schaevitz E100 LVDT. 1k 100 –420 RIPPLE – mV rms 0 100 1k FREQUENCY – Hz 10k 100k 10 Figure 15. Gain and Phase Characteristics vs. Frequency (0 kHz–50 kHz) 10 0.01µF 0 –10 –20 0.033µF 1 2.5kHz, C SHUNT 1nF 2.5kHz, C SHUNT 10nF 0.1 0.01 0.1 1 C2, C3, C4; C2 = C3 = C4 – µF 10 GAIN – dB –30 0.1µF –40 –50 –60 –70 R2 = 81kΩ fEXC = 10kHz Figure 17. Output Voltage Ripple vs. Filter Capacitance 1k 100 RIPPLE – mV rms 10 0.01µF 0 PHASE SHIFT – Degrees –60 0.1µF –120 0.033µF –180 –240 –300 –360 R2 = 81kΩ fEXC = 10kHz 1 10kHz, CSHUNT 1nF 10kHz, CSHUNT 10nF 0.1 0.001 0.01 0.1 1 C2, C3, C4; C2 = C3 = C4 – µF 10 Figure 18. Output Voltage Ripple vs. Filter Capacitance 0 100 1k FREQUENCY – Hz 10k Figure 16. Gain and Phase Characteristics vs. Frequency (0 kHz–10 kHz) REV. B –9– AD698 Determining LVDT Sensitivity LVDT sensitivity can be determined by measuring the LVDT secondary voltages as a function of primary drive and core position, and performing a simple computation. Energize the LVDT at its recommended primary drive level, VPRI (3 V rms for the E100). Set the core displacement to its mechanical full-scale position and measure secondary voltages VA and VB. Sensitivity = VSECONDARY V PRI × d – Low Cost Setpoint Controller – Mechanical Follower Servo Loop – Differential Gaging and Precision Differential Gaging AC BRIDGE SIGNAL CONDITIONER From Figure 19, Sensitivity = 0.72 3 V × 100 mils = 2.4 mV /V mil Bridge circuits which use dc excitation are often plagued by errors caused by thermocouple effects, 1/f noise, dc drifts in the electronics, and line noise pickup. One way to get around these problems is to excite the bridge with an ac waveform, amplify the bridge output with an ac amplifier, and synchronously demodulate the resulting signal. The ac phase and amplitude information from the bridge is recovered as a dc signal at the output of the synchronous demodulator. The low frequency system noise, dc drifts, and demodulator noise all get mixed to the carrier frequency and can be removed by means of a lowpass filter. The AD698 with the addition of a simple ac gain stage can be used to implement an ac bridge. Figure 20 shows the connections for such a system. The AD698 oscillator provides ac excitation for the bridge. The low level bridge signal is amplified by the gain stage created by A1, A2 to provide a differential input to the A Channel of the AD698. The signal is then synchronously detected by A Channel. The B Channel is used to detect the level of the bridge excitation. The ratio of A/B is then calculated and converted to an output voltage by R2. An optional phase lag/lead network can be added in front of the A comparator to adjust for phase delays through the bridge and the amplifier, or if the phase delay is small, it can be ignored or compensated for by a gain adjustment. This circuit can be used for resistive bridges such as strain gages, or for inductive or capacitive bridges that are commonly used for pressure or flow sensors. The low level signal outputs of these sensors are susceptible to noise and interference and are good candidates for ac signal processing techniques. Component Selection VSEC WHEN VPRI 3V rms VA 1.71V rms 0.99V rms VB d = –100 mils d=0 d = +100 mils Figure 19. LVDT Secondary Voltage vs. Core Displacement Thermal Shutdown and Loading Considerations The AD698 is protected by a thermal overload circuit. If the die temperature reaches 165°C, the sine wave excitation amplitude gradually reduces, thereby lowering the internal power dissipation and temperature. Due to the ratiometric operation of the decoder circuit, only small errors result from the reduction of the excitation amplitude. Under these conditions the signal-processing section of the AD698 continues to meet its output specifications. The thermal load depends upon the voltage and current delivered to the load as well as the power supply potentials. An LVDT Primary will present an inductive load to the sine wave excitation. The phase angle between the excitation voltage and current must also be considered, further complicating thermal calculations. APPLICATIONS Amplifiers A1, A2 will be chosen depending on the type of bridge that is conditioned. Capacitive bridges should use an amplifier with low bias current; a large bleeder resistor will be required from the amplifier inputs to ground to provide a path for the dc bias current. Resistive and inductive bridges can use a more general purpose amplifier. The dc performance of A1, A2 are not as important as their ac performance. DC errors such as voltage offset will be chopped out by the AD698 since they are not synchronous to the carrier frequency. The oscillator amplitude and span resistor for the AD698 may be chosen by first computing the transfer function or sensitivity of the bridge and the ac amplifier. This ratio will correspond to the A/B term in the AD698 transfer function. For example, suppose that a resistive strain gage with a sensitivity, S, of 2 mV/V at full scale is used. Select an arbitrary target value for A/B that is close to its maximum value such as A/B = 0.8. Then choose a gain for the ac amplifier so that the strain gage transfer function from excitation to output also equals 0.8. Thus the required amplifier gain will be [A/B]/ S; or 0.8/ 0.002 V/V = 400. Then select values for RS and RG. For the gain stage: Most of the applications for the AD598 can also be implemented with the AD698. Please refer to the applications written for the AD598 for a detailed explanation. See AD598 data sheet for: – Proving Ring-Weigh Scale – Synchronous Operation of Multiple LVDTs – High Resolution Position-to-Frequency Circuit –10– REV. B AD698 2 × RS  VOUT =  × V IN  RG + 1    Solving for VOUT/VIN = 400 and setting RG = 100 Ω then: RS = [400 – 1] × RG/2 = 19.95 kΩ Choose an oscillator amplitude that is in the range of 1 V to 3.5 V rms. For an input excitation level of 3 V rms, the output signal from the amplifier gain stage will be 3.5 V rms × 0.8 V or 2.4 V rms, which is in the acceptable range. Since A/B is known, the value of R2, the output FS resistor may be chosen by the formula: VOUT = A/B × 500 µA × R2 For a 10 V output at FS, with an A/B of 0.8; solve for R2. R2 = 10 V [0.8 × 500 µA] = 25.0 kΩ This will result in a VOUT of 10 V for a full-scale signal from the bridge. The other components, C1, C2, C3, C4 may be selected by following the guidelines on general device operation mentioned earlier. If a gain trim is required, then a trim resistor can be used to adjust either R2 or RG. Bridge offsets should be adjusted by a trim network on the OFFSET 1 and OFFSET 2 pins of the AD698. +15V –15V 6.8µF 100nF 6.8µF 100nF 1 –VS 2 EXC1 3 EXC2 4 LEV1 R1 5 LEV2 AD698 +VS 24 R4 R3 OFFSET1 23 OFFSET2 22 SIG REF 21 RL SIG OUT 20 R2 VOUT SIGNAL REFERENCE 6 FREQ1 FEEDBACK 19 RESISTORS, INDUCTORS OR CAPACITORS C1 7 FREQ2 8 BFILT1 C2 9 BFILT2 A1 RS 12 –AIN RG RS +AIN 13 PHASE LAG/LEAD NETWORK RS A2 DUAL OP AMP C D C 10 –BIN 11 +BIN AFILT2 16 –ACOMP 15 +ACOMP 14 A B PHASE LAG A B C RT D PHASE LEAD A B RT RS C C D RS C OUT FILT 18 AFILT1 17 C3 C4 1000pF PHASE LAG = Arc Tan (Hz RC); PHASE LEAD = Arc Tan 1/(Hz RC) WHERE R = RS// (RS + RT) Figure 20. AD698 Interconnection Diagram for AC Bridge Applications REV. B –11– AD698 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Pin Cerdip (Wide) 0.005 (0.13) MIN 0.098 (2.49) MAX 24 13 0.610 (15.5) 0.520 (13.2) PIN 1 1 12 0.620 (15.75) 0.590 (15.00) 1.280 (32.51) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 15 ° 0° 0.015 (0.38) 0.008 (0.20) 28-Pin PLCC 0.180 (4.57) 0.165 (4.19) 0.025 (0.63) 0.015 (0.38) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 5 4 PIN 1 IDENTIFIER 0.056 (1.42) 0.042 (1.07) 26 25 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66) 0.050 (1.27) BSC TOP VIEW 11 0.020 (0.50) R 12 0.456 (11.58) SQ 0.450 (11.43) 0.495 (12.57) SQ 0.485 (12.32) 18 19 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16) –12– REV. B PRINTED IN U.S.A. C1827a–5–7/95