AD7010

a FEATURES Single +5 V Supply On-Chip /4 DQPSK Modulator Root-Raised-Cosine Tx Filters, = 0.5 Two 10-Bit D/A Converters 4th Order Reconstruction Filters Differential Analog Outputs On-Chip Ramp Up/Down Power Control On-Chip Tx Offset Calibration Very Low Power Dissipation, 30 mW typ Power Down Mode < 5 A On-Chip Voltage Reference 24-Pin SSOP APPLICATIONS Japanese Digital Cellular Telephony CMOS JDC /4 DQPSK Baseband Transmit Port AD7010 GENERAL DESCRIPTION The AD7010 is a complete low power, CMOS, π/4 DQPSK modulator with single +5 V power supply. The part is designed to perform the baseband conversion of I and Q transmit waveforms in accordance with the Japanese Digital Cellular Telephone system. The on-chip π/4 Differential Quadrature Phase Shift Keying (DQPSK) digital modulator, which includes the Root Raised Cosine filters, generates I and Q data in response to the transmit data stream. The AD7010 also contains ramp control envelope logic to shape the I and Q output waveforms when ramping up or down at the beginning or end of a transmit burst. Besides providing all the necessary logic to perform π/4 DQPSK modulation, the part also provides reconstruction filters to smooth the DAC outputs, providing continuous time analog outputs. The AD7010 generates differential analog outputs for both the I and Q signals. As it is a necessity for all digital mobile systems to use the lowest possible power, the device has power down options. The AD7010 is housed in a space efficient 24-pin SSOP (Shrink Small Outline Package). FUNCTIONAL BLOCK DIAGRAM DGND VDD VAA AGND POWER Tx DATA π/4 DQPSK MODULATOR 10-BIT I-DAC RECONSTRUCTION FILTERS ITx ITx CALIBRATION CIRCUITRY Tx CLK 10-BIT Q-DAC RECONSTRUCTION FILTERS QTx QTx READY AD7010 BIN 2.46V REFERENCE BOUT MCLK BYPASS MODE1 MODE2 REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD7010–SPECIFICATIONS1 Parameter DIGITAL MODE TRANSMIT No. of Channels Output Signal Range Differential Output Range Signal Vector Magnitude2 Error Vector Magnitude2 Offset Vector Magnitude2 JDC Spurious Power2, 3 @ 25 kHz @ 50 kHz @ 75 kHz @ 100 kHz, 150 kHz, 200 kHz REFERENCE & CHANNEL SPECIFICATIONS Reference, VREF Reference Accuracy I and Q Gain Matching Power Down Option LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES VDD IDD Transmit Section Active Transmit Section Powered Down4 (VAA = VDD = +5 V 10%; Test = AGND = DGND = 0 V; fMCLK = 2.688 MHz; Power = VDD. All specifications are TMIN to TMAX unless otherwise noted.) AD7010ARS 2 VREF ± VREF/4 ± VREF/2 0.875 ± 7.5% 1 2.5 0.5 2.5 –30 –25 –60 –55 –70 –65 –70 –65 2.46 ±5 ± 0.2 Yes VDD–0.9 0.9 10 10 VDD–0.4 0.4 4.5/5.5 8 6 35 5 Units Test Conditions/Comments (ITx–ITx) and (QTx–QTx) For Each Analog Output I Channel = (ITx–ITx) and Q Channel = (QTx–QTx) Measured Differentially Volts Volts Volts max % rms typ % rms max % typ % max dB typ dB max dB typ dB max dB typ dB max dB typ dB max Volts % dB max Measured @ 10 kHz Power = 0 V V min V max µA max pF max V min V max V min/V max mA max mA typ µA max µA max Power = VDD MCLK Active MCLK Inactive |IOUT| ≤ 40 µA |IOUT| ≤ 1.6 mA NOTES 1 Operating temperature ranges as follows: A Version: –40 °C to +85 °C. 2 See Terminology. 3 Measured in continuous transmission and Burst transmission with the I and Q channels ramping up and down at the beginning and end of each burst. 4 Measured while the digital inputs to the transmit interface are static and equal to 0 V or V DD. Specifications subject to change without notice. ORDERING GUIDE Model AD7010ARS Temperature Range –40°C to +85°C Package Description Package Option Shrink Small Outline Package RS-24 –2– REV. B AD7010 ABSOLUTE MAXIMUM RATINGS* (TA = +25 °C unless otherwise noted) ITx/QTx 20pF 20kΩ VDD Tx, VDD Rx to AGND . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . –0.3 V to VDD to + 0.3 V Analog I/O Voltage to AGND . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C SSOP θJA Thermal Impedance . . . . . . . . . . . . . . . . +122°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AD7010 20kΩ 40kΩ ITx / QTx 20pF Figure 1. Analog Output Load Test Circuit Q MODULAR OUTPUT DURING FTEST I Table I. MODE 1 0 0 1 MODE 2 0 1 X Operation Digital JDC Mode FTEST Factory Test, Reserved Figure 2. Modulator State During FTEST CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7010 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE MASTER CLOCK TIMING Parameter t1 t2 t3 300 100 100 (VAA = VDD = +5 V otherwise noted.) 10%; AGND = DGND = O V. All specifications are TMIN to TMAX unless Units ns min ns min ns min Description MCLK Cycle Time MCLK High Time MCLK Low Time Limit at TA = –40 C to +85 C t1 t2 MCLK CL 100pF TO OUTPUT PIN 1.6mA IOL +2.1V t3 200µA IOH Figure 3. Master Clock (MCLK) Timing Figure 4. Load Circuit for Digital Outputs REV. B –3– AD7010 (V TRANSMIT SECTION TIMING T Parameter t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 10 t1 – 10 4097t1 + 70 10 t1 – 10 t1 + 70 3t1 + 70 64t1 32t1 32t1 50 0 3t1 124t1 7.5t9 30t1 10 10 AA MIN = VDD = +5 V 10%; AGND = DGND = 0 V, fMCLK = 2.688 MHz. All specifications are to TMAX unless otherwise noted.) Units ns min ns max ns max ns min ns max ns max ns ns ns ns ns min ns min ns max ns max ns ns max ns max ns max Description POWER Setup Time. MCLK rising edge, after POWER high, to READY rising edge. BIN Setup Time. MCLK to READY low propagation delay. MCLK rising edge, after BIN high, to first TxCLK rising edge. TxCLK Cycle Time. TxCLK High Time. TxCLK Low Time. TxCLK falling edge to TxDATA setup time. TxCLK falling edge to TxDATA hold time. BIN low setup to last transmitted symbol after ramp down. BIN low hold to last transmitted symbol after ramp down. Ramp down cycle time after the last transmitted symbol. Last TxCLK falling edge to READY rising edge. Digital Output Rise Time. Digital Output Fall Time. Limit at TA = –40°C to +85°C MCLK POWER t4 READY t7 t5 BIN t6 t8 t9 t11 t12 t13 Xk TxCLK t10 Yk TxDATA Figure 5. Transmit Timing at the Start of a Tx Burst MCLK POWER t17 READY BIN t14 t15 TxCLK t16 TxDATA XN+4 YN+4 XN+5 XN+8 YN+8 Figure 6. Transmit Timing at the End of a Tx Burst –4– REV. B AD7010 PIN FUNCTION DESCRIPTION SSOP Pin Number Mnemonic Function Positive power supply for analog section. Positive power supply for digital section, both supplies should be externally tied together. Analog ground for transmit section. Digital ground for transmit section, both grounds should be externally tied together. POWER SUPPLY 19 VAA 5 VDD 14, 18, 23 AGND 6 DGND ANALOG SIGNAL AND REFERENCE 13 BYPASS Reference decoupling output. A decoupling capacitor should be connected between this pin a and AGND. 16, 17 ITx, ITx Differential analog outputs for the I channel, representing true and complementary outputs of the I waveform. 21, 20 QTx, QTx Differential analog outputs for the Q channel, representing true and complementary outputs of the Q waveform. TRANSMIT INTERFACE AND CONTROL 7 MCLK Master clock, digital input. This pin should be driven by a 2.688 MHz CMOS compatible clock source in digital mode. 3 TxCLK This is a digital output, transmit clock. This may be used to clock in transmit data at 42 kHz. 4 TxDATA This is a digital input. This pin is used to clock in transmit data on the falling edge of TxCLK at a rate of 42 kHz. 2 BIN This is a digital input. This input is used to initiate the ramping up (BIN high) or down (BIN low) of the I and Q waveforms. 24 BOUT Burst out, digital output. This is the BIN input delayed by the pipeline delay, both digital and analog, of the AD7010. This can be used to turn on and off the RF amplifiers in synchronization with the I and Q waveforms. 1 POWER Transmit sleep mode, digital input. When this goes low, the AD7010 goes into sleep mode, drawing minimal current. When this pin goes high, the AD7010 is brought out of sleep mode and initiates a self-calibration routine to eliminate the offset between ITx & ITx and the offset between QTx & QTx. 12 READY Transmit ready, digital output. This output goes high once the self-calibration routine is complete. 9, 11 MODE1, Mode control, digital inputs. These are used to enter the AD7010 into three different MODE2 operating modes, see Table I. 8, 10, 15, 22 NC No Connects. These pins are no connects and should not be used as routes for other circuit signals. SSOP PIN CONFIGURATION POWER BIN TxCLK TxDATA VDD DGND MCLK NC MODE1 NC MODE2 READY 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 BOUT AGND NC QTx QTx VAA AGND ITx ITx NC AGND BYPASS AD7010 TOP VIEW (Not to Scale) 19 18 17 16 15 14 13 REV. B –5– AD7010 TERMINOLOGY Error Vector Magnitude Table II. This is a measure of the rms error vector introduced by the AD7010 where signal error vector is defined as the rms deviation of a transmitted symbol from its ideal position, as illustrated in Figure 7, when filtered by an ideal RRC filter. Gain Matching Between Channels Xk 1 0 0 1 Yk 1 1 0 0 k This is the Gain matching between the I and Q outputs, measured when transmitting all zeros. Offset Vector Magnitude –3 π/4 3 π/4 π/4 –π/4 This is a measure of the offset vector introduced by the AD7010 as illustrated in Figure 7. The offset vector is calculated so as to minimize the rms error vector for each of the constellation points. Output Signal Range and Differential Output Range The output signal range is the output voltage swing and dc bias level for each of the analog outputs. The Differential Output Range is the difference between ITx and ITx for the I channel and the difference between QTx and QTx for the Q Channel. JDC Spurious Power Figure 8 shows the functional block diagram of the π/4 DQPSK modulator. The transmit serial data (TxDATA) is first converted into Di-bit symbols [Xk, Yk], using a 2-bit serial to parallel converter. The data is then differentially encoded; symbols are transmitted as changes in phase rather than absolute phases. Each symbol represents a phase change, as illustrated in Table II, and this along with the previously transmitted symbol determines the next symbol to be transmitted. The differential phase encoder generates I and Q impulses [Ik, Qk] in response to the Di-bit symbols according to: Ik = COS[φk–1 + ∆φk] Qk = SIN[φk–1 + ∆φk] π/4 DQPSK DIGITAL MODULATOR Xk TxDATA 2-BIT SERIAL TO PARALLEL CONVERTER Ik DIFFERENTIAL PHASE ENCODER Qk ROOT-RAISED 10 COSINE FILTER ROOT-RAISED 10 COSINE FILTER I DATA This is the rms sum of the spurious power measured at multiples of 25 kHz, in a rectangular window of ± 10.5 kHz, relative to twice the rms power in a RRC window in the 0 kHz to 10.5 kHz band. Signal Vector Magnitude This is the radius of the IQ constellation diagram as illustrated in Figure 7. Q ERROR VECTOR Yk Q DATA Figure 8. π/4 DQPSK Modulator Functional Block Diagram SIGNAL VECTOR Figure 9 illustrates the π/4 DQPSK constellation diagram as described above, showing the eight possible states for [Ik, Qk]. The Ik and Qk impulses are then filtered by FIR Root-Raised Cosine Filters (α = 0.5), generating 10-bit I and Q data. The FIR Root-Raised Cosine Filters have an impulse response of ± 4 symbols. Q I OFFSET VECTOR 0,0 Figure 7. CIRCUIT DESCRIPTION The transmit section of the AD7010 generates π/4 DQPSK I and Q waveforms in accordance with JDC specification. This is accomplished by a digital π/4 DQPSK modulator, which includes the Root-Raised Cosine filters (α = 0.5), followed by two 10-bit DACs and on-chip reconstruction filters. The π/4 DQPSK (Differential Quadrature Phase Shift Keying) digital modulator generates 10-bit I and Q data in response to the transmit data stream. The 10-bit I and Q DACs are filtered by on-chip reconstruction filters, which also generate differential analog outputs for both I and Q channels. The π/4 DQPSK modulator generates 10-bit I and Q data (Inphase and Quadrature) which are loaded into the I and Q 10-bit transmit DACs. /4 DQPSK Modulator TRANSMIT SECTION I Figure 9. π/4 DQPSK Constellation Diagram Transmit Calibration When the transmit section is brought out of sleep mode (Power high), the transmit section initiates a self-calibration routine to remove the offset between ITx and ITx and the offset between QTx and QTx. READY goes high on the completion of the selfcalibration routine. Once READY goes high, BIN (Burst In) can be brought high to initiate a transmit burst. –6– REV. B AD7010 Ramp-Up/Down Envelope Logic The AD7010 provides on-chip envelope shaping logic, providing power shaping control for the beginning and end of a transmit burst. When BIN (Burst In) is brought high, the modulator is reset to a transmitting all zeros state (i.e., Xk = Yk = 0) and continues to transmit all zeros for the first two symbols, during which the ramp-up envelope goes from zero to full scale as illustrated in Figure 10. The next symbol to be transmitted is [I1, Q1], which represents the first two data bits clocked in after BIN going high, i.e., [X1, Y1]. These are 4th order Bessel low-pass filters with a –3 dB frequency of approximately 22 kHz, the frequency response is illustrated in Figure 12. The filters are designed to have a linear phase response in the passband and due to the reconstruction filters being on-chip, the phase mismatch between the I and Q transmit channels is kept to a minimum. 0 –10 –20 MAGNITUDE – dBs –30 –40 –50 –60 –70 –80 0.1 1 10 FREQUENCY – kHz 100 1000 2 SYMBOLS 11 t – COS π 22 2T 2 SYMBOLS 1 1 t + COS π 2 2 2T Figure 10. Ramp Envelope When BIN is brought low, indicating the end of a transmit burst, the current Di-bit symbol [XN+4, YN+4] that the AD7010 is receiving will be the last symbol to be computed for the 4 symbol ramp-down sequence. Also the Nth symbol is the last active symbol prior to ramping down. However, because the impulse response is equal to ± 4 symbols, four additional symbols are required to fully compute the analog outputs when transmitting the (N+4)th symbol. Hence there will be eight subsequent TxCLKs, latching four additional Di-bit symbols: [XN+5, YN+5] to [XN+8, XN+8]. As Figure 11 illustrates, the ramp-down envelope reaches zero after two symbols, hence the third and fourth symbols do not actually get transmitted. Reconstruction Filters Figure 12. Reconstruction Filter Frequency Response for I and Q DACs, MCLK = 2.688 MHz Transmit Section Digital Interface MODE1 = MODE2 = DGND: Digital π/4 DQPSK Mode Figures 5 and 6 show the timing diagrams for the transmit interface when operating in JDC π/4 DQPSK mode. Power is sampled on the rising edge of MCLK. When Power is brought high, the transmit section is brought out of sleep mode and initiates a self-calibration routine as described above. Once the self-calibration is complete, the READY signal goes high to indicate that a transmit burst can now begin. BIN (Burst in) is brought high to initiate a transmit burst and should only be brought high if the READY signal is already high. The reconstruction filters smooth the DAC output signals, providing continuous time I and Q waveforms at the output pins. BIN TxCLK TxDATA X1 Y1 XN YN XN+1 YN+1 XN+2 YN+2 XN+3 YN+3 XN+4 YN+4 XN+5 YN+5 XN+6 YN+6 XN+7 YN+7 XN+8 YN+8 BOUT = 480 t1 (ITx–ITx), (QTx–QTx) 2 SYMBOL RAMP-UP ENVELOPE 2 SYMBOL RAMP-DOWN ENVELOPE SYMBOL PHASE MAX EFFECT 0 0 0 0 I1 Q1 IN QN IN+1 QN+1 IN+2 QN+2 IN+3 QN+3 IN+4 QN+4 Figure 11. Transmit Burst REV. B –7– AD7010 1.2 1.2 0.8 Q Channel – Volts Q Channel – Volts 0.8 0.4 0.4 0 0 –0.4 –0.4 –0.8 –0.8 –1.2 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 –1.2 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 I Channel – Volts I Channel – Volts Figure 13. AD7010 I vs. Q Waveforms when Transmitting Random Data 1.2 Figure 15. AD7010 Transmit Constellation Diagram 1.2 0.8 Q Channel – Volts Q Channel – Volts 0.8 0.4 0.4 0 0 –0.4 –0.4 –0.8 –0.8 –1.2 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 –1.2 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 I Channel – Volts I Channel – Volts Figure 14. AD7010 I vs. Q Waveforms Filtered by an Ideal Root Raised Cosine Receive Filter Figure 16. AD7010 Constellation Diagram when Filtered by an Ideal Root Raised Cosine Receive Filter When BIN goes high, the READY signal goes low on the next rising edge of MCLK and TxCLK becomes active after a further two MCLK cycles. TxCLK can be used to clock out the transmit data from the ASIC or DSP on the rising edge of TxCLK and the AD7010 will latch TxDATA on the falling edge of TxCLK. When BIN is brought low, the AD7010 will continue to clock in the current Di-bit symbol (XN+4, YN+4) and will continue for a further eight TxCLK cycles (four symbols). After the final TxCLK, READY goes high waiting for BIN to be brought high to begin the next transmit burst. When Power is brought low, this puts the transmit section into a low power sleep mode, drawing minimal current. The analog outputs go high impedance while in low power sleep mode. MODE1 = DGND; MODE2 = VDD: Frequency Test Mode A special FTEST (Frequency TEST) mode is provided for the customer, where no phase modulation takes place and the modulator outputs remain static. ITx is set to zero and QTx is set to full scale as Figure 2 illustrates. However, the normal ramp-up/down envelope is still applied during the beginning and end of a burst. MODE1 = VDD; MODE2 = DGND: Factory Test Mode MODE1 = MODE2 = VDD: Factory Test Mode These modes are reserved for factory test only and should not be used by the customer for correct device operation. –8– PIN 1 1 OUTLINE DIMENSIONS Dimensions are shown in inches and (mm). 24-Lead SSOP (RS-24) 24 13 0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64) 12 0.328 (8.33) 0.318 (8.08) 0.07 (1.78) 0.066 (1.67) 0.008 (0.203) 0.002 (0.050) 0.0256 (0.65) BSC 0.009 (0.229) 0.005 (0.127) 8° 0° 0.037 (0.94) 0.022 (0.559) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS REV. B PRINTED IN U.S.A. C1779a–5–7/94