4-Channel, I2C, Ultra Low Power,
12-Bit ADC in 20-Lead LFCSP/TSSOP
AD7091R-5
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
MUXOUT
VIN2
REGCAP
2.5V
VREF
VIN0
VIN1
REFIN/
REFOUT
VDD
ADCIN
INPUT
MUX
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
VIN3
ON-CHIP
OSC
CHANNEL
SEQUENCER
RESET
CONVST/GPO1
SDA
CONTROL
LOGIC
I2C INTERFACE
SCL
AS0
AS1
AD7091R-5
GND
VDRIVE
ALERT/BUSY/ GPO2 GND
GPO0
12093-001
I2C-compatible serial interface supports standard and
fast modes
Ultra low power: 90 µW typical at 3 V in fast mode
Specified for VDD of 2.7 V to 5.25 V
On-chip accurate 2.5 V reference, 5 ppm/°C typical drift
4 single-ended analog input channels
ALERT function
BUSY function
Autocycle mode
Wide input bandwidth
68 dB signal-to-noise ratio (SNR) typical at input
frequency of 1 kHz
Flexible power/throughput rate management
No pipeline delays
Power-down mode
550 nA typical at VDD = 5.25 V
435 nA typical at VDD = 3 V
20-lead LFCSP and TSSOP packages
Temperature range: −40°C to +125°C
Figure 1.
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
Diagnostic/monitoring functions
GENERAL DESCRIPTION
The AD7091R-5 is a 12-bit, multichannel, ultra low power, successive approximation analog-to-digital converter (ADC). The
AD7091R-5 operates from a single 2.7 V to 5.25 V power supply
and typically consumes only 24 µA at a 3 V supply in fast mode.
The AD7091R-5 provides a 2-wire serial interface compatible
with I2C interfaces. The conversion process can be controlled by
a sample mode via the CONVST/GPO1 pin, an autocycle mode
selected through software control, or a command mode in
which conversions occur across I2C write operations.
The device contains a wide bandwidth track-and-hold amplifier
that can handle input frequencies up to 1.5 MHz. The AD7091R-5
also features an on-chip conversion clock, an on-chip accurate
2.5 V reference, and a programmable out of bounds user alert
function.
Rev. A
The AD7091R-5 offers four single-ended analog input channels
with a channel sequencer that allows a preprogrammed
selection of channels to be converted sequentially.
The AD7091R-5 uses advanced design techniques to achieve
ultra low power dissipation without compromising performance. It
also features flexible power management options. An on-chip
configuration register allows the user to set up different operating
conditions. These include power management, alert functionality,
busy indication, channel sequencing, and general-purpose output
pins. The MUXOUT and ADCIN pins allow signal conditioning of the
multiplexer output before acquisition by the ADC.
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AD7091R-5
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
I2C Register Access ..................................................................... 19
Applications ....................................................................................... 1
Conversion Result Register ....................................................... 20
Functional Block Diagram .............................................................. 1
Channel Register ........................................................................ 21
General Description ......................................................................... 1
Configuration Register .............................................................. 22
Revision History ............................................................................... 2
Alert Indication Register ........................................................... 24
Specifications..................................................................................... 3
Channel x Low Limit Register .................................................. 26
I C Timing Specifications ............................................................ 5
Channel x High Limit Register ................................................. 26
2
Absolute Maximum Ratings............................................................ 6
Channel x Hysteresis Register .................................................. 26
Thermal Resistance ...................................................................... 6
I C Interface .................................................................................... 27
ESD Caution .................................................................................. 6
Serial Bus Address Byte ............................................................. 27
Pin Configurations and Function Descriptions ........................... 7
General I2C Timing .................................................................... 27
Typical Performance Characteristics ............................................. 9
Writing to the AD7091R-5 ............................................................ 28
Terminology .................................................................................... 14
Writing Two Bytes of Data to a 16-Bit Register ..................... 28
Theory of Operation ...................................................................... 15
Writing to Multiple Registers.................................................... 28
Circuit Information .................................................................... 15
Reading Data from the AD7091R-5............................................. 29
Converter Operation .................................................................. 15
Reading Two Bytes of Data from a 16-Bit Register ............... 29
ADC Transfer Function ............................................................. 15
Modes of Operation ....................................................................... 30
Reference ..................................................................................... 15
Sample Mode .............................................................................. 30
Power Supply ............................................................................... 16
Command Mode ........................................................................ 30
Device Reset ................................................................................ 16
Autocycle Mode .......................................................................... 32
Analog Input ............................................................................... 16
Power-Down Mode .................................................................... 32
Driver Amplifier Choice ............................................................ 17
Alert ............................................................................................. 33
Typical Connection Diagram ................................................... 17
Busy .............................................................................................. 33
I C Registers .................................................................................... 19
Channel Sequencer .................................................................... 33
Addressing Registers .................................................................. 19
Outline Dimensions ....................................................................... 34
Slave Address............................................................................... 19
Ordering Guide .......................................................................... 34
2
2
REVISION HISTORY
2/2018—Rev. 0 to Rev. A
Changes to Command Mode Section and Figure 43 ................. 31
Updated Outline Dimensions ....................................................... 34
Changes to Ordering Guide .......................................................... 34
7/2015—Revision 0: Initial Version
Rev. A | Page 2 of 34
Data Sheet
AD7091R-5
SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, fSCL = 400 kHz, fast SCL mode, VREF = 2.5 V internal/external, TA = −40°C to +125°C,
unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Signal-to-Noise-and-Distortion Ratio
(SINAD)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Channel to Channel Isolation
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Offset Error Matching
Offset Error Drift
Gain Error
Gain Error Matching
Gain Error Drift
ANALOG INPUT
Input Voltage Range 1
DC Leakage Current
Input Capacitance 2
Multiplexer On Resistance
VOLTAGE REFERENCE INPUT/OUTPUT
REFOUT 3
REFIN3
Drift
Power-On Time
LOGIC INPUTS
Input Voltage
High (VIH)
Low (VIL)
Input Current (IIN)
LOGIC OUTPUTS
Output Voltage
High (VOH)
Low (VOL)
Floating State Leakage Current
Output Coding
Test Conditions/Comments
fIN = 1 kHz sine wave
Min
Typ
At −3 dB
At −0.1 dB
Guaranteed no missing codes to 12 bits
TA = 25°C
TA = 25°C
12
−1.25
−0.9
−1.5
−1.5
TA = 25°C
TA = 25°C
−0.1
−0.1
At ADCIN
0
−1
Internal reference output, TA = 25°C
External reference input
dB
dB
−80
−81
−105
5
40
1.5
1.2
dB
dB
dB
ns
ps
MHz
MHz
+1.25
+0.9
+1.5
+1.5
+0.1
+0.1
2.5
V
µA
pF
pF
Ω
Ω
2.51
VDD
V
V
ppm/°C
ms
5
50
CREF = 2.2 µF
0.7 × VDRIVE
VIN = 0 V or VDRIVE
−1
ISOURCE = 200 µA
ISINK = 200 µA
VDRIVE − 0.2
−1
Rev. A | Page 3 of 34
0.01
Bits
LSB
LSB
mV
mV
ppm/°C
% FS
% FS
ppm/°C
VREF
+1
10
1.5
50
100
2.49
1.0
Unit
68
67
±0.8
±0.3
±0.3
±0.3
2
0.0
0.0
1
During acquisition phase
Outside acquisition phase
VDD = 5.0 V
VDD = 2.5 V
Max
0.3 × VDRIVE
+1
0.4
+1
Straight (natural) binary
V
V
µA
V
V
µA
AD7091R-5
Parameter
CONVERSION RATE
Conversion Time
Update Rate
Autocycle Setting 00
Autocycle Setting 01
Autocycle Setting 10
Autocycle Setting 11
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE Range
IDD
Normal Mode—Static
Normal Mode—Operational
Power-Down Mode
IDRIVE
Normal Mode—Static
Normal Mode—Operational
Total Power Dissipation 4
Normal Mode—Static
Normal Mode—Operational
Power-Down Mode
Data Sheet
Test Conditions/Comments
Min
Typ
Max
550
90
180
360
720
100
200
400
800
ns
110
220
440
880
22.22
μs
μs
μs
μs
kSPS
5.25
5.25
V
V
22
21.6
26
24
25
23
70
0.550
0.550
0.435
50
46
55
52
54
51
105
17
8
15
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
2
1
6
5
5
4
4
3.5
15
14
14
13
µA
µA
µA
µA
µA
µA
130
70
170
90
160
85
210
3
3
1.4
290
150
370
200
360
195
315
95
33
50
µW
µW
µW
µW
µW
µW
µW
µW
µW
µW
fSCL = 400 kHz, command mode
2.7
1.8
VIN = 0 V
VDD = 5.25 V
VDD = 3 V
VDD = 5.25 V, fSCL = 400 kHz
VDD = 3 V, fSCL = 400 kHz
VDD = 5.25 V, fSCL = 100 kHz
VDD = 3 V, fSCL = 100 kHz
VDD = 3 V, autocycle mode
VDD = 5.25 V
VDD = 5.25 V, TA = −40°C to +85°C
VDD = 3 V
VIN = 0 V
VDRIVE = 5.25 V
VDRIVE = 3 V
VDRIVE = 5.25 V, fSCL = 400 kHz
VDRIVE = 3 V, fSCL = 400 kHz
VDRIVE = 5.25 V, fSCL = 100 kHz
VDRIVE = 3 V, fSCL = 100 kHz
VIN = 0 V
VDD = VDRIVE = 5.25 V
VDD = VDRIVE = 3 V
VDD = VDRIVE = 5.25 V, fSCL = 400 kHz
VDD = VDRIVE = 3 V, fSCL = 400 kHz
VDD = VDRIVE = 5.25 V, fSCL = 100 kHz
VDD = VDRIVE = 3 V, fSCL = 100 kHz
VDD = VDRIVE = 3 V, autocycle mode
VDD = 5.25 V
VDD = 5.25 V, TA = −40°C to +85°C
VDD = VDRIVE = 3 V
Unit
The multiplexer input voltage must not exceed VDD.
Sample tested during initial release to ensure compliance.
3
When referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, see the Pin Configurations and Function Descriptions section.
4
Total power dissipation includes contributions from VDD, VDRIVE, and REFIN (see Note 3).
1
2
Rev. A | Page 4 of 34
Data Sheet
AD7091R-5
I2C TIMING SPECIFICATIONS
All values measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with rise time and fall time measured
between 0.3 × VDRIVE and 0.7 × VDRIVE (see Figure 2). VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, VREF = 2.5 V internal/external, TA =
TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
fSCL
Min
t1
4
0.6
4.7
1.3
250
100
0
0
4.7
0.6
4
0.6
4.7
1.3
4
0.6
t2
t3
t4 1
t5
t6
t7
t8
Limit at TMIN, TMAX
Typ Max
100
400
3.45
0.9
t9
1000
300
300
300
1000
300
1000
300
300
300
50
20 + 0.1CB
t10
20 + 0.1CB
t11
20 + 0.1CB
t11A
20 + 0.1CB
t12
tSP
tRESETPW
tRESET_DELAY
Description
Serial clock frequency, standard mode
Fast mode
SCL high time, standard mode
Fast mode
SCL low time, standard mode
Fast mode
Data setup time, standard mode
Fast mode
Data hold time, standard mode
Fast mode
Setup time for a repeated start condition, standard mode
Fast mode
Hold time for a repeated start condition, standard mode
Fast mode
Bus-free time between a stop and a start condition, standard mode
Fast mode
Setup time for a stop condition, standard mode
Fast mode
Rise time of the SDA signal, standard mode
Fast mode
Fall time of the SDA signal, standard mode
Fast mode
Rise time of the SCL signal, standard mode
Fast mode
Rise time of the SCL signal after a repeated; not shown in Figure 2, standard mode
Start condition and after an acknowledge bit, fast mode
Fall time of the SCL signal, standard mode
Fast mode
Pulse width of the suppressed spike; not shown in Figure 2, fast mode
RESET pulse width (see Figure 35)
RESET pulse delay upon power-up (see Figure 35)
A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
t2
t11
t12
t6
SCL
t6
t4
t1
t3
t5
t8
t9
t10
SDA
P
t7
S
S
P
12093-002
1
20 + 0.1CB
0
10
50
Unit
kHz
kHz
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S = START CONDITION
P = STOP CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. A | Page 5 of 34
AD7091R-5
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 3.
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
VDD to GND
VDRIVE to GND
Analog Input Voltage to GND
Digital Input1 Voltage to GND
Digital Output2 Voltage to GND
Input Current to Any Pin Except
Supplies3
Operating Temperature Range
Storage Temperature Range
Junction Temperature
ESD
Human Body Model (HBM)
Field Induced Charged Device
Model (FICDM)
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VREF + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
Table 4. Thermal Resistance
Package Type
20-Lead LFCSP_WQ
20-Lead TSSOP
ESD CAUTION
±10 mA
−40°C to +125°C
−65°C to +150°C
150°C
1.5 kV
500 V
The digital input pins include the following: AS0, RESET, AS1, SCL, SDA,
and CONVST/GPO1.
2
The digital output pins include: ALERT/BUSY/GPO0, GPO2, and SDA.
3
Transient currents of up to 100 mA do not cause SCR latch-up.
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 6 of 34
θJA
52
84.3
θJC
6.5
18.4
Unit
°C/W
°C/W
Data Sheet
AD7091R-5
16 SCL
17 CONVST/GPO1
19 AS0
18 VDRIVE
20 RESET
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AS0 1
20
RESET 2
19
CONVST/GPO1
VDD 1
15 SDA
VDD 3
18
SCL
REGCAP 2
14 AS1
17
SDA
REFIN/REFOUT 3
16
AS1
GND 4
15
GND
MUXOUT 7
14
ADCIN
VIN0 8
13
VIN1
VIN2 9
12
VIN3
ALERT/BUSY/GPO0 10
11
GPO2
13 GND
12 ADCIN
11 VIN1
NOTES
1. EXPOSED PAD. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. IT IS RECOMMENDED THAT THE PAD BE
SOLDERED TO GND.
Figure 3. Pin Configuration, 20-Lead TSSOP
12093-003
VIN3 10
GPO2 9
MUXOUT 5
ALERT/BUSY/GPO0 8
GND 6
TOP VIEW
(Not to Scale)
VIN2 7
TOP VIEW
(Not to Scale)
AD7091R-5
VIN0 6
REFIN/REFOUT 5
AD7091R-5
12093-004
REGCAP 4
VDRIVE
Figure 4. Pin Configuration, 20-Lead LFCSP
Table 5. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
1
19
Mnemonic
AS0
2
3
4
20
1
2
RESET
VDD
REGCAP
5
3
REFIN/REFOUT
6, 15
7
4, 13
5
GND
MUXOUT
8
9
10
6
7
8
VIN0
VIN2
ALERT/BUSY/GPO0
11
12
13
14
9
10
11
12
GPO2
VIN3
VIN1
ADCIN
Description
I2C Address Bit 0. Together with AS1, the logic state of these two inputs selects a unique I2C
address for the AD7091R-5. The device address depends on the logic state of these pins.
Reset. Logic input. This pin resets the device when pulled low.
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
Decoupling Capacitor Pin for Voltage Output from the Internal Regulator. Decouple this output
pin separately to GND using a 2.2 µF capacitor.
Voltage Reference Output, 2.5 V. Decouple this pin to GND. The typical recommended
decoupling capacitor value is 2.2 µF. The user can either access the internal 2.5 V reference or
overdrive the internal reference with the voltage applied to this pin. The reference voltage range for
an externally applied reference is 1.0 V to VDD.
Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-5.
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or
buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the
conditioning network to the ADCIN pin.
Analog Input for Channel 0. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input for Channel 2. Single-ended analog input. The analog input range is 0 V to VREF.
This is a multifunction pin determined by the configuration register.
Alert Output Pin (ALERT). When functioning as ALERT, this pin is a logic output indicating that a
conversion result has fallen outside the limit of the register settings.
Busy Output (BUSY). The BUSY pin indicates when a conversion is taking place.
General-Purpose Digital Output 0 (GPO0).
General-Purpose Digital Output 2.
Analog Input for Channel 3. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input for Channel 1. Single-ended analog input. The analog input range is 0 V to VREF.
ADC Input. This pin allows direct access to the ADC. If no external filtering or buffering is
required, tie this pin directly to the MUXOUT pin; otherwise, tie the input of the conditioning
network to the MUXOUT pin.
Rev. A | Page 7 of 34
AD7091R-5
Data Sheet
Pin No.
TSSOP
LFCSP
16
14
Mnemonic
AS1
17
15
SDA
18
16
SCL
19
17
CONVST/GPO1
20
18
VDRIVE
N/A 1
21
EPAD
1
Description
I2C Address Bit 1. Together with AS0, the logic state of these two inputs selects a unique I2C
address for the AD7091R-5. The device address depends on the logic state of these pins.
Serial Data Input/Output. This open-drain output requires a pull-up resistor. The output coding is
straight binary for the voltage channels.
Digital Input Serial I2C Bus Clock. This input requires a pull-up resistor. The data transfer rate in I2C
mode is compatible with both 100 kHz (standard mode) and 400 kHz (fast mode) operating
modes.
This is a multifunction pin determined by the configuration register and mode of conversion.
Convert Start Input Signal (CONVST). Edge triggered logic input. The falling edge of CONVST
places the ADC into hold mode and initiates a conversion. The logic level of CONVST at EOC
controls the power modes of the AD7091R-5.
General-Purpose Digital Output 1 (GPO1). When in command or autocycle mode, this pin can
function as a general-purpose digital output.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the
interface operates. Connect decoupling capacitors between VDRIVE and GND. The typical
recommended values are 10 µF and 0.1 µF. The voltage range on this pin is 1.8 V to 5.25 V and
may differ from the voltage range at VDD, but must never exceed it by more than 0.3 V.
Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be
soldered to GND.
N/A means not applicable.
Rev. A | Page 8 of 34
Data Sheet
AD7091R-5
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
–0.2
–0.4
–0.4
VDD = 3.0V
VREF = 2.5V
fSCL = 400kHz
TA = 25°C
POSITIVE INL = +0.43 LSB
NEGATIVE INL = –0.66 LSB
–0.6
–0.8
–1.0
0
512
1024
1536
0
–0.2
VDD = 3.0V
VREF = 2.5V
–0.6
fSCL = 400kHz
TA = 25°C
POSITIVE DNL = +0.41 LSB
NEGATIVE DNL = –0.41 LSB
–0.8
2048
2560
3072
3584
4095
CODE
–1.0
0
512
1024
VDD = 5.25V
0.8 VREF = EXTERNAL
fSCL = 400kHz
0.6 TA = 25°C
0.2
DNL (LSB)
4095
0
–0.2
0.2
0
–0.2
–0.4
MIN INL (LSB)
MIN DNL (LSB)
–0.6
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
REFERENCE INPUT VOLTAGE (V)
5.5
Figure 6. Minimum/Maximum INL vs. External Reference Input Voltage
7000
6000
VDD = VDRIVE = 3.3V
VREF = 2.5V
8192 SAMPLES
TA = 25°C
5000
3000
2000
1000
684
0
2028
2029
2030
CODE
3.0
3.5
4.0
4.5
5.0
5.5
4000
4353
3762
3500
3000
2500
2000
1500
1000
500
0
12093-206
290
2.5
VDD = VDRIVE = 3.3V
VREF = 2.5V
8192 SAMPLES
TA = 25°C
4500
4000
2.0
Figure 9. Minimum/Maximum DNL vs. External Reference Input Voltage
7218
5000
1.5
REFERENCE INPUT VOLTAGE (V)
NUMBER OF OCCURRENCES
8000
–1.0
1.0
12093-231
–1.0
1.0
12093-234
–0.8
50
27
2042
2043
2044
2045
CODE
Figure 10. Histogram of a DC Input at Code Transition
Figure 7. Histogram of a DC Input at Code Center
Rev. A | Page 9 of 34
12093-209
INL (LSB)
3584
MAX DNL (LSB)
0.4
MAX INL (LSB)
–0.8
NUMBER OF OCCURRENCES
3072
1.0
VDD = 5.25V
0.8 VREF = EXTERNAL
fSCL = 400kHz
0.6 TA = 25°C
–0.6
2560
Figure 8. DNL vs. Code
1.0
–0.4
2048
CODE
Figure 5. INL vs. Code
0.4
1536
12093-208
DNL (LSB)
1.0
12093-205
INL (LSB)
TYPICAL PERFORMANCE CHARACTERISTICS
AD7091R-5
Data Sheet
–60
–80
–100
–120
69
11.3
68
11.1
67
10.9
66
10.7
65
10.5
VDD = 3.0V
VREF = EXTERNAL
10.3
fSCL = 400kHz
fIN = 1kHz
SIGNAL AMPLITUDE = –0.5dB 10.1
TA = 25°C
9.9
3.0
3.5
4.0
4.5
5.0
64
–140
63
0
2000
4000
6000
8000
10000
FREQUENCY (Hz)
12093-207
62
1.0
–70
–40
–60
–74
–76
–80
–100
–78
–80
–82
–84
–120
–86
–140
–88
0
2000
4000
6000
8000
10000
FREQUENCY (Hz)
–90
12093-210
–160
VDD = 3.3V
VREF = 2.5V
SIGNAL AMPLITUDE = –0.5dB
fSCL = 400kHz
TA = 25°C
–72
THD (dB)
ADC OUTPUT SPECTRUM (dB)
Figure 14. SNR, SINAD, and ENOB vs. Reference Input Voltage
VDD = VDRIVE = 3.3V
VREF = 2.5V INTERNAL
fIN = 1kHz
fSAMPLE = 22.2kSPS
fSCL = 400kHz
SNR = 68.4dB
SINAD = 68.2dB
THD = –83.3dB
SFDR = –87.9dB
–20
2.5
REFERENCE INPUT VOLTAGE (V)
Figure 11. 10 kHz FFT, VDD = 3.0 V, VREF = 2.5 V External
0
2.0
1.5
1
10
100
ANALOG INPUT FREQUENCY (kHz)
Figure 12. 10 kHz FFT, VDD = 3.0 V, VREF = 2.5 V Internal
70
12093-109
–160
11.5
ENOB (Bits)
–40
11.7
SNR
SINAD
ENOB
70
SNR, SINAD (dB)
–20
ADC OUTPUT SPECTRUM (dB)
71
VDD = VDRIVE = 3.3V
VREF = 2.5V EXTERNAL
TA = 25°C
fIN = 1kHz
fSAMPLE = 22.2kSPS
fSCL = 400kHz
SNR = 68.3dB
SINAD = 68.2dB
THD = –85.3dB
SFDR = –88.2dB
12093-213
0
Figure 15. THD vs. Analog Input Frequency
70.0
SNR
SINAD
69.5
69
SNR (dB)
68.5
67
1
10
INPUT FREQUENCY (kHz)
66.5
100
Figure 13. SNR, SINAD vs. Input Frequency
VDD = 3.0V
VREF = 2.5V
fSCL = 400kHz
fIN = 1kHz
TA = 25°C
66.0
–10
–9
–8
–7
–6
–5
–4
–3
INPUT LEVEL (dB)
Figure 16. SNR vs. Input Level
Rev. A | Page 10 of 34
–2
–1
0
12093-215
67.0
VDD = 3.3V
VREF = 2.5V
SIGNAL AMPLITUDE = –0.5dB
fSCL = 400kHz
TA = 25°C
65
64
68.0
67.5
66
12093-108
SNR, SINAD (dB)
69.0
68
Data Sheet
–81
–83
–85
–87
–89
–91
–95
1.0
1.5
2.0
3.0
2.5
3.5
4.0
4.5
5.0
REFERENCE INPUT VOLTAGE (V)
TOTAL POWER-DOWN CURRENT (µA)
–82
–83
25
20
15
–84
–85
VDD = 5.0V
fSCL = 400kHz
fIN = 1kHz
–88
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 18. THD vs. Temperature
5.25V
5.0V
3.3V
2.7V
6
5
4
3
2
1
25
–40
85
125
Figure 21. Total Power-Down Current vs. Temperature for Various Supply
Voltages
2.510
VDD = 3.0V
VREF = 2.5V
fSCL = 400kHz
fIN = 1kHz
–55°C
–40°C
+25°C
+85°C
+125°C
VDD = VDRIVE = 3.0V
68.6
2.505
VREF (V)
68.0
67.8
2.500
67.6
2.495
67.4
67.2
67.0
–55
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
12093-122
SNR (dB)
125
TEMPERATURE (°C)
68.8
68.2
85
7
0
12093-129
–89
68.4
25
2.490
0
10
20
30
40
50
60
70
CURRENT LOAD (µA)
80
90
100
Figure 22. Reference Voltage Output (VREF) vs. Current Load
for Various Temperatures
Figure 19. SNR vs. Temperature
Rev. A | Page 11 of 34
12093-223
THD (dB)
30
8
–81
–90
–55
35
Figure 20. Operational IDD Supply Current vs. Temperature
for Various VDD Supply Voltages
–80
–87
40
TEMPERATURE (°C)
Figure 17. THD, SFDR vs. Reference Input Voltage
–86
2.70V
3.00V
5.25V
VDD = 3.0V
VREF = INTERNAL 2.5V
fSCL = 400kHz
10
–55
12093-216
–93
45
12093-220
–79
THD, SFDR (dB)
50
VDD = 3.0V
VREF = EXTERNAL
fSCL = 400kHz
fIN = 1kHz
SIGNAL AMPLITUDE = –0.5dB
TA = 25°C
12093-127
–77
THD
SFDR
OPERATIONAL IDD SUPPLY CURRENT (µA)
–75
AD7091R-5
AD7091R-5
1.5
VDD = 3.0V
VREF = 2.5V
fSCL = 400kHz
OFFSET
OFFSET
OFFSET
OFFSET
0.10
ERROR CH 0
ERROR CH 1
ERROR CH 2
ERROR CH 3
VDD = 3.0V
VREF = 2.5V
fSCL = 400kHz
0.08
0.06
GAIN ERROR (% FS)
1.0
OFFSET ERROR (mV)
Data Sheet
0.5
0
–0.5
GAIN ERROR CH 0
GAIN ERROR CH 1
GAIN ERROR CH 2
GAIN ERROR CH 3
0.04
0.02
0
–0.02
–0.04
–0.06
–1.0
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
–0.10
–55
–35
25
45
65
105
125
105
125
85
Figure 26. Gain Error vs. Temperature
0.10
VDD = 3.0V
VREF = 2.5V
fSCL = 400kHz
VDD = 3.0V
VREF = 2.5V
fSCL = 400kHz
0.08
GAIN ERROR MATCH (% FS)
OFFSET ERROR MATCH (mV)
1.0
5
TEMPERATURE (°C)
Figure 23. Offset Error vs. Temperature
1.5
–15
12093-227
–35
12093-224
–1.5
–55
12093-328
–0.08
0.5
0
–0.5
–1.0
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
–0.10
–55
12093-325
–1.5
–55
45
65
85
VDD = 3.0V
VREF = 2.5V
fSCL = 400kHz
TA = 25°C
10k
100k
RIPPLE FREQUENCY (Hz)
1M
Figure 25. PSRR vs. Ripple Frequency
VDD = 3.0V
fSAMPLE = 22.22kSPS
f
= 400kHz
–85 SCL
TA = 25°C
–90
–95
–100
–105
–110
1
10
100
INPUT FREQUENCY (kHz)
Figure 28. Channel to Channel Isolation vs. Input Frequency
Rev. A | Page 12 of 34
12093-229
CHANNEL TO CHANNEL ISOLATION (dB)
INTERNAL REFERENCE
12093-326
PSRR (dB)
EXTERNAL REFERENCE
85
75
1k
25
–80
90
80
5
Figure 27. Gain Error Match vs. Temperature
105
95
–15
TEMPERATURE (°C)
Figure 24. Offset Error Match vs. Temperature
100
–35
Data Sheet
2.510
–89
–91
–93
–95
–97
–99
–101
–103
–105
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 29. Channel to Channel Isolation vs. Temperature
–50
–55
TA = 25°C
VDD = 3V
fIN = 10kHz
fSCL = 400kHz
–70
–75
–80
100
1k
SOURCE IMPEDANCE (Ω)
10k
12093-110
THD (dB)
–65
10
2.500
2.495
2.490
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE (°C)
Figure 31. Internal Reference Voltage vs. Temperature
–60
–85
2.505
Figure 30. THD vs. Source Impedance
Rev. A | Page 13 of 34
125
12093-135
–87
INTERNAL REFERENCE VOLTAGE (V)
VDD = 3.0V
fSAMPLE = 22.22kSPS
fSCL = 400kHz
fIN = 1kHz
12093-230
CHANNEL TO CHANNEL ISOLATION (dB)
–85
AD7091R-5
AD7091R-5
Data Sheet
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. For the
AD7091R-5, the endpoints of the transfer function are zero
scale, a point ½ LSB below the first code transition, and full
scale, a point ½ LSB above the last code transition.
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Offset Error
The offset error is the deviation of the first code transition
(00 … 000 to 00 … 001) from the ideal (such as GND + 0.5 LSB).
Offset Error Match
Offset error match is the difference in offset error between any
two input channels.
Gain Error
For the AD7091R-5, the gain error is the deviation of the last
code transition (111 … 110 to 111 … 111) from the ideal (such
as VREF − 1.5 LSB) after the offset error has been adjusted out.
Gain Error Match
Gain error match is the difference in gain error between any
two input channels.
Transient Response Time
The track-and-hold amplifier returns to track mode after the
end of conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±0.5 LSB, after the end of conversion.
See the I2C Interface section for more details.
Channel to Channel Isolation
Channel to channel isolation is a measure of the level of crosstalk
between the selected channel and all the other channels. It is
measured by applying a full-scale, 10 kHz sine wave signal to all
unselected input channels and determining the degree to which
the signal attenuates in the selected channel that has a dc signal
applied to it. Figure 28 shows the worst case across all channels
for the AD7091R-5.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental.
For the AD7091R-5, it is defined as
THD (dB ) = 20 log
V2 2 + V3 2 + V4 2 + V5 2 + V6 2
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum; however,
for ADCs where the harmonics are buried in the noise floor, it
is a noise peak.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the measured ratio of the signal-to-noise-and-distortion
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical SINAD for an ideal N-bit converter with
a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02N + 1.76) (dB)
Thus, for a 12-bit converter, the SINAD ratio is 74 dB.
Rev. A | Page 14 of 34
Data Sheet
AD7091R-5
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7091R-5 is a 12-bit, ultra low power single-supply ADC.
The device operates from a 2.7 V to 5.25 V supply. The AD7091R-5
can function in both standard and fast I2C operating modes.
The AD7091R-5 provides a 4:1 multiplexer and an on-chip,
track-and-hold amplifier, and is housed in either a 20-lead
LFCSP or 20-lead TSSOP package. These packages offer considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the device. An internally generated clock is implemented to control the successive
approximation ADC. The reference voltage for the AD7091R-5
is provided externally or is generated internally by an accurate
on-chip reference source. The analog input range for the
AD7091R-5 is 0 V to VREF.
When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B, causing the comparator to become unbalanced (see
Figure 33). Using the control logic, the charge redistribution DAC
adds and subtracts fixed amounts of charge from the sampling
capacitor to bring the comparator back into a balanced condition.
When the SAR decisions are made, the comparator inputs are
rebalanced. From these SAR decisions, the control logic
generates the ADC output code.
ADC TRANSFER FUNCTION
The output coding of the AD7091R-5 is straight binary. The
designed code transitions occur midway between successive
integer LSB values, such as ½ LSB and 1½ LSB. The LSB size for the
AD7091R-5 is VREF/4096. The ideal transfer characteristic for
the AD7091R-5 is shown in Figure 34.
The AD7091R-5 also features a power-down option to save
power between conversions. The power-down feature is
accessed through the standard serial interface as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7091R-5 is a successive approximation ADC based on a
charge redistribution digital-to-analog converter (DAC). Figure 32
and Figure 33 show simplified schematics of the ADC. Figure 32
shows the ADC during its acquisition phase. When Switch 2 (SW2)
is closed and Switch 1 (SW1) is in Position A, the comparator is
held in a balanced condition, and the sampling capacitor
acquires the signal on ADCIN.
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
A
SW1
B
ACQUISITION
PHASE
CONTROL
LOGIC
SW2
COMPARATOR
GND
12093-015
ADCIN
VDD/2
Figure 32. ADC Acquisition Phase
SAMPLING
CAPACITOR
SW1
B
CONVERSION
PHASE
GND
CONTROL
LOGIC
SW2
COMPARATOR
VDD/2
12093-016
ADCIN
1LSB = VREF /4096
011...111
000...010
000...001
000...000
0V 1LSB
ANALOG INPUT
+VREF – 1LSB
Figure 34. Transfer Characteristic
REFERENCE
The AD7091R-5 can operate with either the internal 2.5 V on-chip
reference or an externally applied reference. The logic state of
the P_DOWN LSB bit in the configuration register determines
whether the internal reference is used. The internal reference is
selected for the ADCs when the P_DOWN LSB bit is set to 1.
When the P_DOWN LSB bit is set to 0, supply an external
reference in the range of 2.5 V to VDD through the REFIN/
REFOUT pin. At power-up, the internal reference disables by
default.
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When operating the AD7091R-5
in internal reference mode, the 2.5 V internal reference is available
at the REFIN/REFOUT pin, which is typically decoupled to GND
using a 2.2 µF capacitor. It is recommended to buffer the internal
reference before applying it elsewhere in the system.
CHARGE
REDISTRIBUTION
DAC
A
111...000
12093-017
ADC CODE
111...111
111...110
The reference buffer requires 50 ms to power up and charge the
2.2 µF decoupling capacitor.
Figure 33. ADC Conversion Phase
Rev. A | Page 15 of 34
AD7091R-5
Data Sheet
POWER SUPPLY
ANALOG INPUT
The AD7091R-5 uses two power supply pins: a core supply (VDD)
and a digital input/output interface supply (VDRIVE). VDRIVE allows
direct interfacing with any logic between 1.8 V and 5.25 V. To
reduce the number of supplies needed, VDRIVE and VDD can be
tied together depending upon the logic levels of the system. The
AD7091R-5 is independent of power supply sequencing between
VDRIVE and VDD. Additionally, the AD7091R-5 is insensitive to
power supply variations over a wide frequency range, as shown
in Figure 25.
Figure 36 shows an equivalent circuit of the analog input structure
of the AD7091R-5. The two diodes, D1 and D2, provide ESD
protection for the analog input. Ensure that the analog input
signal never exceeds the supply rails by more than 300 mV
because this causes these diodes to become forward-biased and
start conducting current into the substrate. These diodes can
conduct a maximum of 10 mA without causing irreversible
damage to the device.
REFIN/
VDD REFOUT
D1
VINx
C1
400fF
Table 6. Recommended Power Management Devices1
Product
ADP7102
ADM7160
ADP162
1
Description
20 V, 300 mA, low noise, CMOS LDO
Ultralow noise, 200 mA linear regulator
Ultralow quiescent current, CMOS linear regulator
For the latest recommended power management devices, see the AD7091R-5
product page.
DEVICE RESET
Upon power-up, a reset pulse of at least 10 ns in width must be
provided on the RESET pin to ensure proper initialization of
the device. Failure to apply the reset pulse may result in a device
malfunction. See Figure 35 for reset pulse timing relative to
power supply establishment.
At any time, the RESET pin can reset the device and the
contents of all internal registers, including the command register,
to their default state. To activate the reset operation, bring
the RESET pin low for a minimum of 10 ns while it is
asynchronous to the SCL signal. It is imperative that the RESET
pin be held at a stable logic level at all times to ensure normal
operation.
tRESET_DELAY
VDD
RESET
tRESETPW
Figure 35. RESET Pin Power Up Timing
12093-141
VDRIVE
D3
C2
R1 3.6pF
500Ω
D2
CONVERSION PHASE SWITCH OPEN
TRACK PHASE SWITCH CLOSED
12093-019
The AD7091R-5 powers down automatically at the end of each
conversion phase; therefore, the power scales linearly with the
sampling rate. The automatic power-down feature makes the
AD7091R-5 device ideal for low sampling rates (of even a few
hertz) and battery-powered applications.
Figure 36. Equivalent Analog Input Circuit
The C1 capacitor in Figure 36 is typically approximately 400 fF
and can primarily be attributed to pin capacitance. The R1 resistor
is a lumped component made up of the on resistance of a switch.
This resistor is typically approximately 500 Ω. The C2 capacitor
is the ADC sampling capacitor and typically has a capacitance of
3.6 pF.
In applications where harmonic distortion and SNR are critical,
drive the analog inputs from low impedance sources. Large source
impedances significantly affect the ac performance of the ADC,
which can necessitate using input buffer amplifiers, as shown in
Figure 37. The choice of the op amp is a function of the
particular application.
When no amplifiers are driving the analog input, limit the source
impedance to low values. The maximum source impedance depends
on the amount of THD that can be tolerated. The THD increases
as the source impedance increases and performance degrades.
Use an external filter on the analog input signal paths to the
AD7091R-5 VINx pins to achieve the specified performance.
This filter can be a one-pole, low-pass RC filter or similar.
Connect the MUXOUT pin directly to the ADCIN pin. Insert a buffer
amplifier in the path, if desired. When sequencing channels, do
not place a filter between MUXOUT and the input to any buffer
because doing so leads to crosstalk. If a buffer is not implemented,
do not place a filter between MUXOUT and ADCIN when sequencing
channels because doing so leads to crosstalk.
Rev. A | Page 16 of 34
Data Sheet
AD7091R-5
DRIVER AMPLIFIER CHOICE
TYPICAL CONNECTION DIAGRAM
Although the AD7091R-5 is easy to drive, a driver amplifier
must meet the following requirements:
Figure 37 and Figure 38 show typical connection diagrams for the
AD7091R-5.
•
Connect a positive power supply in the 2.7 V to 5.25 V range to
the VDD pin. The typical values for the VDD decoupling capacitors
are 100 nF and 10 µF. Place these capacitors as close as possible
to the device pins. Take care to decouple the REFIN/REFOUT pin
to achieve specified performance. The typical value for the
REFIN/REFOUT capacitor is 2.2 µF, which provides an analog input
range of 0 V to VREF. The typical value for the regulator bypass
(REGCAP) decoupling capacitor is 1 µF. The voltage applied to the
VDRIVE input controls the voltage of the serial interface; therefore,
connect this pin to the supply voltage of the microprocessor. Set
VDRIVE in the 1.8 V to 5.25 V range. The typical values for the
VDRIVE decoupling capacitors are 100 nF and 10 µF. The 16-bit
conversion result (3 address bits, 1 alert bit, and 12 data bits) is
output in 2 bytes with the most significant byte (MSBs)
presented first.
Keep the noise generated by the driver amplifier as low as
possible to preserve the SNR and transition noise performance
of the AD7091R-5. The noise from the driver is filtered by
the one-pole, low-pass filter of the AD7091R-5 analog input
circuit, made by R1 and C2, or by the external filter, if one
is used. Because the typical noise of the AD7091R-5 is 350 µV
rms, the SNR degradation due to the amplifier is
SNR LOSS
•
•
350
= 20 log
π
350 2 + f −3dB ( Ne N ) 2
2
where:
f−3dB is the input bandwidth, in megahertz, of the AD7091R-5
(1.5 MHz), or the cutoff frequency of the input filter, if one
is used.
N is the noise gain of the amplifier (for example, gain = 1
in a buffered configuration; see Figure 37).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
For ac applications, the driver must have a THD
performance that is commensurate with the AD7091R-5.
If a buffer is placed between MUXOUT and ADCIN, the driver
amplifier and the AD7091R-5 analog input circuit must
settle for a full-scale step onto the capacitor array at a 12-bit
level (0.0244%, 244 ppm). In an amplifier data sheet,
settling at 0.1% to 0.01% is more commonly specified and
may differ significantly from the settling time at a 12-bit
level. Be sure to verify the amplifier settling time before
driver selection.
When an externally applied reference is required, disable the
internal reference using the configuration register. Choose an
externally applied reference voltage in the range of 1.0 V to VDD
and connect it to the REFIN/REFOUT pin.
For applications where power consumption is a concern, use the
power-down mode of the ADC to improve power performance.
See the Modes of Operation section for additional details.
Table 7. Recommended Driver Amplifiers
Product
ADA4805-1
AD8031
AD8032
AD8615
1
Description1
Low noise, low power, wide bandwidth amplifier
Low voltage, low power, single channel amplifier
Low voltage, low power, dual channel amplifier
Low frequency, low voltage amplifier
For the latest recommended ADC driver products, see the AD7091R-5
product page.
Rev. A | Page 17 of 34
AD7091R-5
Data Sheet
VDRIVE
47kΩ
10µF
100nF
100nF
10µF
VDD
VDRIVE
1µF
SCL
AS1
AD7091R-5
ANALOG
INPUT
MICROCONTROLLER/
MICROPROCESSOR/
DSP
SDA
REGCAP
AS0
VIN0
CONVST/GPO1
ALERT/BUSY/GPO0
ANALOG
INPUT
VIN3
REFIN/
REFOUT
GND
ADCIN
MUXOUT
2.2µF
OPTIONAL
BUFFER
12093-018
33Ω
560pF
Figure 37. Typical Connection Diagram with Optional Buffer
VDRIVE
47kΩ
10µF
100nF
10µF
VDD
100nF
VDRIVE
SDA
REGCAP
SCL
1µF
33Ω
ANALOG
INPUT
AD7091R-5
VIN0
MICROCONTROLLER/
MICROPROCESSOR/
DSP
AS1
AS0
CONVST/GPO1
560pF
ALERT/BUSY/GPO0
ANALOG
INPUT
560pF
VIN3
GND
REFIN/
REFOUT
ADCIN
MUXOUT
2.2µF
Figure 38. Typical Connection Diagram Without Optional Buffer
Rev. A | Page 18 of 34
12093-140
33Ω
Data Sheet
AD7091R-5
I2C REGISTERS
The AD7091R-5 has several user-programmable registers. Table 9
contains the complete list of registers.
The registers are either read/write (R/W) or read only (R). Data
can be written to or read back from the read/write registers.
Read only registers can only be read. Any write to a read only
register or unimplemented register address is considered no
operation (NOP) command, which is an I2C command that the
AD7091R-5 ignores. After a write to a read only register, the
output on the subsequent I2C frame is all zeros provided that
there was no conversion before the next I2C frame. Similarly, any
read of an unimplemented register outputs zeros.
ADDRESSING REGISTERS
A serial transfer on the AD7091R-5 consists of nine SCL cycles.
Data is sent over the serial bus in groups of nine bits—eight bits
of data from the transmitter followed by an acknowledge bit from
the receiver. Data transitions on the SDA line must occur during
the low period of the clock signal and remain stable during the
high period. The receiver pulls the SDA line low during the
acknowledge bit to signal that the preceding byte has been received
correctly. If this is not the case, cancel the transaction. The first
byte that the master sends must consist of a 7-bit slave address,
followed by a data direction bit. Each device on the bus has a
unique slave address; therefore, the first byte sets up communication
with a single slave device for the duration of the transaction.
The transaction can be used either to write to a slave device (data
direction bit = 0) or to read data from it (data direction bit = 1). In
the case of a read transaction, it is often necessary to first write
to the slave device (in a separate write transaction) to tell it
from which register to read. Reading and writing cannot be
combined in one transaction.
When the transaction is complete, the master can maintain
control of the bus, initiating a new transaction by generating
another start bit (high to low transition on SDA while SCL is
high). This is known as a repeated start. Alternatively, the bus
can be relinquished by releasing the SCL line followed by the
SDA line. This low to high transition on SDA while SCL is high
is known as a stop bit (P), and it leaves the I2C bus in its idle
state (no current is consumed by the bus).
SLAVE ADDRESS
The first byte that the user writes to the device is the slave
address byte. The AD7091R-5 has a 7-bit slave address. On the
AD7091R-5, the three MSBs of the 7-bit slave address are fixed
to 3’b010. The four LSBs are set by the user via external pins.
Two address select pins are on each device, and high, low, or no
connect can be detected on each pin, giving nine combinations.
Table 8 shows the four LSBs of the slave address for the AD7091R-5
for different configurations of the address select pins.
Table 8. Slave Addresses
AS11
VDD
VDD
VDD
NC
NC
NC
GND
GND
GND
1
AS01
VDD
NC
GND
VDD
NC
GND
VDD
NC
GND
A3
0
0
0
1
1
1
1
1
1
A2
0
0
0
0
0
0
1
1
1
A1
0
1
1
0
1
1
0
1
1
NC means leave the ASx pins floating, VDD means pulled high, and GND
means pulled low.
I2C REGISTER ACCESS
Table 9. Register Descriptions
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
A0
0
0
1
0
0
1
0
0
1
Register Name
Conversion result
Channel
Configuration
Alert indication
Channel 0 low limit
Channel 0 high limit
Channel 0 hysteresis
Channel 1 low limit
Channel 1 high limit
Channel 1 hysteresis
Channel 2 low limit
Channel 2 high limit
Channel 2 hysteresis
Channel 3 low limit
Channel 3 high limit
Channel 3 hysteresis
Default
0x0000
0x0000
0x00C0
0x0000
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
Rev. A | Page 19 of 34
Access
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AD7091R-5
Data Sheet
CONVERSION RESULT REGISTER
The conversion result register is a 16-bit, read only register that stores the results from the most recent ADC conversion in straight binary
format. The channel ID of the converted channel and the alert status are also included in this register.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[ 1 5 ] RSV ( R)
Re se rve d
[ 1 1 :0 ] CO N V_RESULT ( R)
12 -b it Co nve rsio n re sult
[ 1 4 :1 3 ] CH _ID ( R)
2 -b it Channe l ID
[ 1 2 ] ALERT ( R)
Ale rt flag
0 : No Ale rt.
1: Ale rt has o ccure d .
Table 10. Conversion Result Bit Map
MSB
B15
RSV
B14
B13
CH_ID
B12
ALERT
B11
B10
B9
B8
B7
B6
B5
CONV_RESULT
B4
B3
B2
B1
Table 11. Bit Descriptions for the Conversion Result Register
Bit(s)
15
[14:13]
Name
RSV
CH_ID
12
ALERT
[11:0]
CONV_RESULT
Description
Reserved
2-bit channel ID of the channel converted
B14
B13
Analog Input Channel
0
0
Channel 0
0
1
Channel 1
1
0
Channel 2
1
1
Channel 3
Alert flag
0: no alert occurred
1: alert has occurred
12-bit conversion result
Rev. A | Page 20 of 34
Reset
0x0
0x0
Access
R
R
0x0
R
0x000
R
LSB
B0
Data Sheet
AD7091R-5
CHANNEL REGISTER
The channel register on the AD7091R-5 is an 8-bit, read/write register. Each of the four analog input channels has one corresponding bit in
the channel register. To select a channel for inclusion in the channel conversion sequence, set the corresponding channel bit to 1 in the
channel register. There is a latency of one conversion before the channel conversion sequence is updated. If the channel register is
programmed with a new value, the conversion sequence is reset to the lowest numbered channel in the new value.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[ 7 :4 ] RS V ( R)
Re se rve d
[ 0 ] CH 0 ( R/W )
Co nve rt o n Channe l 0
0 : Disab le Channe l 0 .
1: Enab le Channe l 0 .
[ 3 ] CH 3 ( R/W )
Co nve rt o n Channe l 3
0 : Disab le Channe l 3 .
1: Enab le Channe l 3 .
[ 1 ] CH 1 ( R/W )
Co nve rt o n Channe l 1
0 : Disab le Channe l 1.
1: Enab le Channe l 1.
[ 2 ] CH 2 ( R/W )
Co nve rt o n Channe l 2
0 : Disab le Channe l 2 .
1: Enab le Channe l 2 .
Table 12. Channel Bit Map
MSB
B7
B6
B5
B4
B3
CH3
RSV
B2
CH2
B1
CH1
LSB
B0
CH0
Table 13. Bit Descriptions for the Channel Register
Bit(s)
[7:4]
3
Name
RSV
CH3
2
CH2
1
CH1
0
CH0
Description
Reserved
Convert on Channel 3
0: disable Channel 3
1: enable Channel 3
Convert on Channel 2
0: disable Channel 2
1: enable Channel 2
Convert on Channel 1
0: disable Channel 1
1: enable Channel 1
Convert on Channel 0
0: disable Channel 0
1: enable Channel 0
Rev. A | Page 21 of 34
Reset
0x00
0x0
Access
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
AD7091R-5
Data Sheet
CONFIGURATION REGISTER
The configuration register is a 16-bit, read/write register that sets the operating modes of the AD7091R-5.
15
14 13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
[ 1 5 ] A L ER T _D R IV E_T YP E ( R /W )
D r iv e Ty p e o f ALERT/BU SY/GPO 0 p in
0 : ALERT/BU SY/GPO 0 p in is o f o p e n - d r a in
d r iv e ty p e .
1 : ALERT/BU SY/GPO 0 p in is o f CM O S d r iv e
ty p e .
[ 1 : 0 ] P _D O W N ( R /W )
Po w e r D o w n m o d e
0 0 : Mo d e 0 .
0 1: Mo d e 1.
10 : Mo d e 2 .
11: Mo d e 3 .
[ 1 4 ] G P O 2 ( R /W )
Va lu e a t GPO 2
0 : D r iv e '0 ' o n GPO 2 p in .
1 : D r iv e '1 ' o n GPO 2 p in .
[ 2 ] G P O 1 ( R /W )
Va lu e a t GPO 1
0 : D r iv e '0 ' o n GPO 1 p in .
1 : D r iv e '1 ' o n GPO 1 p in .
[ 1 3 ] RS V ( R)
Re s e r v e d
[ 3 ] A L ER T _P O L _o r _G P O 0 ( R /W )
Po la r ity o f ALERT/BU SY/GPO 0 p in ( if ALERT_EN
is 1 ) o r v a lu e a t GPO 0
0 : Ac tiv e LO W ALERT Po la r ity ( if ALERT_EN
is 1 ) o r GPO 0 = 0 .
1 : Ac tiv e H IGH ALERT Po la r ity ( if ALERT_EN
is 1 ) o r GPO 0 = 1 .
[ 1 2 ] RS V ( R)
Re s e r v e d
[ 1 1 ] F L T R ( R /W )
En a b le Glitc h Filte r o n SD A/SCL
0 : En a b le '5 0 n s ' Glitc h - filte r in g o n SD A/SCL
lin e s .
1 : By p a s s th e Glitc h - Filte r .
[ 1 0 ] C M D ( R /W )
Co m m a n d M o d e
0 : Sa m p le m o d e ( if
m o d e ( if AU TO =
1 : Co m m a n d m o d e
m o d e ( if AU TO =
[ 4 ] A L ER T _EN _o r _G P O 0 ( R /W )
En a b le ALERT o r GPO 0
1 : ALERT/BU SY/GPO 0 p in is u s e d fo r ALERT/BU SY
s ta tu s .
0 : ALERT/BU SY/GPO 0 p in w ill b e u s e d a s
a GPO .
AU TO = 0 ) o r Au to c y c le
1)
( if AU TO = 0 ) o r Sa m p le
1)
[ 5 ] B U S Y ( R /W )
ALERT/BU SY/GPO 0 p in in d ic a te s if th e
p a r t is b u s y c o n v e r tin g
0 : ALERT/BU SY/GPO 0 p in is n o t u s e d fo r
BU SY s ta tu s .
1 : ALERT/BU SY/GPO 0 p in is u s e d fo r BU SY
s ta tu s p r o v id e d ALERT_EN is 1 . Els e ,
th is w ill a lw a y s b e r e a d - b a c k a s 0 .
[ 9 ] S R S T ( R /W )
So ftw a r e Re s e t b it
0 : So ft- Re s e t n o t a c tiv e .
1 : Ac t iv a t e So ft- Re s e t.
[ 7 : 6 ] C y c le _t im e r ( R /W )
Tim e r v a lu e fo r Au to c y c le m o d e
0 0 : 1 0 0 u S.
0 1 : 2 0 0 u S.
1 0 : 4 0 0 u S.
1 1 : 8 0 0 u S.
[ 8 ] A U T O ( R /W )
Au to c y c le M o d e
0 : Sa m p le m o d e ( if CM D = 0 ) o r Co m m a n d
m o d e ( if CM D = 1 )
1 : Au to - c y c le m o d e ( if CM D = 0 ) o r Sa m p le
m o d e ( if CM D = 1 )
Table 14. Configuration Bit Map
MSB
B15
ALERT_
DRIVE_
TYPE
B14
GPO2
B13
RSV
B12
RSV
B11
FLTR
B10
CMD
B9
SRST
B8
AUTO
B7 B6
CYCLE_
TIMER
B5
BUSY
B4
ALERT_
EN_OR_
GPO0
B3
ALERT_
POL_OR_
GPO0
B2
GPO1
LSB
B1 B0
P_DOWN
Table 15. Bit Descriptions for the Configuration Register1
Bit(s)
15
Name
ALERT_DRIVE_TYPE
14
GPO2
13
12
RSV
RSV
Description
Drive the type of the ALERT/BUSY/GPO0 pin.
0: the ALERT/BUSY/GPO0 pin is open-drain drive type.
1: the ALERT/BUSY/GPO0 pin is CMOS drive type.
Value at GPO2.
0: drive 0 on GPO2 pin.
1: drive 1 on GPO2 pin.
Reserved.
Reserved.
Rev. A | Page 22 of 34
Reset
0x0
Access
RW
0x0
RW
0x00
0x00
R
R
Data Sheet
Bit(s)
11
Name
FLTR
10
CMD
9
SRST
8
AUTO
[7:6]
CYCLE_TIMER
5
BUSY
4
ALERT_EN_OR_GPO0
3
ALERT_POL_OR_GPO0
2
GPO1
[1:0]
P_DOWN
1
AD7091R-5
Description
Enable the glitch filter on SDA/SCL.
0: enable 50 ns glitch filtering on the SDA/SCL lines.
1: bypass the glitch filter.
Command mode.
0: sample mode (if AUTO = 0) or autocycle mode (if AUTO = 1).
1: command mode (if AUTO = 0) or sample mode (if AUTO = 1).
Software reset bit. Setting this bit resets the internal digital control logic, the conversion
result and alert indication registers, but not the other memory-mapped registers.
This bit is automatically cleared in the next clock cycle.
0: soft reset not active.
1: activate soft reset.
Autocycle mode.
0: sample mode (if CMD = 0) or command mode (if CMD = 1).
1: autocycle mode (if CMD = 0) or sample mode (if CMD = 1).
Timer value for autocycle mode.
00: 100 μs.
01: 200 μs.
10: 400 μs.
11: 800 μs.
ALERT/BUSY/GPO0 pin indicates if the device is busy converting.
0: the ALERT/BUSY/GPO0 pin is not used for the busy status.
1: the ALERT/BUSY/GPO0 pin is used for the busy status provided
ALERT_EN_OR_GPO0 is 1. Otherwise, this bit is always read back as 0.
Enable the ALERT/BUSY/GPO0 pin or GPO0.
1: the ALERT/BUSY/GPO0 pin is used for the ALERT/BUSY status.
0: the ALERT/BUSY/GPO0 pin is used as a GPO.
Polarity of the ALERT/BUSY/GPO0 pin (if ALERT_EN_OR_GPO0 is 1) or value at GPO0.
0: active low ALERT/BUSY/GPO0 polarity (if ALERT_EN_OR_GPO0 is 1) or GPO0 = 0.
1: active high ALERT/BUSY/GPO0 polarity (if ALERT_EN_OR_GPO0 is 1) or GPO0 = 1.
Value at GPO1.
0: drive 0 on the CONVST/GPO1 pin.
1: drive 1 on the CONVST/GPO1 pin.
Power-down modes.
Setting Mode
00
Mode 0
01
Mode 1
10
Mode 2
11
Mode 3
Sleep Mode/Bias Generator
Off
Off
On
On
Internal Reference
Off
On
Off
On
The AD7091R-5 supports the I2C standard glitch filter, but does not support clock stretching or general call addressing.
Rev. A | Page 23 of 34
Reset
0x0
Access
RW
0x0
RW
0x0
RWAC
0x0
RW
0x3
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
R/W
AD7091R-5
Data Sheet
ALERT INDICATION REGISTER
The 8-bit alert indication register is a read only register that provides information on an alert event. If a conversion result activates the
ALERT/BUSY/GPO0 pin, as described in the Channel x Low Limit Register section and the Channel x High Limit Register section, read
the alert register to determine the source of the alert. The register contains two status bits per channel, one corresponding to the high
limit, and the other to the low limit. The bit with a status equal to 1 shows where the violation occurred, that is, on which channel, and
whether the violation occurred on the upper or lower limit. If a second alert event occurs on another channel between receiving the first
alert and interrogating the alert register, the corresponding bit for that alert event is also set.
The contents of the alert indication register are reset by reading it. When the AD7091R-5 uses the I2C interface to read the alert indication
register, the register is reset at the fourth SCL clock of the byte. By this time, the data from the register has moved to the I2C shift register.
The alert bits for any unimplemented channels always return zeros.
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
[ 7 ] Lo _3 ( R)
Lo w ale rt Channe l 3
0 : No ale rt o n Channe l 3 .
1: Lo w ale rt o ccurre d o n Channe l 3 .
[ 0 ] H i_0 ( R)
Hig h ale rt Channe l 0
0 : No ale rt o n Channe l 0 .
1: Hig h ale rt o ccurre d o n Channe l 0 .
[ 6 ] H i_3 ( R)
Hig h ale rt Channe l 3
0 : No ale rt o n Channe l 3 .
1: Hig h ale rt o ccurre d o n Channe l 3 .
[ 1 ] Lo _0 ( R)
Lo w ale rt Channe l 0
0 : No ale rt o n Channe l 0 .
1: Lo w ale rt o ccurre d o n Channe l 0 .
[ 5 ] Lo _2 ( R)
Lo w ale rt Channe l 2
0 : No ale rt o n Channe l 2 .
1: Lo w ale rt o ccurre d o n Channe l 2 .
[ 2 ] H i_1 ( R)
Hig h ale rt Channe l 1
0 : No ale rt o n Channe l 1.
1: Hig h ale rt o ccurre d o n Channe l 1.
[ 4 ] H i_2 ( R)
Hig h ale rt Channe l 2
0 : No ale rt o n Channe l 2 .
1: Hig h ale rt o ccurre d o n Channe l 2 .
[ 3 ] Lo _1 ( R)
Lo w ale rt Channe l 1
0 : No ale rt o n Channe l 1.
1: Lo w ale rt o ccurre d o n Channe l 1.
Table 16. Alert Indication Bit Map
MSB
B7
LO_3
B6
HI_3
B5
LO_2
B4
HI_2
B3
LO_1
B2
HI_1
LSB
B0
HI_0
B1
LO_0
Table 17. Bit Descriptions for the Alert Indication Register
Bit(s)
7
Bit Name
LO_3
6
HI_3
5
LO_2
4
HI_2
3
LO_1
Description
Channel 3 low alert status
0: no alert on Channel 3
1: low alert occurred on Channel 3
Channel 3 high alert status
0: no alert on Channel 3
1: high alert occurred on Channel 3
Channel 2 low alert status
0: no alert on Channel 2
1: low alert occurred on Channel 2
Channel 2 high alert status
0: no alert on Channel 2
1: high alert occurred on Channel 2
Channel 1 low alert status
0: no alert on Channel 1
1: low alert occurred on Channel 1
Rev. A | Page 24 of 34
Reset
0x0
Access
R
0x0
R
0x0
R
0x0
R
0x0
R
Data Sheet
Bit(s)
2
Bit Name
HI_1
1
LO_0
0
HI_0
AD7091R-5
Description
Channel 1 high alert status
0: no alert on Channel 1
1: high alert occurred on Channel 1
Channel 0 low alert status
0: no alert on Channel 0
1: low alert occurred on Channel 0
Channel 0 high alert status
0: no alert on Channel 0
1: high alert occurred on Channel 0
Rev. A | Page 25 of 34
Reset
0x0
Access
R
0x0
R
0x0
R
AD7091R-5
Data Sheet
CHANNEL x LOW LIMIT REGISTER
Of the 16 bits, only the twelve least significant bits (LSBs) are
used, Bit B11 to Bit B0. Bit B15 to Bit B12 are not used.
Each analog input channel of the AD7091R-5 has its own low
limit register. The low limit registers are 16-bit read/write
registers. See Table 9 for the register addresses. The low limit
registers store the lower limit of the conversion value that
activates the ALERT output.
CHANNEL x HYSTERESIS REGISTER
Each analog input channel of the AD7091R-5 has its own
hysteresis register, which are 16-bit read/write registers. See
Table 9 for the register addresses. The hysteresis register stores
the hysteresis value (N) when using the limit registers. The
hysteresis value determines the reset point for the ALERT/
BUSY/GPO0 pin if a violation of the limits has occurred.
Of the 16 bits, only the twelve least significant bits (LSBs) are
used, Bit B11 to Bit B0. Bit B15 to Bit B12 are not used.
CHANNEL x HIGH LIMIT REGISTER
Of the 16 bits, only the twelve least significant bits (LSBs) are
used, Bit B11 to Bit B0. Bit B15 to Bit B12 are not used.
Each analog input channel of the AD7091R-5 has its own high
limit register. The high limit registers are 16-bit read/write
registers. See Table 9 for the register addresses. The high limit
registers store the upper limit of the conversion value that
activates the ALERT output.
Table 18. Channel x Low Limit Bit Map
MSB
B15
B14
B13
RSV
B12
B11
B10
B9
B8
B7
B6
B5
CHx LOW LIMIT
B4
B3
B2
B1
LSB
B0
Table 19. Bit Descriptions for Channel x Low Limit Register
Bits
[15:12]
[11:0]
Bit Name
RSV
CHx LOW LIMIT
Description
Reserved
Low limit value for Channel x
Reset
0x00
0x000
Access
R
R/W
Table 20. Channel x High Limit Bit Map
MSB
B15
B14
B13
RSV
B12
B11
B10
B9
B8
B7
B6
B5
CHx HIGH LIMIT
B4
B3
B2
B1
LSB
B0
Table 21. Bit Descriptions for Channel x High Limit Register
Bits
[15:12]
[11:0]
Bit Name
RSV
CHx HIGH LIMIT
Description
Reset
0x00
0xFFF
High limit value for Channel x
Access
R
R/W
Table 22. Channel x Hysteresis Bit Map
MSB
B15
B14
B13
RSV
B12
B11
B10
B9
B8
B7
B6
B5
CHx HYSTERISIS
B4
B3
B2
B1
LSB
B0
Table 23. Bit Descriptions for the Channel x Hysteresis Register
Bits
[15:12]
[11:0]
Bit Name
RSV
CHx HYSTERISIS
Description
Hysteresis value for Channel x
Rev. A | Page 26 of 34
Reset
0x00
0xFFF
Access
R
R/W
Data Sheet
AD7091R-5
I2C INTERFACE
Control of the AD7091R-5 is carried out via the I2C-compatible
serial bus. The AD7091R-5 is connected to this bus as a slave
device under the control of a master device such as the processor.
as a high to low transition on the serial data line (SDA) while
the serial clock line (SCL) remains high. This indicates that a
data stream follows. The master device must generate the clock.
SERIAL BUS ADDRESS BYTE
Data is sent over the serial bus in groups of nine bits—eight bits
of data from the transmitter are followed by an acknowledge bit
(ACK) from the receiver. Data transitions on the SDA line must
occur during the low period of the clock signal and remain
stable during the high period. The receiver must pull the SDA
line low during the acknowledge bit to signal that the preceding
byte has been received correctly. If this is not the case, cancel
the transaction.
The first byte that the user writes to the device is the slave
address byte. Similar to all I2C-compatible devices, the
AD7091R-5 has a 7-bit serial address. The three MSBs of this
address are set to 010. The four LSBs are user programmable by
the three-state input pins, AS0 and AS1, as shown in Table 24.
In Table 24, high means tie the pin to VDRIVE, low means tie the
pin to GND, and NC refers to a pin left floating. Note that in
NC cases, the stray capacitance on the pin must be less than
30 pF to allow correct detection of the floating state; therefore,
any printed circuit board trace must be kept as short as possible.
The first byte that the master sends must consist of a 7-bit slave
address, followed by a data direction bit. Each device on the
bus has a unique slave address; therefore, the first byte sets up
communication with a single slave device for the duration of the
transaction.
Table 24. Slave Address Control Using Three-State Input Pins
AS1
High
High
High
NC
NC
NC
Low
Low
Low
Slave Address (A6 to A0)
Binary
Hex
010 0000
0x20
010 0010
0x22
010 0011
0x23
010 1000
0x28
010 1010
0x2A
010 1011
0x2B
010 1100
0x2C
010 1110
0x2E
010 1111
0x2F
AS0
High
NC
Low
H
NC
Low
High
NC
Low
The transaction can be used either to write to a slave device
(data direction bit = 0) or to read data from it (data direction
bit = 1). In the case of a read transaction, it is often necessary
first to write to the slave device (in a separate write transaction)
to tell it from which register to read. Reading and writing
cannot be combined in one transaction.
When the transaction is complete, the master can maintain
control of the bus, initiating a new transaction by generating
another start bit (high to low transition on SDA while SCL is
high). This is known as a repeated start (SR). Alternatively, the
bus can be relinquished by releasing the SCL line followed by
the SDA line. This low to high transition on SDA while SCL is
high is known as a stop bit (P), and it leaves the I2C bus in its
idle state (no current is consumed by the bus).
GENERAL I2C TIMING
Figure 39 shows the timing diagram for general read and write
operations using an I2C compliant interface.
The example in Figure 39 shows a simple write transaction
with an AD7091R-5 as the slave device. In this example, the
AD7091R-5 register pointer is being set up for a future read
transaction.
When no device is driving the bus, both SCL and SDA are high.
This is known as the idle state. When the bus is idle, the master
initiates a data transfer by establishing a start condition, defined
SCL
A6
START COND
BY MASTER
A5
A4
A3
A2
A1
A0
SLAVE ADDRESS BYTE
USER PROGRAMMABLE
4 LSBs
R/W
P7
P6
P5
ACK. BY
AD7091R-5
Figure 39. General I2C Timing
Rev. A | Page 27 of 34
P4
P3
P2
REGISTER ADDRESS
P1
P0
ACK. BY
AD7091R-5
STOP BY
MASTER
12093-040
SDA
AD7091R-5
Data Sheet
WRITING TO THE AD7091R-5
WRITING TWO BYTES OF DATA TO A 16-BIT
REGISTER
WRITING TO MULTIPLE REGISTERS
Writing to multiple address registers consists of the following
steps (see Figure 41):
With the exception of the channel register, all registers on the
AD7091R-5 are 16-bit registers; therefore, two bytes of data are
required to write a value to any one of these registers. Writing
two bytes of data to a register consists of the following sequence
(see Figure 40):
5.
6.
7.
8.
9.
S
SLAVE ADDRESS
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
0
SA
REG POINTER
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
SA
DATA[15:8]
SA
DATA[7:0]
SA
P
S = START CONDITION
SR = REPEATED START
P = STOP CONDITION
SA = SLAVE ACKNOWLEDGE
A = NOT ACKNOWLEDGE
Figure 40. Writing Two Bytes of Data to a 16-Bit Register
SLAVE ADDRESS
S
...
0
SA
POINT TO CH0 HIGH LIMIT (0x05)
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
POINT TO CONFIG REG (0x02)
SA
DATA[15:8]
SA
SA
SA
DATA[15:8]
DATA[7:0]
S = START CONDITION
SR = REPEATED START
P = STOP CONDITION
SA = SLAVE ACKNOWLEDGE
A = NOT ACKNOWLEDGE
SA
DATA[7:0]
SA
...
P
12093-060
3.
4.
3.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an acknowledge on SDA.
The master sends a register address. The slave asserts an
acknowledge on SDA.
The master sends the first data byte (most significant).
The slave asserts an acknowledge on SDA.
The master sends the second data byte (least significant).
The slave asserts an acknowledge on SDA.
The master asserts a stop condition on SDA to end the
transaction.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by
the write bit (low).
The addressed slave device (AD7091R-5) asserts an
acknowledge on SDA.
The master sends a register address, for example, the
configuration register address.
The slave asserts an acknowledge on SDA.
The master sends the first data byte.
The slave asserts an acknowledge on SDA.
The master sends the second data byte.
The slave asserts an acknowledge on SDA.
The master sends a second register address, for example,
the Channel 0 high limit register.
The slave asserts an acknowledge on SDA.
The master sends the first data byte.
The slave asserts an acknowledge on SDA.
The master sends the second data byte.
The slave asserts an acknowledge on SDA.
The master asserts a stop condition on SDA to end the
transaction.
12093-059
1.
2.
1.
2.
Figure 41. Writing to Multiple Registers
Rev. A | Page 28 of 34
Data Sheet
AD7091R-5
READING DATA FROM THE AD7091R-5
READING TWO BYTES OF DATA FROM A 16-BIT
REGISTER
Reading two bytes of data from a 16-bit register consists of the
following sequence (see Figure 42):
Reading the contents from any of the 16-bit registers is a 2-byte
read operation. In this protocol, the first part of the transaction
writes to the register pointer. When the register address has
been set up, any number of reads can be performed from that
particular register without writing to the address pointer register
again. When the required number of reads is complete, the
master must not acknowledge the final byte. This tells the slave
to stop transmitting, allowing a stop condition to be asserted by
the master. Further reads from this register can be performed in
a future transaction without rewriting to the register pointer.
1.
2.
If a read from a different address is required, the relevant
register address must be written to the address pointer register
and, again, any number of reads from this register can then be
performed. In the following example, the master device reads
three lots of 2-byte data from a slave device, but as many lots
consisting of two bytes can be read as required. This protocol
assumes that the particular register address has been set up by
a single-byte write operation to the address pointer register.
...
DATA[15:8]
1
A
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
A
DATA[7:0]
A
DATA[15:8]
A
16.
DATA[7:0]
A
DATA[15:8]
A
DATA[7:0]
A
...
P
S = START CONDITION
SR = REPEATED START
P = STOP CONDITION
A = ACKNOWLEDGE
A = NOT ACKNOWLEDGE
12093-061
SLAVE ADDRESS
S
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The addressed slave device asserts an acknowledge on SDA.
The master receives the data byte.
The master asserts an acknowledge on SDA.
The master receives the second data byte.
The master asserts an acknowledge on SDA.
The master receives the data byte.
The master asserts an acknowledge on SDA.
The master receives the second data byte.
The master asserts an acknowledge on SDA.
The master receives the data byte.
The master asserts an acknowledge on SDA.
The master receives the second data byte.
The master asserts a not acknowledge on SDA to notify the
slave that the data transfer is complete.
The master asserts a stop condition on SDA to end the
transaction.
Figure 42. Reading Three Lots of Two Bytes of Data from the Conversion Result Register (Conversion Register Pointer Already Set)
Rev. A | Page 29 of 34
AD7091R-5
Data Sheet
MODES OF OPERATION
There are three methods of initiating a conversion on the
AD7091R-5 with the I2C interface: sample mode using
the CONVST/GPO1 pin, command mode, and autocycle mode.
In the CONVST/GPO1 pin mode, conversions are done on
demand. Whenever the CONVST/GPO1 pin is toggled, an ADC
conversion happens. In command mode, the read of the
conversion result register starts the conversion. In autocycle
mode, conversions occur on the selected channels in the
background periodically. This mode monitors whether signals
cross certain threshold levels, the absolute value being relatively
unimportant.
SAMPLE MODE
At power-up, the device wakes up in sample mode and selects
Channel 0 for conversion. Sample mode can be selected subsequently by writing a value of 0 to both the CMD and auto bits of
the configuration register or by writing a value of 1 to both the
CMD and auto bits. In sample mode, conversions are controlled
by toggling the active low CONVST/GPO1 pin.
To perform conversion on a channel other than Channel 0 or on
a sequence of channels, before initiating any conversion, write
to the channel register to select the channels for conversion. On
each CONVST pulse, the next channel in the selected sequence
is converted starting from the lowest numbered channel
selected (0, 1 … 7).
A high to low transition on the CONVST/GPO1 pin puts the
track-and-hold circuit into hold mode and samples the analog
input. The conversion is initiated and requires approximately
550 ns to complete. When the conversion process is finished,
the track-and-hold circuit goes back into track.
To read back data stored in the conversion result register, first
wait until the conversion is finished. If the address pointer is
pointing to the conversion result register, the conversion data
can be read using the protocol described in Figure 42.
Otherwise, the address pointer must be set to point at the
conversion result register before conversion data can be read.
When the conversion result read is completed, the user may
pull the CONVST pin low again to start another conversion.
Do not toggle the CONVST pin when activity is occurring on
the I2C bus.
COMMAND MODE
In command mode, the AD7091R-5 converts on demand on
either a single channel or a sequence of channels. This mode of
operation allows a conversion to be selected automatically any
time a write operation occurs to the command register. In
command mode, the AD7091R-5 converts the next programmed
channel when the conversion result register is read. To enter this
mode, the required combination of channels is written into the
channel register. Select command mode operation by writing
CMD = 1 and auto = 0 in the configuration register. Following
the write operation, the AD7091R-5 must be addressed again to
indicate that a read operation is required from the conversion
result register.
The conversion starts on the first positive edge of SCL after the
ACK for the previous byte is sent to avoid starting a conversion
during the ACK cycle. This does not create an issue with the exact
time that the conversion data must be sent on the I2C bus because
the first three bits sent on the I2C bus correspond to the channel
for which the conversion data belongs. After the conversion is
completed, the ADC powers down. The next conversion in the
sequence starts after a subsequent read from the conversion
result register is initiated. The device cycles through the selected
channels from the lowest selected channel number in the sequence
to the next until all channels in the sequence are converted.
After all channels in the sequence are converted, the sequence
rolls back to the lowest numbered channel enabled so that the
sequence can be repeated indefinitely.
To stop converting in the command mode, the master does not
acknowledge the final byte of data. This NACK stops the
AD7091R-5 transmission, allowing the master to assert a stop
condition on the bus. On the receipt of an I2C NACK condition,
the AD7091R-5 stops converting, but the content of the
configuration register is preserved. After the device is
readdressed and a read initiated from the conversion result
register, the AD7091R-5 begins converting on the previously
selected sequence of channels.
The conversion sequence starts at the first selected channel in
the sequence. That is, if Channel 1, Channel 2, and Channel 3
are selected and a stop condition occurs after the result for
Channel 1 is read, on the resumption of conversions, Channel 2
is converted and the conversion sequence continues. This
happens provided the channel register is not written in between
conversions. However, if the channel register is written, this
results in the conversion starting from Channel 1.
Rev. A | Page 30 of 34
Data Sheet
AD7091R-5
17. The slave (AD7091R-5) asserts an acknowledge on SDA.
18. The master receives a data byte, which contains the
channel address bits, the alert bit, and the four MSBs of the
converted result for Channel 0.
19. The master then asserts an acknowledge on SDA.
20. The master receives the second data byte, which contains
the eight LSBs of the converted result for Channel 0. The
master then asserts on acknowledge on SDA.
21. Step 18 to Step 20 repeat for Channel 1 and Channel 2.
22. After the master has received the results from all the
selected channels, the slave again converts and outputs
the result for the first channel in the selected sequence.
Step 18 to Step 21 are repeated.
23. The master asserts a not acknowledge on SDA and a stop
condition on SDA to end the conversion and exit
command mode.
The example in Figure 43 shows command mode converting on
a sequence of channels including Channel 0, Channel 1, and
Channel 2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device (AD7091R-5) asserts an
acknowledge on SDA.
The master sends the configuration register address (0x02).
The slave asserts an acknowledge on SDA.
The master sends the first data byte (0x06) to the
configuration register, which selects the command mode.
The slave asserts an acknowledge on SDA.
The master sends the second data byte (0x00) to the
configuration register.
The slave asserts an acknowledge on SDA.
The master sends the channel register address (0x01).
The slave asserts an acknowledge on SDA.
The master sends the data byte (0x07) to the channel register,
which selects Channel 0, Channel 1, and Channel 2.
The slave asserts an acknowledge on SDA.
The master sends the conversion result register address (0x00).
The slave asserts an acknowledge on SDA.
The master sends a repeated start and the 7-bit slave
address followed by the read bit (high).
S
0
SLAVE ADDRESS
SA
POINT TO CONFIG REG (0x02)
...
POINT TO CHANNEL REG (0x01)
SA
...
POINT TO RESULT REG (0x00)
SA
...
CH0[7:0]
*
A
... * CH AD (0010)
...
CH0[7:0]
A
........
* = POSITION OF SAMPLING START
COMMAND = 0x07
SR
SLAVE ADDRESS
CH1[11:8]
CH AD (0001)
CH2[11:8]
To change the conversion sequence, rewrite a new sequence to
the command mode. If a new write to the channel register is
performed while an existing conversion sequence is underway,
the existing conversion sequence is terminated and the next
conversion performed is the first selected channel from the new
sequence. The maximum throughput that can be achieved using
this mode with a 400 kHz I2C clock is (400 kHz/18) = 22.22 kSPS.
A
A
SA
...
1
SA
COMMAND = 0x06
*
CH1[7:0]
A
CH2[7:0]
CH2[7:0]
SA
A
P
*
CH AD (0000)
A
CH ID (0000)
SA
CH0[11:8]
A
SA
...
...
CH0[11:8]
A
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 43. Command Mode Operation
Rev. A | Page 31 of 34
COMMAND = 0x00
...
S = START CONDITION
SR = REPEATED START
P = STOP CONDITION
SA = SLAVE ACKNOWLEDGE
A = NOT ACKNOWLEDGE
12093-062
1.
2.
AD7091R-5
Data Sheet
AUTOCYCLE MODE
Table 25. Autocycle Interval Time
The AD7091R-5 can be configured to convert continuously on a
programmable sequence of channels, making it the ideal mode of
operation for system monitoring. These conversions occur
automatically at intervals chosen by the CYCLE_TIMER bits in
the configuration register. Typically, this mode is used to
monitor a selection of channels automatically with the limit
registers programmed to signal an out of bounds condition via
the alert function. Reads and writes can be performed at any
time (the conversion result register contains the most recent
conversion result).
Command
00
01
10
11
To enter this mode, the required combination of channels that
must be monitored is written into the channel register. The
required interval between conversions is selected by writing
into the CYCLE_TIMER bits in the configuration register.
Autocycle mode operation can then be selected by writing
CMD = 0 and auto = 1 in the configuration register. If more
than one channel bit is set in the channel register, the ADC
automatically cycles through the channel sequence, starting
with the lowest channel and working its way up through the
sequence. After the sequence is complete, the ADC starts
converting on the lowest channel again, continuing to loop
through the sequence until this mode is exited.
As soon as a conversion is complete, the conversion result is
compared with the content of the limit registers. The alert register
is updated automatically with the result of the comparison.
If a violation of the limit registers is found, the alert bit in the
conversion result register is set and, if the ALERT/BUSY/GPO0
pin functionality is selected in the configuration register, the
ALERT/BUSY/GPO0 pin is asserted with the polarity
determined by ALERT_POL_OR_GPO0 bit in the
configuration register.
If an out-of-cycle conversion is required while autocycle mode
is active, it is necessary to disable autocycle mode before
proceeding to the command or sample mode. When the
conversion is complete, the user can reenable autocycle mode.
In autocycle mode, the AD7091R-5 does not enter power-down
on receipt of a stop condition; therefore, conversions and alert
monitoring continues to function.
The CYCLE_TIMER value in the configuration register controls
the time of conversion in autocycle mode. Four separate time
intervals are available, and each is a multiple of the BASE_TIME.
The reset value used is 8 × BASE_TIME. The base time for the
AD7091R-5 is approximately 100 μs.
Writing to the channel register or the configuration register
when in autocycle mode results in a reset of the cycle timer.
This process ensures that the latest information is used for cycle
timer calculation.
Interval Time
1 × BASE_TIME
2 × BASE_TIME
4 × BASE_TIME
8 × BASE_TIME
Approximate Interval
100 μs (10 kSPS)
200 μs (5 kSPS)
400 μs (2.5 kSPS)
800 μs (1.25 kSPS)
Do not write to the limit and hysteresis registers when the
AD7091R-5 is in autocycle mode. If these registers are written
by chance, the design stalls the internal cycle timer counters for
one SCL period when the registers are being updated. A write to
the channel register and the configuration register in autocycle
mode restarts the cycle timer counters.
Because the alert indication register is read to clear, read the
register only when an alert is indicated. Otherwise, there is a
risk of inadvertently clearing the alert register and the alert bit
in the conversion result register.
POWER-DOWN MODE
Power-down mode is intended for use in applications where slower
throughput rates and lower power consumption are required;
either the ADC is powered down between each conversion, or a
burst of conversions can be performed at a higher throughput rate,
and the ADC is then powered down for a relatively long duration
between these bursts of several conversions. When the AD7091R-5
is in power-down mode, all analog circuitry is powered down;
however, the serial interface is active.
The serial interface of the AD7091R-5 is functional in powerdown; therefore, the user may read back the last conversion result
even after the device enters power-down mode.
To enter power-down, write to the power-down configuration
bits in the configuration register, as seen in Table 15. To enter
full power-down mode, set the sleep mode/bias generator bit to 1,
and set the internal reference bit to 0, which ensures that all analog
circuitry and the internal reference powers down. When the
internal reference is enabled, it consumes power any time Bit 0 of
the configuration register is set to 1.
To exit this mode of operation and power up the AD7091R-5,
set the MSB of the P_DOWN word to 1. If a power-up of the
internal reference is desired, the P_DOWN LSB must also be set
to 1. When using the internal reference, and the device is in full
power-down mode, wait to perform conversions until the internal
reference has had time to power up and settle. The reference buffer
requires 50 ms to power up and charge the 2.2 µF decoupling
capacitor during the power-up time. After power-up is complete,
the ADC is fully powered up, and the input signal is properly
acquired. To start the next conversion, operate the interface as
described in the Modes of Operation section.
Rev. A | Page 32 of 34
Data Sheet
AD7091R-5
ALERT
BUSY
The alert functionality is used as an out of bounds indicator. An
alert event is triggered when the value in the conversion result
register exceeds the CHx high limit value in the Channel x high
limit register or falls below the CHx low limit value in the
Channel x low limit register for a selected channel.
When the ALERT/BUSY/GPO0 pin is configured as a BUSY
output, the pin indicates when a conversion is taking place. The
ALERT/BUSY/GPO0 pin is configured as BUSY by configuring
the following bits in the configuration register:
Detailed alert information is accessible in the alert register. The
register contains two status bits per channel, one corresponding
to the high limit, and the other to the low limit. A logical OR of
alert signals for all channels creates a common alert value. This
value can be accessed by the alert bit in the conversion result
register and configured to drive out on the ALERT/BUSY/GPO0
pin. The ALERT/BUSY/GPO0 pin is configured as an ALERT
output by configuring the following bits in the configuration
register:
•
•
•
Set the ALERT_EN_OR_GPO0 bit (Bit 4) to 1.
Set the busy bit (Bit 5) to 0.
Set the ALERT_POL_OR_GPO0 bit (Bit 3) to 0 for the
ALERT/BUSY/GPO0 pin to be active low and set it to 1 for
the ALERT/BUSY/GPO0 pin to be active high.
The alert register, alert bit, and ALERT/BUSY/GPO0 pin are
cleared by reading the alert register contents. Additionally, if the
conversion result goes beyond the hysteresis value for a selected
channel, the alert bit corresponding to that channel is reset
automatically. Issuing a software reset also clears the alert status.
The ALERT/BUSY/GPO0 pin has an open-drain configuration
that allows the alert outputs of several AD7091R-5 devices to be
wired together when the ALERT/BUSY/GPO0 pin is active low.
The ALERT/BUSY/GPO0 pin configuration can be controlled
by the ALERT_DRIVE_TYPE bit, Bit 15 of the configuration
register.
The ALERT_POL_OR_GPO0 bit (Bit 3 of the configuration
register) sets the active polarity of the alert output. The powerup default is active low.
•
•
•
Set the ALERT_EN_OR_GPO0 bit, Bit 4, to 1.
Set the busy bit, Bit 5, to 1.
Set the ALERT_POL_OR_GPO0 bit, Bit 3, to 0 for the
ALERT/BUSY/GPO0 pin to be active low, and set it to 1 for
the ALERT/BUSY/GPO0 pin to be active high.
When using the ALERT/BUSY/GPO0 output pin, an external
pull-up resistor is required because the output is an open-drain
configuration. Connect the external pull-up resistor to VDRIVE. The
resistor value is application dependent; however, it must be large
enough to avoid excessive sink currents at the
ALERT/BUSY/GPO0 output pin.
CHANNEL SEQUENCER
The AD7091R-5 includes a channel sequencer useful for scanning
channels in a repeated fashion. Channels included in the sequence
are configured in the channel register. If all the bits in the
channel register are 0, Channel 0 is selected by default, and all
conversions occur on this channel. If the channel register is
nonzero, the conversion sequence starts from the lowest
numbered channel enabled in the channel register. The sequence
cycles through all the enabled channels in ascending order.
After all the channels in the sequence are converted, the
sequence starts again.
There is a latency of one conversion before the channel conversion
sequence is updated. If the channel register is programmed with
a new value, the conversion sequence is reset to the lowest
numbered channel in the new value.
When using the ALERT/BUSY/GPO0 output pin, an external
pull-up resistor is required because the output is an open-drain
configuration. Connect the external pull-up resistor to VDRIVE.
The resistor value is application dependent; however, it must be
large enough to avoid excessive sink currents at the
ALERT/BUSY/GPO0 output pin.
Rev. A | Page 33 of 34
AD7091R-5
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
16
0.50
BSC
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
20
1
15
2.65
2.50 SQ
2.35
EXPOSED
PAD
5
11
0.50
0.40
0.30
TOP VIEW
0.80
0.75
0.70
SIDE VIEW
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PKG-003578
10
6
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
10-12-2017-C
PIN 1
INDICATOR
0.30
0.25
0.20
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-11.
Figure 44. 20-Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-10)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
4.50
4.40
4.30
1
PIN 1
10
0.65
BSC
0.15
0.05
COPLANARITY
0.10
1.20 MAX
0.30
0.19
6.40 BSC
0.20
0.09
SEATING
PLANE
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 45. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD7091R-5BCPZ
AD7091R-5BCPZ-RL7
AD7091R-5BRUZ
AD7091R-5BRUZ-RL7
EVAL-AD7091R-5SDZ
EVAL-SDP-CB1Z
1
Channels
4
4
4
4
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
20-Lead Lead Frame Chip Scale Package [LFCSP]
20-Lead Lead Frame Chip Scale Package [LFCSP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board
Evaluation Controller Board
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12093-0-2/18(A)
Rev. A | Page 34 of 34
Package Option
CP-20-10
CP-20-10
RU-20
RU-20
工商网监
湘ICP备2023018690号
