AD712

Dual Precision, Low Cost, High Speed BiFET Op Amp AD712 FEATURES Enhanced replacement for LF412 and TL082 AC performance Settles to ±0.01% in 1.0 μs 16 V/μs minimum slew rate (AD712J) 3 MHz minimum unity-gain bandwidth (AD712J) DC performance 200 V/mV minimum open-loop gain (AD712K) Surface mount available in tape and reel in accordance with the EIA-481A standard MIL-STD-883B parts available Single version available: AD711 Quad version: AD713 Available in PDIP, SOIC_N, and CERDIP packages CONNECTION DIAGRAM AMPLIFIER NO. 1 OUTPUT INVERTING INPUT NONINVERTING INPUT V– 1 2 3 4 AMPLIFIER NO. 2 8 7 V+ OUTPUT INVERTING 6 INPUT AD712 5 NONINVERTING INPUT Figure 1. 8-Lead PDIP (N-Suffix), SOIC_N (R-Suffix), and CERDIP (Q-Suffix) GENERAL DESCRIPTION The AD712 is a high speed, precision, monolithic operational amplifier offering high performance at very modest prices. Its very low offset voltage and offset voltage drift are the results of advanced laser wafer trimming technology. These performance benefits allow the user to easily upgrade existing designs that use older precision BiFETs and, in many cases, bipolar op amps. The superior ac and dc performance of this op amp makes it suitable for active filter applications. With a slew rate of 16 V/μs and a settling time of 1 μs to ±0.01%, the AD712 is ideal as a buffer for 12-bit digital-to-analog and analog-to-digital converters and as a high speed integrator. The settling time is unmatched by any similar IC amplifier. The combination of excellent noise performance and low input current also make the AD712 useful for photo diode preamps. Common-mode rejection of 88 dB and open-loop gain of 400 V/mV ensure 12-bit performance even in high speed unity-gain buffer circuits. The AD712 is pinned out in a standard op amp configuration and is available in seven performance grades. The AD712J and AD712K are rated over the commercial temperature range of 0°C to 70°C. The AD712A is rated over the industrial temperature range of −40°C to +85°C. The AD712S is rated over the military temperature range of −55°C to +125°C and is available processed to MIL-STD-883B, Rev. C. Extended reliability PLUS screening is available, specified over the commercial and industrial temperature ranges. PLUS screening includes 168-hour burn-in, in addition to other environmental and physical tests. The AD712 is available in 8-lead PDIP, SOIC_N, and CERDIP packages. PRODUCT HIGHLIGHTS 1. The AD712 offers excellent overall performance at very competitive prices. 2. The Analog Devices, Inc. advanced processing technology and 100% testing guarantee a low input offset voltage (3 mV maximum, J grade). Input offset voltage is specified in the warmed-up condition. 3. Together with precision dc performance, the AD712 offers excellent dynamic response. It settles to ±0.01% in 1 μs and has a minimum slew rate of 16 V/μs. Thus, this device is ideal for applications such as DAC and ADC buffers that require a combination of superior ac and dc performance. Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. 00823-001 AD712 TABLE OF CONTENTS Features .............................................................................................. 1 Connection Diagram ....................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Typical Performance Characteristics ............................................. 6 Settling Time ................................................................................... 11 Optimizing Settling Time.......................................................... 11 Op Amp Settling Time—A Mathematical Model.................. 12 Applications Information .............................................................. 14 Guarding...................................................................................... 14 Digital-to-Analog Converter Applications ............................. 14 Noise Characteristics ................................................................. 15 Driving the Analog Input of an Analog-to-Digital Converter .................................................... 15 Driving a Large Capacitive Load.............................................. 16 Filters................................................................................................ 17 Active Filter Applications.......................................................... 17 Second-Order Low-Pass Filter.................................................. 17 9-Pole Chebychev Filter............................................................. 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 20 REVISION HISTORY 8/06—Rev. F to Rev. G Edits to Figure 1 ................................................................................ 1 Change to 9-Pole Chebychev Filter Section................................ 18 7/02—Rev. D to Rev. E Edits to Features.................................................................................1 9/01—Rev. C to Rev. D 6/06—Rev. E to Rev. F Updated Format..................................................................Universal Deleted B, C, and T Models...............................................Universal Changes to General Description .................................................... 1 Changes to Product Highlights....................................................... 1 Changes to Specifications Section.................................................. 3 Changes to Figure 43...................................................................... 15 Edits to Features.................................................................................1 Edits to General Description ...........................................................1 Edits to Connection Diagram..........................................................1 Edits to Ordering Guide ...................................................................3 Deleted Metalization Photograph ...................................................3 Edits to Absolute Maximum Ratings .............................................3 Edits to Figure 7.................................................................................9 Edits to Outline Dimensions......................................................... 15 Rev. G | Page 2 of 20 AD712 SPECIFICATIONS VS = ±15 V @ TA = 25°C, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. Table 1. Parameter INPUT OFFSET VOLTAGE 1 Initial Offset TMIN to TMAX vs. Temp vs. Supply TMIN to TMAX Long-Term Offset Stability INPUT BIAS CURRENT 2 VCM = 0 V VCM = 0 V @ TMAX VCM = ±10 V INPUT OFFSET CURRENT VCM = 0 V VCM = 0 V @ TMAX MATCHING CHARACTERISTICS Input Offset Voltage TMIN to TMAX Input Offset Voltage Drift Input Bias Current Crosstalk @ f = 1 kHz @ f = 100 kHz FREQUENCY RESPONSE Small Signal Bandwidth Full Power Response Slew Rate Settling Time to 0.01% Total Harmonic Distortion INPUT IMPEDANCE Differential Common Mode INPUT VOLTAGE RANGE Differential 3 Common-Mode Voltage 4 TMIN to TMAX Common-Mode Rejection Ratio VCM = ±10 V TMIN to TMAX VCM = ±11 V TMIN to TMAX INPUT VOLTAGE NOISE Min AD712J/A/S Typ 0.3 7 95 15 25 0.6/1.6/26 75 1.7/4.8/77 100 25 0.6/1.6/26 3/1/1 4/2/2 20/20/20 25 120 90 3.0 16 4.0 200 20 1.0 0.0003 3×1012||5.5 3×1012||5.5 ±20 +14.5, −11.5 −VS + 4 +VS − 2 −VS + 4 3.4 18 1.2 120 90 4.0 200 20 1.0 0.0003 3×1012||5.5 3×1012||5.5 ±20 +14.5, −11.5 +VS − 2 Max 3/1/1 4/2/2 20/20/20 80 80 Min AD712K Typ 0.2 7 100 15 20 0.5 75 1.7 100 25 0.6 1.0 2.0 10 25 Max 1.0 2.0 10 Unit mV mV μV/°C dB dB μV/month pA nA pA pA nA mV mV μV/°C pA dB dB MHz kHz V/μs μs % Ω||pF Ω||pF V V V 76 76/76/76 10 0.3/0.7/11 5 0.1 1.2 76 76/76/76 70 70/70/70 88 84 84 80 2 45 22 18 16 Rev. G | Page 3 of 20 80 80 76 74 88 84 84 80 2 45 22 18 16 dB dB dB dB μV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz AD712 Parameter INPUT CURRENT NOISE OPEN-LOOP GAIN OUTPUT CHARACTERISTICS Voltage Current POWER SUPPLY Rated Performance Operating Range Quiescent Current 1 2 3 Min 150 100/100/100 +13, −12.5 ±12/±12/±12 AD712J/A/S Typ 0.01 400 Max Min 200 100 +13, −12.5 ±12 AD712K Typ 0.01 400 Max Unit pA/√Hz V/mV V/mV V V mA V V mA +13.9, −13.3 +13.8, −13.1 +25 ±15 +13.9, −13.3 +13.8, −13.1 +25 ±15 ±4.5 +5.0 ±18 +6.8 ±4.5 +5.0 ±18 +6.0 Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = 25°C. Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = 25°C. For higher temperatures, the current doubles every 10°C. Defined as voltage between inputs, such that neither exceeds ±10 V from ground. 4 Typically exceeding −14.1 V negative common-mode voltage on either input results in an output phase reversal. Rev. G | Page 4 of 20 AD712 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Internal Power Dissipation1 Input Voltage2 Output Short-Circuit Duration Differential Input Voltage Storage Temperature Range Q-Suffix N-Suffix and R-Suffix Operating Temperature Range AD712J/K AD712A AD712S Lead Temperature Range (Soldering 60 sec) 1 Rating ±18 V ±18 V Indefinite +VS and −VS −65°C to +150°C −65°C to +125°C 0°C to 70°C −40°C to +85°C −55°C to +125°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal characteristics: 8-lead PDIP package: 8-lead CERDIP package: 8-lead SOIC package: θJA = 165°C/W θJC = 22°C/W; θJA = 110°C/W θJA = 100°C/W 2 For supply voltages less than ±18 V, the absolute maximum voltage is equal to the supply voltage. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. G | Page 5 of 20 AD712 TYPICAL PERFORMANCE CHARACTERISTICS 20 6 INPUT VOLTAGE SWING (V) 15 QUIESCENT CURRENT (mA) 00823-002 5 10 4 RL = 2kΩ 25°C 5 3 0 5 10 SUPPLY VOLTAGE ± V 15 20 0 5 10 SUPPLY VOLTAGE ± V 15 20 Figure 2. Input Voltage Swing vs. Supply Voltage 20 INPUT BIAS CURRENT (VCM = 0) (Amps) Figure 5. Quiescent Current vs. Supply Voltage 106 OUTPUT VOLTAGE SWING (V) 107 15 +VOUT –VOUT 10 108 109 RL = 2kΩ 25°C 5 1010 1011 00823-003 0 5 10 SUPPLY VOLTAGE ± V 15 20 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 Figure 3. Output Voltage Swing vs. Supply Voltage 30 Figure 6. Input Bias Current vs. Temperature 100 OUTPUT VOLTAGE SWING (V p-p) 25 20 ±15V SUPPLIES 15 OUTPUT IMPEDANCE (Ω) 10 1.0 10 0.1 5 00823-004 100 1k LOAD RESISTANCE (Ω) 10k 10k 100k FREQUENCY (Hz) 1M 10M Figure 4. Output Voltage Swing vs. Load Resistance Figure 7. Output Impedance vs. Frequency Rev. G | Page 6 of 20 00823-007 0 10 0.01 1k 00823-006 0 1012 –60 00823-005 0 2 AD712 100 100 100 MAX J GRADE LIMIT 80 OPEN-LOOP GAIN (dB) 80 PHASE MARGIN (Degrees) 00823-013 00823-012 00823-011 INPUT BIAS CURRENT (pA) 75 VS = 15V 25°C 50 60 60 40 40 20 25 GAIN PHASE 2kΩ 100pF LOAD 20 0 0 –5 0 5 COMMON MODE VOLTAGE (V) 10 00823-008 0 –10 –20 10 100 1k 10k 100k 1M –20 10M FREQUENCY (Hz) Figure 8. Input Bias Current vs. Common-Mode Voltage 26 Figure 11. Open-Loop Gain and Phase Margin vs. Frequency 125 SHORT-CIRCUIT CURRENT LIMIT (mA) 24 22 20 18 16 14 12 00823-009 + OUTPUT CURRENT 120 OPEN-LOOP GAIN (dB) 115 110 RL = 2kΩ 25°C – OUTPUT CURRENT 105 100 10 –60 –40 –20 0 20 40 60 80 100 AMBIENT TEMPERATURE (°C) 120 140 95 0 5 10 SUPPLY VOLTAGE ± V 15 20 Figure 9. Short-Circuit Current Limit vs. Temperature 5.0 POWER SUPPLY REJECTION (dB) Figure 12. Open-Loop Gain vs. Supply Voltage 110 100 + SUPPLY UNITY-GAIN BANDWIDTH (MHz) 4.5 80 60 – SUPPLY 40 4.0 3.5 20 VS = ±15V SUPPLIES WITH 1V p-p SINEWAVE 25°C 00823-010 3.0 –60 –40 –20 0 20 40 60 80 100 120 140 0 10 100 1k 10k 100k 1M TEMPERATURE (°C) SUPPLY MODULATION FREQUENCY (Hz) Figure 10. Unity-Gain Bandwidth vs. Temperature Figure 13. Power Supply Rejection vs. Frequency Rev. G | Page 7 of 20 AD712 100 VS = ±15V VCM = 1V p-p 25°C –70 80 –80 3V rms RL = 2kΩ CL = 100pF –90 CMR (dB) THD (dB) 60 –100 40 –110 20 –120 00823-014 10 100 1k 10k 100k 1M 1k FREQUENCY (Hz) 10k FREQUENCY (Hz) 100k Figure 14. Common-Mode Rejection vs. Frequency 30 1k Figure 17. Total Harmonic Distortion vs. Frequency OUTPUT VOLTAGE SWING (V p-p) INPUT NOISE VOLTAGE (nV/√Hz) 25 RL = 2kΩ 25°C VS = ±15V 20 100 15 10 10 5 00823-015 1M FREQUENCY (Hz) 10M 1 10 100 1k FREQUENCY (Hz) 10k 100k Figure 15. Large Signal Frequency Response 10 OUTPUT SWING FROM 0V TO ±VOLTS Figure 18. Input Noise Voltage Spectral Density 25 8 6 SLEW RATE (V/µs) 20 4 2 0 –2 –4 –6 –8 0.6 0.8 0.7 SETTLING TIME (µs) 0.9 1.0 00823-016 1% 0.1% ERROR 1% 0.1% 0.01% 0.01% 15 10 5 Figure 16. Output Swing and Error vs. Settling Time Figure 19. Slew Rate vs. Input Error Signal Rev. G | Page 8 of 20 00823-019 –10 0.5 0 0 100 200 300 400 500 600 700 INPUT ERROR SIGNAL (mV) (AT SUMMING JUNCTION) 800 900 00823-018 0 100k 1 00823-017 0 –130 100 AD712 25 +VS 0.1µF SLEW RATE (V/µs) 8 VIN –VS –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 00823-020 15 –60 Figure 20. Slew Rate vs. Temperature +VS 0.1µF 100 90 Figure 23. Unity-Gain Follower + INPUT 8 1/2 2kΩ 0.1µF AD712 – 4 OUTPUT 100pF –VS 00823-021 10 0% 00823-023 SQUARE WAVE INPUT 5V 1µs Figure 21. THD Test Circuit Figure 24. Unity-Gain Follower Pulse Response (Large Signal) VOUT +VS 100 20kΩ 6 5 2.2kΩ 90 20V p-p VIN 5kΩ VOUT 10V IN 5kΩ 4 –VS 00823-022 CROSSTALK = 20 log 50mV 100ns Figure 22. Crosstalk Test Circuit Figure 25. Unity-Gain Follower Pulse Response (Small Signal) Rev. G | Page 9 of 20 00823-025 + + 3 AD712 1/2 1 7 AD712 1/2 – – 2 8 10 0% 00823-024 + 20 – 1/2 RL 2kΩ VOUT CL 100pF AD712 4 0.1µF AD712 5kΩ +VS 0.1µF 100 00823-026 50mV 200ns Figure 26. Unity-Gain Inverter Figure 28. Unity-Gain Inverter Pulse Response (Small Signal) 100 90 10 0% 00823-027 5V 1µs Figure 27. Unity-Gain Inverter Pulse Response (Large Signal) Rev. G | Page 10 of 20 00823-028 + SQUARE WAVE INPUT – VIN 5kΩ 90 8 1/2 RL 2kΩ VOUT CL 100pF AD712 4 0.1µF –VS 10 0% AD712 SETTLING TIME OPTIMIZING SETTLING TIME Most bipolar high speed digital-to-analog converters (DACs) have current outputs; therefore, for most applications, an external op amp is required for a current-to-voltage conversion. The settling time of the converter/op amp combination depends on the settling time of the DAC and output amplifier. A good approximation is In addition to a significant improvement in settling time, the low offset voltage, low offset voltage drift, and high open-loop gain of the AD71x family assure 12-bit accuracy over the full operating temperature range. The excellent high speed performance of the AD712 is shown in the oscilloscope photos in Figure 30 and Figure 31. Measurements were taken using a low input capacitance amplifier connected directly to the summing junction of the AD712 and both figures show a worst-case situation: full-scale input transition. The 4 kΩ [10 kΩ||8 kΩ = 4.4 kΩ] output impedance of the DAC, together with a 10 kΩ feedback resistor, produce an op amp noise gain of 3.25. The current output from the DAC produces a 10 V step at the op amp output (0 to −10 V shown in Figure 30, and −10 V to 0 V shown in Figure 31). Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%) requires that 375 μV or less appears at the summing junction. This means that the error between the input and output (that voltage which appears at the AD712 summing junction) must be less than 375 μV. As shown in Figure 30, the total settling time for the AD712/AD565A combination is 1.2 microseconds. t S Total = (tS DAC)2 + (t S AMP )2 The settling time of an op amp DAC buffer varies with the noise gain of the circuit, the DAC output capacitance, and the amount of external compensation capacitance across the DAC output scaling resistor. Settling time for a bipolar DAC is typically 100 ns to 500 ns. Previously, conventional op amps have required much longer settling times than have typical state-of-the-art DACs; therefore, the amplifier settling time has been the major limitation to a high speed, voltage output, digital-to-analog function. The introduction of the AD71x family of op amps with their 1 μs (to ±0.01% of final value) settling time permits the full high speed capabilities of most modern DACs to be realized. 0.1µF BIPOLAR OFFSET ADJUST REF OUT + 10V REF IN – 19.95kΩ 0.5mA IREF REF GND VCC R1 100Ω BIPOLAR OFF R2 GAIN 100Ω ADJUST 20V SPAN 5kΩ 10V SPAN 5kΩ DAC OUT AD565A 9.95kΩ 10pF +15V 0.1µF DAC 20kΩ IOUT = 4 × IREF × CODE IO 8kΩ Figure 29. ±10 V Voltage Output Bipolar DAC Rev. G | Page 11 of 20 00823-029 –VEE 0.1µF POWER GND MSB LSB – + 8 1/2 AD712 4 OUTPUT –10V TO +10V 0.1µF –15V AD712 Where 1mV 100 90 5V ωO = unity-gain frequency of the op amp. 2π SUMMING JUNCTION GN = noise gain of circuit ⎛1 + R ⎞ . ⎟ ⎜ ⎟ ⎜ ⎝ RO ⎠ 0V 10 0% 00823-030 This equation can then be solved for Cf OUTPUT CX = 500ns –10V RC X ωO + (1 − GN ) 2 − GN +2 RωO RωO (2) Figure 30. Settling Characteristics for AD712 with AD565A, Full-Scale Negative Transition 1mV 100 90 5V In these equations, Capacitance CX is the total capacitance appearing at the inverting terminal of the op amp. When modeling a DAC buffer application, the Norton equivalent circuit shown in Figure 32 can be used directly; Capacitance CX is the total capacitance of the output of the DAC plus the input capacitance of the op amp (because the two are in parallel). + 1/2 AD712 – SUMMING JUNCTION VOUT CF R RL CL 0V OUTPUT 10 0% –10V 500ns 00823-031 Figure 32. Simplified Model of the AD712 Used as a Current-Out DAC Buffer Figure 31. Settling Characteristics for AD712 with AD565A, Full-Scale Positive Transition OP AMP SETTLING TIME—A MATHEMATICAL MODEL The design of the AD712 gives careful attention to optimizing individual circuit components; in addition, a careful trade-off was made: the gain bandwidth product (4 MHz) and slew rate (20 V/μs) were chosen to be high enough to provide very fast settling time but not too high to cause a significant reduction in phase margin (and therefore, stability). Thus designed, the AD712 settles to ±0.01%, with a 10 V output step, in under 1 μs, while retaining the ability to drive a 250 pF load capacitance when operating as a unity-gain follower. If an op amp is modeled as an ideal integrator with a unity-gain crossover frequency of ωO/2π, then Equation 1 accurately describes the small signal behavior of the circuit of Figure 32, consisting of an op amp connected as an I-to-V converter at the output of a bipolar or CMOS DAC. This equation would completely describe the output of the system if not for the finite slew rate and other nonlinear effects of the op amp. VO −R = I IN R(C X ) 2 ⎛ G N s +⎜ ⎜ ω + RC f ωO ⎝O ⎞ ⎟ s +1 ⎟ ⎠ When RO and IO are replaced with their Thevenin VIN and RIN equivalents, the general-purpose inverting amplifier shown in Figure 33 is created. Note that when using this general model, Capacitance CX is either the input capacitance of the op amp, if a simple inverting op amp is being simulated, or the combined capacitance of the DAC output and the op amp input if the DAC buffer is being modeled. + 1/2 AD712 – RIN VIN CX VOUT CF R 00823-033 RL CL Figure 33. Simplified Model of the AD712 Used as an Inverter (1) In either case, Capacitance CX causes the system to go from a one-pole to a two-pole response; this additional pole increases settling time by introducing peaking or ringing in the op amp output. Because the value of CX can be estimated with reasonable accuracy, Equation 2 can be used to choose a small capacitor (CF) to cancel the input pole and optimize amplifier response. Figure 34 is a graphical solution of Equation 2 for the AD712 with R = 4 kΩ. Rev. G | Page 12 of 20 00823-032 IO RO CX AD712 60 5V 50 100 90 40 GN = 4.0 CX 30 GN = 3.0 GN = 2.0 GN = 1.5 10 0% 20 10 5mV 60 00823-034 500ns 0 0 10 20 30 CF 40 50 Figure 34. Value of Capacitor CF vs. Value of CX Figure 36. Settling Characteristics 0 V to −10 V Step Upper Trace: Output of AD712 Under Test (5 V/Div) Lower Trace: Amplified Error Voltage (0.01%/Div) The photos of Figure 35 and Figure 36 show the dynamic response of the AD712 in the settling test circuit of Figure 37. 5V 100 90 The input of the settling time fixture is driven by a flat top pulse generator. The error signal output from the false summing node of A1 is clamped, amplified by A2, and then clamped again. The error signal is thus clamped twice: once to prevent overloading Amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. The Tektronix oscilloscope preamp type 7A26 was carefully chosen because it does not overload with these input levels. Amplifier A2 needs to be a very high speed FET-input op amp; it provides a gain of 10, amplifying the error signal output of A1. 10 0% 5mV 500ns Figure 35. Settling Characteristics 0 V to +10 V Step Upper Trace: Output of AD712 Under Test (5 V/Div) Lower Trace: Amplified Error Voltage (0.01%/Div) 00823-035 5pF HP2835 + 1/2 AD712 – 0.47µF 0.47µF 205Ω VERROR × 5 TEKTRONIX 7A26 OSCILLOSCOPE PREAMP INPUT SECTION 20pF 1MΩ HP2835 4.99kΩ DATA DYNAMICS 5109 VIN 10kΩ 200Ω 4.99kΩ 5 TO 18pF –15V +15V 10kΩ 1.1kΩ 0.2 TO 0.6pF 10kΩ AD712 5kΩ 0.1µF (OR EQUIVALENT FLAT TOP PULSE GENERATION) 1/2 VOUT 10pF 0.1µF –15V +15V Figure 37. Settling Time Test Circuit Rev. G | Page 13 of 20 00823-037 00823-036 GN = 1.0 – + AD712 APPLICATIONS INFORMATION GUARDING The low input bias current (15 pA) and low noise characteristics of the AD712 BiFET op amp make it suitable for electrometer applications such as photo diode preamplifiers and picoampere current-to-voltage converters. The use of a guarding technique, such as that shown in Figure 38, in printed circuit board layout and construction is critical to minimize leakage currents. The guard ring is connected to a low impedance potential at the same level as the inputs. High impedance signal lines should not be extended for any unnecessary length on the printed circuit board. PDIP (N), CERDIP (Q), AND SOIC (R) PACKAGES. 4 5 6 3 2 7 00823-038 Figure 39 and Figure 40 show the AD712 and AD7545 (12-bit CMOS DAC) configured for unipolar binary (2-quadrant multiplication) or bipolar (4-quadrant multiplication) operation. Capacitor C1 provides phase compensation to reduce overshoot and ringing. VDD R2A* C1A 33pF OUT1 VREF +15V 0.1µF VIN R1A* AD7545 AGND DGND ANALOG COMMON *REFER TO TABLE 3 DB11 TO DB0 VDD R2B* C1B 33pF 1 AGND DGND ANALOG COMMON DB11 TO DB0 DIGITAL-TO-ANALOG CONVERTER APPLICATIONS The AD712 is an excellent output amplifier for CMOS DACs. It can be used to perform both 2-quadrant and 4-quadrant operations. The output impedance of a DAC using an inverted R-2R ladder approaches R for codes containing many 1s, and 3R for codes containing a single 1. For codes containing all 0s, the output impedance is infinite. For example, the output resistance of the AD7545 modulates between 11 kΩ and 33 kΩ. Therefore, with an 11 kΩ DAC internal feedback resistance, the noise gain varies from 2 to 4/3. This changing noise gain modulates the effect of the input offset voltage of the amplifier, resulting in nonlinear DAC amplifier performance. The AD712K with guaranteed 700 μV offset voltage minimizes this effect to achieve 12-bit performance. VDD R2* C1 33pF OUT1 VREF AD7545 AGND DB11 TO DB0 12 DATA INPUT *FOR VALUES OF R1 AND R2 SEE TABLE 3 DGND +15V –15V Figure 39. Unipolar Binary Operation R1 and R2 calibrate the zero offset and gain error of the DAC. Specific values for these resistors depend upon the grade of AD7545 and are listed in Table 3. Table 3. Recommended Trim Resistor Values vs. Grades of the AD7545 for VDD = 5 V Trim Resistor R1 R2 JN/AQ 500 Ω 150 Ω KN/BQ 200 Ω 68 Ω LN 100 Ω 33 Ω GLN 20 Ω 6.8 Ω R4 20kΩ 1% 0.1µF R5 20kΩ 1% ANALOG COMMON Figure 40. Bipolar Operation Rev. G | Page 14 of 20 00823-040 + + R1* AD712 R3 10kΩ 1% – VIN – GAIN ADJUST VDD RFB 1/2 AD712 0.1µF 1/2 VOUT –15V 00823-039 *REFER TO TABLE 3 + Figure 38. Board Layout for Guarding Inputs VIN R1B* VREF AD7545 – 8 GAIN ADJUST VDD RFB OUT1 – + GAIN ADJUST VDD RFB AD712 1/2 VOUTA AD712 0.1µF 1/2 VOUTB AD712 Figure 41 and Figure 42 show the settling time characteristics of the AD712 when used as a DAC output buffer for the AD7545. 1mV 100 90 DRIVING THE ANALOG INPUT OF AN ANALOG-TO-DIGITAL CONVERTER An op amp driving the analog input of an ADC, such as that shown in Figure 43, must be capable of maintaining a constant output voltage under dynamically changing load conditions. In successive approximation converters, the input current is compared to a series of switched trial currents. The comparison point is diode clamped, but can deviate several hundred millivolts resulting in high frequency modulation of analog-to-digital input current. The output impedance of a feedback amplifier is made artificially low by the loop gain. At high frequencies, where the loop gain is low, the amplifier output impedance can approach its open-loop value. Most IC amplifiers exhibit a minimum open-loop output impedance of 25 Ω due to currentlimiting resistors. 12/8 CS AO GAIN ADJUST R2 100Ω R1 100Ω OFFSET ADJUST 1/2 STS HIGH BITS 10 0% 00823-041 5V 500ns Figure 41. Positive Settling Characteristics for AD712 with AD7545 1mV 100 90 R/C AD574A MIDDLE CE BITS REF IN REF OUT BIP OFF 10VIN 20VIN AC LOW BITS +5V +15V –15V DC 00823-043 +15V 10 0% 00823-042 0.1µF 5V 500ns Figure 42. Negative Settling Characteristics for AD712 with AD7545 NOISE CHARACTERISTICS The random nature of noise, particularly in the flicker noise region, makes it difficult to specify in practical terms. At the same time, designers of precision instrumentation require certain guaranteed maximum noise levels to realize the full accuracy of their equipment. All grades of the AD712 are sample tested on an AQL basis to a limit of 6 μV p-p, 0.1 Hz to 10 Hz. A few hundred microamps reflected from the change in converter loading can introduce errors in instantaneous input voltage. If the analog-to-digital conversion speed is not excessive and the bandwidth of the amplifier is sufficient, the amplifier output returns to the nominal value before the converter makes its comparison. However, many amplifiers have relatively narrow bandwidth yielding slow recovery from output transients. The AD712 is ideally suited to drive high speed analog-to-digital converters because it offers both wide bandwidth and high open-loop gain. Rev. G | Page 15 of 20 + –15V ±10V ANALOG INPUT – AD712 0.1µF ANALOG COM Figure 43. AD712 as An ADC Unity-Gain Buffer AD712 1mV 100 90 PD711 BUFF DRIVING A LARGE CAPACITIVE LOAD The circuit in Figure 46 uses a 100 Ω isolation resistor that enables the amplifier to drive capacitive loads exceeding 1500 pF; the resistor effectively isolates the high frequency feedback from the load and stabilizes the circuit. Low frequency feedback is returned to the amplifier summing junction via the low-pass filter formed by the 100 Ω series resistor and the Load Capacitance CL. Figure 47 shows a typical transient response for this connection. 00823-044 10 0% 500mV –10V ADC IN 200ns 4.99kΩ 30pF +VIN 0.1µF +– Figure 44. ADC Input Unity Gain Buffer Recovery Times, −10 V ADC IN 4.99kΩ INPUT 100 90 R1 2kΩ 10kΩ 20Ω 10 0% 00823-045 C1 UP TO 00823-046 1500pF 1500pF 1000pF Figure 46. Circuit for Driving a Large Capacitive Load 500mV –5V ADC IN 200ns 5V 100 90 Figure 45. ADC Input Unity Gain Buffer Recovery Times, −5 V ADC IN 10 0% 00823-047 Figure 47. Transient Response RL = 2 kΩ, CL = 500 pF Rev. G | Page 16 of 20 + TYPICAL CAPACITANCE LIMIT FOR VARIOUS LOAD RESISTORS – 1mV PD711 BUFF AD712 0.1µF –+ –VIN 1/2 100Ω C1 R1 OUTPUT 1µs AD712 FILTERS ACTIVE FILTER APPLICATIONS In active filter applications using op amps, the dc accuracy of the amplifier is critical to optimal filter performance. The amplifier offset voltage and bias current contribute to output error. Offset voltage is passed by the filter and can be amplified to produce excessive output offset. For low frequency applications requiring large value input resistors, bias currents flowing through these resistors also generate an offset voltage. In addition, at higher frequencies, the op amp dynamics must be carefully considered. Here, slew rate, bandwidth, and openloop gain play a major role in op amp selection. The slew rate must be fast as well as symmetrical to minimize distortion. The amplifier bandwidth in conjunction with the filter gain dictates the frequency response of the filter. The use of a high performance amplifier such as the AD712 minimizes both dc and ac errors in all active filter applications. R1 20kΩ R2 20kΩ C2 280pF C1 560pF +15V 0.1µF VIN + 1/2 AD712 – VOUT 0.1µF 00823-048 –15V Figure 48. Second-Order Low-Pass Filter An important property of filters is their out-of-band rejection. The simple 20 kHz low-pass filter shown in Figure 48, can be used to condition a signal contaminated with clock pulses or sampling glitches that have considerable energy content at high frequencies. The low output impedance and high bandwidth of the AD712 minimize high frequency feedthrough as shown in Figure 49. The upper trace is that of another low cost BiFET op amp showing 17 dB more feedthrough at 5 MHz. REF 20.0 dBm 10dB/DIV RANGE 15.0dBm OFFSET .0 Hz 0dB SECOND-ORDER LOW-PASS FILTER Figure 48 depicts the AD712 configured as a second-order, Butterworth low-pass filter. With the values as shown, the corner frequency is 20 kHz; however, the wide bandwidth of the AD712 permits a corner frequency as high as several hundred kilohertz. Equations for component selection are as follows: R1 = R2 = A user selected value (10 kΩ to 100 kΩ, typical) C1 (in farads) = 1.414 (2π) f cutoff (R1) TYPICAL BIFET ( ) C2 = 0.707 (2π) f cutoff (R1) ( ) AD712 CENTER 5 000 000.0Hz RBW 30kHz VBW 30kHz SPAN 10 000 000.0Hz ST .8 SEC Figure 49. High Frequency Feedthrough Rev. G | Page 17 of 20 00823-049 AD712 +15V 0.1µF +15V 0.1µF 0.001µF 2800Ω 4.9395E –15 A 6190Ω 5.9276E –15 6490Ω 5.9276E –15 6190Ω 4.9395E –15 2800Ω VIN + A1 AD711 – + A2 0.1µF + B + C + D + AD711 – VOUT 0.1µF 4.99kΩ –15V 100kΩ * * * * 0.001µF 124kΩ –15V 00823-050 4.99kΩ *SEE TEXT Figure 50. 9-Pole Chebychev Filter 9-POLE CHEBYCHEV FILTER Figure 50 and Figure 51 show the AD712 and its dual counterpart, the AD711, as a 9-pole Chebychev filter using active frequency dependent negative resistors (FDNRs). With a cutoff frequency of 50 kHz and better than 90 dB rejection, it can be used as an antialiasing filter for a 12-bit data acquisition system with 100 kHz throughput. As shown in Figure 50, the filter is comprised of four FDNRs (A, B, C, D) having values of 4.9395 × 10−15 and 5.9276 × 10–15 farad-seconds. Each FDNR active network provides a two-pole response for a total of eight poles. The ninth pole consists of a 0.001 μF capacitor and a 124 kΩ resistor at Pin 3 of Amplifier A2. Figure 51 depicts the circuits for each FDNR with the proper selection of R. To achieve optimal performance, the 0.001 μF capacitors must be selected for 1% or better matching and all resistors should have 1% or better tolerance. + 0.001µF +15V 0.1µF + 1/2 R AD712 – 0.1µF 1/2 AD712 Figure 51. FDNR for 9-Pole Chebychev Filter REF 5.0dBm 10dB/DIV MARKER 96 800.0Hz –90dBm RANGE –5.0dBm START.0Hz RBW 300Hz VBW 30Hz STOP 200 000.0Hz ST 69.6 SEC Figure 52. High Frequency Response for 9-Pole Chebychev Filter Rev. G | Page 18 of 20 00823-052 00823-051 R: 24.9kΩ FOR 4.9395E –15 29.4kΩ FOR 5.9276E –15 – 0.001µF –15V 1.0kΩ 4.99kΩ + AD712 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 1 5 0.005 (0.13) MIN 8 0.055 (1.40) MAX 5 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.310 (7.87) 0.220 (5.59) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 1 4 PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 0.100 (2.54) BSC 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 15° 0° 0.015 (0.38) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) MIN 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.430 (10.92) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) COMPLIANT TO JEDEC STANDARDS MS-001-BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 53. 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) Figure 54. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 4 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) × 45° 0.25 (0.0099) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 55. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. G | Page 19 of 20 AD712 ORDERING GUIDE Model AD712AQ AD712JN AD712JNZ1 AD712JR AD712JR-REEL AD712JR-REEL7 AD712JRZ1 AD712JRZ-REEL1 AD712JRZ-REEL71 AD712KN AD712KNZ1 AD712KR AD712KR-REEL AD712KR-REEL7 AD712KRZ1 AD712KRZ-REEL1 AD712KRZ-REEL71 AD712SQ/883B 1 Temperature Range −40°C to +85°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C −55°C to +125°C Package Description 8-Lead CERDIP 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead CERDIP Package Option Q-8 N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 Q-8 Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 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