8-Channel, Low Noise, Low Power, 24-Bit,
Sigma-Delta ADC with PGA and Reference
AD7124-8
Data Sheet
FEATURES
Low-side power switch
General-purpose outputs
Multiple filter options
Internal temperature sensor
Self and system calibration
Sensor burnout detection
Automatic channel sequencer
Per channel configuration
Power supply: 2.7 V to 3.6 V and ±1.8 V
Independent interface power supply
Power-down current: 5 µA maximum
Temperature range: −40°C to +125°C
32-lead LFCSP
3-wire or 4-wire serial interface
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
ESD: 4 kV
3 power modes
RMS noise
Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical)
Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical)
Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical)
Up to 22 noise free bits in all power modes (gain = 1)
Output data rate
Full power: 9.38 SPS to 19,200 SPS
Mid power: 2.34 SPS to 4800 SPS
Low power: 1.17 SPS to 2400 SPS
Rail-to-rail analog inputs for gains > 1
Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle
settling)
Diagnostic functions (which aid safe integrity level (SIL)
certification)
Crosspoint multiplexed analog inputs
8 differential/15 pseudo differential inputs
Programmable gain (1 to 128)
Band gap reference with 10 ppm/°C drift maximum (70 µA)
(B grade)
Matched programmable excitation currents
Internal clock oscillator
On-chip bias voltage generator
APPLICATIONS
Temperature measurement
Pressure measurement
Industrial process control
Instrumentation
Smart transmitters
FUNCTIONAL BLOCK DIAGRAM
1.9V
LDO
REGCAPA
VBIAS
BANDGAP
REF
AVDD
AVSS
CROSSPOINT
MUX
AIN0/IOUT/VBIAS
AIN1/IOUT/VBIAS
AIN2/IOUT/VBIAS/P1
AIN3/IOUT/VBIAS/P2
AIN4/IOUT/VBIAS/P3
AIN5/IOUT/VBIAS/P4
AIN6/IOUT/VBIAS
AIN7/IOUT/VBIAS
AIN8/IOUT/VBIAS
AIN9/IOUT/VBIAS
AIN10/IOUT/VBIAS
AIN11/IOUT/VBIAS
AIN12/IOUT/VBIAS
AIN13/IOUT/VBIAS
AIN14/IOUT/VBIAS/REFIN2(+)
AIN15/IOUT/VBIAS/REFIN2(–)
REFIN2(+)
REFIN2(–)
AVSS
AVDD
1.8V
LDO
REFERENCE
BUFFERS
BUF
BURNOUT
DETECT
IOVDD REGCAPD
REFIN1(+) REFIN1(–)
REFOUT
PGA1
24-BIT
Σ-Δ ADC
PGA2
BUF
VARIABLE
DIGITAL
FILTER
SERIAL
INTERFACE
AND
CONTROL
LOGIC
X-MUX
GPOs
TEMPERATURE
SENSOR
PSW
POWER
SWITCH
SCLK
CS
ANALOG
BUFFERS
AVSS
DIAGNOSTICS
DOUT/RDY
DIN
CHANNEL
SEQUENCER
SYNC
DIAGNOSTICS
AVDD
COMMUNICATIONS
POWER SUPPLY
SIGNAL CHAIN
DIGITAL
EXCITATION
CURRENTS
INTERNAL
CLOCK
CLK
AD7124-8
AVSS
AVSS
DGND
13048-001
AVDD
Figure 1.
Rev. E
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AD7124-8
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Calibration................................................................................... 52
Applications ....................................................................................... 1
Span and Offset Limits .............................................................. 53
Functional Block Diagram .............................................................. 1
System Synchronization ............................................................ 54
Revision History ............................................................................... 3
Digital Filter .................................................................................... 55
General Description ......................................................................... 5
Sinc4 Filter ................................................................................... 55
Specifications..................................................................................... 6
Sinc3 Filter ................................................................................... 57
Timing Characteristics .............................................................. 11
Fast Settling Mode (Sinc4 + Sinc1 Filter) .................................. 59
Absolute Maximum Ratings .......................................................... 14
Fast Settling Mode (Sinc3 + Sinc1 Filter) .................................. 61
Thermal Resistance .................................................................... 14
Post Filters ................................................................................... 63
ESD Caution ................................................................................ 14
Summary of Filter Options ....................................................... 66
Pin Configuration and Function Descriptions ........................... 15
Diagnostics ...................................................................................... 67
Terminology .................................................................................... 18
Signal Chain Check .................................................................... 67
Typical Performance Characteristics ........................................... 19
Reference Detect ......................................................................... 67
RMS Noise and Resolution............................................................ 28
Calibration, Conversion, and Saturation Errors .................... 67
Full Power Mode ......................................................................... 28
Overvoltage/Undervoltage Detection ..................................... 67
Mid Power Mode ........................................................................ 31
Power Supply Monitors ............................................................. 68
Low Power Mode ........................................................................ 34
LDO Monitoring ........................................................................ 68
Getting Started ................................................................................ 37
MCLK Counter ........................................................................... 68
Overview...................................................................................... 37
SPI SCLK Counter...................................................................... 68
Power Supplies ............................................................................ 38
SPI Read/Write Errors ............................................................... 69
Digital Communication............................................................. 38
SPI_IGNORE Error ................................................................... 69
Configuration Overview ........................................................... 40
Checksum Protection ................................................................ 69
ADC Circuit Information .............................................................. 45
Memory Map Checksum Protection ....................................... 69
Analog Input Channel ............................................................... 45
ROM Checksum Protection...................................................... 70
External Impedance When Using a Gain of 1 ........................ 46
Burnout Currents ....................................................................... 71
Programmable Gain Array (PGA) ........................................... 47
Temperature Sensor ................................................................... 71
Reference ..................................................................................... 47
Grounding and Layout .................................................................. 72
Bipolar/Unipolar Configuration .............................................. 47
Applications Information .............................................................. 73
Data Output Coding .................................................................. 48
Temperature Measurement Using a Thermocouple .............. 73
Excitation Currents .................................................................... 48
Temperature Measurement Using an RTD ............................. 74
Bridge Power-Down Switch ...................................................... 48
Flowmeter.................................................................................... 76
Logic Outputs.............................................................................. 48
On-Chip Registers .......................................................................... 78
Bias Voltage Generator .............................................................. 49
Communications Register......................................................... 79
Clock ............................................................................................ 49
Status Register ............................................................................. 79
Power Modes ............................................................................... 49
ADC_CONTROL Register ....................................................... 80
Standby and Power-Down Modes............................................ 49
Data Register ............................................................................... 82
Digital Interface .......................................................................... 50
IO_CONTROL_1 Register........................................................ 82
DATA_STATUS .......................................................................... 52
IO_CONTROL_2 Register........................................................ 84
Serial Interface Reset (DOUT_RDY_DEL and CS_EN Bits) 52
ID Register................................................................................... 85
Reset ............................................................................................. 52
Error Register .............................................................................. 85
Rev. E | Page 2 of 94
Data Sheet
AD7124-8
ERROR_EN Register ..................................................................86
Offset Registers............................................................................ 92
MCLK_COUNT Register ..........................................................87
Gain Registers .............................................................................. 92
Channel Registers........................................................................88
Outline Dimensions ........................................................................ 93
Configuration Registers .............................................................90
Ordering Guide ........................................................................... 94
Filter Registers .............................................................................91
REVISION HISTORY
4/2018—Rev. D to Rev. E
Changes to Features Section ............................................................ 1
Changes to General Description Section ....................................... 5
Added Table 1; Renumbered Sequentially ..................................... 5
Changes to Drift Parameter, External REFIN Voltage Parameter,
and Note 12, Table 3 .......................................................................... 8
Changes to Table 7 ..........................................................................16
Changes to Figure 14 ......................................................................19
Changes to Figure 42, Figure 44, and Figure 45 ..........................24
Changes to Reference Section........................................................37
Changes to Accessing the ADC Register Map Section and Reset
Column, Table 39 ............................................................................39
Changes to External Impedance When Using a Gain of 1
Section ..............................................................................................46
Changes to Reference Section........................................................47
Changes to Standby and Power-Down Modes Section ..............49
Changes to Calibration Section .....................................................53
Change to Sinc3 Output Data Rate and Settling Time Section .57
Change to Calibration, Conversion, and Saturation Errors
Section ..............................................................................................67
Changes to MCLK Counter Section .............................................68
Changes to Memory Map Checksum Protection Section .........69
Changes to Addr. 0x05, Reset Column, Table 64 and Note 1,
Table 64 .............................................................................................78
Changes to Mode Value 0010, Description Column, Table 68
and Mode Value 0110, Description Column, Table 68 ..............81
Changes to ID Register Section .....................................................85
Changes to Description Column, Table 73 ..................................88
Changes to Bits[4:0], Description Column, Table 74 .................89
Changes to Configuration Registers Section ...............................90
Updated Outline Dimensions ........................................................93
Changes to Ordering Guide ...........................................................94
7/2016—Rev. C to Rev. D
Change to Features Section .............................................................. 1
Changes to Specifications Section and Table 2.............................. 5
Changes to Table 4 ..........................................................................13
Change to Table 8 ............................................................................27
Changes to Table 9 and Table 10 ...................................................28
Change to Table 25 ..........................................................................32
Changes to Table 28 ........................................................................33
Change to Table 29 ..........................................................................34
Change to Accessing the ADC Register Map Section and
Table 38 .............................................................................................38
Changes to Diagnostics Section, Table 44, and Table 45 ...........41
Added External Impedance When Using a Gain of 1 Section
and Figure 74, Figure 75, and Figure 76; Renumbered
Sequentially ...................................................................................... 45
Changes to Standby and Power-Down Modes Section .............. 48
Changes to Single Conversion Mode Section ............................. 49
Changes to Continuous Read Mode Section ............................... 51
Changes to Sinc4 Output Data Rate/Settling Time Section ....... 54
Changes to Sinc4 Zero Latency Section ....................................... 55
Changes to Sinc3 Output Data Rate and Settling Time Section ...... 56
Changes to Sinc3 Zero Latency Section ........................................ 57
Change to Output Data Rate and Settling Time, Sinc4 + Sinc1
Filter Section .................................................................................... 59
Change to Output Data Rate and Settling Time, Sinc3 + Sinc1
Filter Section .................................................................................... 60
Changes to SPI_IGNORE Error Section ...................................... 68
Added ROM Checksum Protection Section................................ 69
Changes to Table 63 ........................................................................ 77
Changes to ID Register Section, Error Register Section, and
Table 70 ............................................................................................. 84
Changes to ERROR_EN Register Section and Table 71 ............ 85
Changes to Table 73 ........................................................................ 88
12/2015—Rev. B to Rev. C
Changed +105°C to +125°C .........................................Throughout
Change to Features Section.............................................................. 1
Change to General Description Section......................................... 4
Changes to Table 2 ............................................................................ 5
Added Endnote 4, Table 2; Renumbered Sequentially ................. 9
Change to Table 4 ............................................................................ 13
Changes to Figure 16 Through Figure 21 .................................... 19
Changes to Figure 22 Through Figure 25 .................................... 20
Changes to Figure 29, Figure 32, and Figure 33 .......................... 21
Changes to Figure 36 Through Figure 39 .................................... 22
Changes to Figure 40 Through Figure 45 .................................... 23
Changes to Figure 46 and Figure 47 ............................................. 24
Changes to Figure 63 ...................................................................... 26
Change to Table 17 .......................................................................... 30
Change to Accessing the ADC Register Map Section ................ 38
Change to Table 63 .......................................................................... 76
Change to ID Register Section ...................................................... 83
Changes to Table 73 ........................................................................ 86
Changes to Ordering Guide ........................................................... 91
Rev. E | Page 3 of 94
AD7124-8
Data Sheet
7/2015—Rev. A to Rev. B
Changes to Figure 29 ...................................................................... 21
Change to Single Conversion Mode Section............................... 49
Changes to Calibration Section .................................................... 51
Changes to Figure 82 ...................................................................... 53
Changes to Figure 90 ...................................................................... 56
Changes to Figure 98 ...................................................................... 58
Changes to Figure 104.................................................................... 60
Changes to Reference Detect Section and Figure 118 ............... 65
Changes to Table 70 ........................................................................ 83
Changes to Table 71 ................................................................................. 84
Changes to Table 75 ........................................................................ 89
5/2015—Rev. 0 to Rev. A
Changes to Temperature Measurement Using a Thermocouple
Section .............................................................................................. 71
Changed AINM to AINP, Table 70 .............................................. 83
Changed REFOUT to Internal Reference, Table 73................... 86
4/2015—Revision 0: Initial Version
Rev. E | Page 4 of 94
Data Sheet
AD7124-8
GENERAL DESCRIPTION
The AD7124-8 is a low power, low noise, completely integrated
analog front end for high precision measurement applications.
The device contains a low noise, 24-bit Σ-Δ analog-to-digital
converter (ADC), and can be configured to have 8 differential
inputs or 15 single-ended or pseudo differential inputs. The onchip low gain stage ensures that signals of small amplitude can
be interfaced directly to the ADC.
One of the major advantages of the AD7124-8 is that it gives the
user the flexibility to employ one of three integrated power
modes. The current consumption, range of output data rates,
and rms noise can be tailored with the power mode selected.
The device also offers a multitude of filter options, ensuring that
the user has the highest degree of flexibility.
The AD7124-8 can achieve simultaneous 50 Hz and 60 Hz
rejection when operating at an output data rate of 25 SPS (single
cycle settling), with rejection in excess of 80 dB achieved at lower
output data rates.
The AD7124-8 establishes the highest degree of signal chain
integration. The device contains a precision, low noise, low
drift internal band gap reference and accepts an external
differential reference, which can be internally buffered. Other
key integrated features include programmable low drift excitation
current sources, burnout currents, and a bias voltage generator,
which sets the common-mode voltage of a channel to AVDD/2.
The low-side power switch enables the user to power down
bridge sensors between conversions, ensuring the absolute
minimal power consumption of the system. The device also
allows the user the option of operating with either an internal
clock or an external clock.
The integrated channel sequencer allows several channels to be
enabled simultaneously, and the AD7124-8 sequentially converts
on each enabled channel, simplifying communication with the
device. As many as 16 channels can be enabled at any time, a
channel being defined as an analog input or a diagnostic such as
a power supply check or a reference check. This unique feature
allows diagnostics to be interleaved with conversions. The
AD7124-8 also supports per channel configuration. The device
allows eight configurations or setups. Each configuration
consists of gain, filter type, output data rate, buffering, and
reference source. The user can assign any of these setups on a
channel by channel basis.
The AD7124-8 also has extensive diagnostic functionality
integrated as part of its comprehensive feature set. These
diagnostics include a cyclic redundancy check (CRC), signal
chain checks, and serial interface checks, which lead to a more
robust solution. These diagnostics reduce the need for external
components to implement diagnostics, resulting in reduced
board space needs, reduced design cycle times, and cost savings.
The failure modes effects and diagnostic analysis (FMEDA) of a
typical application has shown a safe failure fraction (SFF) greater
than 90% according to IEC 61508.
The device operates with a single analog power supply from 2.7 V
to 3.6 V or a dual 1.8 V power supply. The digital supply has a
range of 1.65 V to 3.6 V. It is specified for a temperature range
of −40°C to +125°C. The AD7124-8 is housed in a 32-lead
LFCSP package.
Note that, throughout this data sheet, multifunction pins, such
as DOUT/RDY, are referred to either by the entire pin name or
by a single function of the pin, for example, RDY, when only
that function is relevant.
E
A
E
A
A
The AD7124-8 B grade has some operational and performance
differences from the AD7124-8. Table 1 lists the differences.
Unless otherwise noted, all references to AD7124-8 refer to the
device and not to the B grade.
Table 1. Differences Between AD7124-8 and AD7124-8 B Grade
Parameter
LFCSP Package Height
Internal Reference Drift
Excitation Currents in Standby Mode
Gain of 1, High Impedance Loads
AD7124-8
0.75 mm
15 ppm/°C
Disabled
Impacts settling time when switching channels
AD7124-8 B Grade
0.95 mm
10 ppm/°C
Remain active if enabled
Does not impact settling time when switching channels
Table 2. AD7124-8 Overview
Parameter
Maximum Output Data Rate
RMS Noise (Gain = 128)
Peak-to-Peak Resolution at 1200 SPS
(Gain = 1)
Typical Current (ADC + PGA)
Low Power Mode
2400 SPS
24 nV
16.4 bits
Mid Power Mode
4800 SPS
20 nV
17.1 bits
Full Power Mode
19,200 SPS
23 nV
18 bits
255 µA
355 µA
930 µA
Rev. E | Page 5 of 94
AD7124-8
Data Sheet
SPECIFICATIONS
AVDD = 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V,
REFINx(+) = 2.5 V, REFINx(−) = AVSS, master clock = 614.4 kHz, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1
ADC
Output Data Rate, fADC
Low Power Mode
Mid Power Mode
Full Power Mode
No Missing Codes2
Min
Typ
1.17
2.34
9.38
24
24
Max
Unit
2400
4800
19,200
SPS
SPS
SPS
Bits
Bits
ppm of FSR
ppm of FSR
FS3 > 2, sinc4 filter
FS3 > 8, sinc3 filter
See the RMS Noise and Resolution
section
See the RMS Noise and Resolution
section
Gain = 12
Gain > 14
±15
200/gain
In order of
noise
µV
µV
Gain = 1 to 8
Gain = 16 to 128
10
80
40
10
40
20
10
nV/°C
nV/°C
nV/°C
nV/°C
nV/°C
nV/°C
nV/°C
Gain = 1 or gain > 16
Gain = 2 to 8
Gain = 16
Gain = 1 or gain > 16
Gain = 2 to 8
Gain = 16
%
%
%
%
Gain = 1, TA = 25°C
Gain > 1
Gain = 2 to 8, TA = 25°C
Gain = 16 to 128
Resolution
RMS Noise and Update Rates
Integral Nonlinearity (INL)
−4
−15
Offset Error5
Before Calibration
After Internal Calibration/System
Calibration
Offset Error Drift vs. Temperature6
Low Power Mode
Mid Power Mode
Full Power Mode
Gain Error5, 7
Before Internal Calibration
After Internal Calibration
After System Calibration
Gain Error Drift vs. Temperature
Power Supply Rejection
Low Power Mode
Mid Power Mode2
Full Power Mode
Common-Mode Rejection8
At DC2
At DC
Sinc3, Sinc4 Filter2
At 50 Hz, 60 Hz
At 50 Hz
At 60 Hz
±1
±2
−0.0025
−0.016
+4
+15
+0.0025
−0.3
+0.004
±0.025
In order of
noise
1
+0.016
2
87
96
92
100
99
85
105
1029, 2
115
1059, 2
Test Conditions/Comments
ppm/°C
dB
dB
dB
dB
dB
90
115
120
120
120
120
Rev. E | Page 6 of 94
AIN = 1 V/gain, external reference
Gain = 2 to 16
Gain = 1 or gain > 16
Gain = 2 to 16
Gain = 1 or gain > 16
dB
dB
dB
dB
dB
AIN = 1 V, gain = 1
AIN = 1 V/gain, gain 2 or 4
AIN = 1 V/gain, gain 2 or 4
AIN = 1 V/gain, gain ≥ 8
AIN = 1 V/gain, gain ≥ 8
dB
dB
dB
10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
50 SPS, 50 Hz ± 1 Hz
60 SPS, 60 Hz ± 1 Hz
Data Sheet
Parameter1
Fast Settling Filters2
At 50 Hz
At 60 Hz
Post Filters2
At 50 Hz, 60 Hz
Normal Mode Rejection2
Sinc4 Filter
External Clock
At 50 Hz, 60 Hz
At 50 Hz
At 60 Hz
Internal Clock
At 50 Hz, 60 Hz
At 50 Hz
At 60 Hz
Sinc3 Filter
External Clock
At 50 Hz, 60 Hz
At 50 Hz
At 60 Hz
Internal Clock
At 50 Hz, 60 Hz
At 50 Hz
At 60 Hz
Fast Settling Filters
External Clock
At 50 Hz
At 60 Hz
Internal Clock
At 50 Hz
At 60 Hz
Post Filters
External Clock
At 50 Hz, 60 Hz
Internal Clock
At 50 Hz, 60 Hz
AD7124-8
Min
Typ
Max
Unit
Test Conditions/Comments
115
115
dB
dB
First notch at 50 Hz, 50 Hz ± 1 Hz
First notch at 60 Hz, 60 Hz ± 1 Hz
130
130
dB
dB
20 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
25 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
120
80
dB
dB
120
120
dB
dB
10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
50 SPS, REJ6010 =1, 50 Hz ± 1 Hz,
60 Hz ± 1 Hz
50 SPS, 50 Hz ± 1 Hz
60 SPS, 60 Hz ± 1 Hz
98
66
dB
dB
92
92
dB
dB
100
65
dB
dB
100
100
dB
dB
73
52
dB
dB
68
68
dB
dB
10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
50 SPS, REJ6010 = 1, 50 Hz ± 1 Hz,
60 Hz ± 1 Hz
50 SPS, 50 Hz ± 1 Hz
60 SPS, 60 Hz ± 1 Hz
40
40
dB
dB
First notch at 50 Hz, 50 Hz ± 0.5 Hz
First notch at 60 Hz, 60 Hz ± 0.5 Hz
24.5
24.5
dB
dB
First notch at 50 Hz, 50 Hz ± 0.5 Hz
First notch at 60 Hz, 60 Hz ± 0.5 Hz
86
62
dB
dB
20 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
25 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
67
50
dB
dB
20 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
25 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
Rev. E | Page 7 of 94
10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
50 SPS, REJ6010 = 1, 50 Hz ± 1 Hz,
60 Hz ± 1 Hz
50 SPS, 50 Hz ± 1 Hz
60 SPS, 60 Hz ± 1 Hz
10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
50 SPS, REJ6010 = 1, 50 Hz ± 1 Hz,
60 Hz ± 1 Hz
50 SPS, 50 Hz ± 1 Hz
60 SPS, 60 Hz ± 1 Hz
AD7124-8
Parameter1
ANALOG INPUTS11
Differential Input Voltage Ranges12
Absolute AIN Voltage Limits2
Gain = 1 (Unbuffered)
Gain = 1 (Buffered)
Gain > 1
Analog Input Current
Gain > 1 or Gain = 1 (Buffered)
Low Power Mode
Absolute Input Current
Differential Input Current
Analog Input Current Drift
Mid Power Mode
Absolute Input Current
Differential Input Current
Analog Input Current Drift
Full Power Mode
Absolute Input Current
Differential Input Current
Analog Input Current Drift
Gain = 1 (Unbuffered)
Absolute Input Current
Analog Input Current Drift
REFERENCE INPUT
Internal Reference
Initial Accuracy
Drift
AD7124-8
AD7124-8 B Grade
Output Current
Load Regulation
Power Supply Rejection
External Reference
External REFIN Voltage2
Absolute REFIN Voltage Limits2
Reference Input Current
Buffered
Low Power Mode
Absolute Input Current
Reference Input Current Drift
Mid Power Mode
Absolute Input Current
Reference Input Current Drift
Full Power Mode
Absolute Input Current
Reference Input Current Drift
Unbuffered
Absolute Input Current
Reference Input Current Drift
Normal Mode Rejection
Common-Mode Rejection
Data Sheet
Min
Typ
Max
±VREF/gain
AVSS − 0.05
AVSS + 0.1
AVSS − 0.05
AVDD + 0.05
AVDD − 0.1
AVDD + 0.05
Unit
Test Conditions/Comments
V
VREF = REFINx(+) − REFINx(−), or
internal reference
V
V
V
±1
±0.2
25
nA
nA
pA/°C
±1.2
±0.4
25
nA
nA
pA/°C
±3.3
±1.5
25
nA
nA
pA/°C
±2.65
1.1
µA/V
nA/V/°C
Current varies with input voltage
2.5 − 0.2%
2.5
2.5 + 0.2%
V
TA = 25°C
2
2
2
8
15
10
10
ppm/°C
ppm/°C
ppm/°C
mA
µV/mA
dB
TA = 25°C to 125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
AVDD
AVDD + 0.05
AVDD − 0.1
V
V
V
REFIN = REFINx(+) − REFINx(−)
Unbuffered
Buffered
50
85
0.5
AVSS − 0.05
AVSS + 0.1
2.5
±0.5
10
nA
pA/°C
±1
10
nA
pA/°C
±3
10
nA
pA/°C
±12
6
µA
nA/°C
100
dB
Same as for analog inputs
Rev. E | Page 8 of 94
Data Sheet
Parameter1
EXCITATION CURRENT SOURCES (IOUT0/IOUT1)
Output Current
AD7124-8
Min
5
2
0.2
Hysteresis
Input Currents
Input Capacitance
%
ppm/°C
%
AVDD − 0.37
AVSS − 0.05
AVDD − 0.48
V
30
µs/nF
±0.5
13,584
°C
codes/°C
10
30
0.5/2/4
AVDD − 0.6
0.4
1.6
1.55
1
0.7
AVDD + 0.04
AVSS − 0.04
614.4 − 5%
614.4
50:50
614.4 + 5%
2.4576
45:55 to 55:45
0.3 × IOVDD
0.35 × IOVDD
0.7
0.7 × IOVDD
0.65 × IOVDD
1.7
2
0.2
−1
TA = 25°C
Matching between IOUT0 and
IOUT1, VOUT = 0 V
AVDD = 3 V ± 5%
50 µA/100 µA/250 µA/500 µA
current sources, 2% accuracy
750 µA and 1000 µA current
sources, 2% accuracy
Available on any analog input pin
V
AVSS + (AVDD −
AVSS)/2
6.7
7
Test Conditions/Comments
Available on any analog input pin
µA
AVSS − 0.05
VBIAS Generator Start-Up Time
High, VINH
Unit
ppm/°C
%/V
%/V
V
BIAS VOLTAGE (VBIAS) GENERATOR
VBIAS
TEMPERATURE SENSOR
Accuracy
Sensitivity
LOW-SIDE POWER SWITCH
On Resistance (RON)
Allowable Current2
BURNOUT CURRENTS
AIN Current
DIGITAL OUTPUTS (P1 to P4)
Output Voltage
High, VOH
Low, VOL
DIAGNOSTICS
Power Supply Monitor Detect Level
Analog Low Dropout Regulator (ALDO)
Digital LDO (DLDO)
Reference Detect Level
AINM/AINP Overvoltage Detect Level
AINM/AINP Undervoltage Detect Level
INTERNAL/EXTERNAL CLOCK
Internal Clock
Frequency
Duty Cycle
External Clock
Frequency
Duty Cycle Range
LOGIC INPUTS2
Input Voltage
Low, VINL
Max
50/100/250/
500/750/1000
±4
50
±0.5
Initial Tolerance
Drift
Current Matching
Drift Matching2
Line Regulation (AVDD)
Load Regulation
Output Compliance2
Typ
0.6
+1
10
Rev. E | Page 9 of 94
Dependent on the capacitance
connected to AINx
Ω
mA
Continuous current
µA
Analog inputs must be buffered
V
V
ISOURCE = 100 µA
ISINK = 100 µA
V
V
V
V
V
AVDD − AVSS ≥ 2.7 V
IOVDD ≥ 1.75 V
REF_DET_ERR bit active if VREF < 0.7 V
kHz
%
MHz
%
Internal divide by 4
V
V
V
V
V
V
V
V
µA
pF
1.65 V ≤ IOVDD < 1.9 V
1.9 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD ≤ 3.6 V
1.65 V ≤ IOVDD < 1.9 V
1.9 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD < 2.7 V
2.7 V ≤ IOVDD ≤ 3.6 V
1.65 V ≤ IOVDD ≤ 3.6 V
VIN = IOVDD or GND
All digital inputs
AD7124-8
Parameter1
LOGIC OUTPUTS (INCLUDING CLK)
Output Voltage2
High, VOH
Low, VOL
Floating State Leakage Current
Floating State Output Capacitance
Data Output Coding
SYSTEM CALIBRATION2
Calibration Limit
Full-Scale
Zero-Scale
Input Span
POWER SUPPLY VOLTAGES FOR ALL POWER
MODES
AVDD to AVSS
Low Power Mode
Mid Power Mode
Full Power Mode
IOVDD to GND
AVSS to GND
IOVDD to AVSS
POWER SUPPLY CURRENTS11, 13
IAVDD, External Reference
Low Power Mode
Gain = 12
Gain = 1 IAVDD Increase per AINx Buffer2
Gain = 2 to 8
Gain = 16 to 128
IAVDD Increase per Reference Buffer2
Mid Power Mode
Gain = 12
Gain = 1 IAVDD Increase per AINx Buffer2
Gain = 2 to 8
Gain = 16 to 128
IAVDD Increase per Reference Buffer2
Full Power Mode
Gain = 12
Gain = 1 IAVDD Increase per AINx Buffer2
Gain = 2 to 8
Gain = 16 to 128
IAVDD Increase per Reference Buffer2
IAVDD Increase
Due to Internal Reference2
Due to VBIAS2
Due to Diagnostics2
IIOVDD
Low Power Mode
Mid Power Mode
Full Power Mode
Data Sheet
Min
Typ
Max
Unit
Test Conditions/Comments
0.4
+1
V
V
µA
pF
ISOURCE = 100 µA
ISINK = 100 µA
IOVDD − 0.35
−1
10
Offset binary
1.05 × FS
2.1 × FS
V
V
V
3.6
3.6
3.6
3.6
0
5.4
V
V
V
V
V
V
125
15
205
235
10
140
25
250
300
20
µA
µA
µA
µA
µA
150
30
275
330
20
170
40
345
430
30
µA
µA
µA
µA
µA
315
90
660
875
85
350
135
830
1200
120
µA
µA
µA
µA
µA
50
70
µA
15
4
20
5
µA
µA
20
25
55
35
40
80
µA
µA
µA
−1.05 × FS
0.8 × FS
2.7
2.7
2.9
1.65
−1.8
Rev. E | Page 10 of 94
All buffers off
All gains
All buffers off
All gains
All buffers off
All gains
Independent of power mode; the
reference buffers are not required
when using this reference
Independent of power mode
Data Sheet
AD7124-8
Parameter1
POWER-DOWN CURRENTS13
Standby Current
IAVDD
IIOVDD
Power-Down Current
IAVDD
IIOVDD
Min
Typ
Max
Unit
Test Conditions/Comments
Independent of power mode
7
8
15
20
µA
µA
LDOs on only
1
1
3
2
µA
µA
Temperature range = −40°C to +125°C.
These specifications are not production tested but are supported by characterization data at the initial product release.
FS is the decimal equivalent of the FS[10:0] bits in the filter registers.
4
The nonlinearity is production tested in full power mode. For the other power modes, this specification is supported by characterization data at the initial product
release.
5
Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system fullscale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
6
Recalibration at any temperature removes these errors.
7
Gain error applies to both positive and negative full-scale. A factory calibration is performed at gain = 1, TA = 25°C.
8
When gain > 1, the common-mode voltage is between (AVSS + 0.1 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).
9
Specification is for a wider common-mode voltage between (AVSS − 0.05 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).
10
REJ60 is a bit in the filter registers. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz and
60 Hz rejection.
11
When the gain is greater than 1, the analog input buffers are enabled automatically. The buffers can only be disabled when the gain equals 1.
12
When VREF = (AVDD − AVSS), the typical differential input equals 0.92 × VREF/gain for the low and mid power modes and 0.86 × VREF/gain for full power mode when gain > 1.
13
The digital inputs are equal to IOVDD or DGND with excitation currents and bias voltage generator disabled.
1
2
3
TIMING CHARACTERISTICS
AVDD = 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V, Input
Logic 0 = 0 V, Input Logic 1 = IOVDD, unless otherwise noted.
Table 4.
Parameter1, 2
t3
t4
t12
Min
100
100
Typ
Max
3/MCLK3
12/MCLK
24/MCLK
Unit
ns
ns
ns
ns
ns
µs
t13
6
25
50
µs
µs
µs
t14
Test Conditions/Comments
SCLK high pulse width
SCLK low pulse width
Delay between consecutive read/write operations
Full power mode
Mid power mode
Low power mode
DOUT/RDY high time if DOUT/RDY is low and the next
conversion is available
Full power mode
Mid power mode
Low power mode
SYNC low pulse width
Full power mode
Mid power mode
Low power mode
E
E
A
A
A
E
A
3/MCLK
12/MCLK
24/MCLK
READ OPERATION
t1
t24
t56, 7
t6
t78
t
7
7A
0
0
10
0
ns
ns
ns
80
80
80
ns
ns
ns
ns
A
CS falling edge to DOUT/RDY active time
SCLK active edge5 to data valid delay
Bus relinquish time after CS inactive edge
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high
The DOUT_RDY_DEL bit is cleared, the CS_EN bit is
cleared
The DOUT_RDY_DEL bit is set, the CS_EN bit is cleared
Data valid after CS inactive edge, the CS_EN bit is set
E
A
E
A
A
A
E
A
A
E
A
A
E
A
A
10
ns
110
t5
ns
ns
Rev. E | Page 11 of 94
E
A
E
A
A
E
A
E
A
A
A
A
A
E
E
A
A
A
AD7124-8
Parameter1, 2
WRITE OPERATION
t8
t9
t10
t11
Data Sheet
Min
Typ
Max
0
30
25
0
Unit
Test Conditions/Comments
ns
ns
ns
ns
CS falling edge to SCLK active edge5 setup time
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
1
These specifications were sample tested during the initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of IOVDD and
timed from a voltage level of IOVDD/2.
2
See Figure 3, Figure 4, Figure 5, and Figure 6.
3
MCLK is the master clock frequency.
4
These specifications are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
5
The SCLK active edge is the falling edge of SCLK.
6
These specifications are derived from the measured time taken by the data output to change by 0.5 V when loaded with the circuit shown in Figure 2. The measured
number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. The times quoted in the timing characteristics are the true bus
relinquish times of the device and, therefore, are independent of external bus loading capacitances.
7 RDY
returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although subsequent reads must not occur close to the next output update. In continuous read mode, the digital word can be read only once.
8
When the CS_EN bit is cleared, the DOUT/RDY pin changes from its DOUT function to its RDY function, following the last inactive edge of the SCLK. When CS_EN is set,
the DOUT pin continues to output the LSB of the data until the CS inactive edge.
Timing Diagrams
ISINK (100µA)
TO OUTPUT PIN
IOVDD/2
ISOURCE (100µA)
13048-002
25pF
Figure 2. Load Circuit for Timing Characterization
CS (I)
t6
t5
t1
DOUT/RDY (O)
MSB
LSB
t2
t7
t3
t4
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram (CS_EN Bit Cleared)
Rev. E | Page 12 of 94
13048-003
SCLK (I)
Data Sheet
AD7124-8
CS (I)
t6
t1
t5
DOUT/RDY (O)
MSB
LSB
t7A
t2
t3
13048-004
SCLK (I)
t4
I = INPUT, O = OUTPUT
Figure 4. Read Cycle Timing Diagram (CS_EN Bit Set)
E
A
A
CS (I)
t11
t8
SCLK (I)
t9
t10
MSB
LSB
13048-005
DIN (I)
I = INPUT, O = OUTPUT
Figure 5. Write Cycle Timing Diagram
t12
WRITE
DIN
WRITE
t12
t12
READ
READ
13048-006
DOUT/RDY
SCLK
Figure 6. Delay Between Consecutive Serial Operations
CS
DIN
t13
13048-007
DOUT/RDY
SCLK
Figure 7. DOUT/RDY High Time when DOUT/RDY is Initially Low and the Next Conversion is Available
E
A
E
A
A
A
SYNC (I)
13048-008
t14
MCLK (I)
Figure 8. SYNC Pulse Width
E
A
A
Rev. E | Page 13 of 94
AD7124-8
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 5.
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
AVDD to AVSS
IOVDD to DGND
IOVDD to AVSS
AVSS to DGND
Analog Input Voltage to AVSS
Reference Input Voltage to AVSS
Digital Input Voltage to DGND
Digital Output Voltage to DGND
AINx/Digital Input Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature, Soldering
Reflow
ESD Ratings
Human Body Model (HBM)
Field-Induced Charged Device
Model (FICDM)
Machine Model
Rating
−0.3 V to +3.96 V
−0.3 V to +3.96 V
−0.3 V to +5.94 V
−1.98 V to +0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
10 mA
−40°C to +125°C
−65°C to +150°C
150°C
Table 6. Thermal Resistance
Package Type
32-Lead LFCSP
ESD CAUTION
260°C
4 kV
1250 V
400 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. E | Page 14 of 94
θJA
32.5
θJC
32.71
Unit
°C/W
Data Sheet
AD7124-8
32
31
30
29
28
27
26
25
CS
CLK
SCLK
DIN
DOUT/RDY
SYNC
AVDD
PSW
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
AD7124-8
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
REGCAPA
AVSS
REFOUT
AIN15/IOUT/VBIAS/REFIN2(–)
AIN14/IOUT/VBIAS/REFIN2(+)
AIN13/IOUT/VBIAS
AIN12/IOUT/VBIAS
AIN11/IOUT/VBIAS
NOTES
1. CONNECT EXPOSED PAD TO AVSS.
13048-009
AIN5/IOUT/VBIAS/P4
AIN6/IOUT/VBIAS
AIN7/IOUT/VBIAS
REFIN1(+)
REFIN1(–)
AIN8/IOUT/VBIAS
AIN9/IOUT/VBIAS
AIN10/IOUT/VBIAS
9
10
11
12
13
14
15
16
REGCAPD
IOVDD
DGND
AIN0/IOUT/VBIAS
AIN1/IOUT/VBIAS
AIN2/IOUT/VBIAS/P1
AIN3/IOUT/VBIAS/P2
AIN4/IOUT/VBIAS/P3
Figure 9. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
2
Mnemonic
REGCAPD
IOVDD
3
4
DGND
AIN0/IOUT/VBIAS
5
AIN1/IOUT/VBIAS
6
AIN2/IOUT/VBIAS/P1
7
AIN3/IOUT/VBIAS/P2
8
AIN4/IOUT/VBIAS/P3
Description
Digital LDO Regulator Output. Decouple this pin to DGND with a 0.1 µF capacitor.
Serial Interface Supply Voltage, 1.65 V to 3.6 V. IOVDD is independent of AVDD. Therefore, the serial interface
can operate at 1.65 V with AVDD at 3.6 V, for example.
Digital Ground Reference Point.
Analog Input 0/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via
the configuration registers to be the positive or negative terminal of a differential or pseudo differential
input. Alternatively, the internal programmable excitation current source can be made available at this pin.
Either IOUT1 or IOUT0 can be switched to this output. A bias voltage midway between the analog power
supply rails can be generated at this pin.
Analog Input 1/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via
the configuration registers to be the positive or negative terminal of a differential or pseudo differential
input. Alternatively, the internal programmable excitation current source can be made available at this pin.
Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power
supply rails can be generated at this pin.
Analog Input 2/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 1. This
input pin is configured via the configuration registers to be the positive or negative terminal of a
differential or pseudo differential input. Alternatively, the internal programmable excitation current source
can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage
midway between the analog power supply rails can be generated at this pin. This pin can also be configured
as a general-purpose output bit, referenced between AVSS and AVDD.
Analog Input 3/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 2. This
input pin is configured via the configuration registers to be the positive or negative terminal of a
differential or pseudo differential input. Alternatively, the internal programmable excitation current source
can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage
midway between the analog power supply rails can be generated at this pin. This pin can also be configured
as a general-purpose output bit, referenced between AVSS and AVDD.
Analog Input 4/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 3. This
input pin is configured via the configuration registers to be the positive or negative terminal of a
differential or pseudo differential input. Alternatively, the internal programmable excitation current source
can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage
midway between the analog power supply rails can be generated at this pin. This pin can also be configured
as a general-purpose output bit, referenced between AVSS and AVDD.
Rev. E | Page 15 of 94
AD7124-8
Pin No.
9
Mnemonic
AIN5/IOUT/VBIAS/P4
10
AIN6/IOUT/VBIAS
11
AIN7/IOUT/VBIAS
12
REFIN1(+)
13
14
REFIN1(−)
AIN8/IOUT/VBIAS
15
AIN9/IOUT/VBIAS
16
AIN10/IOUT/VBIAS
17
AIN11/IOUT/VBIAS
18
AIN12/IOUT/VBIAS
19
AIN13/IOUT/VBIAS
20
AIN14/IOUT/VBIAS/
REFIN2(+)
Data Sheet
Description
Analog Input 5/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 4. This
input pin is configured via the configuration registers to be the positive or negative terminal of a
differential or pseudo differential input. Alternatively, the internal programmable excitation current source
can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage
midway between the analog power supply rails can be generated at this pin. This pin can also be configured
as a general-purpose output bit, referenced between AVSS and AVDD.
Analog Input 6/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via
the configuration registers to be the positive or negative terminal of a differential or pseudo differential
input. Alternatively, the internal programmable excitation current source can be made available at this pin.
Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power
supply rails can be generated at this pin.
Analog Input 7/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via
the configuration registers to be the positive or negative terminal of a differential or pseudo differential
input. Alternatively, the internal programmable excitation current source can be made available at this pin.
Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power
supply rails can be generated at this pin.
Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−).
REFIN1(+) can be anywhere between AVDD and AVSS + 0.5 V. The nominal reference voltage (REFIN1(+) −
REFIN1(−)) is 2.5 V, but the device functions with a reference from 0.5 V to AVDD.
Negative Reference Input. This reference input can be anywhere between AVSS and AVDD – 0.5 V.
Analog Input 8/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the
configuration registers to be the positive or negative terminal of a differential or pseudo differential input.
Alternatively, the internal programmable excitation current source can be made available at this pin. Either
IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply
rails can be generated at this pin.
Analog Input 9/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the
configuration registers to be the positive or negative terminal of a differential or pseudo differential input.
Alternatively, the internal programmable excitation current source can be made available at this pin. Either
IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply
rails can be generated at this pin.
Analog Input 10/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the
configuration registers to be the positive or negative terminal of a differential or pseudo differential input.
Alternatively, the internal programmable excitation current source can be made available at this pin. Either
IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply
rails can be generated at this pin.
Analog Input 11/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the
configuration registers to be the positive or negative terminal of a differential or pseudo differential input.
Alternatively, the internal programmable excitation current source can be made available at this pin. Either
IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply
rails can be generated at this pin.
Analog Input 12/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the
configuration registers to be the positive or negative terminal of a differential or pseudo differential input.
Alternatively, the internal programmable excitation current source can be made available at this pin. Either
IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply
rails can be generated at this pin.
Analog Input 13/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the
configuration registers to be the positive or negative terminal of a differential or pseudo differential input.
Alternatively, the internal programmable excitation current source can be made available at this pin. Either
IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply
rails can be generated at this pin.
Analog Input 14/Output of Internal Excitation Current Source/Bias Voltage/Positive Reference Input. This
input pin is configured via the configuration registers to be the positive or negative terminal of a
differential or pseudo differential input. Alternatively, the internal programmable excitation current source
can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage
midway between the analog power supply rails can be generated at this pin. This pin also functions as a
positive reference input for REFIN2(±). REFIN2(+) can be anywhere between AVDD and AVSS + 0.5 V. The
nominal reference voltage (REFIN2(+) to REFIN2(−)) is 2.5 V, but the device functions with a reference from 0.5 V
to AVDD.
Rev. E | Page 16 of 94
Data Sheet
AD7124-8
Pin No.
21
Mnemonic
AIN15/IOUT/VBIAS/
REFIN2(−)
22
23
REFOUT
AVSS
24
25
26
27
REGCAPA
PSW
AVDD
SYNC
E
A
Description
Analog Input 15/Output of Internal Excitation Current Source/Bias Voltage/Negative Reference Input. This
input pin is configured via the configuration registers to be the positive or negative terminal of a
differential or pseudo differential input. Alternatively, the internal programmable excitation current source
can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage
midway between the analog power supply rails can be generated at this pin. This pin also functions as the
negative reference input for REFIN2(±). This reference input can be anywhere between AVSS and AVDD – 0.5 V.
Internal Reference Output. The buffered output of the internal 2.5 V voltage reference is available on this pin.
Analog Supply Voltage. The voltage on AVDD is referenced to AVSS. The differential between AVDD and AVSS
must be between 2.7 V and 3.6 V in mid or low power mode and between 2.9 V and 3.6 V in full power
mode. AVSS can be taken below 0 V to provide a dual power supply to the AD7124-8. For example, AVSS
can be tied to −1.8 V and AVDD can be tied to +1.8 V, providing a ±1.8 V supply to the ADC.
Analog LDO Regulator Output. Decouple this pin to AVSS with a 0.1 µF capacitor.
Low-Side Power Switch to AVSS.
Analog Supply Voltage, Relative to AVSS.
Synchronization Input. This pin is a logic input that allows synchronization of the digital filters and analog
modulators when using a number of AD7124-8 devices. When SYNC is low, the nodes of the digital filter,
the filter control logic, and the calibration control logic are reset, and the analog modulator is held in a
reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low.
Serial Data Output/Data Ready Output. DOUT/RDY functions as a serial data output pin to access the
output shift register of the ADC. The output shift register can contain data from any of the on-chip data or
control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a
conversion. If the data is not read after the conversion, the pin goes high before the next update occurs.
The DOUT/RDY falling edge can also be used as an interrupt to a processor, indicating that valid data is
available. With an external serial clock, the data can be read using the DOUT/RDY pin. When CS is low, the
data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on
the SCLK rising edge.
Serial Data Input to the Input Shift Register on the ADC. Data in the input shift register is transferred to
the control registers within the ADC, with the register selection bits of the communications register
identifying the appropriate register.
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK pin has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous
with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock
with the information being transmitted to or from the ADC in smaller batches of data.
Clock Input/Clock Output. The internal clock can be made available at this pin. Alternatively, the internal
clock can be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be
driven from a common clock, allowing simultaneous conversions to be performed.
Chip Select Input. This is an active low logic input that selects the ADC. Use CS to select the ADC in systems
with more than one device on the serial bus or as a frame synchronization signal in communicating with the
device. CS can be hardwired low if the serial peripheral interface (SPI) diagnostics are unused, allowing the
ADC to operate in 3-wire mode with SCLK, DIN, and DOUT interfacing with the device.
Exposed Pad. Connect the exposed pad to AVSS.
E
A
A
E
28
DOUT/RDY
A
E
E
A
A
A
A
E
A
A
E
A
A
E
A
A
E
A
E
A
29
DIN
30
SCLK
31
CLK
32
CS
E
A
E
A
E
A
EP
A
A
Rev. E | Page 17 of 94
A
E
A
A
A
AD7124-8
Data Sheet
TERMINOLOGY
AINM
AINM refers to the negative analog input.
Offset Error
Offset error is the deviation of the first code transition from the
ideal AINP voltage (AINM + 0.5 LSB) when operating in the
unipolar mode.
Integral Nonlinearity (INL)
INL is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be
confused with bipolar zero), a point 0.5 LSB below the first code
transition (000 … 000 to 000 … 001), and full scale, a point
0.5 LSB above the last code transition (111 … 110 to 111 …
111). The error is expressed in ppm of the full-scale range.
In bipolar mode, offset error is the deviation of the midscale
transition (0111 … 111 to 1000 … 000) from the ideal AINP
voltage (AINM − 0.5 LSB).
Offset Calibration Range
In the system calibration modes, the AD7124-8 calibrates offset
with respect to the analog input. The offset calibration range
specification defines the range of voltages that the AD7124-8
can accept and still calibrate offset accurately.
Gain Error
Gain error is the deviation of the last code transition (111 …
110 to 111 … 111) from the ideal AINP voltage (AINM +
VREF/gain − 3/2 LSBs). Gain error applies to both unipolar
and bipolar analog input ranges.
Full-Scale Calibration Range
The full-scale calibration range is the range of voltages that the
AD7124-8 can accept in the system calibration mode and still
calibrate full scale correctly.
AINP
AINP refers to the positive analog input.
Gain error is a measure of the span error of the ADC. It
includes full-scale errors but not zero-scale errors. For unipolar
input ranges, it is defined as full-scale error minus unipolar
offset error; whereas for bipolar input ranges it is defined as
full-scale error minus bipolar zero error.
Input Span
In system calibration schemes, two voltages applied in sequence
to the AD7124-8 analog input define the analog input range.
The input span specification defines the minimum and
maximum input voltages from zero to full scale that the
AD7124-8 can accept and still calibrate gain accurately.
Rev. E | Page 18 of 94
CODES (HEX)
Figure 10. Noise Histogram Plot (Full Power Mode, Post Filter, Output Data
Rate = 25 SPS, Gain = 1)
CODES (HEX)
10,000 SAMPLES
400
1000
400
0
Figure 11. Noise Histogram Plot (Mid Power Mode, Post Filter, Output Data
Rate = 25 SPS, Gain = 1)
300
Figure 12. Noise Histogram Plot (Low Power Mode, Post Filter, Output Data
Rate = 25 SPS, Gain = 1)
CODES (HEX)
700
10,000 SAMPLES
400
600
200
100
100
50
0
CODES (HEX)
Rev. E | Page 19 of 94
13048-011
0
13048-013
10,000 SAMPLES
13048-015
CODES (HEX)
7FFFE9
7FFFFA
800002
800009
800011
800019
800020
800028
800030
800038
80003F
800047
80004F
800057
80005E
800066
80006E
800075
80007D
800085
80008D
800094
80009C
8000A4
OCCURRENCE
1000
7FFF2A
7FFF64
7FFF75
7FFF86
7FFF97
7FFFA8
7FFFB8
7FFFC9
7FFFDA
7FFFEB
7FFFFC
80000C
80001D
80002E
80003F
800050
800060
800071
800082
800093
8000A4
8000B4
8000C5
600
OCCURRENCE
7FFFDC
7FFFDB
7FFFDA
7FFFD9
7FFFD8
7FFFD7
7FFFD6
7FFFD5
7FFFD4
7FFFD3
7FFFD2
7FFFD1
7FFFD0
7FFFCF
7FFFCE
OCCURRENCE
1500
7FFEED
7FFF03
7FFF1A
7FFF30
7FFF47
7FFF5D
7FFF74
7FFF8A
7FFFA1
7FFFB8
7FFFCE
7FFFE5
7FFFFB
800012
800028
80003F
800055
80006C
800083
800099
8000B0
8000C6
8000DD
8000F3
80010A
800121
400
OCCURRENCE
1200
13048-010
CODES (HEX)
13048-012
7FFFC6
7FFFC7
7FFFC8
7FFFC9
7FFFCA
7FFFCB
7FFFCC
7FFFCD
7FFFCE
7FFFCF
7FFFD0
7FFFD1
7FFFD2
7FFFD3
7FFFD4
7FFFD5
7FFFD6
7FFFD7
7FFFD8
7FFFD9
7FFFDA
7FFFDB
7FFFDC
7FFFDD
7FFFDE
7FFFDF
7FFFE0
7FFFE1
7FFFE2
7FFFE3
OCCURRENCE
2500
13048-014
7FFFC1
7FFFC3
7FFFC5
7FFFC7
7FFFC9
7FFFCB
7FFFCD
7FFFCF
7FFFD1
7FFFD3
7FFFD5
7FFFD7
7FFFD9
7FFFDB
7FFFDD
7FFFDF
7FFFE1
7FFFE3
7FFFE5
7FFFE7
7FFFE9
7FFFEB
7FFFED
7FFFF0
7FFFF2
OCCURRENCE
Data Sheet
AD7124-8
TYPICAL PERFORMANCE CHARACTERISTICS
350
300
10,000 SAMPLES
2000
250
200
150
100
500
50
0
Figure 13. Noise Histogram Plot (Full Power Mode, Post Filter, Output Data
Rate = 25 SPS, Gain = 128)
10,000 SAMPLES
350
800
300
250
200
150
200
100
50
0
Figure 14. Noise Histogram Plot (Mid Power Mode, Post Filter, Output Data
Rate = 25 SPS, Gain = 128)
350
10,000 SAMPLES
500
300
250
200
150
0
Figure 15. Noise Histogram Plot (Low Power Mode, Post Filter, Output Data
Rate = 25 SPS, Gain = 128)
AD7124-8
Data Sheet
60
60
100 UNITS
40
OFFSET ERROR (µV)
20
0
–20
0
–20
–40
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
–60
–40
13048-016
–60
–40
20
35
50
65
80
95
110
125
60
100 UNITS
100 UNITS
40
OFFSET ERROR (µV)
20
0
–20
–40
20
0
–20
–40
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
–60
–40
13048-017
–60
–40
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 17. Input Referred Offset Error vs. Temperature
(Gain = 8, Mid Power Mode)
13048-020
OFFSET ERROR (µV)
5
Figure 19. Input Referred Offset Error vs. Temperature
(Gain = 16, Full Power Mode)
40
Figure 20. Input Referred Offset Error vs. Temperature
(Gain = 16, Mid Power Mode)
60
60
100 UNITS
100 UNITS
40
OFFSET ERROR (µV)
40
20
0
–20
20
0
–20
–40
–40
–60
–40
–25
–10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
125
13048-018
OFFSET ERROR (µV)
–10
TEMPERATURE (°C)
Figure 16. Input Referred Offset Error vs. Temperature
(Gain = 8, Full Power Mode)
60
–25
13048-019
–40
20
Figure 18. Input Referred Offset Error vs. Temperature
(Gain = 8, Low Power Mode)
–60
–40
–25
–10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
Figure 21. Input Referred Offset Error vs. Temperature
(Gain = 16, Low Power Mode)
Rev. E | Page 20 of 94
125
13048-021
OFFSET ERROR (µV)
40
100 UNITS
Data Sheet
AD7124-8
60
0.045
100 UNITS
56 UNITS
0.040
0.035
0.030
20
GAIN ERROR (%)
OFFSET ERROR (µV)
40
0
–20
0.025
0.020
0.015
0.010
0.005
–40
–10
5
20
35
50
80
65
95
110
125
TEMPERATURE (°C)
13048-022
–25
–0.005
–40
20
35
50
65
80
95
3
56 UNITS
110
125
GAIN = 1
GAIN = 8
GAIN = 16
2
INL (PPM OF FSR)
0
–0.0005
–0.0010
1
0
–1
–2
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
–3
–2.5
13048-023
–0.0015
–40
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
ANALOG INPUT VOLTAGE × GAIN (V)
Figure 23. Input Referred Gain Error vs. Temperature (Gain = 1)
13048-026
GAIN ERROR (%)
5
Figure 25. Input Referred Gain Error vs. Temperature (Gain = 16)
0.0005
0.015
–10
TEMPERATURE (°C)
Figure 22. Input Referred Offset Error vs. Temperature
(Gain = 1, Analog Input Buffers Enabled)
0.0010
–25
13048-025
0
–60
–40
Figure 26. INL vs. Differential Input Signal (Analog Input × Gain),
ODR = 50 SPS, External 2.5 V Reference
4
56 UNITS
GAIN = 1
GAIN = 8
GAIN = 16
3
0.010
INL (ppm of FSR)
0.005
0
1
0
–1
–2
–0.005
–0.010
–40
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 24. Input Referred Gain Error vs. Temperature (Gain = 8)
–4
–2.5
–1.5
–0.5
0.5
1.5
2.5
ANALOG INPUT VOLTAGE × GAIN (V)
Figure 27. INL vs. Differential Input Signal (Analog Input × Gain),
ODR = 50 SPS, Internal Reference
Rev. E | Page 21 of 94
13048-227
–3
13048-024
GAIN ERROR (%)
2
AD7124-8
25
Data Sheet
30
109 UNITS
109 UNITS
25
20
OCCURRENCE
COUNTS
20
15
10
15
10
5
5
0
–0.85035
–0.76635
Figure 31. IOUTx Current Initial Matching Histogram (500 µA)
2.5020
490
30 UNITS
29 UNITS
2.5015
485
EXCITATION CURRENT (µA)
2.5010
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
2.4975
480
475
470
465
5
–10
20
35
50
65
80
110
95
125
TEMPERATURE (°C)
460
–40
–25
35
50
65
80
95
110
125
110
125
0
EXCITATION CURRENT MISMATCH (%)
29 UNITS
20
15
10
5
–2.534660
EXCITATION CURRENT ACCURACY (%)
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–40
–25
–10
5
20
35
50
65
80
95
TEMPERATURE (°C)
13048-030
–2.707408
–3.880156
–3.052904
–3.225652
–3.398400
–3.571148
–3.743986
–3.916644
0
–4.089392
20
Figure 32. Excitation Current Drift (500 µA)
109 UNITS
–4.262140
5
TEMPERATURE (°C)
Figure 29. Internal Reference Voltage vs. Temperature
25
–10
Figure 30. IOUTx Current Initial Accuracy Histogram (500 µA)
Figure 33. Excitation Current Drift Matching (500 µA)
Rev. E | Page 22 of 94
13048-033
–25
13048-028
2.4965
–40
13048-032
2.4970
OCCURRENCE
INTERNAL REFERENCE VOLTAGE (V)
–0.79435
–0.82235
–0.85035
–0.87835
–0.90635
–0.93435
–0.96235
EXCITATION CURRENT MATCHING (%)
Figure 28. Internal Reference Voltage Histogram
13048-031
INITIAL ACCURACY (V)
–0.99035
–1.01835
2.500671
13048-027
2.500471
2.500272
2.500073
2.499874
2.499675
2.499476
2.499277
2.499078
2.498879
2.498680
0
AD7124-8
1.0
450
0.9
400
0.8
ANALOG CURRENT (µA)
350
0.7
0.6
0.5
0.4
50µA
100µA
250µA
500µA
750µA
1mA
0.2
0.1
0
0
0.33
250
200
150
100
50
0.66
0.99 1.32
1.65
1.98
2.31
2.64
2.97 3.30
VLOAD (V)
0
–40
–10
–25
5
20
35
50
65
80
95
110
125
Figure 37. Analog Current vs. Temperature (Mid Power Mode)
350
1.000
0.995
300
0.985
0.980
0.975
0.970
0.965
50µA
100µA
250µA
500µA
750µA
0.955
0.33
0.66
0.99 1.32
1.65
1.98
2.31
2.64
2.97 3.30
VLOAD (V)
GAIN = 1, AIN BUFFERS OFF
GAIN = 1, AIN BUFFERS ON
GAIN = 2 TO 8
GAIN = 16 TO 128
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 38. Analog Current vs. Temperature (Low Power Mode)
1200
70
GAIN = 1, AIN BUFFERS OFF
GAIN = 2 TO 8
GAIN = 1, AIN BUFFERS ON
GAIN = 16 TO 128
DIGITAL CURRENT (µA)
60
800
600
400
200
FULL POWER
MID POWER
LOW POWER
50
40
30
20
10
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
13048-036
0
–40
100
0
–40
Figure 35. Output Compliance (AVDD = 3.3 V)
1000
150
50
0.950
0
200
Figure 36. Analog Current vs. Temperature (Full Power Mode)
0
–40
–25
–10
5
20
35
50
65
80
95
TEMPERATURE (°C)
Figure 39. Digital Current vs. Temperature
Rev. E | Page 23 of 94
110
125
13048-039
0.960
250
13048-038
ANALOG CURRENT (µA)
0.990
13048-035
EXCITATION CURRENT (NORMALIZED)
1, AIN BUFFERS OFF
2 TO 8
1, AIN BUFFERS ON
16 TO 128
TEMPERATURE (°C)
Figure 34. Output Compliance (AVDD = 3.3 V)
ANALOG CURRENT (µA)
GAIN =
GAIN =
GAIN =
GAIN =
13048-037
0.3
300
13048-034
EXCITATION CURRENT (NORMALIZED)
Data Sheet
AD7124-8
Data Sheet
6
2
4
0
2
CURRENT (nA)
–4
–6
–14
–40
–25
–10
–8
GAIN = 2
GAIN = 8
GAIN = 32
GAIN = 128
GAIN = 1
GAIN = 4
GAIN = 16
GAIN = 64
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
–10
–40
13048-040
–12
–4
–6
–8
–10
–2
GAIN = 1
GAIN = 4
GAIN = 16
GAIN = 64
–25
–10
GAIN = 2
GAIN = 8
GAIN = 32
GAIN = 128
5
20
35
50
65
TEMPERATURE (°C)
Figure 40. Absolute Analog Input Current vs. Temperature (Full Power Mode)
80
95
110
125
13048-041
CURRENT (nA)
0
–2
Figure 43. Differential Analog Input Current vs. Temperature (Full Power Mode)
1
0
–1
CURRENT (nA)
CURRENT (nA)
–2
–3
–4
–5
–6
–7
–10
5
20
35
GAIN = 1
GAIN = 4
GAIN = 16
GAIN = 64
50
65
TEMPERATURE (°C)
80
95
110
125
GAIN = 2
GAIN = 8
GAIN = 32
GAIN = 128
TEMPERATURE (°C)
Figure 44. Differential Analog Input Current vs. Temperature (Mid Power Mode)
CURRENT (nA)
CURRENT (nA)
Figure 41. Absolute Analog Input Current vs. Temperature (Mid Power Mode)
13048-043
–25
GAIN = 2
GAIN = 8
GAIN = 32
GAIN = 128
GAIN = 2
GAIN = 8
GAIN = 32
GAIN = 128
TEMPERATURE (°C)
GAIN = 1
GAIN = 4
GAIN = 16
GAIN = 64
13048-044
GAIN = 1
GAIN = 4
GAIN = 16
GAIN = 64
Figure 42. Absolute Analog Input Current vs. Temperature (Low Power Mode)
GAIN = 2
GAIN = 8
GAIN = 32
GAIN = 128
TEMPERATURE (°C)
13048-045
–9
–40
GAIN = 1
GAIN = 4
GAIN = 16
GAIN = 64
13048-042
–8
Figure 45. Differential Analog Input Current vs. Temperature (Low Power Mode)
Rev. E | Page 24 of 94
Data Sheet
AD7124-8
0
23
22
–1.5
–2.0
–2.5
–3.0
–4.0
–40
FULL POWER
MID POWER
LOW POWER
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 46. Reference Input Current vs. Temperature (Reference Buffers Enabled)
17
16
15
G
G
G
G
G
G
G
G
G
14
13
12
10
= 1 BUFF OFF
=1
=2
=4
=8
= 16
= 32
= 64
= 128
10
1
100
1k
10k
OUTPUT DATA RATE, SETTLED (SPS)
Figure 49. Peak-to-Peak Resolution vs. Output Data Rate (Settled), Sinc3 Filter
(Full Power Mode)
1.2
23
32 UNITS
22
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
19
18
17
16
15
G
G
G
G
G
G
G
G
G
14
13
12
11
15 25 40 50 60 70 85 95 105 115 125
TEMPERATURE (°C)
Figure 47. Temperature Sensor Accuracy
1
22
21
21
PEAK-TO-PEAK RESOLUTION (Bits)
23
20
19
18
17
16
13
12
11
= 1 BUFF OFF
=1
=2
=4
=8
= 16
= 32
= 64
= 128
1
10
100
1k
OUTPUT DATA RATE, SETTLED (SPS)
1k
10k
20
19
18
17
16
15
G
G
G
G
G
G
G
G
G
14
13
12
11
10
10k
Figure 48. Peak-to-Peak Resolution vs. Output Data Rate (Settled), Sinc4 Filter
(Full Power Mode)
= 1 BUFF OFF
=1
=2
=4
=8
= 16
= 32
= 64
= 128
10
13048-048
14
100
Figure 50. Peak-to-Peak Resolution vs. Output Data Rate, Sinc4 + Sinc1 Filter
(Full Power Mode)
22
G
G
G
G
G
G
G
G
G
10
OUTPUT DATA RATE (SPS)
23
15
= 1 BUFF OFF
=1
=2
=4
=8
= 16
= 32
= 64
= 128
10
13048-047
–0.6
–40 –30 –20 –10 0
PEAK-TO-PEAK RESOLUTION (Bits)
21
20
13048-050
PEAK-TO-PEAK RESOLUTION (Bits)
TEMPERATURE SENSOR ERROR (%)
18
11
13048-046
–3.5
20
19
1
10
100
OUTPUT DATA RATE (SPS)
1k
10k
13048-051
CURRENT (nA)
–1.0
21
13048-049
PEAK-TO-PEAK RESOLUTION (Bits)
–0.5
Figure 51. Peak-to-Peak Resolution vs. Output Data Rate, Sinc3 + Sinc1 Filter
(Full Power Mode)
Rev. E | Page 25 of 94
Data Sheet
23
22
22
21
21
18
17
16
15
G
G
G
G
G
G
G
G
G
14
13
12
11
10
= 1 BUFF OFF
=1
=2
=4
=8
= 16
= 32
= 64
= 128
1
10
100
1k
10k
100k
18
17
16
15
13
12
22
PEAK-TO-PEAK RESOLUTION (Bits)
21
20
19
18
17
16
12
11
= 1 BUFF OFF
=1
=2
=4
=8
= 16
= 32
= 64
= 128
1
10
100
1k
10k
100k
OUTPUT DATA RATE, SETTLED (SPS)
Figure 53. Peak-to-Peak Resolution vs. Output Data Rate (Settled), Sinc3 Filter
(Mid Power Mode)
21
19
18
17
16
15
13
12
10
1
23
PEAK-TO-PEAK RESOLUTION (Bits)
20
19
18
17
16
13
12
11
1
10
100
OUTPUT DATA RATE (SPS)
1k
100
1k
10k
21
20
19
18
17
16
15
G
G
G
G
G
G
G
G
G
14
13
12
11
10
10
= 1 AIN BUFF OFF
=1
=2
=4
=8
= 16
= 32
= 64
= 128
9
13048-054
14
= 1 BUFF OFF
=1
=2
=4
=8
= 16
= 32
= 64
= 128
10
Figure 56. Peak-to-Peak Resolution vs. Output Data Rate (Settled), Sinc4 Filter
(Low Power Mode)
22
21
= 1 AIN BUFF OFF
=1
=2
=4
=8
= 16
= 32
= 64
= 128
OUTPUT DATA RATE, SETTLED (SPS)
22
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
14
23
15
1k
20
11
10
13048-053
13
100
Figure 55. Peak-to-Peak Resolution vs. Output Data Rate, Sinc3 + Sinc1 Filter
(Mid Power Mode)
23
G
G
G
G
G
G
G
G
G
10
OUTPUT DATA RATE (SPS)
22
14
= 1 BUFF OFF
=1
=2
=4
=8
= 16
= 32
= 64
= 128
1
23
15
G
G
G
G
G
G
G
G
G
14
10
Figure 52. Peak-to-Peak Resolution vs. Output Data Rate (Settled), Sinc4 Filter
(Mid Power Mode)
PEAK-TO-PEAK RESOLUTION (Bits)
19
11
OUTPUT DATA RATE, SETTLED (SPS)
PEAK-TO-PEAK RESOLUTION (Bits)
20
1
10
100
1k
OUTPUT DATA RATE, SETTLED (SPS)
Figure 54. Peak-to-Peak Resolution vs. Output Data Rate, Sinc4 + Sinc1 Filter
(Mid Power Mode)
13048-056
19
10k
13048-057
20
13048-055
PEAK-TO-PEAK RESOLUTION (Bits)
23
13048-052
PEAK-TO-PEAK RESOLUTION (Bits)
AD7124-8
Figure 57. Peak-to-Peak Resolution vs. Output Data Rate (Settled), Sinc3 Filter
(Low Power Mode)
Rev. E | Page 26 of 94
Data Sheet
AD7124-8
35
23
GAIN = 1, LOW POWER
GAIN = 1, MID POWER
GAIN = 1, FULL POWER
GAIN = 8, LOW POWER
GAIN = 8, MID POWER
GAIN = 8, FULL POWER
GAIN = 16, LOW POWER
GAIN = 16, MID POWER
GAIN = 16, FULL POWER
30
21
DIGITAL CURRENT (µA)
20
19
18
17
16
G
G
G
G
G
G
G
G
G
14
13
12
11
10
= 1 BUFF OFF
=1
=2
=4
=8
= 16
= 32
= 64
= 128
1
25
20
15
10
5
10
100
1k
OUTPUT DATA RATE (SPS)
0
Figure 58. Peak-to-Peak Resolution vs. Output Data Rate, Sinc4 + Sinc1 Filter
(Low Power Mode)
0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Figure 61. Digital Current vs. Wait Time in Standby Mode, ADC in Single
Conversion Mode (50 SPS)
1000
22
21
800
20
RMS NOISE (nV)
19
18
17
16
G
G
G
G
G
G
G
G
G
14
13
12
11
10
= 1 BUFF OFF
=1
=2
=4
=8
= 16
= 32
= 64
= 128
200
10
1
400
100
1k
OUTPUT DATA RATE (SPS)
0
–0.08
Figure 59. Peak-to-Peak Resolution vs. Output Data Rate, Sinc3 + Sinc1 Filter
(Low Power Mode)
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
ANALOG INPUT VOLTAGE (V)
13048-202
15
LOW POWER, EXTERNAL REF
MID POWER, EXTERNAL REF
FULL POWER, EXTERNAL REF
LOW POWER INTERNAL REF
MID POWER, INTERNAL REF
FULL POWER, INTERNAL REF
600
13048-059
Figure 62. RMS Noise vs. Analog Input Voltage for the Internal Reference and
External Reference (Gain = 32, 50 SPS)
400
4
29 UNITS
GAIN = 1, LOW POWER
GAIN = 1, MID POWER
GAIN = 1, FULL POWER
GAIN = 8, LOW POWER
GAIN = 8, MID POWER
GAIN = 8, FULL POWER
GAIN = 16, LOW POWER
GAIN = 16, MID POWER
GAIN = 16, FULL POWER
300
250
3
OSCILLATOR ERROR (%)
350
200
150
100
2
1
0
–1
–2
50
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
WAIT TIME IN STANDBY MODE (Seconds)
0.9
1.0
–3
–40
13048-200
0
–25
–10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
Figure 60. Analog Current vs. Wait Time in Standby Mode, ADC in Single
Conversion Mode (50 SPS)
Rev. E | Page 27 of 94
Figure 63. Internal Oscillator Error vs. Temperature
125
13048-029
PEAK-TO-PEAK RESOLUTION (Bits)
0.2
WAIT TIME IN STANDBY MODE (Seconds)
23
ANALOG CURRENT (µA)
0.1
13048-201
15
13048-058
PEAK-TO-PEAK RESOLUTION (Bits)
22
AD7124-8
Data Sheet
RMS NOISE AND RESOLUTION
in parentheses) is calculated based on peak-to-peak noise
(shown in parentheses). The peak-to-peak resolution represents
the resolution for which there is no code flicker.
Table 8 through Table 37 show the rms noise, peak-to-peak
noise, effective resolution, and noise-free (peak-to-peak)
resolution of the AD7124-8 for various output data rates, gain
settings, and filters. The numbers given are for the bipolar input
range with an external 2.5 V reference. These numbers are
typical and are generated with a differential input voltage of 0 V
when the ADC is continuously converting on a single channel.
It is important to note that the effective resolution is calculated
using the rms noise, whereas the peak-to-peak resolution (shown
Effective Resolution = Log2(Input Range/RMS Noise)
Peak-to-Peak Resolution = Log2(Input Range/Peak-to-Peak
Noise
FULL POWER MODE
Sinc4
Table 8. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Full Power Mode
Filter
Word
(Dec.)
2047
1920
960
480
384
320
240
120
60
30
15
8
4
2
1
Output
Data
Rate
(SPS)
9.4
10
20
40
50
60
80
160
320
640
1280
2400
4800
9600
19,200
Output Data
Rate (Zero
Latency
Mode) (SPS)
2.34
2.5
5
10
12.5
15
20
40
80
160
320
600
1200
2400
4800
f3dB
(Hz)
2.16
2.3
4.6
9.2
11.5
13.8
18.4
36.8
73.6
147.2
294.4
552
1104
2208
4416
Gain = 1
0.24 (1.5)
0.23 (1.5)
0.31 (2.1)
0.42 (3)
0.48 (3.2)
0.51 (3.3)
0.6 (4.8)
0.86 (6.9)
1.2 (8.9)
1.7 (13)
2.4 (19)
3.3 (25)
4.9 (38)
8.8 (76)
72 (500)
Gain = 2
0.15 (0.89)
0.14 (0.89)
0.22 (1.3)
0.3 (2.1)
0.33 (2.1)
0.35 (2.4)
0.41 (3)
0.55 (4.1)
0.76 (6.1)
1.1 (8.8)
1.6 (13)
2.3 (16)
3.4 (25)
6.8 (61)
38 (270)
Gain = 4
0.091 (0.6)
0.094 (0.6)
0.13 (0.89)
0.19 (1.4)
0.2 (1.3)
0.23 (1.3)
0.28 (1.8)
0.37 (2.5)
0.53 (4.1)
0.74 (5.7)
1.1 (8.4)
1.5 (12)
2.4 (20)
4.9 (34)
21 (150)
Gain = 8
0.071 (0.41)
0.076 (0.42)
0.1 (0.6)
0.14 (0.97)
0.16 (1.1)
0.17 (1.2)
0.19 (1.3)
0.29 (2)
0.4 (2.7)
0.57 (4.1)
0.82 (6)
1.2 (8)
2 (13)
4.3 (27)
13 (95)
Gain = 16
0.045 (0.26)
0.048 (0.27)
0.069 (0.41)
0.09 (0.63)
0.1 (0.75)
0.11 (0.78)
0.13 (0.86)
0.2 (1.2)
0.26 (1.8)
0.38 (2.9)
0.55 (4)
0.76 (6)
1.3 (9.1)
2.6 (21)
7.5 (57)
Gain = 32
0.031 (0.17)
0.03 (0.19)
0.044 (0.26)
0.063 (0.39)
0.068 (0.43)
0.077 (0.5)
0.09 (0.54)
0.13 (0.84)
0.18 (1.2)
0.26 (2)
0.38 (2.5)
0.53 (4)
0.83 (6.4)
1.7 (13)
4.4 (33)
Gain = 64
0.025 (0.15)
0.025 (0.16)
0.035 (0.22)
0.053 (0.34)
0.059 (0.42)
0.064 (0.41)
0.072 (0.48)
0.11 (0.7)
0.15 (0.95)
0.22 (1.6)
0.3 (2.3)
0.43 (3.2)
0.68 (4.8)
1.3 (12)
3.3 (26)
Gain = 128
0.023 (0.14)
0.025 (0.15)
0.034 (0.22)
0.043 (0.27)
0.048 (0.28)
0.056 (0.35)
0.063 (0.45)
0.098 (0.6)
0.14 (0.86)
0.19 (1.4)
0.26 (1.8)
0.37 (2.7)
0.58 (4.3)
1.2 (9.4)
2.8 (23)
Table 9. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Full Power Mode
Filter
Word
(Dec.)
2047
1920
960
480
384
320
240
120
60
30
15
8
4
2
1
Output
Data Rate
(SPS)
9.4
10
20
40
50
60
80
160
320
640
1280
2400
4800
9600
19,200
Output Data Rate
(Zero Latency
Mode) (SPS)
2.34
2.5
5
10
12.5
15
20
40
80
160
320
600
1200
2400
4800
Gain = 1
24 (21.7)
24 (21.7)
23.9 (21.2)
23.5 (20.7)
23.3 (20.5)
23.2 (20.3)
23 (20)
22.5 (19.5)
22 (19.1)
21.5 (18.5)
21 (18)
20.5 (17.5)
20 (17)
19.1 (16)
16.1 (13.3)
Gain = 2
24 (21.4)
24 (21.4)
23.5 (20.8)
23 (20.3)
22.9 (20.2)
22.8 (20)
22.6 (19.7)
22.1 (19.2)
21.6 (18.6)
21.1 (18.1)
20.5 (17.6)
20.1 (17.2)
19.5 (16.5)
18.5 (15.3)
16 (13.2)
Gain = 4
23.7 (21)
23.7 (21)
23.2 (20.4)
22.6 (19.8)
22.5 (19.6)
22.4 (19.5)
22.1 (19.3)
21.7 (18.9)
21.2 (18.2)
20.7 (17.7)
20.2 (17.2)
19.7 (16.7)
19 (16)
18 (15.1)
15.9 (13)
Rev. E | Page 28 of 94
Gain = 8
23.1 (20.5)
23 (20.5)
22.5 (20)
22.1 (19.3)
21.9 (19.1)
21.8 (19)
21.6 (18.9)
21 (18.3)
20.6 (17.8)
20.1 (17.2)
19.5 (16.7)
19 (16.2)
18.3 (15.6)
17.2 (14.5)
15.5 (12.7)
Gain = 16
22.7 (20.2)
22.6 (20.1)
22.1 (19.5)
21.7 (18.9)
21.5 (18.7)
21.4 (18.6)
21.2 (18.5)
20.6 (18)
20.2 (17.4)
19.7 (16.8)
19.1 (16.3)
18.6 (15.7)
17.9 (15.1)
16.9 (13.9)
15.4 (12.4)
Gain = 32
22.3 (19.8)
22.3 (19.7)
21.8 (19.2)
21.2 (18.6)
21.1 (18.5)
21 (18.3)
20.7 (18.1)
20.1 (17.5)
19.7 (17)
19.2 (16.3)
18.7 (15.9)
18.2 (15.3)
17.5 (14.6)
16.5 (13.5)
15.1 (12.2)
Gain = 64
21.6 (19)
21.6 (19)
21.1 (18.4)
20.5 (17.8)
20.4 (17.7)
20.2 (17.6)
20 (17.3)
19.5 (16.9)
19 (16.3)
18.5 (15.6)
18 (15.1)
17.5 (14.6)
16.8 (14)
15.9 (12.7)
14.6 (11.5)
Gain = 128
20.7 (18.1)
20.7 (18.1)
20.1 (17.4)
19.8 (17.1)
19.6 (17)
19.4 (16.6)
19.2 (16.4)
18.6 (16)
18.1 (15.5)
17.6 (14.8)
17.2 (14.4)
16.7 (13.8)
16 (13.2)
15 (12)
13.8 (10.8)
Data Sheet
AD7124-8
Sinc3
Table 10. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Full Power Mode
Filter
Word
(Dec.)
2047
1920
1280
640
384
320
160
80
40
20
10
6
3
2
1
Output
Data
Rate
(SPS)
9.4
10
20
30
50
60
120
240
480
960
1920
3200
6400
9600
19,200
Output
Data Rate
(Zero
Latency
Mode)
(SPS)
3.13
3.33
5
10
16.67
20
40
80
160
320
640
1066.67
2133.33
3200
6400
f3dB
(Hz)
2.56
2.72
5.44
8.16
13.6
16.32
32.64
65.28
130.56
261.12
522.24
870.4
1740.8
2611.2
5222.4
Gain = 1
0.23 (1.5)
0.24 (1.5)
0.31 (1.8)
0.4 (2.6)
0.53 (3.3)
0.55 (3.6)
0.78 (5.1)
1.1 (7)
1.5 (11)
2.3 (16)
3.2 (26)
4.9 (38)
25 (170)
110 (820)
890 (6500)
Gain = 2
0.15 (0.89)
0.15 (0.89)
0.18 (1.2)
0.26 (1.6)
0.3 (2.2)
0.37 (2.4)
0.53 (3.4)
0.73 (4.9)
1.1 (6.8)
1.5 (9.8)
2.2 (16)
3.2 (24)
13 (89)
54 (390)
430 (3000)
Gain = 4
0.096 (0.58)
0.096 (0.6)
0.12 (0.82)
0.17 (1.2)
0.2 (1.6)
0.24 (1.8)
0.35 (2.3)
0.49 (3.2)
0.67 (4.5)
0.99 (6.6)
1.5 (11)
2.1 (15)
7.1 (54)
28 (210)
220 (1500)
Gain = 8
0.07 (0.38)
0.07 (0.4)
0.09 (0.55)
0.11 (0.82)
0.17 (1.1)
0.19 (1.3)
0.26 (1.8)
0.37 (2.6)
0.52 (3.7)
0.75 (5.1)
1.1 (8.5)
1.6 (12)
4.3 (35)
14 (110)
110 (790)
Gain = 16
0.046 (0.25)
0.05 (0.26)
0.059 (0.35)
0.088 (0.52)
0.1 (0.75)
0.12 (0.8)
0.17 (1.1)
0.25 (1.6)
0.34 (2.2)
0.53 (3.5)
0.73 (5.5)
1 (7.7)
2.4 (18)
7.4 (57)
55 (390)
Gain = 32
0.033 (0.16)
0.034 (0.17)
0.041 (0.24)
0.055 (0.36)
0.075 (0.51)
0.084 (0.54)
0.12 (0.85)
0.17 (1.2)
0.25 (1.7)
0.35 (2.4)
0.49 (3.9)
0.68 (5.6)
1.5 (11)
3.9 (27)
28 (190)
Gain = 64
0.023 (0.11)
0.023 (0.12)
0.033 (0.18)
0.048 (0.27)
0.062 (0.39)
0.068 (0.44)
0.1 (0.66)
0.14 (1)
0.19 (1.4)
0.28 (2.1)
0.4 (3.2)
0.56 (4.2)
1.1 (8.4)
2.3 (17)
14 (100)
Gain = 128
0.017 (0.09)
0.018 (0.09)
0.027 (0.14)
0.039 (0.22)
0.056 (0.33)
0.06 (0.37)
0.097 (0.55)
0.12 (0.78)
0.17 (1.2)
0.25 (1.8)
0.35 (2.7)
0.48 (3.6)
0.9 (6.7)
1.7 (13)
7.6 (56)
Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Full Power Mode
Filter
Word
(Dec.)
2047
1920
1280
640
384
320
160
80
40
20
10
6
3
2
1
Output
Data
Rate
(SPS)
9.4
10
20
30
50
60
120
240
480
960
1920
3200
6400
9600
19,200
Output Data
Rate (Zero
Latency Mode)
(SPS)
3.13
3.33
5
10
16.67
20
40
80
160
320
640
1066.67
2133.33
3200
6400
Gain = 1
24 (21.7)
24 (21.7)
24 (21.4)
23.6 (20.9)
23.2 (20.5)
23.1 (20.4)
22.6 (19.9)
22.1 (19.4)
21.6 (18.8)
21.1 (18.3)
20.6 (17.6)
19.9 (17)
17.6 (14.8)
15.5 (12.6)
12.5 (9.7)
Gain = 2
24 (21.4)
24 (21.4)
23.7 (21)
23.2 (20.5)
22.8 (20.1)
22.7 (20)
22.2 (19.5)
21.7 (19)
21.2 (18.5)
20.7 (18)
20.1 (17.2)
19.6 (16.6)
17.6 (14.8)
15.5 (12.6)
12.5 (9.7)
Gain = 4
23.6 (21)
23.6 (21)
23.2 (20.5)
22.8 (20)
22.4 (19.6)
22.3 (19.4)
21.8 (19)
21.3 (18.6)
20.8 (18.1)
20.3 (17.5)
19.7 (16.8)
19.2 (16.3)
17.4 (14.5)
15.4 (12.6)
12.5 (9.7)
Gain = 8
23.1 (20.6)
23.1 (20.6)
22.7 (20.1)
22.2 (19.5)
21.8 (19.1)
21.7 (18.9)
21.2 (18.4)
20.7 (17.9)
20.2 (17.4)
19.7 (16.9)
19.1 (16.2)
18.6 (15.6)
17.2 (14.1)
15.4 (12.5)
12.5 (9.6)
Gain = 16
22.7 (20.3)
22.6 (20.2)
22.3 (19.8)
21.8 (19.2)
21.4 (18.7)
21.3 (18.6)
20.8 (18.1)
20.3 (17.6)
19.8 (17.1)
19.2 (16.4)
18.7 (15.8)
18.2 (15.3)
17 (14.1)
15.4 (12.4)
12.5 (9.6)
Gain = 32
22.2 (19.9)
22.2 (19.8)
21.9 (19.3)
21.4 (18.7)
21 (18.2)
20.8 (18.1)
20.3 (17.5)
19.8 (17)
19.3 (16.5)
18.8 (16)
18.3 (15.3)
17.8 (14.8)
16.7 (13.8)
15.3 (12.5)
12.4 (9.6
Gain = 64
21.7 (19.3)
21.7 (19.3)
21.2 (18.7)
20.6 (18.1)
20.3 (17.6)
20.1 (17.4)
19.6 (16.9)
19.1 (16.3)
18.6 (15.8)
18.1 (15.2)
17.6 (14.6)
17.1 (14.2)
16.3 (13.2)
15 (12.2)
12.4 (9.6)
Gain = 128
21 (18.7)
21 (18.7)
20.5 (18.1)
19.9 (17.4)
19.4 (16.9)
19.3 (16.7)
18.7 (16.1)
18.3 (15.6)
17.8 (15)
17.3 (14.4)
16.8 (13.8)
16.3 (13.4)
15.4 (12.5)
14.5 (11.6)
12.3 (9.5)
Post Filters
Table 12. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Full Power Mode
Output Data Rate (SPS)
16.67
20
25
27.27
Gain = 1
0.51 (3.3)
0.53 (3.3)
0.57 (3.6)
0.6 (3.9)
Gain = 2
0.34 (2.1)
0.36 (2.1)
0.37 (2.2)
0.38 (2.2)
Gain = 4
0.21 (1.3)
0.23 (1.3)
0.25 (1.6)
0.26 (1.6)
Gain = 8
0.16 (0.97)
0.18 (1)
0.18 (1.2)
0.19 (1.2)
Rev. E | Page 29 of 94
Gain = 16
0.11 (0.65)
0.11 (0.65)
0.12 (0.75)
0.13 (0.82)
Gain = 32
0.075 (0.41)
0.078 (0.45)
0.082 (0.47)
0.084 (0.55)
Gain = 64
0.062 (0.34)
0.062 (0.34)
0.062 (0.38)
0.072 (0.44)
Gain = 128
0.051(0.3)
0.051 (0.3)
0.055 (0.31)
0.063 (0.43)
AD7124-8
Data Sheet
Table 13. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Full Power Mode
Output Data Rate (SPS)
16.67
20
25
27.27
Gain = 1
23.2 (20.5)
23.2 (20.5)
23.1 (20.4)
23 (20.3)
Gain = 2
22.8 (20.2)
22.7 (20.2)
22.7 (20.1)
22.6 (20.1)
Gain = 4
22.5 (19.9)
22.3 (19.9)
22.2 (19.6)
22.2 (19.5)
Gain = 8
21.9 (19.3)
21.7 (19.2)
21.7 (19)
21.7 (19)
Gain = 16
21.5 (18.9)
21.5 (18.9)
21.3 (18.7)
21.2 (18.5)
Gain = 32
21 (18.5)
20.9 (18.4)
20.9 (18.3)
20.8 (18.1)
Gain = 64
20.3 (17.8)
20.3 (17.8)
20.3 (17.7)
20.1 (17.4)
Gain = 128
19.5 (17)
19.5 (17)
19.5 (17)
19.2 (16.5)
Fast Settling Filter (Sinc4 + Sinc1)
Table 14. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Full Power Mode (Average by 16)
Filter
Word
(Dec.)
384
120
24
20
2
1
Output
Data Rate
(SPS)
2.63
8.42
42.11
50.53
505.26
1010.53
Gain = 1
0.19 (1.2)
0.32 (2.1)
0.69 (4.6)
0.71 (5.1)
2.4 (18)
4.8 (35)
Gain = 2
0.11 (0.75)
0.2 (1.3)
0.44 (3)
0.49 (3.1)
1.6 (10)
3 (20)
Gain = 4
0.077 (0.52)
0.13 (0.97)
0.29 (2.1)
0.3 (2.2)
1.1 (8.3)
1.9 (12)
Gain = 8
0.063 (0.34)
0.1 (0.63)
0.23 (1.6)
0.25 (1.7)
0.87 (5.5)
1.4 (8.8)
Gain = 16
0.036 (0.21)
0.067 (0.46)
0.14 (0.99)
0.16 (1.1)
0.56 (3.5)
0.89 (5.2)
Gain = 32
0.027 (0.17)
0.045 (0.28)
0.1 (0.72)
0.11 (0.78)
0.47 (2.9)
0.57 (3.7)
Gain = 64
0.021 (0.11)
0.039 (0.23)
0.081 (0.54)
0.09 (0.6)
0.33 (2.1)
0.49 (3)
Gain = 128
0.019 (0.098)
0.031 (0.2)
0.07 (0.49)
0.082 (0.57)
0.3 (2)
0.44 (3)
Table 15. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Full Power Mode (Average by 16)
Filter Word
(Dec.)
384
120
24
20
2
1
Output Data Rate
(SPS)
2.63
8.42
42.11
50.53
505.26
1010.53
Gain = 1
24 (22)
23.9 (21.2)
22.8 (20)
22.7 (19.9)
21 (18.1)
20 (17.1)
Gain = 2
24 (21.7)
23.6 (20.8)
22.4 (19.7)
22.3 (19.6)
20.6 (17.9)
19.7 (16.9)
Gain = 4
23.9 (21.2)
23.3 (20.3)
22.1 (19.2)
22 (19.1)
20.2 (17.2)
19.3 (16.6)
Gain = 8
23.3 (20.8)
22.5 (19.9)
21.4 (18.6)
21.2 (18.5)
19.5 (16.8)
18.8 (16.1)
Gain = 16
23 (20.5)
22.2 (19.4)
21.1 (18.3)
20.9 (18.1)
19.1 (16.4)
18.4 (15.9)
Gain = 32
22.5 (19.8)
21.9 (19.1)
20.5 (17.7)
20.4 (17.6)
18.4 (15.7)
18.1 (15.4)
Gain = 64
21.8 (19.5)
20.9 (18.4)
19.9 (17.1)
19.7 (17)
17.8 (15.2)
17.3 (14.7)
Gain = 128
21 (18.6)
20.2 (17.6)
19.1 (16.3)
18.9 (16.1)
17 (14.3)
16.5 (13.7)
Fast Settling Filter (Sinc3 + Sinc1)
Table 16. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Full Power Mode (Average by 16)
Filter Word
(Dec.)
384
120
24
20
2
1
Output Data Rate
(SPS)
2.78
8.89
44.44
53.33
533.33
1066.67
Gain = 1
0.22 (1.4)
0.31 (2.1)
0.7 (4.8)
0.77 (5.2)
6.1 (46)
44 (320)
Gain = 2
0.13 (0.75)
0.21 (1.3)
0.46 (3.1)
0.5 (3.4)
3.2 (23)
22 (160)
Gain = 4
0.081 (0.44)
0.13 (0.89)
0.29 (2.1)
0.31 (2.3)
1.8 (12)
11 (80)
Gain = 8
0.048 (0.3)
0.1 (0.63)
0.22 (1.5)
0.24 (1.6)
1.1 (7.5)
5.7 (40)
Gain = 16
0.039 (0.24)
0.068 (0.47)
0.14 (0.95)
0.17 (1)
0.65 (4.3)
2.9 (22)
Gain = 32
0.026 (0.18)
0.047 (0.28)
0.098 (0.67)
0.11 (0.73)
0.4 (2.7)
1.5 (11)
Gain = 64
0.025 (0.13)
0.036 (0.25)
0.079 (0.56)
0.09 (0.66)
0.31 (2.2)
0.83 (6.2)
Gain = 128
0.019 (0.11)
0.033 (0.17)
0.071 (0.44)
0.077 (0.48)
0.27 (2)
0.54 (4)
Table 17. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Full Power Mode (Average by 16)
Filter Word
(Dec.)
384
120
24
20
2
1
Output Data Rate
(SPS)
2.78
8.89
44.44
53.33
533.33
1066.67
Gain = 1
24 (21.8)
24 (21.2)
22.8 (20)
22.6 (19.9)
19.7 (16.8)
16.8 (13.9)
Gain = 2
24 (21.7)
23.5 (20.9)
22.4 (19.6)
22.3 (19.5)
19.6 (16.8)
16.8 (13.9)
Gain = 4
23.9 (21.4)
23.2 (20.4)
22.1 (19.2)
22 (19.1)
19.4 (16.6)
16.8 (13.9)
Gain = 8
23.6 (21)
22.6 (19.9)
21.4 (18.7)
21.3 (18.6)
19.1 (16.3)
16.7 (13.9)
Rev. E | Page 30 of 94
Gain = 16
22.9 (20.3)
22.1 (19.4)
21.1 (18.3)
20.8 (18.2)
18.9 (16.1)
16.7 (13.8)
Gain = 32
22.5 (19.8)
21.7 (19.1)
20.6 (17.8)
20.4 (17.7)
18.6 (15.8)
16.6 (13.8)
Gain = 64
21.6 (19.2)
21 (18.3)
19.9 (17.1)
19.7 (16.9)
17.9 (15.1)
16.5 (13.6)
Gain = 128
21 (18.4)
20.2 (17.8)
19.1 (16.5)
19 (16.3)
17.2 (14.3)
16.1 (13.3)
Data Sheet
AD7124-8
MID POWER MODE
Sinc4
Table 18. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Mid Power Mode
Filter
Word
(Dec.)
2047
1920
960
480
240
120
96
80
60
30
15
8
4
2
1
Output
Data
Rate
(SPS)
2.34
2.5
5
10
20
40
50
60
80
160
320
600
1200
2400
4800
Output Data
Rate (Zero
Latency
Mode) (SPS)
0.586
0.625
1.25
2.5
5
10
12.5
15
20
40
80
150
300
600
1200
f3dB
(Hz)
0.52
0.575
1.15
2.3
4.6
9.2
11.5
13.8
18.4
36.8
73.6
138
276
552
1104
Gain = 1
0.22 (1.4)
0.25 (1.4)
0.34 (2)
0.44 (2.8)
0.67 (3.8)
0.98 (6)
1 (7.4)
1.1 (7.2)
1.3 (8.4)
1.8 (11)
2.6 (17)
3.7 (23)
5.3 (36)
9.3 (72)
71 (500)
Gain = 2
0.14 (0.88)
0.17 (0.88)
0.21 (1.2)
0.28 (1.8)
0.4 (2.4)
0.58 (3.6)
0.67 (4.2)
0.7 (4.3)
0.8 (5.1)
1.2 (7.6)
1.7 (11)
2.3 (15)
3.6 (24)
6.8 (53)
37 (270)
Gain = 4
0.095 (0.6)
0.11 (0.6)
0.13 (0.77)
0.19 (1.1)
0.27 (1.6)
0.37 (2.3)
0.41 (2.5)
0.44 (3)
0.53 (3.4)
0.73 (4.6)
1 (6.6)
1.5 (9.6)
2.4 (16)
4.8 (35)
21 (160)
Gain = 8
0.062 (0.38)
0.073 (0.38)
0.085 (0.52)
0.1 (0.82)
0.2 (1.1)
0.27 (1.7)
0.28 (1.9)
0.33 (2.1)
0.37 (2.4)
0.54 (3.4)
0.79 (4.7)
1.2 (7.2)
1.9 (13)
4.1 (34)
13 (98)
Gain = 16
0.048 (0.24)
0.048 (0.24)
0.064 (0.36)
0.1 (0.55)
0.14 (0.85)
0.2 (1.1)
0.23 (1.3)
0.24 (1.4)
0.27 (1.6)
0.39 (2.4)
0.58 (3.4)
0.84 (5)
1.3 (8.2)
2.5 (19)
7.2 (55)
Gain = 32
0.036 (0.17)
0.037 (0.19)
0.052(0.25)
0.072 (0.41)
0.098 (0.64)
0.14 (0.87)
0.15 (0.95)
0.17 (1.1)
0.2 (1.3)
0.28 (1.9)
0.4 (2.5)
0.56 (4)
0.85 (6)
1.7 (13)
4.3 (33)
Gain = 64
0.024 (0.14)
0.024 (0.14)
0.04 (0.21)
0.057 (0.34)
0.081 (0.47)
0.11 (0.74)
0.13 (0.78)
0.14 (0.89)
0.18 (1.1)
0.23 (1.4)
0.33 (2)
0.46 (2.8)
0.68 (4.3)
1.3 (10)
3.1 (24)
Gain = 128
0.02 (0.1)
0.021 (0.1)
0.035 (0.2)
0.048 (0.28)
0.07 (0.43)
0.09 (0.57)
0.11 (0.7)
0.12 (0.75)
0.13 (0.82)
0.19 (1.2)
0.26 (1.5)
0.4 (2.6)
0.6 (4.5)
1.2 (9.7)
2.6 (21)
Table 19. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Mid Power Mode
Filter
Word
(Dec.)
2047
1920
960
480
240
120
96
80
60
30
15
8
4
2
1
Output
Data
Rate
(SPS)
2.34
2.5
5
10
20
40
50
60
80
160
320
600
1200
2400
4800
Output Data
Rate (Zero
Latency Mode)
(SPS)
0.586
0.625
1.25
2.5
5
10
12.5
15
20
40
80
150
300
600
1200
Gain = 1
24 (21.8)
24 (21.8)
23.8 (21.2)
23.4 (20.8)
22.8 (20.3)
22.3 (19.7)
22.2 (19.5)
22.1 (19.4)
21.9 (19.2)
21.4 (18.8)
20.9 (18.2)
20.4 (17.7)
19.8 (17.1)
19 (16.1)
16.1 (13.3)
Gain = 2
24 (21.4)
23.8 (21.4)
23.5 (21)
23.1 (20.4)
22.5 (20)
22 (19.4)
21.8 (19.2)
21.7 (19.1)
21.5 (18.9)
21 (18.9)
20.5 (17.8)
20 (17.3)
19.4 (16.7)
18.5 (15.5)
16 (13.2)
Gain = 4
23.6 (21)
23.5 (21)
23.2 (20.6)
22.7 (20.1)
22.1 (19.6)
21.7 (19)
21.5 (18.9)
21.4 (18.7)
21.1 (18.5)
20.7 (18.5)
20.2 (17.5)
19.7 (17)
19 (16.3)
18 (15.1)
15.9 (12.9)
Gain = 8
23.3 (20.6)
23 (20.6)
22.8 (20.2)
22.2 (19.6)
21.6 (19.1)
21.1 (18.5)
21 (18.3)
20.9 (18.2)
20.7 (18)
20.2 (17.5)
19.6 (17)
19 (16.4)
18.3 (15.6)
17.2 (14.2)
15.5 (12.6)
Rev. E | Page 31 of 94
Gain = 16
22.6 (20.3)
22.6 (20.3)
22.2 (19.7)
21.5 (19.1)
21.1 (18.5)
20.6 (18.1)
20.4 (17.9)
20.3 (17.8)
20.1 (17.6)
19.6 (17)
19 (16.5)
18.5 (15.9)
17.9 (15.2)
16.9 (14)
15.4 (12.5)
Gain = 32
22.1 (19.7)
22 (19.7)
21.5 (19.2)
21 (18.5)
20.6 (17.9)
20.1 (17.5)
19.9 (17.3)
19.8 (17.2)
19.6 (16.9)
19.1 (16.3)
18.6 (15.9)
18.1 (15.3)
17.5 (14.7)
16.5 (13.6)
15.1 (12.2)
Gain = 64
21.6 (19.1)
21.6 (19.1)
20.9 (18.5)
20.4 (17.8)
19.9 (17.3)
19.4 (16.8)
19.2 (16.6)
19.1 (16.4)
18.9 (16.2)
18.4 (15.8)
17.9 (15.3)
17.4 (14.8)
16.8 (14)
15.8 (12.9)
14.6 (11.7)
Gain = 128
20.9 (18.5)
20.8 (18.5)
20.1 (17.6)
19.6 (17.1)
19.1 (16.5)
18.7 (16)
18.5 (15.8)
18.4 (15.7)
18.2 (15.5)
17.7 (15)
17.2 (14.6)
16.6 (13.9)
16 (13.1)
15 (12)
13.9 (10.9)
AD7124-8
Data Sheet
Sinc3
Table 20. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Mid Power Mode
Filter
Word
(Dec.)
2047
960
480
320
160
96
80
40
20
10
5
3
2
1
Output
Data
Rate
(SPS)
2.34
5
10
15
30
50
60
120
240
480
960
1600
2400
4800
Output
Data Rate
(Zero
Latency
Mode) (SPS)
0.78
1.67
3.33
5
10
16.67
20
40
80
160
320
533.33
800
1600
f3dB
(Hz)
0.64
1.36
2.72
4.08
8.16
13.6
16.32
32.64
65.28
130.6
261.1
435.2
652.8
1306
Gain = 1
0.25 (1.5)
0.35 (2.2)
0.5 (3.1)
0.6 (3.8)
0.83 (5.6)
1.1 (7.5)
1.2 (7.7)
1.7 (11)
2.5 (16)
3.5 (24)
6.7 (53)
25 (170)
110 (740)
880 (5800)
Gain = 2
0.17 (1)
0.23 (1.3)
0.31 (1.9)
0.38 (2.4)
0.54 (3.3)
0.72 (4.4)
0.8 (4.8)
1.1 (7)
1.6 (9.7)
2.2 (15)
4.1 (34)
13 (90)
54 (360)
430 (3100)
Gain = 4
0.087 (0.58)
0.14 (0.82)
0.19 (1.3)
0.24 (1.6)
0.34 (2.2)
0.44 (2.9)
0.48 (3.1)
0.7 (4.6)
0.94 (6.2)
1.4 (9.3)
2.5 (19)
7.1 (53)
27 (200)
220 (1500)
Gain = 8
0.065 (0.4)
0.1 (0.58)
0.14 (0.89)
0.17 (1.1)
0.24 (1.6)
0.31 (2)
0.35 (2.2)
0.47 (3.2)
0.7 (5)
1 (7)
1.8 (14)
4.2 (30)
14 (110)
110 (760)
Gain = 16
0.049 (0.27)
0.074 (0.43)
0.1 (0.63)
0.13 (0.8)
0.18 (1.1)
0.24 (1.5)
0.25 (1.6)
0.36 (2.2)
0.53 (3.2)
0.78 (5.3)
1.2 (8.7)
2.4 (18)
7.4 (51)
55 (400)
Gain = 32
0.034 (0.19)
0.053 (0.31)
0.075 (0.44)
0.089 (0.54)
0.13 (0.77)
0.17 (1)
0.18 (1.1)
0.26 (1.7)
0.37 (2.3)
0.56 (3.9)
0.84 (6.4)
1.5 (11)
3.9 (29)
27 (180)
Gain = 64
0.03 (0.16)
0.041 (0.22)
0.6 (0.35)
0.076 (0.46)
0.1 (0.65)
0.14 (0.82)
0.15 (0.94)
0.21 (1.5)
0.31 (2.1)
0.46 (3.1)
0.67 (5)
1.1 (7.8)
2.3 (16)
14 (110)
Gain = 128
0.022 (0.11)
0.034 (0.17)
0.049 (0.28)
0.062 (0.35)
0.088 (0.53)
0.11 (0.7)
0.12 (0.77)
0.18 (1.1)
0.26 (1.8)
0.38 (2.5)
0.57 (3.9)
0.89 (6.8)
1.6 (12)
7.5 (56)
Table 21. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Mid Power Mode
Filter
Word
(Dec.)
2047
960
480
320
160
96
80
40
20
10
5
3
2
1
Output
Data
Rate
(SPS)
2.34
5
10
15
30
50
60
120
240
480
960
1600
2400
4800
Output Data
Rate (Zero
Latency
Mode) (SPS)
0.78
1.67
3.33
5
10
16.67
20
40
80
160
320
533.33
800
1600
Gain = 1
24 (21.7)
23.8 (21.1)
23.3 (20.6)
23 (20.3)
22.5 (19.8)
22.1 (19.4)
22 (19.3)
21.5 (18.8)
21 (18.3)
20.4 (17.7)
19.5 (16.5)
17.6 (14.8)
15.5 (12.7)
12.5 (9.7)
Gain = 2
23.8 (21.2)
23.4 (20.8)
22.9 (20.3)
22.6 (20)
22.1 (19.5)
21.7 (19.1)
21.6 (19)
21.1 (18.5)
20.6 (18)
20.1 (17.3)
19.2 (16.2)
17.5 (14.8)
15.5 (12.7)
12.5 (9.7)
Gain = 4
23.6 (21)
23.1 (20.5)
22.6 (19.9)
22.3 (19.6)
21.8 (19.1)
21.4 (18.7)
21.3 (18.6)
20.8 (18.1)
20.3 (17.6)
19.8 (17)
19 (16)
17.4 (14.5)
15.5 (12.6)
12.5 (9.7)
Gain = 8
23.2 (20.6)
22.6 (20)
22.1 (19.4)
21.8 (19.1)
21.3 (18.6)
20.9 (18.2)
20.8 (18.1)
20.3 (17.6)
19.8 (17)
19.2 (16.4)
18.4 (15.4)
17.2 (14.3)
15.4 (12.6)
12.5 (9.7)
Gain = 16
22.6 (20.1)
22 (19.5)
21.5 (18.9)
21.2 (18.6)
20.7 (18.1)
20.3 (17.7)
20.2 (17.6)
19.7 (17.1)
19.2 (16.6)
18.6 (15.9)
18 (15.1)
17 (14.1)
15.4 (12.6)
12.5 (9.6)
Gain = 32
22.1 (19.6)
21.5 19)
21 (18.4)
20.7 (18.1)
20.2 (17.6)
19.8 (17.2)
19.7 (17.1)
19.2 (16.5)
18.7 (16)
18.1 (15.3)
17.5 (14.6)
16.7 (13.8)
15.3 (12.4)
12.5 (9.6)
Gain = 64
21.3 (18.9)
20.8 (18.4)
20.3 (17.8)
20 (17.4)
19.5 (16.9)
19.1 (16.5)
19.1 (16.3)
18.5 (15.7)
18 (15.2)
17.4 (14.6)
16.8 (13.9)
16.1 (13.3)
15 (12.3)
12.4 (9.5)
Gain = 128
20.7 (18.4)
20.1 (17.8)
19.6 (17.1)
19.3 (16.8)
18.8 (16.2)
18.4 (15.8)
18.3 (15.6)
17.7 (15.1)
17.2 (14.4)
16.7 (13.9)
16.1 (13.3)
15.4 (12.6)
14.6 (11.7)
12.4 (9.4)
Post Filters
Table 22. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Mid Power Mode
Output Data Rate (SPS)
16.67
20
25
27.27
Gain = 1
1.1 (6.3)
1.1 (6.9)
1.2 (8)
1.3 (9.2)
Gain = 2
0.69 (4)
0.7 (4)
0.8 (4.6)
0.82 (4.8)
Gain = 4
0.41 (2.5)
0.41 (2.5)
0.46 (2.8)
0.48 (2.8)
Gain = 8
0.31 (2)
0.33 (2.1)
0.36 (2.3)
0.36 (2.3)
Gain = 16
0.23 (1.4)
0.23 (1.5)
0.25 (1.5)
0.28 (1.6)
Gain = 32
0.17 (0.96)
0.18 (0.96)
0.17 (1)
0.19 (1.1)
Gain = 64
0.13 (0.79)
0.14 (0.81)
0.15 (0.9)
0.16 (1)
Gain = 128
0.11 (0.61)
0.12 (0.67)
0.12 (0.74)
0.13 (0.79)
Table 23. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Mid Power Mode
Output Data Rate (SPS)
16.67
20
25
27.27
Gain = 1
22.1 (19.6)
22.1 (19.5)
22 (19.2)
21.9 (19)
Gain = 2
21.8 (19.2)
21.8 (19.2)
21.6 (19.1)
21.5 (19)
Gain = 4
21.5 (18.9)
21.5 (18.9)
21.4 (18.8)
21.3 (18.8)
Gain = 8
20.9 (18.3)
20.9 (18.2)
20.7 (18.1)
20.7 (18.1)
Rev. E | Page 32 of 94
Gain = 16
20.4 (17.8)
20.4 (17.7)
20.3 (17.6)
21.1 (17.6)
Gain = 32
19.8 (17.3)
19.8 (17.3)
19.7 (17.2)
19.7 (17.1)
Gain = 64
19.2 (16.6)
19 (16.6)
18.9 (16.4)
18.9 (16.3)
Gain = 128
18.4 (16)
18.3 (15.8)
18.2 (15.7)
18.2 (15.6)
Data Sheet
AD7124-8
Fast Settling Filter (Sinc4 + Sinc1)
Table 24. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Mid Power Mode (Average by 16)
Filter Word
(Dec.)
96
30
6
5
2
1
Output Data Rate
(SPS)
2.63
8.42
42.11
50.53
126.32
252.63
Gain = 1
0.36 (2.4)
0.67 (4.2)
1.5 (9)
1.6 (9.3)
2.5 (15)
5.2 (21)
Gain = 2
0.23 (1.5)
0.44 (2.7)
0.96 (6.1)
1 (7.7)
1.6 (11)
3.1 (19)
Gain = 4
0.15 (0.82)
0.26 (1.6)
0.57 (3.7)
0.62 (4)
1 (7.2)
1.8 (11)
Gain = 8
0.1 (0.71)
0.18 (1.1)
0.42 (2.6)
0.46 (3)
0.76 (4.9)
1.4 (9.8)
Gain = 16
0.078 (0.44)
0.14 (0.8)
0.32 (1.9)
0.33 (2)
0.57 (3.7)
0.92 (6.2)
Gain = 32
0.056 (0.35)
0.1 (0.54)
0.22 (1.5)
0.24 (1.6)
0.41 (2.7)
0.62 (4.2)
Gain = 64
0.045 (0.26)
0.08 (0.48)
0.18 (1.1)
0.2 (1.3)
0.32 (2.4)
0.49 (3)
Gain = 128
0.038 (0.21)
0.067 (0.41)
0.15 (0.95)
0.17 (1.2)
0.29 (1.9)
0.41 (3)
Table 25. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Mid Power Mode (Average by 16)
Filter Word
(Dec.)
96
30
6
5
2
1
Output Data Rate
(SPS)
2.63
8.42
42.11
50.53
126.32
252.63
Gain = 1
23.7 (21)
22.8 (20.2)
21.7 (19.1)
21.5 (19)
20.9 (18.3)
19.9 (17.3)
Gain = 2
23.4 (20.7)
22.4 (19.8)
21.3 (18.6)
21.2 (18.4)
20.5 (17.8)
19.6 (17)
Gain = 4
23 (20.5)
22.2 (19.5)
21.1 (18.4)
20.9 (18.2)
20.2 (17.4)
19.4 (16.8)
Gain = 8
22.5 (19.8)
21.7 (19.1)
20.5 (17.9)
20.4 (17.8)
19.6 (17)
18.8 (16)
Gain = 16
21.9 (19.4)
21 (18.6)
19.9 (17.3)
19.8 (17.2)
19.1 (16.4)
18.4 (15.6)
Gain = 32
21.4 (18.8)
20.6 (18.1)
19.4 (16.7)
19.3 (16.6)
18.6 (15.8)
17.9 (15.2)
Gain = 64
20.7 (18.2)
19.9 (17.3)
18.7 (16)
18.5 (15.9)
17.9 (15.2)
17.3 (14.7)
Gain = 128
20 (17.5)
19.1 (16.5)
18 (15.2)
17.8 (15)
17.1 (14.3)
16.5 (13.7)
Fast Settling Filter (Sinc3 + Sinc1)
Table 26. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Mid Power Mode (Average by 16)
Filter Word
(Dec.)
96
30
6
5
2
1
Output Data Rate
(SPS)
2.78
8.89
44.44
53.33
133.33
266.67
Gain = 1
0.39 (2.4)
0.71 (4.2)
1.5 (9.5)
1.6 (11)
6 (37)
44 (320)
Gain = 2
0.25 (1.5)
0.43 (2.5)
0.93 (6)
1 (6.9)
3.2 (20)
23 (160)
Gain = 4
0.16 (1)
0.27 (1.6)
0.59 (3.8)
0.66 (4.2)
1.8 (11)
12 (83)
Gain = 8
0.11 (0.67)
0.19 (1.1)
0.43 (2.6)
0.46 (2.8)
1 (7.2)
5.7 (41)
Gain = 16
0.08 (0.48)
0.15 (1)
0.32 (2.1)
0.35 (2.3)
0.63 (4.5)
3 (20)
Gain = 32
0.058 (0.31)
0.098 (0.64)
0.22 (1.5)
0.24 (1.6)
0.43 (3)
1.6 (9.9)
Gain = 64
0.047 (0.27)
0.083 (0.47)
0.18 (1.1)
0.2 (1.2)
0.33 (2.2)
0.84 (6.4)
Gain = 128
0.039 (0.23)
0.068 (0.4)
0.15 (0.98)
0.17 (1.1)
0.27 (1.8)
0.56 (3.5)
Table 27. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Mid Power Mode (Average by 16)
Filter
Word
(Dec.)
96
30
6
5
2
1
Output Data
Rate (SPS)
2.78
8.89
44.44
53.33
133.33
266.67
Gain = 1
23.6 (21)
22.7 (20.2)
21.7 (19)
21.5 (18.8)
19.7 (17)
16.8 (13.9)
Gain = 2
23.3 (20.7)
22.5 (19.9)
21.4 (18.7)
21.2 (18.5)
19.6 (16.9)
16.7 (13.9)
Gain = 4
22.9 (20.3)
22.2 (19.6)
21 (18.3)
20.9 (18.2)
19.4 (16.8)
16.7 (13.9)
Gain = 8
22.5 (19.8)
21.7 (19.1)
20.5 (17.9)
20.4 (17.8)
19.2 (16.4)
16.7 (13.9)
Rev. E | Page 33 of 94
Gain = 16
21.9 (19.3)
21 (18.3)
19.9 (17.2)
19.8 (17.1)
18.9 (16.1)
16.7 (13.9)
Gain = 32
21.4 (18.9)
20.6 (17.9)
19.4 (16.7)
19.3 (16.6)
18.5 (15.7)
16.6 (13.9)
Gain = 64
20.7 (18.1)
19.8 (17.3)
18.7 (16.1)
18.6 (16)
17.8 (15.1)
16.5 (13.6)
Gain = 128
19.9 (17.4)
19.1 (16.6)
18 (15.3)
17.8 (15.1)
17.1 (14.4)
16.1 (13.4)
AD7124-8
Data Sheet
LOW POWER MODE
Sinc4
Table 28. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Low Power Mode
Filter
Word
(Dec.)
2047
1920
960
480
240
120
60
48
40
30
15
8
4
2
1
Output
Data
Rate
(SPS)
1.17
1.25
2.5
5
10
20
40
50
60
80
160
300
600
1200
2400
Output
Data
Rate
(Zero
Latency
Mode)
(SPS)
0.293
0.3125
0.625
1.25
2.5
5
10
12.5
15
20
40
75
150
300
600
f3dB
(Hz)
0.269
0.288
0.575
1.15
2.3
4.6
9.2
11.5
13.8
18.4
36.8
69
138
276
552
Gain = 1
0.22 (1.2)
0.24 (1.5)
0.37 (2.1)
0.5 (3)
0.65 (4.1)
0.9 (5.8)
1.3 (8)
1.4 (9.3)
1.6 (10)
1.8 (12)
2.6 (17)
3.7 (24)
5.2 (35)
9.4 (57)
72 (470)
Gain = 2
0.15 (0.89)
0.15 (0.89)
0.23 (1.2)
0.3 (1.7)
0.42 (2.5)
0.61 (3.5)
0.82 (5)
0.95 (6)
0.99 (6.6)
1.2 (7.5)
1.8 (11)
2.5 (17)
4 (24)
7.6 (47)
39 (240)
Gain = 4
0.095 (0.67)
0.095 (0.67)
0.13 (0.82)
0.18 (1.2)
0.26 (1.9)
0.38 (2.5)
0.53 (3.7)
0.6 (4.2)
0.64 (4.5)
0.77 (5.1)
1.1 (7.2)
1.6 (11)
2.6 (17)
5.8 (36)
22 (130)
Gain = 8
0.071 (0.41)
0.071 (0.41)
0.1 (0.61)
0.13 (0.77)
0.2 (1.1)
0.28 (1.7)
0.38 (2.4)
0.46 (2.8)
0.47 (3.2)
0.55 (3.7)
0.85 (5.7)
1.2 (7.5)
2.1 (13)
4.9 (32)
16 (110)
Gain = 16
0.053 (0.26)
0.053 (0.26)
0.068 (0.37)
0.099 (0.56)
0.14 (0.8)
0.2 1.2)
0.29 (1.8)
0.32 (2.1)
0.35 (2.2)
0.4 (2.7)
0.56 (3.9)
0.87 (5.6)
1.4 (8.5)
3 (19)
8 (49)
Gain = 32
0.043 (0.2)
0.043 (0.2)
0.055 (0.26)
0.078 (0.39)
0.1 (0.6)
0.15 (0.85)
0.21 (1)
0.24 (1.5)
0.26 (1.7)
0.3 (2)
0.41 (2.5)
0.58 (3.9)
1 (6)
1.9 (11)
4.8 (29)
Gain = 64
0.035 (0.16)
0.035 (0.16)
0.041 (0.23)
0.06 (0.31)
0.085 (0.5)
0.12 (0.68)
0.17 (0.95)
0.2 (1.1)
0.21 (1.3)
0.25 (1.6)
0.33 (2.1)
0.48 (2.9)
0.76 (5.2)
1.4 (9)
3.3 (21)
Gain = 128
0.024 (0.12)
0.024 (0.12)
0.035 (0.17)
0.052 (0.26)
0.072 (0.43)
0.096 (0.6)
0.14 (0.9)
0.16 (1)
0.17 (1.1)
0.19 (1.3)
0.28 (1.6)
0.39 (2.6)
0.6 (3.9)
1.3 (7.8)
2.6 (18)
Table 29. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Low Power Mode
Filter
Word
(Dec.)
2047
1920
960
480
240
120
60
48
40
30
15
8
4
2
1
Output
Data
Rate
(SPS)
1.17
1.25
2.5
5
10
20
40
50
60
80
160
300
600
1200
2400
Output Data
Rate (Zero
Latency
Mode) (SPS)
0.29311
0.3125
0.625
1.25
2.5
5
10
12.5
15
20
40
75
150
300
600
Gain = 1
24 (22)
24 (21.7)
23.7 (21.2)
23.3 (20.7)
22.9 (20.2)
22.4 (19.7)
21.9 (19.2)
21.7 (19)
21.6 (18.9)
21.4 (18.7)
20.9 (18.2)
20.4 (17.7)
19.9 (17.1)
19 (16.4)
16.1 (13.4)
Gain = 2
23.8 (21.4)
23.8 (21.3)
23.4 (21)
23 (20.5)
22.5 (19.9)
22 (19.4)
21.5 (18.9)
21.3 (18.7)
21.2 (18.5)
21 (18.3)
20.4 (17.8)
19.9 (17.2)
19.3 (16.7)
18.3 (15.7)
16 (13.4)
Gain = 4
23.7 (20.9)
23.6 (20.8)
23.2 (20.5)
22.7 (20)
22.2 (19.4)
21.7 (18.9)
21.2 (18.4)
21 (18.2)
20.9 (18.1)
20.6 (17.9)
20.1 (17.4)
19.6 (16.8)
18.9 (16.2)
17.7 (15.1)
15.8 (13.3)
Gain = 8
23.2 (20.5)
23.1 (20.5)
22.6 (20)
22.1 (19.6)
21.6 (19.1)
21.1 (18.5)
20.6 (18)
20.4 (17.8)
20.3 (17.6)
20.1 (17.4)
19.5 (16.8)
19 (16.3)
18.2 (15.6)
17 (14.3)
15.3 (12.5)
Rev. E | Page 34 of 94
Gain = 16
22.7 (20.2)
22.6 (20.1)
22.1 (19.7)
21.6 (19.1)
21.1 (18.6)
20.6 (18)
20.1 (17.4)
19.9 (17.2)
19.8 (17.1)
19.6 (16.8)
19.1 (16.3)
18.5 (15.8)
17.8 (15.2)
16.7 (14)
15.2 (12.5)
Gain = 32
21.8 (19.7)
21.8 (19.6)
21.4 (19.2)
20.9 (18.6)
20.5 (18)
20 (17.5)
19.5 (17.3)
19.3 (16.7)
19.2 (16.5)
19 (16.2)
18.5 (15.7)
18 (15.3)
17.3 (14.7)
16.3 (13.8)
15 (12.4)
Gain = 64
21.3 (18.9)
21.2 (18.9)
20.8 (18.4)
20.3 (17.9)
19.8 (17.2)
19.3 (16.8)
18.8 (16.3)
18.6 (16.1)
18.5 (15.9)
18.3 (15.6)
17.8 (15.2)
17.3 (14.7)
16.7 (13.9)
15.7 (13.1)
14.5 (11.9)
Gain = 128
20.6 (18.3)
20.6 (18.3)
20.1 (17.8)
19.5 (17.2
19.1 (16.5)
18.6 (16)
18.1 (15.4)
17.9 (15.2)
17.8 (15.1)
17.6 (14.9)
17.1 (14.5)
16.6 (13.9)
16 (13.3)
14.9 (12.3)
13.9 (11)
Data Sheet
AD7124-8
Sinc3
Table 30. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Low Power Mode
Filter
Word
(Dec.)
2047
480
240
160
80
48
40
20
10
5
3
2
1
Output
Data
Rate
(SPS)
1.17
5
10
15
30
50
60
120
240
480
800
1200
2400
Output
Data
Rate
(Zero
Latency
Mode)
(SPS)
0.39
1.67
3.33
5
10
16.67
20
40
80
160
266.67
400
800
f3dB
(Hz)
0.32
1.36
2.72
4.08
8.16
13.6
16.32
32.64
65.28
130.6
217.6
326.4
652.8
Gain = 1
0.26 (1.5)
0.51 (3.1)
0.75 (4.5)
0.88 (5.5)
1.3 (7.8)
1.7 (9.9)
1.8 (12)
2.5 (17)
3.5 (25)
6.8 (48)
25 (180)
110 (740)
870 (5600)
Gain = 2
0.17 (0.9)
0.31 (1.9)
0.45 (2.8)
0.55 (3.3)
0.77 (4.9)
1 (6.4)
1.1 (7)
1.6 (10)
2.4 (16)
4.3 (32)
13 (98)
55 (390)
430 (2900)
Gain = 4
0.099 (0.6)
0.2 (1.3)
0.29 (2)
0.3 (2.4)
0.47 (3.3)
0.63 (4.6)
0.71 (5)
0.9 (6.1)7
1.5 (9.9)
2.6 (19)
7.4 (53)
28 (180)
220 (1400)
Gain = 8
0.072 (0.36)
0.15 (0.86)
0.21 (1.3)
0.26 (1.6)
0.36 (2.2)
0.47 (3.1)
0.52 (3.4)
0.73 (5)
1.1 (7.6)
2 (15)
4.5 (34)
15 (100)
110 (670)
Gain = 16
0.055 (0.27)
0.11 (0.65)
0.16 (0.9)
0.19 (1.2)
0.27 (1.7)
0.36 (2.2)
0.39 (2.5)
0.55 (3.7)
0.8 (5.3)
1.3 (9)
2.7 (18)
7.6 (57)
56 (370)
Gain = 32
0.039 (0.21)
0.078 (0.45)
0.11 (0.65)
0.14 (0.79)
0.19 (1.2)
0.26 (1.7)
0.27 (1.8)
0.41 (2.5)
0.56 (3.5)
0.9 (6.5)
1.6 (11)
4 (32)
28 (180)
Gain = 64
0.032 (0.16)
0.063 (0.37)
0.085 (0.51)
0.1 (0.62)
0.15 (0.94)
0.2 ( 1.3)
0.21 (1.4)
0.3 (1.9)
0.45 (2.8)
0.7 (4.5)
1.1 (7.7)
2.4 (16)
14 (100)
Gain = 128
0.026 (0.13)
0.05 (0.28)
0.071 (0.39)
0.089 (0.53)
0.12 (0.72)
0.16 (1)
0.18 (1.3)
0.26 (1.6)
0.37 (2.3)
0.55 (3.3)
0.91 (6)
1.6 (12)
7.6 (52)
Gain = 64
21.2 (18.9)
20.2 (17.7)
19.8 (17.2)
19.5 (16.9)
19 (16.3)
18.6 (15.9)
18.5 (15.8)
18 (15.3)
17.4 (14.8)
16.8 (14.1)
16.1 (13.3)
15 (12.2)
12.5 (9.6)
Gain = 128
20.5 (18.2)
19.6 (17.1)
19.1 (16.6)
18.8 (16.2)
18.3 (15.7)
17.9 (15.2)
17.7 (15.1)
17.2 (14.6)
16.7 (14.1)
16.1 (13.5)
15.4 (12.7)
14.5 (11.6)
12.3 (9.6)
Table 31. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Low Power Mode
Filter
Word
(Dec.)
2047
480
240
160
80
48
40
20
10
5
3
2
1
Output
Data Rate
(SPS)
1.17
5
10
15
30
50
60
120
120
480
800
1200
2400
Output
Data Rate
(Zero
Latency
Mode)
(SPS)
0.39
1.67
3.33
5
10
16.67
20
40
80
160
266.67
400
800
Gain = 1
24 (21.7)
23.2 (20.6)
22.7 (20.1)
22.4 (19.8)
21.9 (19.3)
21.5 (18.9)
21.4 (18.7)
20.9 (18.2)
20.4 (17.6)
19.5 (16.7)
17.6 (14.8)
15.5 (12.7)
12.5 (9.8)
Gain = 2
23.8 (21.4)
22.9 (20.3)
22.4 (19.8)
22.1 (19.5)
21.6 (19)
21.2 (18.6)
21.1 (18.4)
20.6 (17.9)
20 (17.2)
19.2 (16.3)
17.5 (14.6)
15.5 (12.7)
12.5 (9.8)
Gain = 4
23.6 (21)
22.6 (19.9)
22.1 (19.3)
21.8 (19)
21.3 (18.5)
20.9 (18.1)
20.8 (17.9)
20.3 (17.4)
19.7 (16.9)
18.8 (16)
17.4 (14.5)
15.4 (12.7)
12.5 (9.8)
Gain = 8
23 (20.7)
22 (19.5)
21.5 (18.9)
21.2 (18.6)
20.7 (18.1)
20.3 (17.6)
20.2 (17.5)
19.7 (16.9)
19.1 (16.3)
18.2 (15.4)
17.1 (14.2)
15.4 (12.6)
12.5 (9.8
Gain = 16
22.4 (20.1)
21.4 (18.9)
20.9 (18.4)
20.6 (18)
20.1 (17.5)
19.7 (17.1)
19.6 (16.9)
19.1 (16.4)
18.6 (15.9)
17.9 (15.1)
16.8 (14.1)
15.3 (12.4)
12.5 (9.7)
Gain = 32
21.9 (19.5)
20.9 (18.4)
20.4 (17.9)
20.1 (17.6)
19.6 (17)
19.2 (16.5)
19.1 (16.4)
18.6 (15.9)
18.1 (15.4)
17.4 (14.6)
16.6 (13.8)
15.2 (12.3)
12.5 (9.7)
Post Filters
Table 32. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Low Power Mode
Output Data Rate (SPS)
16.67
20
25
27.27
Gain = 1
1.7 (12)
1.7 (11)
1.8 (11)
1.9 (11)
Gain = 2
0.96 (5.8)
1.1 (6.4)
1.1 (6.7)
1.1 (7.3)
Gain = 4
0.65 (4)
0.65 (4.2)
0.68 (4.2)
0.69 (4.4)
Gain = 8
0.45 (2.6)
0.46 (2.6)
0.52 (2.7)
0.54 (2.9)
Gain = 16
0.34 (1.9)
0.36 (1.9)
0.37 (2)
0.4 (2.1)
Gain = 32
0.25 (1.5)
0.26 (1.5)
0.26 (1.6)
0.27 (1.8)
Gain = 64
0.2 (1.2)
0.21 (1.2)
0.22 (1.2)
0.23 (1.4)
Gain = 128
0.16 (0.92)
0.17 (0.93)
0.17 (1.1)
0.18 (1.3)
Table 33. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Low Power Mode
Output Data Rate (SPS)
16.67
20
25
27.27
Gain = 1
21.5 (18.8)
21.5 (18.8)
21.4 (18.8)
21.3 (18.7)
Gain = 2
21.3 (18.7)
21.2 (18.6)
21.2 (18.5)
21.1 (18.4)
Gain = 4
20.9 (18.2)
20.9 (18.2)
20.8 (18.2)
20.8 (18.1)
Gain = 8
21.4 (17.9)
20.4 (17.9)
20.2 (17.8)
20.2 (17.7)
Rev. E | Page 35 of 94
Gain = 16
19.8 (17.3)
19.7 (17.3)
19.7 (17.3)
19.6 (17.2)
Gain = 32
19.3 (16.7)
19.2 (16.7)
19.2 (16.6)
19.1 (16.4)
Gain = 64
18.6 (16.1)
18.6 (16.1)
18.5 (15.9)
18.4 (15.8)
Gain = 128
17.9 (15.4)
17.8 (15.4)
17.8 (15.1)
17.7 (14.9)
AD7124-8
Data Sheet
Fast Settling Filter (Sinc4 + Sinc1)
Table 34. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Low Power Mode (Average by 8)
Filter Word
(Dec.)
96
30
6
5
2
1
Output Data Rate
(SPS)
2.27
7.27
36.36
43.64
109.1
218.18
Gain = 1
0.53 (3.4)
0.89 (5.4)
2.1 (12)
2.2 (13)
3.7 (25)
8.4 (52)
Gain = 2
0.34 (2.2)
0.6 (3.6)
1.4 (8.3)
1.4 (9.7)
2.5 (18)
5.4 (34)
Gain = 4
0.19 (1.2)
0.36 (2.2)
0.82 (5.6)
0.93 (6.5)
1.5 (10)
3.3 (21)
Gain = 8
0.16 (0.97)
0.27 (1.8)
0.64 (3.9)
0.71 (4.2)
1.3 (7.5)
2.6 (16)
Gain = 16
0.1 (0.61)
0.21 (1.2)
0.43 (2.7)
0.5 (3.1)
0.86 (5.6)
1.6 (9.8)
Gain = 32
0.082 (0.48)
0.15 (0.93)
0.33 (2.1)
0.35 (2.4)
0.59 (3.5)
0.97 (6.1)
Gain = 64
0.065 (0.38)
0.12 (0.65)
0.25 (1.6)
0.28 (1.7)
0.47 (3.2)
0.75 (5.4)
Gain = 128
0.058 (0.37)
0.093 (0.59)
0.21 (1.4)
0.23 (1.5)
0.39 (2.4)
0.63 (4.7)
Table 35. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Low Power Mode (Average by 8)
Filter Word
(Dec.)
96
30
6
5
2
1
Output Data
Rate (SPS)
2.27
7.27
36.36
43.64
109.1
218.18
Gain = 1
23.2 (20.5)
22.4 (19.8)
21.2 (18.6)
21.1 (18.5)
20.4 (17.6)
19.2 (16.6)
Gain = 2
22.8 (20.1)
22 (19.4)
20.8 (18.1)
20.7 (18)
19.9 (17.1)
18.8 (16.2)
Gain = 4
22.7 (20)
21.7 (19.1)
20.5 (17.8)
20.4 (17.6)
19.6 (16.9)
18.5 (15.9)
Gain = 8
21.9 (19.3)
21.1 (18.4)
19.9 (17.3)
19.8 (17.2)
18.9 (16.3)
17.9 (15.2)
Gain = 16
21.5 (19)
20.5 (18)
19.5 (16.8)
19.3 (16.6)
18.5 (15.8)
17.6 (15)
Gain = 32
20.9 (18.3)
20 (17.4)
18.9 (16.2)
18.8 (16)
18 (15.4)
17.3 (14.7)
Gain = 64
20.2 (17.6)
19.4 (16.9)
18.3 (15.6)
18.1 (15.5)
17.3 (14.6)
16.7 (13.8)
Gain = 128
19.4 (16.7)
18.7 (16)
17.5 (14.8)
17.4 (14.7)
16.6 (14)
15.9 (13)
Fast Settling Filter (Sinc3 + Sinc1)
Table 36. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Low Power Mode (Average by 8)
Filter Word
(Dec.)
96
30
6
5
2
1
Output Data Rate
(SPS)
2.5
8
40
48
120
240
Gain = 1
0.53 (3.6)
0.92 (5.4)
2.1 (13)
2.3 (14)
11 (72)
88 (530)
Gain = 2
0.33 (2.1)
0.58 (3.4)
1.3 (8.3)
1.5 (8.6)
5.9 (39)
45 (250)
Gain = 4
0.21 (1.4)
0.4 (2.3)
0.83 (6)
0.87 (6.6)
3.2 (23)
22 (140)
Gain = 8
0.15 (0.93)
0.28 (1.6)
0.61 (4.1)
0.7 (4.4)
1.9 (15)
11 (82)
Gain = 16
0.11 (0.6)
0.2 (1.1)
0.44 (3)
0.5 (3.3)
1.1 (8.5)
5.8 (40)
Gain = 32
0.073 (0.44)
0.14 (0.79)
0.33 (2.1)
0.36 (2.3)
0.7 (4.7)
3 (22)
Gain = 64
0.064 (0.39)
0.11 (0.62)
0.26 (1.6)
0.3 (1.7)
0.5 (3.3)
01.6 (11)
Gain = 128
0.051 (0.29)
0.094 (0.51)
0.21 (1.3)
0.23 (1.4)
0.4 (2.4)
0.94 (6.3)
Table 37. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Low Power Mode (Average by 8)
Filter Word
(Dec.)
96
30
6
5
2
1
Output Data Rate
(SPS)
2.5
8
40
48
120
240
Gain = 1
23.2 (20.4)
22.4 (19.8)
21.2 (18.6)
21 (18.4)
18.7 (16.1)
15.8 (13.2)
Gain = 2
22.8 (20.2)
22 (19.5)
20.9 (18.2)
20.7 (18.1)
18.7 (16)
15.8 (13.2)
Gain = 4
22.5 (19.8)
21.6 (19)
20.5 (17.7)
20.4 (17.5)
18.6 (15.8)
15.8 (13.2)
Gain = 8
22 (19.4)
21.1 (18.6)
20 (17.2)
19.8 (17)
18.3 (15.3)
15.7 (12.9)
Rev. E | Page 36 of 94
Gain = 16
21.4 (19)
20.6 (18.1)
19.4 (16.7)
19.3 (16.5)
18.1 (15.2)
15.7 (12.9)
Gain = 32
21 (18.4)
20.1 (17.6)
18.9 (16.2)
18.7 (16.1)
17.8 (15)
15.7 (12.8)
Gain = 64
20.2 (17.6)
19.4 (16.9)
18.2 (15.6)
18 (15.5)
17.3 (14.6)
15.6 (12.8)
Gain = 128
19.6 (17)
18.7 (16.2)
17.5 (14.9)
17.4 (14.8)
16.6 (14)
15.3 (12.6)
Data Sheet
AD7124-8
GETTING STARTED
AVDD
AVDD
REFIN1(+)
IN+
OUT–
IN+
OUT–
OUT+
VBIAS
AIN0
AIN1
AIN2
AIN3
IN–
OUT+
IN–
REFERENCE
DETECT
AVDD
Σ-Δ
ADC
PGA
X-MUX
AIN12
AIN13
REFIN2(+)
REFIN2(–)
RREF
SERIAL
INTERFACE
AND
CONTROL
LOGIC
CHANNEL
SEQUENCER
TEMP
SENSOR
AVSS
DIGITAL
FILTER
VDD
DIAGNOSTICS
REFIN1(–)
PSW
DOUT/RDY
DIN
SCLK
CS
IOVDD
INTERNAL
CLOCK
CLK
SYNC
AD7124-8
REGCAPA
REGCAPD
NOTES
1. SIMPLIFIED BLOCK DIAGRAM SHOWN.
AVSS
DGND
13048-068
AVSS
Figure 64. Basic Connection Diagram
OVERVIEW
Programmable Gain Array (PGA)
The AD7124-8 is a low power ADC that incorporates a Σ-Δ modulator, buffer, reference, gain stage, and on-chip digital filtering,
which is intended for the measurement of wide dynamic ranges,
low frequency signals (such as those in pressure transducers),
weigh scales, and temperature measurement applications.
The analog input signal can be amplified using the PGA. The
PGA allows gains of 1, 2, 4, 8, 16, 32, 64, and 128.
Power Modes
The AD7124-8 offers three power modes: high power mode,
mid power mode, and low power mode. This allows the user
total flexibility in terms of speed, rms noise, and current
consumption.
Analog Inputs
The device can have 8 differential or 15 pseudo differential analog
inputs. The analog inputs can be buffered or unbuffered. The
AD7124-8 uses flexible multiplexing; thus, any analog input pin
can be selected as a positive input (AINP) and any analog input
pin can be selected as a negative input (AINM).
Multiplexer
The on-chip multiplexer increases the channel count of the device.
Because the multiplexer is included on chip, any channel
changes are synchronized with the conversion process.
Reference
The device contains a 2.5 V reference, which has a drift of
15 ppm/°C maximum for the AD7124-8 and 10 ppm/°C
maximum for the AD7124-8 B grade.
Burnout Currents
Two burnout currents, which can be programmed to 500 nA,
2 µA, or 4 µA, are included on chip to detect the presence of the
external sensor.
Σ-Δ ADC and Filter
The AD7124-8 contains a fourth-order Σ-Δ modulator followed
by a digital filter. The device has the following filter options:
•
•
•
•
•
Sinc4
Sinc3
Fast filter
Post filter
Zero latency
Channel Sequencer
The AD7124-8 allows up to 16 configurations, or channels.
These channels can consist of analog inputs, reference inputs, or
power supplies such that diagnostic functions, such as power
supply monitoring, can be interleaved with conversions. The
sequencer automatically converts all enabled channels. When
each enabled channel is selected, the time required to generate
the conversion is equal to the settling time for the selected channel.
Per Channel Configuration
Reference buffers are also included on chip, which can be used
with the internal reference and externally applied references.
The AD7124-8 allows up to eight different setups, each setup
consisting of a gain, output data rate, filter type, and a reference
source. Each channel is then linked to a setup.
Rev. E | Page 37 of 94
AD7124-8
Data Sheet
Serial Interface
The AD7124-8 has a 3-wire or 4-wire SPI. The on-chip registers
are accessed via the serial interface.
Clock
The device has an internal 614.4 kHz clock. Use either this
clock or an external clock as the clock source for the device. The
internal clock can also be made available on a pin if a clock
source is required for external circuitry.
Temperature Sensor
The on-chip temperature sensor monitors the die temperature.
Digital Outputs
The AD7124-8 has four general-purpose digital outputs. These
can be used for driving external circuitry. For example, an
external multiplexer can be controlled by these outputs.
Calibration
Both internal calibration and system calibration are included on
chip; therefore, the user has the option of removing offset or
gain errors internal to the device only, or removing the offset or
gain errors of the complete end system.
Excitation Currents
The device contains two excitation currents that can be set
independently to 50 µA, 100 µA, 250 µA, 500 µA, 750 µA, or 1 mA.
Bias Voltage
A bias voltage generator is included on chip so that signals from
thermocouples can be biased suitably. The bias voltage is set to
AVDD/2 and can be made available on any input. It can supply
multiple channels.
Bridge Power Switch (PSW)
A low-side power switch allows the user to power down bridges
that are interfaced to the ADC.
Diagnostics
The AD7124-8 includes numerous diagnostics features such as
Reference detection
Overvoltage/undervoltage detection
CRC on SPI communications
CRC on the memory map
SPI read/write checks
•
•
AVDD is referred to AVSS. AVDD powers the internal analog
regulator that supplies the ADC.
IOVDD is referred to DGND. This supply sets the interface
logic levels on the SPI interface and powers an internal
regulator for operation of the digital processing.
Single Supply Operation (AVSS = DGND)
When the AD7124-8 is powered from a single supply that is
connected to AVDD, AVSS and DGND can be shorted together
on one single ground plane. With this setup, an external level
shifting circuit is required when using truly bipolar inputs to shift
the common-mode voltage. Recommended regulators include
the ADP162, which has a low quiescent current.
Split Supply Operation (AVSS ≠ DGND)
The AD7124-8 can operate with AVSS set to a negative voltage,
allowing true bipolar inputs to be applied. This allows a truly
fully differential input signal centered around 0 V to be applied
to the AD7124-8 without the need for an external level shifting
circuit. For example, with a 3.6 V split supply, AVDD = +1.8 V
and AVSS = −1.8 V. In this use case, the AD7124-8-internally
level shifts the signals, allowing the digital output to function
between DGND (nominally 0 V) and IOVDD.
When using a split supply for AVDD and AVSS, the absolute
maximum ratings must be considered (see the Absolute
Maximum Ratings section). Ensure that IOVDD is set below
3.6 V to stay within the absolute maximum ratings for the device.
DIGITAL COMMUNICATION
The AD7124-8 has a 3-wire or 4-wire SPI interface that is
compatible with QSPI, MICROWIRE, and DSPs. The interface
operates in SPI Mode 3 and can be operated with CS tied low. In
SPI Mode 3, SCLK idles high, the falling edge of SCLK is the
drive edge, and the rising edge of SCLK is the sample edge. This
means that data is clocked out on the falling/drive edge and data
is clocked in on the rising/sample edge.
DRIVE EDGE
SAMPLE EDGE
13048-069
•
•
•
•
•
The device has two independent power supply pins: AVDD and
IOVDD.
These diagnostics allow a high level of fault coverage in an
application.
Figure 65. SPI Mode 3, SCLK Edges
Accessing the ADC Register Map
POWER SUPPLIES
The AD7124-8 operates with an analog power supply voltage
from 2.7 V to 3.6 V in low or mid power mode and from 2.9 V
to 3.6 V in full power mode. The device accepts a digital power
supply from 1.65 V to 3.6 V.
The communications register controls access to the full register
map of the ADC. This register is an 8-bit, write only register.
On power-up or after a reset, the digital interface defaults to a
state where it expects a write to the communications register;
therefore, all communication begins by writing to the
communications register.
Rev. E | Page 38 of 94
Data Sheet
AD7124-8
The data written to the communications register determines
which register is accessed and if the next operation is a read or
write. The register address bits (Bit 5 to Bit 0) determine the
specific register to which the read or write operation applies.
8-BIT COMMAND
8 BITS, 16 BITS,
OR 24 BITS OF DATA
CMD
DATA
CS
When the read or write operation to the selected register is
complete, the interface returns to its default state, where it
expects a write operation to the communications register.
DIN
In situations where interface synchronization is lost, a write
operation of at least 64 serial clock cycles with DIN high returns
the ADC to its default state by resetting the entire device, including
the register contents. Alternatively, if CS is used with the digital
interface, returning CS high resets the digital interface to its
default state and aborts any current operation.
13048-070
SCLK
Figure 66. Writing to a Register (8-Bit Command with Register Address
Followed by Data of 8 Bits, 16 Bits, or 24 Bits; Data Length Is Dependent on
the Register Selected)
Figure 66 and Figure 67 illustrate writing to and reading from a
register by first writing the 8-bit command to the communications
register followed by the data for the addressed register.
8-BIT COMMAND
8 BITS, 16 BITS,
24 BITS, OR
32 BITS OUTPUT
CS
Reading the ID register is the recommended method for verifying
correct communication with the device. The ID register is a read
only register and contains the value of 0x14 for the AD7124-8
and 0x16 for the AD7124-8 B grade. The communication register
and ID register details are described in Table 38 and Table 39.
CMD
DIN
DOUT/RDY
DATA
13048-071
SCLK
Figure 67. Reading from a Register (8-Bit Command with Register Address
Followed by Data of 8 Bits, 16 Bits, 24 Bits, or 32 Bits; Data Length on DOUT Is
Dependent on the Register Selected, CRC Enabled)
Table 38. Communications Register
Reg.
0x00
Name
COMMS
Bits
[7:0]
Bit 7
WEN
Bit 6
R/W
Bit 5
Bit 4
Bit 3
Bit 2
RS[5:0]
Bits
[7:0]
Bit 7
Bit 6
Bit 5
DEVICE_ID
Bit 4
Bit 3
Bit 1
Bit 0
Reset
0x00
RW
W
Bit 0
Reset
0x14/
0x16
RW
R
Table 39. ID Register
Reg.
0x05
Name
ID
Rev. E | Page 39 of 94
Bit 2
Bit 1
SILICON_REVISION
AD7124-8
Data Sheet
CONFIGURATION OVERVIEW
Channel Configuration
After power-on or reset, the AD7124-8 default configuration is
as follows:
The AD7124-8 has 16 independent analog input channels and
eight independent setups. The user can select any of the analog
input pairs on any channel, as well as any of the eight setups for
any channel, giving the user full flexibility in the channel configuration. This also allows per channel configuration when using all
differential inputs because each channel can have its own
dedicated setup.
•
•
•
Channel: Channel 0 is enabled, AIN0 is selected as the
positive input, and AIN1 is selected as the negative input.
Setup 0 is selected.
Setup: the input and reference buffers are disabled, the gain
is set to 1, and the external reference is selected.
ADC control: the AD7124-8 is in low power mode,
continuous conversion mode and the internal oscillator is
enabled and selected as the master clock source.
Diagnostics: the only diagnostic enabled is the
SPI_IGNORE_ERR function.
Note that only a few of the register setting options are shown;
this list is just an example. For full register information, see the
On-Chip Registers section.
Figure 68 shows an overview of the suggested flow for changing
the ADC configuration, divided into the following three blocks:
•
•
•
•
Channel configuration (see Box A in Figure 68)
Setup (see Box B in Figure 68)
Diagnostics (see Box C in Figure 68)
ADC control (see Box D in Figure 68)
Along with the analog inputs, signals such as the power supply
or reference can also be used as inputs; they are routed to the
multiplexer internally when selected. The AD7124-8 allows the
user to define 16 configurations, or channels, to the ADC. This
allows diagnostics to be interleaved with conversions.
Channel Registers
Use the channel registers to select which input pins are either the
positive analog input or the negative analog input for that
channel. This register also contains a channel enable/disable bit
and the setup selection bits, which are used to select which of
the eight available setups to use for this channel.
When the AD7124-8 is operating with more than one channel
enabled, the channel sequencer cycles through the enabled
channels in sequential order, from Channel 0 to Channel 15. If a
channel is disabled, it is skipped by the sequencer. Details of the
channel register for Channel 0 are shown in Table 40.
A
CHANNEL CONFIGURATION
SELECT POSITIVE AND NEGATIVE INPUT FOR EACH ADC CHANNE L
SELECT ONE OF 8 SETUPS FOR ADC CHANNE L
B
SETUP
8 POSSIBLE ADC SETUPS
SELECT FILTER, OUTPUT DATA RATE, GAIN AND MORE
C
DIAGNOSTICS
ENABLE CRC, SPI READ AND WRITE CHECKS
ENABLE LDO CHECKS, AND MORE
D
ADC CONTROL
SELECT ADC OPERATING MODE, CLOCK SOURCE,
SELECT POWER MODE, DATA + STATUS, AND MORE
13048-072
•
Figure 68. Suggested ADC Configuration Flow
Table 40. Channel 0 Register
Reg. Name
Bits Bit 7
0x09 CHANNEL_0 [15:8] Enable
[7:0]
Bit 6
Bit 5
Setup
Bit 4
Bit 3
Bit 2
0
AINP[2:0]
AINM[4:0]
Rev. E | Page 40 of 94
Bit 1
Bit 0
AINP[4:3]
Reset RW
0x8001 RW
Data Sheet
AD7124-8
ADC Setups
bipolar mode, the ADC accepts negative differential input voltages,
and the output coding is offset binary. In unipolar mode, the ADC
accepts only positive differential voltages, and the coding is straight
binary. In either case, the input voltage must be within the AVDD
and AVSS supply voltages. The user can also select the reference
source using these registers. Four options are available: an
internal 2.5 V reference, an external reference connected
between REFIN1(+) and REFIN1(−), an external reference
connected between REFIN2(+) and REFIN2(−), or AVDD to AVSS.
The PGA gain is also set; gains of 1, 2, 4, 8, 16, 32, 64, and 128
are provided. The analog input buffers and reference input
buffers for the setup can also be enabled using this register.
The AD7124-8 has eight independent setups. Each setup
consists of the following four registers:
•
•
•
•
Configuration register
Filter register
Offset register
Gain register
For example, Setup 0 consists of Configuration Register 0, Filter
Register 0, Offset Register 0, and Gain Register 0. Figure 69
shows the grouping of these registers. The setup is selectable
from the channel registers detailed in the Channel Configuration
section. This allows each channel to be assigned to one of eight
separate setups. Table 41 through Table 44 show the four
registers that are associated with Setup 0. This structure is
repeated for Setup 1 to Setup 7.
Filter Registers
The filter registers select which digital filter is used at the output
of the ADC modulator. The filter type and the output data rate
are selected by setting the bits in this register. For more information,
see the Digital Filter section.
Configuration Registers
The configuration registers allow the user to select the output
coding of the ADC by selecting between bipolar and unipolar. In
FILTER
REGISTERS
CONFIGURATION
REGISTERS
GAIN
REGISTERS
OFFSET
REGISTERS
OFFSET_0 0x29
CONFIG_0
0x19
FILTER_0 0x21
GAIN_0
0x31
CONFIG_1
0x1A
FILTER_1 0x22
GAIN_1
0x32
OFFSET_1 0x2A
CONFIG_2
0x1B
FILTER_2 0x23
GAIN_2
0x33
OFFSET_2 0x2B
CONFIG_3
0x1C
FILTER_3 0x24
GAIN_3
0x34
OFFSET_3 0x2C
GAIN_4
0x1D
FILTER_4 0x25
0x35
OFFSET_4 0x2D
CONFIG_5
0x1E
FILTER_5 0x26
GAIN_5
0x36
OFFSET_5 0x2E
CONFIG_6
0x1F
FILTER_6 0x27
GAIN_6
0x37
OFFSET_6 0x2F
0x20
FILTER_7 0x28
GAIN_7
0x38
OFFSET_7 0x30
CONFIG_7
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
ANALOG INPUT BUFFERS
REFERENCE BUFFERS
BURNOUT
REFERENCE SOURCE
GAIN
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
GAIN CORRECTION
OPTIONALLY
PROGRAMMED
PER SETUP AS REQUIRED
OFFSET CORRECTION
OPTIONALLY PROGRAMMED
PER SETUP AS REQUIRED
SINC4
SINC3
SINC4 + SINC1
SINC3 + SINC1
ENHANCED 50Hz/60Hz REJECTION
13048-073
CONFIG_4
Figure 69. ADC Setup Register Grouping
Table 41. Configuration 0 Register
Reg.
0x19
Name
CONFIG_0
Bits
Bit 7
[15:8]
[7:0] REF_BUFM
Bit 6
Bit 5
Bit 4
0
AIN_BUFP
AIN_BUFM
Bit 3
Bipolar
REF_SEL
Bit 2
Bit 1
Burnout
PGA
Bit 0
REF_BUFP
Reset
0x0860
RW
RW
Table 42. Filter 0 Register
Reg.
0x28
Name
FILTER_0
Bits
Bit 7
[23:9]
[15:8]
[7:0]
Bit 6
Filter
Bit 5
Bit 4
REJ60
Bit 3
0
Bit 2
Bit 1
Bit 0
Reset
RW
POST_FILTER
SINGLE_CYCLE 0x060180 RW
FS[10:8]
FS[7:0]
Table 43. Offset 0 Register
Reg.
0x29
Name
OFFSET_0
Bits
[23:0]
Bits[23:0]
Offset[23:0]
Reset
RW
0x800000 RW
Bits[23:0]
Gain[23:0]
Reset
RW
0x5XXXXX RW
Table 44. Gain 0 Register
Reg.
0x31
Name
GAIN_0
Bits
[23:0]
Rev. E | Page 41 of 94
AD7124-8
Data Sheet
Offset Registers
When a diagnostic is enabled, the corresponding flag is contained
in the error register. All enabled flags are OR’ed to control the
ERR flag in the status register. Thus, if an error occurs (for example,
the SPI CRC check detects an error), the relevant flag (for example,
the SPI_CRC_ERR flag) in the error register is set. The ERR flag
in the status register is also set. This is useful when the status bits
are appended to conversions. The ERR bit indicates if an error has
occurred. The user can then read the error register for more
details on the error source.
The offset registers hold the offset calibration coefficient for the
ADC. The power-on reset value of an offset register is 0x800000.
The offset registers are 24-bit read/write registers. The poweron reset value is automatically overwritten if an internal or
system zero-scale calibration is initiated by the user or if the offset
registers are written to by the user.
Gain Registers
The gain registers are 24-bit registers that hold the gain
calibration coefficient for the ADC. The gain registers are
read/write registers. The gain is factory calibrated at a gain of 1;
thus, the default value varies from device to device. The default
value is automatically overwritten if an internal or system fullscale calibration is initiated by the user. For more information
on calibration, see the Calibration section.
The frequency of the on-chip oscillator can also be monitored
on the AD7124-8. The MCLK_COUNT register monitors the
master clock pulses. Table 45 to Table 47 give more detail on the
diagnostic registers. See the Diagnostics section for more detail
on the diagnostics available.
ADC Control Register
The ADC control register configures the core peripherals for use
by the AD7124-8 and the mode for the digital interface. The
power mode (full power, mid power, or low power) is selected
via this register. Also, the mode of operation is selected, for example,
continuous conversion or single conversion. The user can also
select the standby and power-down modes, as well as any of the
calibration modes. In addition, this register contains the clock
source select bits and the internal reference enable bits. The
reference select bits are contained in the setup configuration
registers (see the ADC Setups section for more information).
Diagnostics
The ERROR_EN register enables and disables the numerous
diagnostics on the AD7124-8. By default, the SPI_IGNORE
function is enabled, which indicates inappropriate times to
write to the ADC (for example, during power-up and during a
reset). Other diagnostics include
•
•
•
•
•
SPI read and write checks, which ensure that only valid
registers are accessed
SCLK counter, which ensures that the correct number of
SCLK pulses are used
SPI CRC
Memory map CRC
LDO checks
The digital interface operation is also selected via the ADC
control register. This register allows the user to enable the data
plus status read and continuous read mode. For more details, see
the Digital Interface section. The details of this register are
shown in Table 48.
Table 45. Error Register
Reg.
0x06
Name
Error
Bits
[23:16]
Bit 7
[15:8]
AINP_OV_
ERR
ALDO_PSM_
ERR
[7:0]
Bit 6
Bit 5
Bit 4
Bit 3
LDO_CAP_ERR
Bit 2
ADC_CAL_ERR
AINM_OV_
ERR
SPI_SCLK_
CNT_ERR
AINM_UV_
ERR
SPI_READ_
ERR
REF_DET_ERR
0
SPI_WRITE_
ERR
SPI_CRC_ERR
0
AINP_UV_
ERR
SPI_IGNORE_
ERR
Bit 1
ADC_CONV_
ERR
DLDO_PSM_
ERR
MM_CRC_
ERR
Bit 0
ADC_SAT_
ERR
0
Bit 1
ADC_CONV_
ERR_EN
DLDO_PSM_
ERR_EN
MM_CRC_
ERR_EN
Bit 0
ADC_SAT_
ERR_EN
ALDO_PSM_
TRIP_TEST_EN
ROM_CRC_
ERR_EN
Reset
0x000000
RW
R
ROM_CRC_
ERR
Table 46. Error Enable Register
Reg.
0x07
Name
ERROR_EN
Bits
[23:16]
Bit 7
0
[15:8]
AINP_OV_
ERR_EN
ALDO_PSM_
ERR_EN
[7:0]
Bit 6
MCLK_CNT_
EN
AINP_UV_
ERR_EN
SPI_IGNORE_
ERR_EN
Bit 5
LDO_CAP_
CHK_TEST_EN
AINM_OV_
ERR_EN
SPI_SCLK_
CNT_ERR_EN
Bit 4
Bit 3
LDO_CAP_CHK
AINM_UV_
ERR_EN
SPI_READ_
ERR_EN
Bit 5
Bit 4
REF_DET_
ERR_EN
SPI_WRITE_
ERR_EN
Bit 2
ADC_CAL_
ERR_EN
DLDO_PSM_
TRIP_TEST_EN
SPI_CRC_
ERR_EN
Reset
0x000040
RW
RW
Reset
0x00
RW
R
Reset
0x0000
RW
RW
Table 47. MCLK Count Register
Reg.
0x08
Name
MCLK_COUNT
Bits
[7:0]
Bit 7
Bit 6
Bit 3
MCLK_COUNT
Bit 2
Bit 1
Bit 0
Table 48. ADC Control Register
Reg.
0x01
Name
ADC_CONTROL
Bits
[15:8]
[7:0]
Bit 7
Bit 6
0
POWER_MORE
Bit 5
Bit 4
Bit 3
CONT_READ
DOUT_RDY_DEL
Mode
Rev. E | Page 42 of 94
Bit 2
DATA_STATUS
Bit 1
CS_EN
Bit 0
REF_EN
CLK_SEL
Data Sheet
AD7124-8
Understanding Configuration Flexibility
In Figure 70, Figure 71, and Figure 72, the registers shown in
black font are programmed for this configuration. The registers
shown in gray font are redundant.
The most straightforward implementation of the AD7124-8 is
to use differential inputs with adjacent analog inputs and run all
of them with the same setup, gain correction, and offset correction
register. For example, the user requires four differential inputs.
In this case, the user selects the following differential inputs: AIN0/
AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7.
Programming the gain and offset registers is optional for any
use case, as indicated by the dashed lines between the register
blocks. If an internal or system offset or full-scale calibration is
performed, the gain and offset registers for the selected channel
are automatically updated.
An alternative way to implement these four fully differential inputs
is by taking advantage of the eight available setups. Motivation for
this includes having a different speed, noise, or gain requirement on
some of the four differential inputs vs. other inputs, or there may be
a specific offset or gain correction for particular channels. Figure 71
shows how each of the differential inputs can use a separate setup,
allowing full flexibility in the configuration of each channel.
CHANNEL
REGISTERS
CH0 0x09
AIN1
CH1 0x0A
AIN2
CH2 0x0B
AIN3
CH3 0x0C
AIN4
CH4 0x0D
AIN5
CH5 0x0E
AIN6
CH6 0x0F
AIN7
CH7 0x10
CH8 0x11
CH9 0x12
CH10 0x13
CH11 0x14
CH12 0x15
CH13 0x16
CONFIGURATION
REGISTERS
FILTER
REGISTERS
CONFIG_0 0x19
SELECT ANALOG INPUT PARTS
ENABLE THE CHANNEL
SELECT SETUP 0
FILTER_0 0x21
GAIN_0
0x31
OFFSET_0 0x29
OFFSET_1 0x2A
0x1A
FILTER_1 0x22
GAIN_1
0x32
CONFIG_2 0x1B
FILTER_2 0x23
GAIN_2
0x33
OFFSET_2 0x2B
CONFIG_3 0x1C
FILTER_3 0x24
GAIN_3
0x34
OFFSET_3 0x2C
CONFIG_4 0x1D
FILTER_4 0x25
GAIN_4
0x35
OFFSET_4 0x2D
CONFIG_5 0x1E
FILTER_5 0x26
GAIN_5
0x36
OFFSET_5 0x2E
CONFIG_6 0x1F
FILTER_6 0x27
GAIN_6
0x37
OFFSET_6 0x2F
CONFIG_7 0x20
FILTER_7 0x28
GAIN_7
0x38
OFFSET_7 0x30
CONFIG_1
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
CH14 0x17
CH15 0x18
OFFSET
REGISTERS
GAIN
REGISTERS
ANALOG INPUT BUFFERS
REFERENCE BUFFERS
BURNOUT
REFERENCE SOURCE
GAIN
OFFSET CORRECTION
GAIN CORRECTION
OPTIONALLY
OPTIONALLY PROGRAMMED
PROGRAMMED
PER SETUP AS REQUIRED
PER SETUP AS REQUIRED
SINC4
SINC3
SINC4 + SINC1
13048-074
AIN0
SINC3 + SINC1
ENHANCED 50Hz/60Hz REJECTION
Figure 70. Four Fully Differential Inputs, All Using a Single Setup (CONFIG_0, FILTER_0, GAIN_0, OFFSET_0)
CHANNEL
REGISTERS
AIN0
CH0
AIN1
CH1 0x0A
AIN2
CH2 0x0B
AIN3
CH3 0x0C
AIN4
CH4 0x0D
AIN5
CH5 0x0E
AIN7
CH6 0x0F
CH7
CH8
CH9
0x10
0x11
0x12
CH10 0x13
CH11 0x14
CH12 0x15
CH13 0x16
CONFIGURATION
REGISTERS
FILTER
REGISTERS
SELECT ANALOG INPUT PARTS
ENABLE THE CHANNEL
SELECT SETUP
OFFSET
REGISTERS
CONFIG_0 0x19
FILTER_0 0x21
GAIN_0
0x31
OFFSET_0 0x29
CONFIG_1
0x1A
FILTER_1 0x22
GAIN_1
0x32
OFFSET_1 0x2A
CONFIG_2 0x1B
FILTER_2 0x23
GAIN_2
0x33
OFFSET_2 0x2B
CONFIG_3 0x1C
FILTER_3 0x24
GAIN_3
0x34
OFFSET_3 0x2C
CONFIG_4 0x1D
FILTER_4 0x25
GAIN_4
0x35
OFFSET_4 0x2D
CONFIG_5 0x1E
FILTER_5 0x26
GAIN_5
0x36
OFFSET_5 0x2E
CONFIG_6 0x1F
FILTER_6 0x27
GAIN_6
0x37
OFFSET_6 0x2F
CONFIG_7 0x20
FILTER_7 0x28
GAIN_7
0x38
OFFSET_7 0x30
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
CH14 0x17
CH15 0x18
GAIN
REGISTERS
ANALOG INPUT BUFFERS
REFERENCE BUFFERS
BURNOUT
REFERENCE SOURCE
GAIN
GAIN CORRECTION
OFFSET CORRECTION
OPTIONALLY
OPTIONALLY PROGRAMMED
PROGRAMMED
PER SETUP AS REQUIRED
PER SETUP AS REQUIRED
SINC4
SINC3
SINC4 + SINC1
SINC3 + SINC1
ENHANCED 50Hz/60Hz REJECTION
Figure 71. Four Fully Differential Inputs with a Separate Setup per Channel
Rev. E | Page 43 of 94
13048-075
AIN6
0x09
AD7124-8
Data Sheet
Figure 72 shows an example of how the channel registers span
between the analog input pins and the setup configurations
downstream. In this random example, two differential inputs and
two single-ended inputs are required. The single-ended inputs are
the AIN0/AIN7 and AIN6/AIN7 combinations. The first differential input pair (AIN0/AIN1) uses Setup 0. The two single-ended
input pairs (AIN0/AIN7 and AIN6/AIN7) are set up as diagnostics;
therefore, they use a separate setup (Setup 1). The final differential
input (AIN2/AIN3) also uses a separate setup: Setup 2.
Given that three setups are selected for use, the CONFIG_0,
CONFIG_1, and CONFIG_2 registers are programmed as
required, and the FILTER_0, FILTER_1, and FILTER_2 registers
are also programmed as required. Optional gain and offset
correction can be employed on a per setup basis by
programming the GAIN_0, GAIN_1, and GAIN_2 registers
and the OFFSET_0, OFFSET_1, and OFFSET_2 registers.
In the example shown in Figure 72, the CHANNEL_0 to
CHANNEL_3 registers are used. Setting the MSB (the enable
bit) in each of these registers enables the four combinations via
the crosspoint multiplexer. When the AD7124-8 converts, the
sequencer transitions in ascending sequential order from
CHANNEL_0 to CHANNEL_1 to CHANNEL_2, and then on
to CHANNEL_3 before looping back to CHANNEL_0 to repeat
the sequence.
CHANNEL
REGISTERS
CHANNEL_0 0x09
AIN1
CHANNEL_1 0x0A
AIN2
CHANNEL_2 0x0B
AIN3
CHANNEL_3 0x0C
AIN4
CHANNEL_4 0x0D
AIN5
CHANNEL_5 0x0E
AIN6
AIN7
CHANNEL_6 0x0F
CHANNEL_7 0x10
CHANNEL_8 0x11
CHANNEL_9 0x12
CHANNEL_10 0x13
CHANNEL_11 0x14
CHANNEL_12 0x15
CHANNEL_13 0x16
FILTER
REGISTERS
CONFIGURATION
REGISTERS
SELECT ANALOG INPUT PARTS
ENABLE THE CHANNEL
SELECT SETUP
0x19
FILTER_0 0x21
GAIN_0
0x31
OFFSET_0 0x29
CONFIG_1
0x1A
FILTER_1 0x22
GAIN_1
0x32
OFFSET_1 0x2A
CONFIG_2
0x1B
FILTER_2 0x23
GAIN_2
0x33
OFFSET_2 0x2B
CONFIG_3
0x1C
FILTER_3 0x24
GAIN_3
0x34
OFFSET_3 0x2C
CONFIG_4
0x1D
FILTER_4 0x25
GAIN_4
0x35
OFFSET_4 0x2D
CONFIG_5
0x1E
FILTER_5 0x26
GAIN_5
0x36
OFFSET_5 0x2E
CONFIG_6
0x1F
FILTER_6 0x27
GAIN_6
0x37
OFFSET_6 0x2F
CONFIG_7
0x20
FILTER_7 0x28
GAIN_7
0x38
OFFSET_7 0x30
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
ANALOG INPUT BUFFERS
REFERENCE BUFFERS
BURNOUT
REFERENCE SOURCE
GAIN
OFFSET
REGISTERS
CONFIG_0
CHANNEL_14 0x17
CHANNEL_15 0x18
GAIN
REGISTERS
GAIN CORRECTION
OFFSET CORRECTION
OPTIONALLY
OPTIONALLY PROGRAMMED
PROGRAMMED
PER SETUP AS REQUIRED
PER SETUP AS REQUIRED
SINC4
SINC3
SINC4 + SINC1
SINC3 + SINC1
ENHANCED 50Hz/60Hz REJECTION
Figure 72. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups
Rev. E | Page 44 of 94
13048-076
AIN0
Data Sheet
AD7124-8
ADC CIRCUIT INFORMATION
ANALOG INPUT CHANNEL
The channels are configured using the AINP[4:0] bits and the
AINM[4:0] bits in the channel registers (see Table 49). The device
can be configured to have 8 differential inputs, 15 pseudo differential inputs, or a combination of both. When using differential
inputs, use adjacent analog input pins to form the input pair. Using
adjacent pins minimizes any mismatch between the channels.
The AD7124-8 uses flexible multiplexing; thus, any of the analog
input pins, AIN0 to AIN15, can be selected as a positive input
or a negative input. This feature allows the user to perform
diagnostics such as checking that pins are connected. It also
simplifies printed circuit board (PCB) design. For example,
the same PCB can accommodate 2-wire, 3-wire, and 4-wire
resistance temperature detectors (RTDs).
The inputs can be buffered or unbuffered at a gain of 1 but are
automatically buffered when the gain exceeds 1. The AINP and
AINM buffers are enabled/disabled separately using the AIN_BUFP
and AIN_BUFM bits in the configuration register (see Table 50).
In buffered mode, the input channel feeds into a high impedance
input stage of the buffer amplifier. Therefore, the input can tolerate
significant source impedances and is tailored for direct connection
to external resistive type sensors such as strain gages or RTDs.
AVDD
AIN0
AVSS
AVDD
When the device is operated in unbuffered mode, the device has
a higher analog input current. Note that this unbuffered input
path provides a dynamic load to the driving source. Therefore,
resistor/capacitor (RC) combinations on the input pins can
cause gain errors, depending on the output impedance of the
source that is driving the ADC input.
AVDD
AIN1
BURNOUT
CURRENTS
AVSS
PGA
TO ADC
AVDD
The absolute input voltage in unbuffered mode (gain = 1)
includes the range between AVSS − 50 mV and AVDD + 50 mV.
The absolute input voltage range in buffered mode at a gain of 1 is
restricted to a range between AVSS + 100 mV and AVDD − 100 mV.
The common-mode voltage must not exceed these limits;
otherwise, linearity and noise performance degrade.
AIN14
AVSS
AVSS
AVDD
When the gain is greater than 1, the analog input buffers are
automatically enabled. The PGA placed in front of the input
buffers is rail-to-rail; thus, in this case, the absolute input voltage
includes the range from AVSS − 50 mV to AVDD + 50 mV.
13048-077
AIN15
AVSS
Figure 73. Analog Input Multiplexer Circuit
Table 49. Channel Register
Reg.
0x09 to
0x18
Name
Bits
CHANNEL_0 to [15:8]
CHANNEL_15 [7:0]
Bit 7
Enable
Bit 6
Bit 5
Setup
Bit 4
Bit 3
Bit 2
Bit 1
0
AINP[2:0]
Bit 0
AINP[4:3]
Reset
0x8001
RW
RW
Reset
0x0860
RW
RW
AINM[4:0]
Table 50. Configuration Register
Reg.
0x19 to
0x20
Name
CONFIG_0 to
CONFIG_7
Bits
[15:8]
[7:0]
Bit 7
Bit 6
REF_BUFM
AIN_BUFP
Bit 5
0
AIN_BUFM
Bit 4
Bit 3
Bipolar
REF_SEL
Rev. E | Page 45 of 94
Bit 2
Bit 1
Burnout
Bit 0
REF_BUFP
PGA
AD7124-8
Data Sheet
EXTERNAL IMPEDANCE WHEN USING A GAIN OF 1
6000
When a gain of 1 is used, the PGA is powered down, reducing
the current consumption. A capacitive network is included at
the PGA output for electromagnetic compatibility (EMC)
purposes. For a gain of 1, this capacitive network is connected
directly to the analog input pins as the PGA is bypassed (see
Figure 76). A precharge buffer is included on the AD7124-8
B grade to charge this capacitive network quickly when switching
channels. The precharge buffer ensures that the analog input is
settled when sampled by the ADC.
RC: 100Ω RESISTOR
1µF CAPICITOR
0.01µF CAPACITOR TO GND
RC: 100Ω RESISTOR
0.1µF CAPICITOR
0.01µF CAPICITOR TO GND
RC: 100Ω RESISTOR
0.01µF CAPICITOR
0.01µF CAPICITOR TO GND
5000
ERROR (µV)
4000
3000
2000
1000
1
10
100
1000
10000
13048-175
–1000
10000
13048-176
0
When using the AD7124-8, which does not include the
precharge buffer, using large external loads at a gain of 1 in
multiplexed applications affects the settling time. Large external
loads affect the initial error on the gain of 1 channel. The
external RC antialiasing filter determines the recovery time of
the channel. When the gain of 1 channel is selected, the
maximum possible error (initial error) is
SETTLED OUTPUT DATA RATE (sps)
Figure 74. Error vs. Settled Output Data Rate
(100 kΩ Resistors in Attenuator Circuit)
7000
RC: 1kΩ RESISTOR
0.01µF CAPICITOR
0.01µF CAPACITOR TO GND
RC: 1kΩ RESISTOR
0.01µF CAPICITOR
NO CAPICITOR TO GND
6000
VERROR = CPAR × (VIN_PREV_CH × GAIN_PREV_CH − VIN) ÷
(CPAR + CFILT)
(1)
5000
4000
ERROR (µV)
where:
CPAR is the internal capacitance (63 pF due to 10 pF/25 pF
network plus 3 pF of parasitic capacitance).
CFILT is the external filter capacitance on the gain of 1 channel.
VIN_PREV_CH is the input voltage of the previous selected channel.
GAIN_PREV_CH is the gain of the previous selected channel.
3000
2000
1000
0
If a fast output data rate is selected, the error in the conversion
has a magnitude comparable with Equation 1. For slower output
data rates, the error is reduced as the ADC takes more time to
process the analog input, which allows the front end to settle.
The settling time is dependent on the time constant of the
external antialiasing filter.
–1000
1
10
100
1000
SETTLED OUTPUT DATA RATE (sps)
Figure 75. Error vs. Settled Output Data Rate (47 kΩ Resistors in Attenuator Circuit)
Figure 74 and Figure 75 show that, at low output data rates, the
ADC allows sufficient time for the gain of 1 channel to settle for
any external load resistance and RC filter values. At intermediate
output data rates, reducing the values of the external RC components reduces the time constant of the external filter so that the
analog input can settle within the allowed time. For high output
data rates, the settling time allowed by the ADC is short; therefore,
a large capacitor from AINP to AINM minimizes the error.
Figure 74 and Figure 75 show the error for different RC filter
combinations on the gain of 1 channel when a resistor
attenuator is connected to the analog input and the ADC is
multiplexed.
For gains > 1, the PGA is used, which isolates the internal
capacitive network from the analog input pins. Therefore, for
gains > 1, there are no restrictions on the external circuitry.
RC ANTIALIASING
FILTER
AVSS
AVSS
MUX
PGA2
ADC
25pF
AINM
AVSS
AD7124-8
10pF
AINP
AVSS
BUFFER
10pF
AVSS
Figure 76. Input Schematic
Rev. E | Page 46 of 94
BUFFER
13048-078
ATTENUATOR
CIRCUIT
Data Sheet
AD7124-8
PROGRAMMABLE GAIN ARRAY (PGA)
X-MUX
When the gain stage is enabled, the output from the multiplexer
is applied to the input of the PGA. The presence of the PGA means
that signals of small amplitude can be gained within the
AD7124-8 and still maintain excellent noise performance.
BUF
PGA1
24-BIT
Σ-Δ ADC
PGA2
13048-080
BUF
ANALOG
BUFFERS
Figure 77. PGA
The AD7124-8 can be programmed to have a gain of 1, 2, 4, 8,
16, 32, 64, or 128 by using the PGA bits in the configuration
register (see Table 50). The PGA consists of two stages. For a
gain of 1, both stages are bypassed. For gains of 2 to 8, a single
stage is used, whereas for gains greater than 8, both stages are used.
The analog input range is ±VREF/gain. Therefore, with an external
2.5 V reference, the unipolar ranges are from 0 mV to 19.53 mV
to 0 V to 2.5 V, and the bipolar ranges are from ±19.53 mV to
±2.5 V. For high reference values, for example, VREF = AVDD, the
analog input range must be limited. Consult the Specifications
section for more details on these limits.
REFERENCE
The AD7124-8 has an embedded 2.5 V reference. The embedded
reference is a low noise, low drift reference with 15 ppm/°C drift
maximum on the AD7124-8 and 10 ppm/°C drift maximum on
the AD7124-8 B grade. Including the reference on the AD7124-8
reduces the number of external components needed in applications
such as thermocouples, leading to a reduced PCB size.
The common-mode range for the differential reference inputs is
from AVSS − 50 mV to AVDD + 50 mV when the reference buffers
are disabled. The reference inputs can also be buffered on-chip.
The buffers require 100 mV of headroom. The reference voltage
of REFIN (REFINx(+) − REFINx(−)) is 2.5 V nominal, but the
AD7124-8 is functional with reference voltages from 0.5 V to
AVDD.
In applications where the excitation (voltage or current) for the
transducer on the analog input also drives the reference voltage
for the devices, the effect of the low frequency noise in the excitation source is removed, because the application is ratiometric. If
the AD7124-8 is used in nonratiometric applications, use a low
noise reference.
The recommended 2.5 V reference voltage sources for the AD7124-8
include the ADR4525, which is a low noise, low power reference.
Note that the reference input provides a high impedance, dynamic
load when unbuffered. Because the input impedance of each
reference input is dynamic, resistor/capacitor combinations on
these inputs can cause dc gain errors if the reference inputs are
unbuffered, depending on the output impedance of the source
driving the reference inputs.
Reference voltage sources typically have low output impedances
and are, therefore, tolerant to having decoupling capacitors on
REFINx(+) without introducing gain errors in the system. Deriving
the reference input voltage across an external resistor means that
the reference input sees a significant external source impedance.
In this situation, using the reference buffers is required.
3V
ADR4525
4.7µF
0.1µF
2.5V REF
REFINx(+)
1µF
4.7µF
REFINx(–)
REFIN1(–)
13048-082
REFIN1(+)
pin. A 0.1 µF decoupling capacitor is required on REFOUT
when the internal reference is active.
REFOUT
BAND GAP
REF
AVDD
AVSS
AVSS
REFIN2(+)
REFIN2(–)
Figure 79. ADR4525 to AD7124-8 Connections
BIPOLAR/UNIPOLAR CONFIGURATION
24-BIT
Σ-Δ ADC
13048-081
REFERENCE
BUFFERS
Figure 78. Reference Connections
This reference can be used to supply the ADC (by setting the
REF_EN bit in the ADC_CONTROL register to 1) or an external
reference can be applied. For external references, the ADC has a
fully differential input capability for the channel. In addition,
the user can select one of two external reference options (REFIN1
or REFIN2). The reference source for the AD7124-8 is selected
using the REF_SEL bits in the configuration register (see Table 50).
When the internal reference is selected, it is internally connected
to the modulator. It can also be made available on the REFOUT
The analog input to the AD7124-8 can accept either unipolar or
bipolar input voltage ranges, which allows the user to tune the
ADC input range to the sensor output range. When a split
power supply is used, the device accepts truly bipolar inputs.
When a single power supply is used, a bipolar input range does
not imply that the device can tolerate negative voltages with
respect to system AVSS. Unipolar and bipolar signals on the
AINP input are referenced to the voltage on the AINM input.
For example, if AINM is 1.5 V and the ADC is configured for
unipolar mode with a gain of 1, the input voltage range on the
AINP input is 1.5 V to 3 V when VREF = AVDD = 3 V. If the ADC
is configured for bipolar mode, the analog input range on the
AINP input is 0 V to AVDD. The bipolar/unipolar option is chosen
by programming the bipolar bit in the configuration register.
Rev. E | Page 47 of 94
AD7124-8
Data Sheet
DATA OUTPUT CODING
IOUT0 IOUT1
VBIAS
When the ADC is configured for unipolar operation, the output
code is natural (straight) binary with a zero differential input
voltage resulting in a code of 00 … 00, a midscale voltage resulting
in a code of 100 … 000, and a full-scale input voltage resulting
in a code of 111 … 111. The output code for any analog input
voltage can be represented as
AVDD
AIN0
AVSS
VBIAS
Code = (2 × AIN × Gain)/VREF
N
AVDD
When the ADC is configured for bipolar operation, the output
code is offset binary with a negative full-scale voltage resulting
in a code of 000 … 000, a zero differential input voltage resulting
in a code of 100 … 000, and a positive full-scale input voltage
resulting in a code of 111 … 111. The output code for any
analog input voltage can be represented as
AVDD
AIN1
BURNOUT
CURRENTS
AVSS
PGA
Code = 2N − 1 × [(AIN × Gain/VREF) + 1]
TO ADC
AVSS
where:
N = 24.
AIN is the analog input voltage.
Gain is the gain setting (1 to 128).
VBIAS
AVDD
13048-083
AIN15
EXCITATION CURRENTS
AVSS
The AD7124-8 also contains two matched, software configurable,
constant current sources that can be programmed to equal 50 µA,
100 µA, 250 µA, 500 µA, 750 µA, or 1 mA. These current sources
can be used to excite external resistive bridges or RTD sensors.
Both current sources source currents from AVDD and can be
directed to any of the analog input pins (see Figure 80).
Figure 80. Excitation Current and Bias Voltage Connections
BRIDGE POWER-DOWN SWITCH
The pins on which the currents are made available are programmed
using the IOUT1_CH and IOUT0_CH bits in the IO_CONTROL_1
register (see Table 51). The magnitude of each current source is
individually programmable using the IOUT1 and IOUT0 bits in
the IO_CONTROL_1 register. In addition, both currents can be
output to the same analog input pin.
Note that the on-chip reference does not need to be enabled
when using the excitation currents.
In bridge applications such as strain gages and load cells, the
bridge itself consumes the majority of the current in the system.
For example, a 350 Ω load cell requires 8.6 mA of current when
excited with a 3 V supply. To minimize the current consumption of
the system, the bridge can be disconnected (when it is not being
used) using the bridge power-down switch. The switch can withstand 30 mA of continuous current, and it has an on resistance
of 10 Ω maximum. The PDSW bit in the IO_CONTROL_1
register controls the switch.
LOGIC OUTPUTS
The AD7124-8 has four general-purpose digital outputs: P1
to P4. These are enabled using the GPIO_CTRL bits in the
IO_CONTROL_1 register (see Table 51). The pins can be
pulled high or low using the GPIO_DATx bits in the register;
that is, the value at the pin is determined by the setting of the
GPIO_DATx bits. The logic levels for these pins are determined
by AVDD rather than by IOVDD. When the IO_CONTROL_1
register is read, the GPIO_DATx bits reflect the actual value at
the pins; this is useful for short-circuit detection.
Table 51. Input/Output Control 1 Register
Reg.
0x03
Name
IO_
CONTROL_
1
Bits
[23:16]
[15:8]
[7:0]
Bit 7
GPIO_DAT4
PDSW
Bit 6
Bit 5
GPIO_DAT3
GPIO_DAT2
0
IOUT1_CH
Bit 4
GPIO_DAT1
IOUT1
Bit 3
GPIO_CTRL4
Rev. E | Page 48 of 94
Bit 2
GPIO_CTRL3
Bit 1
GPIO_CTRL2
IOUT0
IOUT0_CH
Bit 0
GPIO_CTRL1
Reset
0x000000
RW
RW
Data Sheet
AD7124-8
the range of output data rates and performance is affected by
the power mode.
These pins can be used to drive external circuitry, for example,
an external multiplexer. If an external multiplexer is used to
increase the channel count, the multiplexer logic pins can be
controlled via the AD7124-8 general-purpose output pins. The
general-purpose output pins can be used to select the active
multiplexer pin. Because the operation of the multiplexer is
independent of the AD7124-8, reset the modulator and filter
using the SYNC pin or by writing to the mode or configuration
register each time that the multiplexer channel is changed.
Table 52. Power Modes
Power
Mode
Full Power
Mid Power
Low Power
1
BIAS VOLTAGE GENERATOR
Master Clock
(kHz)
614.4
153.6
76.8
Output Data
Rate1 (SPS)
9.37 to 19,200
2.34 to 4800
1.17 to 2400
Current
See the
Specifications
section
Unsettled, using a sinc3/sinc4 filter.
STANDBY AND POWER-DOWN MODES
A bias voltage generator is included on the AD7124-8 (see
Figure 80). It biases the negative terminal of the selected input
channel to (AVDD − AVSS)/2. This function is useful in thermocouple applications, as the voltage generated by the thermocouple
must be biased around some dc voltage if the ADC operates from a
single power supply. The bias voltage generator is controlled using
the VBIASx bits in the IO_CONTROL_2 register (see Table 53).
The power-up time of the bias voltage generator is dependent
on the load capacitance. Consult the Specifications section for
more details.
In standby mode, most blocks are powered down. The LDOs
remain active so that registers maintain their contents. If
enabled, the reference, internal oscillator, digital outputs P1 to
P4, the bias voltage generator and the low-side power switch
remain active. On the AD7124-8 B grade, the excitation currents,
if enabled, also remain active in standby mode. The excitation
currents are disabled on the AD7124-8. These blocks can be
disabled, if required, by setting the corresponding bits
appropriately. The reference detection and LDO capacitor
detection functions are disabled in standby mode.
CLOCK
Other diagnostics remain active if enabled when the ADC is in
standby mode. Diagnostics can be enabled or disabled while in
standby mode. However, any diagnostics that require the master
clock (reference detect, undervoltage/overvoltage detection,
LDO trip tests, memory map CRC, and MCLK counter) must
be enabled when the ADC is in continuous conversion mode or
idle mode; these diagnostics do not function if enabled in
standby mode.
The AD7124-8 includes an internal 614.4 kHz clock on chip.
This internal clock has a tolerance of ±5%. Use either the
internal clock or an external clock as the clock source to the
AD7124-8. The clock source is selected using the CLK_SEL bits
in the ADC_CONTROL register (see Table 54).
The internal clock can also be made available at the CLK pin. This
is useful when several ADCs are used in an application and the
devices must be synchronized. The internal clock from one device
can be used as the clock source for all ADCs in the system. Using a
common clock, the devices can be synchronized by applying a
common reset to all devices, or the SYNC pin can be pulsed.
The standby current is typically 15 µA when the LDOs only are
enabled. If functions such as the bias voltage generator remain
active in standby mode, the current increases by 36 µA typically.
If the internal oscillator remains active in standby mode, the
current increases by 22 µA typically. When exiting standby
mode, the AD7124-8 requires 130 MCLK cycles to power up
and settle. The internal oscillator, if disabled in standby mode,
requires an additional 40 µs to power up and settle. If an external
master clock is being used, ensure that it is active before issuing
the command to exit standby mode. Do not write to the ADC_
CONTROL register again until the ADC has powered up and
settled.
POWER MODES
The AD7124-8 has three power modes: full power mode, mid
power mode, and low power mode. The mode is selected using
the POWER_MODE bits in the ADC_CONTROL register. The
power mode affects the power consumption of the device as
well as changing the master clock frequency. A 614.4 kHz clock
is used by the device. However, this clock is internally divided,
the division factor being dependent on the power mode. Thus,
Table 53. Input/Output Control 2 Register
Reg.
0x04
Name
IO_CONTROL_2
Bit 7
VBIAS15
VBIAS7
Bit 6
VBIAS14
VBIAS6
Bit 5
VBIAS13
VBIAS5
Bit 4
VBIAS12
VBIAS4
Bit 3
VBIAS11
VBIAS3
Bit 2
VBIAS10
VBIAS2
Bit 1
VBIAS9
VBIAS1
Bit 0
VBIAS8
VBIAS0
Reset
0x0000
RW
RW
Reset
0x0000
RW
RW
Table 54. ADC Control Register
Reg.
0x01
Name
ADC_CONTROL
Bit 7
Bit 6
0
POWER_MODE
Bit 5
Bit 4
DOUT_
RDY_DEL
Bit 3
CONT_READ
Mode
Rev. E | Page 49 of 94
Bit 2
DATA_STATUS
Bit 1
CS_EN
Bit 0
REF_EN
CLK_SEL
AD7124-8
Data Sheet
In power-down mode, all blocks are powered down, including
the LDOs. All registers lose their contents, and the digital outputs
P1 to P4 are placed in tristate. To prevent accidental entry to
power-down mode, the ADC must first be placed into standby
mode. If an external master clock is being used, keep it active
until the device is placed in power-down mode. Exiting powerdown mode requires 64 SCLK cycles with CS = 0 and DIN = 1,
that is, a serial interface reset. The AD7124-8 requires 2 ms
typically to power up and settle. The POR_FLAG in the status
register can be monitored to determine the end of the power
up/settling period. After this time, the user can access the on-chip
registers. The power-down current is 2 µA typically.
DIGITAL INTERFACE
The programmable functions of the AD7124-8 are controlled
using a set of on-chip registers. Data is written to these registers
via the serial interface. Read access to the on-chip registers is
also provided by this interface. All communications with the
device must start with a write to the communications register.
After power-on or reset, the device expects a write to its
communications register. The data written to this register
determines whether the next operation is a read operation or a
write operation, and determines to which register this read or
write operation occurs. Therefore, write access to any of the
other registers on the devices begins with a write operation to
the communications register, followed by a write to the selected
register. A read operation from any other register (except when
continuous read mode is selected) starts with a write to the
communications register, followed by a read operation from the
selected register.
The serial interface of the AD7124-8 consists of four signals: CS,
DIN, SCLK, and DOUT/RDY. The DIN line transfers data into
the on-chip registers, whereas DOUT/RDY accesses data from
the on-chip registers. SCLK is the serial clock input for the
device, and all data transfers (either on DIN or DOUT/RDY)
occur with respect to the SCLK signal. The DOUT/RDY pin
also operates as a data ready signal; the line goes low when a
new data-word is available in the output register. It is reset high
when a read operation from the data register is complete. It also
goes high before the data register updates to indicate when not
to read from the device, to ensure that a data read is not attempted
while the register is being updated. CS is used to select a device.
It can decode the AD7124-8 in systems where several components
are connected to the serial bus.
Figure 3 and Figure 4 show timing diagrams for interfacing to
the AD7124-8 with CS decoding the devices. Figure 3 shows the
timing for a read operation from the output shift register of the
AD7124-8. Figure 4 shows the timing for a write operation to
the input shift register. A delay is required between consecutive
SPI communications. Figure 5 shows the delay required between
SPI read/write operations. It is possible to read the same word
from the data register several times, even though the
DOUT/RDY line returns high after the first read operation.
However, care must be taken to ensure that the read operations
are complete before the next output update occurs. In continuous
read mode, the data register can be read only once.
The serial interface can operate in 3-wire mode by tying CS low.
In this case, the SCLK, DIN, and DOUT/RDY lines communicate
with the AD7124-8. The end of the conversion can be monitored
using the RDY bit in the status register. This scheme is suitable
for interfacing to microcontrollers. If CS is required as a decoding
signal, it can be generated from a port pin. For microcontroller
interfaces, it is recommended that SCLK idle high between data
transfers.
The AD7124-8 can be operated with CS being used as a frame
synchronization signal. This scheme is useful for DSP interfaces.
In this case, the first bit (MSB) is effectively clocked out by CS,
because CS normally occurs after the falling edge of SCLK in
DSPs. SCLK can continue to run between data transfers,
provided the timing numbers are obeyed.
CS must be used to frame read and write operations and the
CS_EN bit in the ADC_CONTROL register must be set when
the diagnostics SPI_READ_ERR, SPI_WRITE_ERR, or
SPI_SCLK_CNT_ERR are enabled.
The serial interface can be reset by writing a series of 1s on the
DIN input. See the Reset section for more details. Reset returns
the interface to the state in which it is expecting a write to the
communications register
The AD7124-8 can be configured to continuously convert or
perform a single conversion (see Figure 81 through Figure 83).
Single Conversion Mode
In single conversion mode, the AD7124-8 performs a single
conversion and is placed in standby mode after the conversion
is complete. If a master clock is present (external master clock
or the internal oscillator is enabled), DOUT/RDY goes low to
indicate the completion of a conversion. When the data-word is
read from the data register, DOUT/RDY goes high. The data
register can be read several times, if required, even when
DOUT/RDY is high. Do not read the ADC_CONTROL register
close to the completion of a conversion because the mode bits are
being updated by the ADC to indicate that the ADC is in standby
mode.
If several channels are enabled, the ADC automatically sequences
through the enabled channels and performs a conversion on
each channel. When a conversion is started, DOUT/RDY goes
high and remains high until a valid conversion is available and
CS is low. As soon as the conversion is available, DOUT/RDY
goes low. The ADC then selects the next channel and begins a
conversion. The user can read the present conversion while the
next conversion is being performed. As soon as the next conversion is complete, the data register is updated; therefore, the user
has a limited period in which to read the conversion. When the
ADC has performed a single conversion on each of the selected
channels, it returns to standby mode.
Rev. E | Page 50 of 94
Data Sheet
AD7124-8
If the DATA_STATUS bit in the ADC_CONTROL register is set
to 1, the contents of the status register are output along with the
conversion each time that the data read is performed. The four
LSBs of the status register indicate the channel to which the conversion corresponds.
Continuous Conversion Mode
Continuous conversion is the default power-up mode. The
AD7124-8 converts continuously, and the RDY bit in the status
register goes low each time a conversion is complete. If CS is low,
the DOUT/RDY line also goes low when a conversion is complete.
To read a conversion, write to the communications register,
indicating that the next operation is a read of the data register.
When the data-word is read from the data register, DOUT/RDY
goes high. The user can read this register additional times, if
required. However, the user must ensure that the data register is
not being accessed at the completion of the next conversion;
otherwise the new conversion word is lost.
When several channels are enabled, the ADC automatically
sequences through the enabled channels, performing one
conversion on each channel. When all channels are converted,
the sequence starts again with the first channel. The channels
are converted in order from lowest enabled channel to highest
enabled channel. The data register is updated as soon as each
conversion is available. The DOUT/RDY pin pulses low each
time a conversion is available. The user can then read the
conversion while the ADC converts the next enabled channel.
If the DATA_STATUS bit in the ADC_CONTROL register is set
to 1, the contents of the status register, along with the conversion
data, are output each time the data register is read. The status
register indicates the channel to which the conversion corresponds.
CS
DIN
0x01
0x0004
0x42
DATA
13048-087
DOUT/RDY
SCLK
Figure 81. Single Conversion Configuration
CS
DIN
0x42
DOUT/RDY
0x42
DATA
13048-088
DATA
SCLK
Figure 82. Continuous Conversion Configuration
CS
DIN
0x01
0x0800
DOUT/RDY
DATA
13048-089
DATA
SCLK
Figure 83. Continuous Read Configuration
Rev. E | Page 51 of 94
AD7124-8
Data Sheet
Continuous Read Mode
In continuous read mode, it is not required to write to the
communications register before reading ADC data; apply the
required number of SCLKs after DOUT/RDY goes low to
indicate the end of a conversion. When the conversion is read,
DOUT/RDY returns high until the next conversion is available.
In this mode, the data can be read only once. Ensure that the dataword is read before the next conversion is complete. If the user
has not read the conversion before the completion of the next
conversion, or if insufficient serial clocks are applied to the
AD7124-8 to read the word, the serial output register is reset
when the next conversion is complete, and the new conversion
is placed in the output serial register. The ADC must be configured
for continuous conversion mode to use continuous read mode.
To enable continuous read mode, set the CONT_READ bit in
the ADC_CONTROL register. When this bit is set, the only serial
interface operations possible are reads from the data register. To
exit continuous read mode, write a read data command (0x42)
while the DOUT/RDY pin is low. Alternatively, apply a software
reset, that is, 64 SCLKs with CS = 0 and DIN = 1. This resets the
ADC and all register contents. These are the only commands
that the interface recognizes after it is placed in continuous read
mode. DIN must be held low in continuous read mode until an
instruction is to be written to the device.
If multiple ADC channels are enabled, each channel is output in
turn, with the status bits being appended to the data if DATA_
STATUS is set in the ADC_CONTROL register. The status
register indicates the channel to which the conversion corresponds.
DATA_STATUS
The contents of the status register can be appended to each
conversion on the AD7124-8. This is a useful function if several
channels are enabled. Each time a conversion is output, the
contents of the status register are appended. The four LSBs of
the status register indicate to which channel the conversion
corresponds. In addition, the user can determine if any errors
are being flagged via the ERROR_FLAG bit. To append the status
register contents to every conversion, the DATA_STATUS bit in
the ADC_CONTROL register is set to 1.
SERIAL INTERFACE RESET (DOUT_RDY_DEL AND
CS_EN BITS)
The instant at which the DOUT/RDY pin changes from being a
DOUT pin to a RDY pin is programmable on the AD7124-8. By
default, the DOUT/RDY pin changes functionality after a period of
time following the last SCLK rising edge, the SCLK edge on which
the LSB is read by the processor. This time is 10 ns minimum by
default and, by setting the DOUT_RDY_DEL bit in the ADC_
CONTROL register to 1, can be extended to 110 ns minimum.
By setting the CS_EN bit in the ADC_CONTROL register to 1, the
DOUT/RDY pin continues to output the LSB of the register
being read until CS is taken high. This configuration is useful if
the CS signal is used to frame all read operations. If CS is not
used to frame all read operations, set CS_EN to 0 so that
DOUT/RDY changes functionality following the last SCLK
edge in the read operation.
CS_EN must be set to 1 and the CS signal must be used to frame all
read and write operations when the SPI_READ_ERR,
SPI_WRITE_ERR, and SPI_SCLK_CNT_ERR diagnostic
functions are enabled.
The serial interface is always reset on the CS rising edge, that is,
the interface is reset to a known state whereby it awaits a write
to the communications register. Therefore, if a read or write
operation is performed by performing multiple 8- bit data
transfers, CS must be held low until the all bits are transferred.
RESET
The circuitry and serial interface of the AD7124-8 can be reset
by writing 64 consecutive 1s to the device. This resets the logic,
the digital filter, and the analog modulator, and all on-chip
registers are reset to their default values. A reset is automatically
performed on power-up. A reset requires a time of 90 MCLK
cycles. The POR_FLAG bit in the status register is set to 1 when
the reset is initiated and then is set to 0 when the reset is complete.
A reset is useful if the serial interface becomes asynchronous
due to noise on the SCLK line.
CALIBRATION
The AD7124-8 provides four calibration modes that can be
used to eliminate the offset and gain errors on a per setup basis:
•
•
•
•
Internal zero-scale calibration mode
Internal full-scale calibration mode
System zero-scale calibration mode
System full-scale calibration mode
Only one channel can be active during calibration. After each
conversion, the ADC conversion result is scaled using the ADC
calibration registers before being written to the data register.
The default value of the offset register is 0x800000, and the nominal
value of the gain register is 0x5XXXXX. The calibration range
of the ADC gain is from 0.4 × VREF/gain to 1.05 × VREF/gain.
The following equations show the calculations that are used in
each calibration mode. In unipolar mode, the ideal
relationship—that is, not taking into account the ADC gain
error and offset error—is as follows:
Rev. E | Page 52 of 94
0.75 × VIN
Data =
× 2 23 − (Offset − 0x800000) ×
VREF
Gain
×2
0x400000
Data Sheet
AD7124-8
In bipolar mode, the ideal relationship—that is, not taking into
account the ADC gain error and offset error—is as follows:
0.75 × VIN
Data =
× 2 23 − (Offset − 0x800000) ×
VREF
Gain
+ 0x800000
0x400000
To start a calibration, write the relevant value to the mode bits
in the ADC_CONTROL register. The DOUT/RDY pin and the
RDY bit in the status register go high when the calibration
initiates. When the calibration is complete, the contents of the
corresponding offset or gain register are updated, the RDY bit
in the status register is reset, the DOUT/RDY pin returns low (if
CS is low), and the AD7124-8 reverts to idle mode.
During an internal offset calibration, the selected positive
analog input pin is disconnected, and it is connected internally
to the selected negative analog input pin. For this reason, it is
necessary to ensure that the voltage on the selected negative
analog input pin does not exceed the allowed limits and is free
from excessive noise and interference.
To perform an internal full-scale calibration, a full-scale input
voltage is automatically connected to the selected analog input
for this calibration. A full-scale calibration is recommended
each time the gain of a channel is changed to minimize the fullscale error. When performing internal calibrations, the internal
full-scale calibration must be performed before the internal
zero-scale calibration. Therefore, write the value 0x800000 to
the offset register before performing the internal full-scale
calibration, which ensures that the offset register is at its default
value. The AD7124-8 is factory calibrated at a gain of 1, and the
resulting gain coefficient is the default gain coefficient on the
device. The device does not support further internal full-scale
calibrations at a gain of 1.
System calibrations expect the system zero-scale (offset) and
system full-scale (gain) voltages to be applied to the ADC pins
before initiating the calibration modes. As a result, errors
external to the ADC are removed. The system zero-scale
calibration must be performed before the system full-scale
calibration.
From an operational point of view, treat a calibration like
another ADC conversion. Set the system software to monitor
the RDY bit in the status register or the DOUT/RDY pin to
determine the end of a calibration via a polling sequence or an
interrupt-driven routine.
An internal/system offset calibration and system full-scale
calibration requires a time equal to the settling time of the
selected filter to be completed. The internal full-scale
calibration requires a time equal to four settling periods (gain > 1).
A calibration can be performed at any output data rate. Using
lower output data rates results in better calibration accuracy and
is accurate for all output data rates. A new calibration is required
for a given channel if the reference source or the gain for that
channel is changed.
Offset and system full-scale calibrations can be performed in
any power mode. Internal full-scale calibrations can be performed
in the low power or mid power modes only. Thus, when using
full power mode, the user must select mid or low power mode
to perform the internal full-scale calibration. However, an internal
full-scale calibration performed in low or mid power mode is
valid in full power mode, if the same gain is used.
The offset error is typically ±15 µV for gains of 1 to 8 and
±200/gain µV for higher output data rates. An internal or system
offset calibration reduces the offset error to the order of the
noise. The gain error is factory calibrated at ambient temperature
and at a gain of 1. Following this calibration, the gain error is
±0.0025% maximum. Therefore, internal full-scale calibrations
at a gain of 1 are not supported on the AD7124-8. For other
gains, the gain error is −0.3%. An internal full-scale calibration at
ambient temperature reduces the gain error to ±0.016%
maximum for gains of 2 to 8 and ±0.025% typically for higher
gains. A system full-scale calibration reduces the gain error to the
order of the noise.
The AD7124-8 provides the user with access to the on-chip
calibration registers, allowing the microprocessor to read the
calibration coefficients of the device and to write its own
calibration coefficients from prestored values in the EEPROM.
A read or write of the offset and gain registers can be performed
at any time except during an internal or self-calibration. The
values in the calibration registers are 24 bits wide. The span and
offset of the device can also be manipulated using the registers.
SPAN AND OFFSET LIMITS
Whenever a system calibration mode is used, the amount of
offset and span that can be accommodated is limited. The
overriding requirement in determining the amount of offset
and gain that can be accommodated by the device is the
requirement that the positive full-scale calibration limit is
≤1.05 × VREF/gain. This allows the input range to go 5% above
the nominal range. The built-in headroom in the AD7124-8
analog modulator ensures that the device still operates correctly
with a positive full-scale voltage, which is 5% beyond the nominal.
The range of input span in both the unipolar and bipolar modes
has a minimum value of 0.8 × VREF/gain and a maximum value
of 2.1 × VREF/gain. However, the span, which is the difference
between the bottom of the AD7124-8 input range and the top of
its input range, must account for the limitation on the positive
full-scale voltage. The amount of offset that can be accommodated
depends on whether the unipolar or bipolar mode is being used.
The offset must account for the limitation on the positive fullscale voltage. In unipolar mode, there is considerable flexibility in
handling negative (with respect to AINM) offsets. In both
unipolar and bipolar modes, the range of positive offsets that
can be handled by the device depends on the selected span.
Therefore, in determining the limits for system zero-scale and
full-scale calibrations, the user must ensure that the offset range
Rev. E | Page 53 of 94
AD7124-8
Data Sheet
plus the span range does exceed 1.05 × VREF/gain. This is best
illustrated by looking at a few examples.
If the device is used in unipolar mode with a required span of
0.8 × VREF/gain, the offset range that the system calibration can
handle is from −1.05 × VREF/gain to +0.25 × VREF/gain. If the
device is used in unipolar mode with a required span of
VREF/gain, the offset range that the system calibration can
handle is from −1.05 × VREF/gain to +0.05 × VREF/gain. Similarly,
if the device is used in unipolar mode and required to remove
an offset of 0.2× VREF/gain, the span range that the system
calibration can handle is 0.85 × VREF/gain.
If the device is used in bipolar mode with a required span of
±0.4 × VREF/gain, then the offset range that the system
calibration can handle is from −0.65 × VREF/gain to +0.65 ×
VREF/gain. If the device is used in bipolar mode with a required
span of ±VREF/gain, the offset range the system calibration can
handle is from −0.05 × VREF/gain to +0.05 × VREF/gain.
Similarly, if the device is used in bipolar mode and required to
remove an offset of ±0.2 × VREF/gain, the span range that the
system calibration can handle is ±0.85 × VREF/gain.
SYSTEM SYNCHRONIZATION
The SYNC input allows the user to reset the modulator and the
digital filter without affecting any of the setup conditions on the
device. This allows the user to start gathering samples of the
analog input from a known point in time, that is, the rising edge
of SYNC. Take SYNC low for at least four master clock cycles to
implement the synchronization function.
SYNC pin is low, the AD7124-8 is maintained in this state. On
the SYNC rising edge, the modulator and filter exit this reset
state and, on the next clock edge, the device starts to gather
input samples again. In a system using multiple AD7124-8
devices, a common signal to their SYNC pins synchronizes their
operation. This is normally performed after each AD7124-8 has
performed its own calibration or has calibration coefficients
loaded into its calibration registers. The conversions from the
AD7124-8 devices are then synchronized.
The device exits reset on the master clock falling edge following
the SYNC low to high transition. Therefore, when multiple
devices are being synchronized, pull the SYNC pin high on the
master clock rising edge to ensure that all devices begin
sampling on the master clock falling edge. If the SYNC pin is
not taken high in sufficient time, it is possible to have a
difference of one master clock cycle between the devices; that is,
the instant at which conversions are available differs from
device to device by a maximum of one master clock cycle.
The SYNC pin can also be used as a start conversion command.
In this mode, the rising edge of SYNC starts conversion and the
falling edge of RDY indicates when the conversion is complete.
The settling time of the filter must be allowed for each data
register update. For example, if the ADC is configured to use
the sinc4 filter and zero latency is disabled, the settling time
equals 4/fADC where fADC is the output data rate when
continuously converting on a single channel.
If multiple AD7124-8 devices are operated from a common
master clock, they can be synchronized so that their data
registers are updated simultaneously. A falling edge on the
SYNC pin resets the digital filter and the analog modulator and
places the AD7124-8 into a consistent, known state. While the
Rev. E | Page 54 of 94
Data Sheet
AD7124-8
DIGITAL FILTER
Table 55. Filter Registers
Reg.
0x21 to
0x28
Name
FILTER_0 to
FILTER_7
Bit 7
Bit 6
Filter
Bit 5
Bit 4
REJ60
Bit 3
0
Bit 2
Bit 1
Bit 0
POST_FILTER
SINGLE_CYCLE
FS[10:8]
Reset
0x060180
RW
RW
FS[7:0]
When a channel change occurs, the modulator and filter are
reset. The settling time is allowed to generate the first
conversion after the channel change. Subsequent conversions on
this channel occur at 1/fADC.
CHANNEL
CHANNEL A
CONVERSIONS CH A
The filter bits in the filter register select between the sinc type filter.
SINC FILTER
CH B CH B CH B
1/fADC
DT/fCLK
Figure 85. Sinc4 Channel Change
4
When the AD7124-8 is powered up, the sinc filter is selected by
default. This filter gives excellent noise performance over the
complete range of output data rates. It also gives the best 50 Hz/
60 Hz rejection, but it has a long settling time. In Figure 84, the
blocks shown in gray are unused.
POST
FILTER
SINC3 /SINC4
FILTER
AVERAGING
BLOCK
13048-091
MODULATOR
CH A CH A
NOTES
1. DT = DEAD TIME.
4
CHANNEL B
13048-092
The AD7124-8 offers a great deal of flexibility in the digital
filter. The device has several filter options. The option selected
affects the output data rate, settling time, and 50 Hz and 60 Hz
rejection. The following sections describe each filter type,
indicating the available output data rates for each filter option.
The filter response along with the settling time and 50 Hz and
60 Hz rejection is also discussed.
When conversions are performed on a single channel and a
step change occurs, the ADC does not detect the change in the
analog input. Therefore, it continues to output conversions
at the programmed output data rate. However, it is at least four
conversions later before the output data accurately reflects the
analog input. If the step change occurs while the ADC is
processing a conversion, then the ADC takes five conversions
after the step change to generate a fully settled result.
ANALOG
INPUT
FULLY
SETTLED
Figure 84. Sinc4 Filter
Sinc4 Output Data Rate/Settling Time
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
where:
fADC is the output data rate.
fCLK is the master clock frequency (614.4 kHz in full power mode,
153.6 kHz in mid power mode, and 76.8 kHz in low power mode).
FS[10:0] is the decimal equivalent of the FS[10:0] bits in the
filter register. FS[10:0] can have a value from 1 to 2047.
9.38 SPS to 19,200 SPS for full power mode
2.35 SPS to 4800 SPS for mid power mode
1.17 SPS to 2400 SPS for low power mode
The settling time for the sinc4 filter is equal to
tSETTLE = (4 × 32 × FS[10:0] + Dead Time)/fCLK
where Dead Time = 61 when FS[10:0] = 1 and 95 when
FS[10:0] > 1
1/fADC
Figure 86. Asynchronous Step Change in the Analog Input
The 3 dB frequency for the sinc4 filter is equal to
fADC = fCLK/(32 × FS[10:0])
The output data rate can be programmed from
13048-093
ADC
OUTPUT
f3dB = 0.23 × fADC
Table 56 gives some examples of the relationship between the
values in the FS[10:0] bits and the corresponding output data
rate and settling time.
Table 56. Examples of Output Data Rates and the
Corresponding Settling Times for the Sinc4 Filter
Power Mode
Full Power (fCLK =
614.4 kHz)
Mid Power (fCLK =
153.6 kHz)
Low Power (fCLK =
76.8 kHz)
Rev. E | Page 55 of 94
FS[10:0]
1920
384
320
480
96
80
240
48
40
Output Data
Rate (SPS)
10
50
60
10
50
60
10
50
60
Settling
Time (ms)
400.15
80.15
66.82
400.61
80.61
67.28
401.22
81.22
67.89
AD7124-8
Data Sheet
Sinc4 Zero Latency
Zero latency is enabled by setting the SINGLE_CYCLE bit in
the filter register to 1. With zero latency, the conversion time
when continuously converting on a single channel approximately
equals the settling time. The benefit of this mode is that a similar
period of time elapses between all conversions irrespective of
whether the conversions occur on one channel or whether several
channels are used. When the analog input is continuously sampled
on a single channel, the output data rate equals
When the analog input is constant or a channel change occurs,
valid conversions are available at a near constant output data
rate. When conversions are being performed on a single
channel and a step change occurs on the analog input, the ADC
continues to output fully settled conversions if the step change is
synchronized with the conversion process. If the step change is
asynchronous, one conversion is output from the ADC, which is
not completely settled (see Figure 87).
ANALOG
INPUT
FULLY
SETTLED
fADC = fCLK/(4 × 32 × FS[10:0])
1/fADC
Figure 87. Sinc4 Zero Latency Operation
Dead Time/fCLK
where Dead Time = 61 when FS[10:0] = 1 and 95 when
FS[10:0] > 1.
At low output data rates, this extra delay has little impact on the
value of the settling time. However, at high output data rates, the
delay must be considered. Table 57 summarizes the output data
rate when continuously converting on a single channel and the
settling time when switching between channels for a sample of
FS[10:0] values.
When switching between channels, the AD7124-8 allows the
complete settling time to generate the first conversion after the
channel change. Therefore, the ADC automatically operates in
zero latency mode when several channels are enabled—setting
the SINGLE_CYCLE bit has no benefits.
Sequencer
The description in the Sinc4 Filter section is valid when
manually switching channels, for example, writing to the device
to change channels. When multiple channels are enabled, the
on-chip sequencer is automatically used; the device
automatically sequences between all enabled channels. In this
case, the first conversion takes the complete settling time as
listed in Table 56. For all subsequent conversions, the time
needed for each conversion is the settling time also, but the
dead time is reduced to 30.
Sinc4 50 Hz and 60 Hz Rejection
Figure 88 shows the frequency response of the sinc4 filter when
the output data rate is programmed to 50 SPS and zero latency
is disabled. For the same configuration but with zero latency
enabled, the filter response remains the same but the output data
rate is 12.5 SPS. The sinc4 filter provides 50 Hz (±1 Hz) rejection in
excess of 120 dB minimum, assuming a stable master clock.
Table 57. Examples of Output Data Rates and the
Corresponding Settling Times for the Sinc4 Filter (Zero Latency)
Mid Power (fCLK =
153.6 kHz)
Low Power (fCLK =
76.8 kHz)
FS[10:0]
1920
384
320
480
96
80
240
48
40
–20
–30
FILTER GAIN (dB)
Power Mode
Full Power (fCLK =
614.4 kHz)
Settling
Time (ms)
400.15
80.15
66.82
400.61
80.61
67.28
401.22
81.22
67.89
0
–10
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
25
50
75
100
FREQUENCY (Hz)
125
150
13048-095
When the user selects another channel, there is an extra delay in
the first conversion of
Output Data
Rate (SPS)
2.5
12.5
15
2.5
12.5
15
2.5
12.5
15
13048-094
ADC
OUTPUT
where:
fADC is the output data rate.
fCLK is the master clock frequency.
FS[10:0] is the decimal equivalent of the FS[10:0] bits in the
setup filter register.
Figure 88. Sinc4 Filter Response (50 SPS Output Data Rate, Zero Latency
Disabled or 12.5 SPS Output Data Rate, Zero Latency Enabled)
Rev. E | Page 56 of 94
Data Sheet
AD7124-8
Figure 89 shows the frequency response of the sinc4 filter when
the output data rate is programmed to 60 SPS and zero latency
is disabled. For the same configuration but with zero latency
enabled, the filter response remains the same but the output
data rate is 15 SPS. The sinc4 filter provides 60 Hz (±1 Hz)
rejection of 120 dB minimum, assuming a stable master clock.
0
–10
–20
–30
FILTER GAIN (dB)
–40
0
–10
–50
–60
–70
–80
–20
–90
–30
–40
–110
–120
0
–60
25
75
50
100
125
150
FREQUENCY (Hz)
–70
13048-098
–50
Figure 91. Sinc4 Filter Response (50 SPS Output Data Rate, Zero Latency
Disabled or 12.5 SPS Output Data Rate, Zero Latency Enabled, REJ60 = 1)
–80
–90
SINC3 FILTER
–100
–120
0
30
60
90
120
150
FREQUENCY (Hz)
13048-096
–110
Figure 89. Sinc4 Filter Response (60 SPS Output Data Rate, Zero Latency
Disabled or 15 SPS Output Data Rate, Zero Latency Enabled)
When the output data rate is 10 SPS with zero latency disabled
or 2.5 SPS with zero latency enabled, simultaneous 50 Hz and
60 Hz rejection is obtained. The sinc4 filter provides 50 Hz
(±1 Hz) and 60 Hz (±1 Hz) rejection of 120 dB minimum,
assuming a stable master clock.
A sinc3 filter can be used instead of the sinc4 filter. The filter is
selected using the filter bits in the filter register. This filter has
good noise performance, moderate settling time, and moderate
50 Hz and 60 Hz (±1 Hz) rejection. In Figure 92, the blocks
shown in gray are unused.
POST
FILTER
MODULATOR
SINC3 /SINC4
FILTER
AVERAGING
BLOCK
0
13048-099
FILTER GAIN (dB)
–100
Figure 92. Sinc3 Filter
–10
Sinc Output Data Rate and Settling Time
3
–20
The output data rate (the rate at which conversions are available on
a single channel when the ADC is continuously converting) equals
FILTER GAIN (dB)
–30
–40
–50
fADC = fCLK/(32 × FS[10:0])
–60
–70
–80
–90
–100
0
30
60
90
FREQUENCY (Hz)
120
150
13048-097
–110
–120
Figure 90. Sinc4 Filter Response (10 SPS Output Data Rate, Zero Latency
Disabled or 2.5 SPS Output Data Rate, Zero Latency Enabled)
Simultaneous 50 Hz/60 Hz rejection can also be achieved using
the REJ60 bit in the filter register. When the sinc filter places a
notch a 50 Hz, the REJ60 bit places a first order notch at 60 Hz.
The output data rate is 50 SPS when zero latency is disabled and
12.5 SPS when zero latency is enabled. Figure 91 shows the
frequency response of the sinc4 filter. The filter provides 50 Hz ±
1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming
a stable master clock.
where:
fADC is the output data rate.
fCLK is the master clock frequency (614.4 kHz in full power mode,
153.6 kHz in mid power mode and 76.8 kHz in low power mode).
FS[10:0] is the decimal equivalent of the FS[10:0] bits in the
filter register. FS[10:0] can have a value from 1 to 2047.
The output data rate can be programmed from
•
•
•
9.38 SPS to 19,200 SPS for full power mode
2.35 SPS to 4800 SPS for mid power mode
1.17 SPS to 2400 SPS for low power mode
The settling time for the sinc3 filter is equal to
tSETTLE = (3 × 32 × FS[10:0] + Dead Time)/fCLK
where Dead Time = 61 when FS[10:0] = 1 and 95 FS[10:0] >1.
The 3 dB frequency is equal to
Rev. E | Page 57 of 94
f3dB = 0.262 × fADC
AD7124-8
Data Sheet
Table 58 gives some examples of FS[10:0] settings and the
corresponding output data rates and settling times.
When the analog input is continuously sampled on a single
channel, the output data rate equals
fADC = fCLK/(3 × 32 × FS[10:0])
Table 58. Examples of Output Data Rates and the
Corresponding Settling Times for the Sinc3 Filter
Power Mode
Full Power (fCLK =
614.4 kHz)
Mid Power (fCLK =
153.6 kHz)
Low Power (fCLK =
76.8 kHz)
FS[10:0]
1920
384
320
480
96
80
240
48
40
Output Data
Rate (SPS)
10
50
60
10
50
60
10
50
60
where:
fADC is the output data rate.
fCLK is the master clock frequency.
FS[10:0] is the decimal equivalent of the FS[10:0] bits in the
filter register.
Settling
Time (ms)
300.15
60.15
50.15
300.61
60.61
50.61
301.22
61.22
51.22
When switching channels, there is an extra delay in the first
conversion of
Dead Time/fCLK
where Dead Time = 61 when FS[10:0] = 1 or 95 when FS[10:0] > 1.
When a channel change occurs, the modulator and filter are
reset. The complete settling time is allowed to generate the first
conversion after the channel change (see Figure 93). Subsequent
conversions on this channel are available at 1/fADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A
CHANNEL B
CH A
CH B
CH B
13048-100
1/fADC
NOTES
1. DT = DEAD TIME.
DT/fCLK
Figure 93. Sinc3 Channel Change
When conversions are performed on a single channel and a step
change occurs, the ADC does not detect the change in the
analog input. Therefore, it continues to output conversions at
the programmed output data rate. However, it is at least three
conversions later before the output data accurately reflects the
analog input. If the step change occurs while the ADC is processing
a conversion, the ADC takes four conversions after the step
change to generate a fully settled result.
At low output data rates, this extra delay has little impact on the
value of the settling time. However, at high output data rates, the
delay must be considered. Table 59 summarizes the output data rate
when continuously converting on a single channel and the settling
time when switching between channels for a sample of FS[10:0].
When the user selects another channel, the AD7124-8 allows
the complete settling time to generate the first conversion after
the channel change. Therefore, the ADC automatically operates
in zero latency mode when several channels are enabled—setting
the SINGLE_CYCLE bit has no benefits.
When the analog input is constant or a channel change occurs,
valid conversions are available at a near constant output data
rate. When conversions are being performed on a single channel
and a step change occurs on the analog input, the ADC continues
to output fully settled conversions if the step change is synchronized
with the conversion process. If the step change is asynchronous,
one conversion is output from the ADC that is not completely
settled (see Figure 95).
ANALOG
INPUT
FULLY
SETTLED
ADC
OUTPUT
FULLY
SETTLED
1/fADC
ADC
OUTPUT
13048-102
ANALOG
INPUT
3
1/fADC
13048-101
Figure 95. Sinc Zero Latency Operation
Figure 94. Asynchronous Step Change in the Analog Input
3
Sinc Zero Latency
Zero latency is enabled by setting the SINGLE_CYCLE bit in
the filter register to 1. With zero latency, the conversion time
when continuously converting on a single channel approximately
equals the settling time. The benefit of this mode is that a similar
period of time elapses between all conversions irrespective of
whether the conversions occur on one channel or whether
several channels are used.
Table 59. Examples of Output Data Rates and the
Corresponding Settling Times for the Sinc3 Filter (Zero Latency)
Power Mode
Full Power (fCLK =
614.4 kHz)
Mid Power (fCLK =
153.6 kHz)
Low Power (fCLK =
76.8 kHz)
Rev. E | Page 58 of 94
FS[10:0]
1920
384
320
480
96
80
240
48
40
Output Data
Rate (SPS)
3.33
16.67
20
3.33
16.67
20
3.33
16.67
20
Settling
Time (ms)
300.15
60.15
50.15
300.61
60.61
50.61
301.22
61.22
51.22
Data Sheet
AD7124-8
Sinc3 50 Hz and 60 Hz Rejection
Figure 96 shows the frequency response of the sinc3 filter when
the output data rate is programmed to 50 SPS and zero latency
is disabled. For the same configuration but with zero latency
enabled, the filter response remains the same but the output
data rate is 16.67 SPS. The sinc3 filter gives 50 Hz ± 1 Hz
rejection of 95 dB minimum for a stable master clock.
When the output data rate is 10 SPS with zero latency disabled
or 3.33 SPS with zero latency enabled, simultaneous 50 Hz and
60 Hz rejection is obtained. The sinc3 filter has rejection of 100 dB
minimum at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz (see Figure 98).
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
60
30
0
–10
–30
150
Simultaneous 50 Hz and 60 Hz rejection can also be achieved
using the REJ60 bit in the filter register. When the sinc filter
places a notch a 50 Hz, the REJ60 bit places a first order notch
at 60 Hz. The output data rate is 50 SPS when zero latency is
disabled and 16.67 SPS when zero latency is enabled. Figure 99
shows the frequency response of the sinc3 filter with this configuration. Assuming a stable clock, the rejection at 50 Hz and 60 Hz
(±1 Hz) is in excess of 67 dB minimum.
–40
–50
–60
–70
–80
–90
–100
–110
0
25
75
50
100
125
150
FREQUENCY (Hz)
13048-103
0
–120
Figure 96. Sinc3 Filter Response (50 SPS Output Data Rate, Zero Latency
Disabled or 16.67 SPS Output Data Rate, Zero Latency Enabled)
Figure 97 shows the frequency response of the sinc3 filter when
the output data rate is programmed to 60 SPS and zero latency
is disabled. For the same configuration but with zero latency
enabled, the filter response remains the same but the output
data rate is 20 SPS. The sinc3 filter has rejection of 95 dB
minimum at 60 Hz ± 1 Hz, assuming a stable master clock.
–10
–20
–30
FILTER GAIN (dB)
–40
–50
–60
–70
–80
–90
–100
–110
0
–120
–10
0
–20
25
50
75
100
125
150
FREQUENCY (Hz)
–30
13048-106
FILTER GAIN (dB)
120
Figure 98. Sinc3 Filter Response (10 SPS Output Data Rate, Zero Latency
Disabled or 3.33 SPS Output Data Rate, Zero Latency Enabled)
–20
FILTER GAIN (dB)
90
FREQUENCY (Hz)
13048-105
The description in the Sinc Filter section is valid when manually
switching channels, for example, writing to the device to change
channels. When multiple channels are enabled, the on-chip
sequencer is automatically used; the device automatically
sequences between all enabled channels. In this case, the first
conversion takes the complete settling time as listed in Table 58.
For all subsequent conversions, the time needed for each conversion
is also the settling time, but the dead time is reduced to 30.
3
FILTER GAIN (dB)
Sequencer
Figure 99. Sinc3 Filter Response (50 SPS Output Data Rate, Zero Latency
Disabled or 16.67 SPS Output Data Rate, Zero Latency Enabled, REJ60 = 1)
–40
–50
FAST SETTLING MODE (SINC4 + SINC1 FILTER)
–60
–70
–80
–90
–100
0
30
60
90
FREQUENCY (Hz)
120
150
13048-104
–110
–120
In fast settling mode, the settling time is close to the inverse of
the first filter notch; therefore, the user can achieve 50 Hz and/or
60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz.
The settling time is approximately equal to 1/output data rate.
Therefore, the conversion time is near constant when converting
on a single channel or when converting on several channels.
Figure 97. Sinc3 Filter Response (60 SPS Output Data Rate, Zero Latency
Disabled or 20 SPS Output Data Rate, Zero Latency Enabled)
Rev. E | Page 59 of 94
AD7124-8
Data Sheet
POST
FILTER
Figure 100. Fast Settling Mode, Sinc4 + Sinc1 Filter
Output Data Rate and Settling Time, Sinc4 + Sinc1 Filter
When continuously converting on a single channel, the output
data rate is
When another channel is selected by the user, there is an extra
delay in the first conversion. The settling time is equal to
tSETTLE = ((4 + Avg − 1) × 32 × FS[10:0] + Dead Time)/fCLK
where Dead Time = 95.
The 3 dB frequency is equal to
Table 60 lists sample FS[10:0] settings and the corresponding
output data rates and settling times.
Table 60. Examples of Output Data Rates and the
Corresponding Settling Times (Fast Settling Mode, Sinc4 + Sinc1)
Low Power (fCLK =
76.8 kHz,
Average by 8)
1/fADC
DT/fCLK
Figure 101. Fast Settling, Sinc4 + Sinc1 Filter
When the device is converting on a single channel and a step
change occurs on the analog input, the ADC does not detect the
change and continues to output conversions. If the step change
is synchronized with the conversion, only fully settled results
are output from the ADC. However, if the step change is
asynchronous to the conversion process, there is one intermediate
result, which is not completely settled (see Figure 102).
ANALOG
INPUT
1/fADC
4
Figure 102. Step Change on the Analog Input, Sinc + Sinc1 Filter
Sequencer
The description in the Fast Settling Mode (Sinc4 + Sinc1 Filter)
section is valid when manually switching channels, for example,
writing to the device to change channels. When multiple
channels are enabled, the on-chip sequencer is automatically
used; the device automatically sequences between all enabled
channels. In this case, the first conversion takes the complete
settling time as listed in Table 60. For all subsequent
conversions, the time needed for each conversion is also the
settling time, but the dead time is reduced to 30.
50 Hz and 60 Hz Rejection, Sinc4 + Sinc1 Filter
f3dB = 0.44 × fADC
Mid Power (fCLK =
153.6 kHz,
Average by 16)
NOTES
1. DT = DEAD TIME.
CH B CH B CH B CH B
ADC
OUTPUT
where:
fADC is the output data rate.
fCLK is the master clock frequency (614.4 kHz in full power mode,
153.6 kHz in mid power mode, and 76.8 kHz in low power mode).
Avg is 16 for the full or mid power mode and 8 for low power
mode.
FS[10:0] is the decimal equivalent of the FS[10:0] bits in the
filter register. FS[10:0] can have a value from 1 to 2047.
FS[10:0]
120
24
20
30
6
5
30
6
5
CH A CH A CH A CH A
VALID
fADC = fCLK/((4 + Avg − 1) × 32 × FS[10:0])
Power Mode
Full Power (fCLK =
614.4 kHz,
Average by 16)
CONVERSIONS CH A
CHANNEL B
13048-109
AVERAGING
BLOCK
13048-107
SINC3/SINC4
FILTER
MODULATOR
CHANNEL A
CHANNEL
13048-108
Enable the fast settling mode using the filter bits in the filter
register. In fast settling mode, a sinc1 filter is included after the
sinc4 filter. The sinc1 filter averages by 16 in the full power and
mid power modes and averages by 8 in the low power mode. In
Figure 100, the blocks shown in gray are unused.
First
Notch
(Hz)
10
50
60
10
50
60
10
50
60
Output
Data Rate
(SPS)
8.42
42.11
50.53
8.42
42.11
50.53
7.27
36.36
43.64
Settling
Time
(ms)
118.9
23.9
19.94
119.36
24.36
20.4
138.72
28.72
24.14
When the analog input is constant or a channel change occurs,
valid conversions are available at a near constant output data rate.
Figure 103 shows the frequency response when FS[10:0] is set to
24 in the full power mode or 6 in the mid power mode or low
power mode. Table 60 lists the corresponding output data rate.
The sinc filter places the first notch at
fNOTCH = fCLK/(32 × FS[10:0])
The sinc1 filter places notches at fNOTCH/Avg (Avg equaling 16 for
the full power mode and mid power mode and equaling 8 for
the low power mode). Notches are also placed at multiples of
this frequency; therefore, when FS[10:0] is set to 6 in the full
power mode or mid power mode, a notch is placed at 800 Hz
due to the sinc filter and notches are placed at 50 Hz and
multiples of 50 Hz due to the averaging. In low power mode, a
notch is placed at 400 Hz due to the sinc filter and notches are
placed at 50 Hz and multiples of 50 Hz due to the averaging.
The notch at 50 Hz is a first-order notch; therefore, the notch is
not wide. This means that the rejection at 50 Hz exactly is good,
assuming a stable master clock. However, in a band of 50 Hz ± 1 Hz,
the rejection degrades significantly. The rejection at 50 Hz ± 0.5 Hz
is 40 dB minimum, assuming a stable clock; therefore, a good
master clock source is recommended when using fast settling mode.
Rev. E | Page 60 of 94
Data Sheet
AD7124-8
FAST SETTLING MODE (SINC3 + SINC1 FILTER)
0
–10
In fast settling mode, the settling time is close to the inverse of
the first filter notch; therefore, the user can achieve 50 Hz and/or
60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz.
The settling time is approximately equal to 1/output data rate.
Therefore, the conversion time is near constant when converting
on a single channel or when converting on several channels.
–20
–40
–50
–60
–70
–80
–90
–100
0
30
60
90
120
150
FREQUENCY (Hz)
13048-110
–110
–120
Enable the fast settling mode using the filter bits in the filter
register. In fast settling mode, a sinc1 filter is included after the
sinc3 filter. The sinc1 filter averages by 16 in the full power and
mid power modes and averages by 8 in low power mode. In
Figure 106, the blocks shown in gray are unused.
POST
FILTER
Figure 103. 50 Hz Rejection
MODULATOR
Figure 104 shows the filter response when FS[10:0] is set to 20
in full power mode or 5 in the mid power and low power modes. In
this case, a notch is placed at 60 Hz and multiples of 60 Hz. The
rejection at 60 Hz ± 0.5 Hz is equal to 40 dB minimum.
Figure 106. Fast Settling Mode, Sinc3 + Sinc1 Filter
When continuously converting on a single channel, the output
data rate is
–20
–30
FILTER GAIN (dB)
AVERAGING
BLOCK
Output Data Rate and Settling Time, Sinc3 + Sinc1 Filter
0
–10
fADC = fCLK/((3 + Avg − 1) × 32 × FS[10:0])
–40
where:
fADC is the output data rate.
fCLK is the master clock frequency (614.4 kHz in full power mode,
153.6 kHz in mid power mode, and 76.8 kHz in low power mode).
Avg is 16 in full or mid power mode and 8 in low power mode.
FS[10:0] is the decimal equivalent of the FS[10:0] bits in the
filter register. FS[10:0] can have a value from 1 to 2047.
–50
–60
–70
–80
–90
–100
0
30
60
90
120
150
FREQUENCY (Hz)
13048-111
–110
–120
Figure 104. 60 Hz Rejection
Simultaneous 50 Hz/60 Hz rejection is achieved when FS[10:0]
is set to 384 in full power mode or 30 in the mid power and low
power modes. Notches are placed at 10 Hz and multiples of 10 Hz,
thereby giving simultaneous 50 Hz and 60 Hz rejection. The
rejection at 50 Hz ± 0.5 Hz and 60 Hz ± 0.5 Hz is 44 dB typically.
0
–10
When another channel is selected by the user, there is an extra
delay in the first conversion. The settling time is equal to
tSETTLE = ((3 + Avg − 1) × 32 × FS[10:0] + Dead Time)/fCLK
where Dead Time = 95.
The 3 dB frequency is equal to
f3dB = 0.44 × fNOTCH
Table 61 lists some sample FS[10:0] settings and the
corresponding output data rates and settling times.
Table 61. Examples of Output Data Rates and the
Corresponding Settling Times (Fast Settling Mode, Sinc3 + Sinc1)
–20
–30
–40
Power Mode
Full Power (fCLK =
614.4 kHz,
Average by 16)
–50
–60
–70
–80
–90
Mid Power (fCLK =
153.6 kHz,
Average by 16)
–100
–110
–120
0
30
60
90
120
FREQUENCY (Hz)
Figure 105. Simultaneous 50 Hz and 60 Hz Rejection
150
13048-112
FILTER GAIN (dB)
SINC3 /SINC4
FILTER
13048-113
FILTER GAIN (dB)
–30
Low Power (fCLK =
76.8 kHz,
Average by 8)
Rev. E | Page 61 of 94
FS[10:0]
120
24
20
30
6
5
30
6
5
First Notch
(Hz)
10
50
60
10
50
60
10
50
60
Output Data
Rate (SPS)
8.89
44.44
53.33
8.89
44.44
53.33
8
40
48
Settling
Time (ms)
112.65
22.65
18.9
113.11
23.11
19.36
126.22
26.22
22.06
AD7124-8
Data Sheet
When the analog input is constant or a channel change occurs,
valid conversions are available at a near constant output data rate.
CHANNEL B
NOTES
1. DT = DEAD TIME.
CH B CH B CH B CH B
1/fADC DT/fCLK
0
–10
Figure 107. Fast Settling, Sinc3 + Sinc1 Filter
–20
–30
FILTER GAIN (dB)
When the device is converting on a single channel and a step
change occurs on the analog input, the ADC does not detect
the change and continues to output conversions. When the step
change is synchronized with the conversion, only fully settled
results are output from the ADC. However, if the step change is
asynchronous to the conversion process, one intermediate result
is not completely settled (see Figure 108).
–40
–50
–60
–70
–80
–90
–100
ANALOG
INPUT
–110
VALID
–120
0
ADC
OUTPUT
30
60
90
120
150
Figure 108. Step Change on the Analog Input, Sinc3 + Sinc1 Filter
Sequencer
The description in the Fast Settling Mode (Sinc3 + Sinc1 Filter)
section is valid when manually switching channels, for example,
writing to the device to change channels. When multiple
channels are enabled, the on-chip sequencer is automatically
used; the device automatically sequences between all enabled
channels. In this case, the first conversion takes the complete
settling time as listed in Table 61. For all subsequent conversions,
the time needed for each conversion is also the settling time,
but the dead time is reduced to 30.
Figure 109. 50 Hz Rejection
Figure 110 shows the filter response when FS[10:0] is set to 20
in full power mode or 5 in the mid power and low power modes. In
this case, a notch is placed at 60 Hz and multiples of 60 Hz. The
rejection at 60 Hz ± 0.5 Hz is equal to 40 dB minimum.
0
–10
–20
–30
FILTER GAIN (dB)
1/fADC
13048-115
FREQUENCY (Hz)
13048-116
CONVERSIONS CH A CH A CH A CH A CH A
50 Hz and 60 Hz Rejection, Sinc3 + Sinc1 Filter
–40
–50
–60
–70
–80
–90
Figure 109 shows the frequency response when FS[10:0] is set to
24 in the full power mode or 6 in the mid power mode or low
power mode. Table 61 lists the corresponding output data rate.
–100
–110
–120
0
The sinc filter places the first notch at
30
60
90
FREQUENCY (Hz)
120
150
13048-117
CHANNEL A
13048-114
CHANNEL
The notch at 50 Hz is a first-order notch; therefore, the notch is not
wide. This means that the rejection at 50 Hz exactly is good, assuming a stable master clock. However, in a band of 50 Hz ± 1 Hz, the
rejection degrades significantly. The rejection at 50 Hz ± 0.5 Hz is
40 dB minimum, assuming a stable clock; therefore, a good master
clock source is recommended when using fast settling mode.
Figure 110. 60 Hz Rejection
fNOTCH = fCLK/(32 × FS[10:0])
The averaging block places notches at fNOTCH/Avg (Avg equaling
16 for the full power mode and mid power mode and equaling 8
for the low power mode). Notches are also placed at multiples of
this frequency; therefore, when FS[10:0] is set to 6 in full power
mode or mid power mode, a notch is placed at 800 Hz due to
the sinc filter and notches are placed at 50 Hz and multiples of
50 Hz due to the averaging. In low power mode, a notch is
placed at 400 Hz due to the sinc filter and notches are placed at
50 Hz and multiples of 50 Hz due to the averaging.
Simultaneous 50 Hz/60 Hz rejection is achieved when FS[10:0]
is set to 384 in full power mode or 30 in the mid power and low
power modes. Notches are placed at 10 Hz and multiples of 10 Hz,
thereby giving simultaneous 50 Hz and 60 Hz rejection. The
rejection at 50 Hz ± 0.5 Hz and 60 Hz ± 0.5 Hz is 42 dB typically.
Rev. E | Page 62 of 94
Data Sheet
AD7124-8
filters are realized by post filtering the output of the sinc3 filter.
The filter bits must be set to all 1s to enable the post filter. The post
filter option to use is selected using the POST_FILTER bits in the
filter register. In Figure 112, the blocks shown in gray are unused.
0
–10
–20
–40
–50
POST
FILTER
–60
MODULATOR
–70
SINC3/SINC4
FILTER
AVERAGING
BLOCK
–80
–90
13048-119
FILTER GAIN (dB)
–30
Figure 112. Post Filters
–100
30
0
60
90
120
150
FREQUENCY (Hz)
13048-118
–110
–120
Figure 111. Simultaneous 50 Hz and 60 Hz Rejection
POST FILTERS
The post filters provide rejection of 50 Hz and 60 Hz
simultaneously and allow the user to trade off settling time and
rejection. These filters can operate up to 27.27 SPS or can reject
up to 90 dB of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz interference. These
Table 62 shows the output data rates with the accompanying
settling times and the rejection.
When continuously converting on a single channel, the first
conversion requires a time of tSETTLE. Subsequent conversions
occur at 1/fADC. When multiple channels are enabled (either
manually or using the sequencer), the settling time is required
to generate a valid conversion on each enabled channel.
Table 62. AD7124-8 Post Filters: Output Data Rate, Settling Time (tSETTLE), and Rejection
Output Data
Rate (SPS)
27.27
25
20
16.67
1
f3dB
(Hz)
17.28
15.12
13.38
12.66
tSETTLE, Full Power
Mode (ms)
38.498
41.831
51.831
61.831
tSETTLE, Mid Power
Mode (ms)
38.998
42.331
52.331
62.331
tSETTLE, Low Power
Mode (ms)
39.662
42.995
52.995
62.995
Stable master clock used.
Rev. E | Page 63 of 94
Simultaneous Rejection of 50 Hz ± 1 Hz
and 60 Hz ± 1 Hz (dB)1
47
62
86
92
Data Sheet
0
–10
–20
–20
–30
–30
–50
–60
–60
–70
–70
–80
–90
–90
–100
–100
40
100
200
300
400
500
600
FREQUENCY (Hz)
Figure 113. DC to 600 Hz, 27.27 SPS Output Data Rate, 36.67 ms Settling Time
0
–10
–20
–20
–30
–30
FILTER GAIN (dB)
0
–50
–60
–80
–90
–90
–100
40
–100
55
60
65
70
Figure 114. Zoom in 40 Hz to 70 Hz, 27.27 SPS Output Data Rate, 36.67 ms
Settling Time
0
–20
–20
–30
–30
FILTER GAIN (dB)
0
–10
–60
–70
100
200
300
400
500
600
Figure 117. DC to 600 Hz, 20 SPS Output Data Rate, 50 ms Settling Time
0
–50
70
FREQUENCY (Hz)
–10
–40
65
–60
–70
FREQUENCY (Hz)
60
–50
–80
50
55
–40
–70
45
50
Figure 116. Zoom in 40 Hz to 70 Hz, 25 SPS Output Data Rate, 40 ms Settling Time
–10
–40
45
FREQUENCY (Hz)
13048-121
–40
–50
–60
–70
–80
–80
–90
–100
40
100
200
300
FREQUENCY (Hz)
400
500
600
13048-122
–90
–100
40
Figure 115. DC to 600 Hz, 25 SPS Output Data Rate, 40 ms Settling Time
45
50
55
FREQUENCY (Hz)
60
65
70
13048-125
FILTER GAIN (dB)
–50
–80
0
FILTER GAIN (dB)
–40
13048-124
–40
13048-123
FILTER GAIN (dB)
0
–10
13048-120
FILTER GAIN (dB)
AD7124-8
Figure 118. Zoom in 40 Hz to 70 Hz, 20 SPS Output Data Rate, 50 ms Settling Time
Rev. E | Page 64 of 94
AD7124-8
0
0
–10
–10
–20
–20
–30
–30
FILTER GAIN (dB)
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–90
–100
40
0
100
200
300
FREQUENCY (Hz)
400
500
600
13048-126
–90
–100
Figure 119. DC to 600 Hz, 16.667 SPS Output Data Rate, 60 ms Settling Time
45
50
55
FREQUENCY (Hz)
60
65
70
13048-127
FILTER GAIN (dB)
Data Sheet
Figure 120. Zoom in 40 Hz to 70 Hz, 16.667 SPS Output Data Rate, 60 ms
Settling Time
Rev. E | Page 65 of 94
AD7124-8
Data Sheet
SUMMARY OF FILTER OPTIONS
The AD7124-8 has several filter options. The filter that is
chosen affects the output data rate, settling time, the rms noise,
the stop band attenuation, and the 50 Hz and 60 Hz rejection.
Table 63 shows some sample configurations and the
corresponding performance in terms of throughput and 50 Hz
and 60 Hz rejection.
Table 63. Filter Summary1
Filter
Sinc4
Sinc4, Zero Latency
Sinc3
Fast Settling (Sinc4 + Sinc1)
Fast Settling (Sinc3 + Sinc1)
Post Filter
1
2
Power Mode
All
All
All
All
All
All
All
All
All
All
All
Full/mid
Low
Full/mid
Low
Full/mid
Low
Full/mid
Low
Full/mid
Low
Full/mid
Low
All
All
All
All
Output Data Rate (SPS)
10
50
50
60
12.5
12.5
15
10
50
50
60
50.53
43.64
42.11
36.36
8.4
7.27
53.33
48
44.44
40
8.89
8
27.27
25
20
16.67
REJ60
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
50 Hz Rejection (dB)2
120 dB (50 Hz and 60 Hz)
120 dB (50 Hz only)
82 dB (50 Hz and 60 Hz)
120 dB (60 Hz only)
120 dB (50 Hz only)
82 dB (50 Hz and 60 Hz)
120 dB (60 Hz only)
100 dB (50 Hz and 60 Hz)
95 dB (50 Hz only)
67 dB (50 Hz and 60 Hz)
95 dB (60 Hz only)
40 dB (60 Hz only)
40 dB (60 Hz only)
40 dB (50 Hz only)
40 dB (50 Hz only)
40 dB (50 Hz and 60 Hz)
40 dB (50 Hz and 60 Hz)
40 dB (60 Hz only)
40 dB (60 Hz only)
40 dB (50 Hz only)
40 dB (50 Hz only)
40 dB (50 Hz and 60 Hz)
40 dB (50 Hz and 60 Hz)
47 dB (50 Hz and 60 Hz)
62 dB (50 Hz and 60 Hz)
85 dB (50 Hz and 60 Hz)
90 dB (50 Hz and 60 Hz)
These calculations assume a stable master clock.
For fast settling mode, the 50 Hz/60 Hz rejection is measured in a band of ±0.5 Hz around 50 Hz and/or 60 Hz. For all other modes, a region of ±1 Hz around 50 Hz
and/or 60 Hz is used.
Rev. E | Page 66 of 94
Data Sheet
AD7124-8
DIAGNOSTICS
The AD7124-8 has numerous diagnostic functions on chip. Use
these features to ensure
is performed, check the status of the REF_DET_ERR bit at the
end of the calibration cycle.
•
•
•
•
•
The reference detect flag may be set when the device exits of
standby mode. Therefore, read the error register after exiting
standby mode to reset the flag to 0.
Read/write operations are to valid registers only
Only valid data is written to the on-chip registers
Appropriate decoupling is used on the LDOs
The external reference, if used, is present
The ADC modulator and filter are working within
specification
CALIBRATION, CONVERSION, AND SATURATION
ERRORS
Functions such as the reference and power supply voltages can
be selected as inputs to the ADC. The AD7124-8 can therefore
check the voltages connected to the device. The AD7124-8 also
generates an internal 20 mV signal that can be applied internally to
a channel by selecting the V_20MV_P to V_20MV_M channel
in the channel register. The PGA can be checked using this
function. As the PGA setting is increased, for example, the
signal as a percent of the analog input range is reduced by a
factor of two. This allows the user to check that the PGA is
functioning correctly.
REFERENCE DETECT
The AD7124-8 includes on-chip circuitry to detect if there is a
valid reference for conversions or calibrations when the user
selects an external reference as the reference source. This is a
valuable feature in applications such as RTDs or strain gages
where the reference is derived externally.
OUTPUT: 0 WHEN REFIN ≤0.7
1 WHEN REFIN 1) takes a time of four settling
periods.
Internal full-scale calibrations cannot be performed in the full power mode. So, if using the full-power mode, select mid or low
power mode for the internal full-scale calibration. This calibration is valid in full power mode as the same reference and gain are
used. When performing internal zero-scale and internal full-scale calibrations, the internal full-scale calibration must be
performed before the internal zero-scale calibration. Therefore, write 0x800000 to the offset register before performing any
internal full-scale calibration, which resets the offset register to its default value.
Rev. E | Page 81 of 94
AD7124-8
Mode
Value
0111
1000
1001
to1111
Data Sheet
Description
System zero-scale (offset) calibration. Connect the system zero-scale input to the channel input pins of the selected channel. RDY
goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode
following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A system zeroscale calibration is required each time the gain of a channel is changed. Select only one channel when full-scale calibration is
being performed. A system zero-scale calibration takes a time of one settling period to be performed.
System full-scale (gain) calibration. Connect the system full-scale input to the channel input pins of the selected channel. RDY goes
high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following
a calibration. The measured full-scale coefficient is placed in the gain register of the selected channel. A full-scale calibration is
required each time the gain of a channel is changed. Select only one channel when full-scale calibration is being performed. A
system full-scale calibration takes a time of one settling period to be performed.
Reserved.
DATA REGISTER
RS[5:0] = 0, 0, 0, 0, 1, 0
Power-On/Reset = 0x000000
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from
this register, the RDY bit/pin is set.
IO_CONTROL_1 REGISTER
RS[5:0] = 0, 0, 0, 0, 1, 1
Power-On/Reset = 0x000000
Table 69 outlines the bit designations for the register. Bit 23 is the first bit of the data stream. The number in parentheses indicates the
power-on/reset default status of that bit.
Bit 7
GPIO_DAT4 (0)
PDSW (0)
Bit 6
Bit 5
GPIO_DAT3 (0) GPIO_DAT2 (0)
0 (0)
IOUT1_CH (0)
Bit 4
GPIO_DAT1 (0)
IOUT1 (0)
Bit 3
GPIO_CTRL4 (0)
Bit 2
GPIO_CTRL3 (0)
Bit 1
GPIO_CTRL2 (0)
IOUT0 (0)
IOUT0_CH (0)
Bit 0
GPIO_CTRL1 (0)
Table 69. IO_CONTROL_1 Register Bit Descriptions
Bits
23
Bit Name
GPIO_DAT4
22
GPIO_DAT3
21
GPIO_DAT2
20
GPIO_DAT1
19
GPIO_CTRL4
Description
Digital Output P4. When GPIO_CTRL4 is set, the GPIO_DAT4 bit sets the value of the P4 general-purpose
output pin. When GPIO_DAT4 is high, the P4 output pin is high. When GPIO_DAT4 is low, the P4 output
pin is low. When the IO_CONTROL_1 register is read, the GPIO_DAT4 bit reflects the status of the P4 pin if
GPIO_CTRL4 is set.
Digital Output P3. When GPIO_CTRL3 is set, the GPIO_DAT3 bit sets the value of the P3 general-purpose
output pin. When GPIO_DAT3 is high, the P3 output pin is high. When GPIO_DAT3 is low, the P3 output
pin is low. When the IO_CONTROL_1 register is read, the GPIO_DAT3 bit reflects the status of the P3 pin if
GPIO_CTRL3 is set.
Digital Output P2. When GPIO_CTRL2 is set, the GPIO_DAT2 bit sets the value of the P2 general-purpose
output pin. When GPIO_DAT2 is high, the P2 output pin is high. When GPIO_DAT2 is low, the P2 output
pin is low. When the IO_CONTROL_1 register is read, the GPIO_DAT2 bit reflects the status of the P2 pin if
GPIO_CTRL2 is set.
Digital Output P1. When GPIO_CTRL1 is set, the GPIO_DAT1 bit sets the value of the P1 general-purpose
output pin. When GPIO_DAT1 is high, the P1 output pin is high. When GPIO_DAT1 is low, the P1 output
pin is low. When the IO_CONTROL_1 register is read, the GPIO_DAT1 bit reflects the status of the P1 pin if
GPIO_CTRL1 is set.
Digital Output P4 enable. When GPIO_CTRL4 is set, the digital output P4 is active. When GPIO_CTRL4 is
cleared, the pin functions as analog input pin AIN5.
Rev. E | Page 82 of 94
Data Sheet
Bits
18
Bit Name
GPIO_CTRL3
17
GPIO_CTRL2
16
GPIO_CTRL1
15
PDSW
14
13:11
0
IOUT1
10:8
IOUT0
7:4
IOUT1_CH
AD7124-8
Description
Digital Output P3 enable. When GPIO_CTRL3 is set, the digital output P3 is active. When GPIO_CTRL3 is
cleared, the pin functions as analog input pin AIN4.
Digital Output P2 enable. When GPIO_CTRL2 is set, the digital output P2 is active. When GPIO_CTRL2 is
cleared, the pin functions as analog input pin AIN3.
Digital Output P1 enable. When GPIO_CTRL1 is set, the digital output P1 is active. When GPIO_CTRL1 is
cleared, the pin functions as analog input pin AIN2.
Bridge power-down switch control bit. Set this bit to close the bridge power-down switch PDSW to
AGND. The switch can sink up to 30 mA. Clear this bit to open the bridge power-down switch. When the
ADC is placed in standby mode, the bridge power-down switch remains active.
This bit must be programmed with a Logic 0 for correct operation.
These bits set the value of the excitation current for IOUT1.
000 = off.
001 = 50 µA.
010 = 100 µA
011 = 250 µA.
100 = 500 µA.
101 = 750 µA.
110 = 1000 µA
111 = 1000 µA.
These bits set the value of the excitation current for IOUT0.
000 = off.
001 = 50 µA.
010 = 100 µA
011 = 250 µA.
100 = 500 µA.
101 = 750 µA.
110 = 1000 µA
111 = 1000 µA.
Channel select bits for the excitation current for IOUT1.
0000 = IOUT1 is available on the AIN0 pin.
0001 = IOUT1 is available on the AIN1 pin.
0010 = IOUT1 is available on the AIN2 pin.
0011 = IOUT1 is available on the AIN3 pin.
0100 = IOUT1 is available on the AIN4 pin.
0101 = IOUT1 is available on the AIN5 pin.
0110 = IOUT1 is available on the AIN6 pin.
0111 = IOUT1 is available on the AIN7 pin.
1000 = IOUT1 is available on the AIN8 pin.
1001 = IOUT1 is available on the AIN9 pin.
1010 = IOUT1 is available on the AIN10 pin.
1011 = IOUT1 is available on the AIN11 pin.
1100 = IOUT1 is available on the AIN12 pin.
1101 = IOUT1 is available on the AIN13 pin.
1110 = IOUT1 is available on the AIN14 pin.
0111 = IOUT1 is available on the AIN15 pin.
Rev. E | Page 83 of 94
AD7124-8
Bits
3:0
Data Sheet
Bit Name
IOUT0_CH
Description
Channel select bits for the excitation current for IOUT0.
0000 = IOUT0 is available on the AIN0 pin.
0001 = IOUT0 is available on the AIN1 pin.
0010 = IOUT0 is available on the AIN2 pin.
0011 = IOUT0 is available on the AIN3 pin.
0100 = IOUT0 is available on the AIN4 pin.
0101 = IOUT0 is available on the AIN5 pin.
0110 = IOUT0 is available on the AIN6 pin.
0111 = IOUT0 is available on the AIN7 pin.
1000 = IOUT0 is available on the AIN8 pin.
1001 = IOUT0 is available on the AIN9 pin.
1010 = IOUT0 is available on the AIN10 pin.
1011 = IOUT0 is available on the AIN11 pin.
1100 = IOUT0 is available on the AIN12 pin.
1101 = IOUT0 is available on the AIN13 pin.
1110 = IOUT0 is available on the AIN14 pin.
1111 = IOUT0 is available on the AIN15 pin.
IO_CONTROL_2 REGISTER
RS[5:0] = 0, 0, 0, 1, 0, 0
Power-On/Reset = 0x0000
Table 70 outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the
power-on/reset default status of that bit. The internal bias voltage can be enabled on multiple channels.
Bit 7
VBIAS15 (0)
VBIAS7 (0)
Bit 6
VBIAS14 (0)
VBIAS6 (0)
Bit 5
VBIAS13 (0)
VBIAS5 (0)
Bit 4
VBIAS12 (0)
VBIAS4 (0)
Bit 3
VBIAS11 (0)
VBIAS3 (0)
Bit 2
VBIAS10 (0)
VBIAS2 (0)
Bit 1
VBIAS9 (0)
VBIAS1 (0)
Bit 0
VBIAS8 (0)
VBIAS0 (0)
Table 70. IO_CONTROL_2 Register Bit Descriptions
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
VBIAS15
VBIAS14
VBIAS13
VBIAS12
VBIAS11
VBIAS10
VBIAS9
VBIAS8
VBIAS7
VBIAS6
VBIAS5
VBIAS4
VBIAS3
VBIAS2
VBIAS1
VBIAS0
Description
Enable the bias voltage on the AIN15 channel. When set, the internal bias voltage is available on AIN15.
Enable the bias voltage on the AIN14 channel. When set, the internal bias voltage is available on AIN14.
Enable the bias voltage on the AIN13 channel. When set, the internal bias voltage is available on AIN13.
Enable the bias voltage on the AIN12 channel. When set, the internal bias voltage is available on AIN12.
Enable the bias voltage on the AIN11 channel. When set, the internal bias voltage is available on AIN11.
Enable the bias voltage on the AIN10 channel. When set, the internal bias voltage is available on AIN10.
Enable the bias voltage on the AIN9 channel. When set, the internal bias voltage is available on AIN9.
Enable the bias voltage on the AIN8 channel. When set, the internal bias voltage is available on AIN8.
Enable the bias voltage on the AIN7 channel. When set, the internal bias voltage is available on AIN7.
Enable the bias voltage on the AIN6 channel. When set, the internal bias voltage is available on AIN6.
Enable the bias voltage on the AIN5 channel. When set, the internal bias voltage is available on AIN5.
Enable the bias voltage on the AIN4 channel. When set, the internal bias voltage is available on AIN4.
Enable the bias voltage on the AIN3 channel. When set, the internal bias voltage is available on AIN3.
Enable the bias voltage on the AIN2 channel. When set, the internal bias voltage is available on AIN2.
Enable the bias voltage on the AIN1 channel. When set, the internal bias voltage is available on AIN1.
Enable the bias voltage on the AIN0 channel. When set, the internal bias voltage is available on AIN0.
Rev. E | Page 84 of 94
Data Sheet
AD7124-8
ID REGISTER
RS[5:0] = 0, 0, 0, 1, 0, 1
Power-On/Reset = 0x14 (AD7124-8)/0x16 (AD7124-8 B Grade)
The identification number for the AD7124-8 is stored in the ID register. This is a read only register.
ERROR REGISTER
RS[5:0] = 0, 0, 0, 1, 1, 0
Power-On/Reset = 0x000000
Diagnostics, such as checking overvoltages and checking the SPI interface, are included on the AD7124-8. The error register contains the
flags for the different diagnostic functions. The functions are enabled and disabled using the ERROR_EN register.
Table 71 outlines the bit designations for the register. Bit 23 is the first bit of the data stream. The number in parentheses indicates the
power-on/reset default status of that bit.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AINM_UV_ERR
(0)
SPI_READ_ERR
(0)
LDO_CAP_ERR
(0)
REF_DET_ERR
(0)
SPI_WRITE_ERR
(0)
ADC_CAL_ERR
(0)
0 (0)
ADC_CONV_ERR
(0)
DLDO_PSM_ERR
(0)
MM_CRC_ERR
(0)
ADC_SAT_ERR
(0)
0 (0)
0 (0)
AINP_OV_ERR
(0)
ALDO_PSM_ERR
(0)
AINP_UV_ERR (0)
AINM_OV_ERR (0)
SPI_IGNORE_ERR
(0)
SPI_SCLK_CNT_ERR
(0)
SPI_CRC_ERR
(0)
ROM_CRC_ERR
(0)
Table 71. Error Register Bit Descriptions
Bits
23:20
19
Bit Name
0
LDO_CAP_ERR
18
ADC_CAL_ERR
17
16
15
14
13
12
11
ADC_CONV_ERR
ADC_SAT_ERR
AINP_OV_ERR
AINP_UV_ERR
AINM_OV_ERR
AINM_UV_ERR
REF_DET_ERR
10
9
8
7
6
0
DLDO_PSM_ERR
0
ALDO_PSM_ERR
SPI_IGNORE_ERR
5
SPI_SCLK_CNT_ERR
4
3
2
1
SPI_READ_ERR
SPI_WRITE_ERR
SPI_CRC_ERR
MM_CRC_ERR
0
ROM_CRC_ERR
Description
These bits must be programmed with a Logic 0 for correct operation.
Analog/digital LDO decoupling capacitor check. This flag is set if the decoupling capacitors required for the
analog and digital LDOs are not connected to the AD7124-8.
Calibration check. If a calibration is initiated but not completed, this flag is set to indicate that an error
occurred during the calibration. The associated calibration register is not updated.
This bit indicates whether a conversion is valid. This flag is set if an error occurs during a conversion.
ADC saturation flag. This flag is set if the modulator is saturated during a conversion.
Overvoltage detection on AINP.
Undervoltage detection on AINP.
Overvoltage detection on AINM.
Undervoltage detection on AINM.
Reference detection. This flag indicates when the external reference being used by the ADC is open circuit or
less than 0.7 V.
This bit must be programmed with a Logic 0 for correct operation.
Digital LDO error. This flag is set if an error is detected with the digital LDO.
This bit must be programmed with a Logic 0 for correct operation.
Analog LDO error. This flag is set if an error is detected with the analog LDO voltage.
When a CRC check of the internal registers is being performed, the on-chip registers cannot be written to.
User write instructions are ignored by the ADC. This bit is set when the CRC check of the registers is
occurring. The bit is cleared when the check is complete; write operations can only be performed then.
All serial communications are some multiple of eight bits. This bit is set when the number of SCLK cycles is
not a multiple of eight.
This bit is set when an error occurs during an SPI read operation.
This bit is set when an error occurs during an SPI write operation.
This bit is set if an error occurs in the CRC check of the serial communications.
Memory map error. A CRC calculation is performed on the memory map each time that the registers are
written to. Following this, periodic CRC checks are performed on the on-chip registers. If the register
contents have changed, the MM_CRC_ERR bit is set.
ROM error. A CRC calculation is performed on the ROM contents (contains the default register values) on
power-up. If the contents have changed, the ROM_CRC_ERR bit is set.
Rev. E | Page 85 of 94
AD7124-8
Data Sheet
ERROR_EN REGISTER
RS[5:0] = 0, 0, 0, 1, 1, 1
Power-On/Reset = 0x000040
All the diagnostic functions can be enabled or disabled by setting the appropriate bits in this register.
Table 72 outlines the bit designations for the register. Bit 23 is the first bit of the data stream. The number in parentheses indicates the
power-on/reset default status of that bit.
Bit 7
0 (0)
AINP_OV_
ERR_EN (0)
ALDO_PSM_
ERR_EN (0)
Bit 6
MCLK_CNT_
EN (0)
AINP_UV_
ERR_EN (0)
SPI_IGNORE_
ERR_EN (0)
Bit 5
LDO_CAP_CHK_
TEST_EN (0)
AINM_OV_ERR_
EN (0)
SPI_SCLK_CNT_
ERR_EN (0)
Bit 4
Bit 3
LDO_CAP_CHK (0)
AINM_UV_
ERR_EN (0)
SPI_READ_
ERR_EN (0)
REF_DET_ERR_
EN (0)
SPI_WRITE_
ERR_EN (0)
Bit 2
ADC_CAL_ERR_
EN (0)
DLDO_PSM_
TRIP_TEST_EN (0)
SPI_CRC_ERR_
EN (0)
Bit 1
ADC_CONV_ERR_
EN (0)
DLDO_PSM_ERR_
EN (0)
MM_CRC_ERR_
EN (0)
Bit 0
ADC_SAT_
ERR_EN (0)
ALDO_PSM_
TRIP_TEST_EN (0)
ROM_CRC_ERR_
EN (0)
Table 72. ERROR_EN Register Bit Descriptions
Bits
23
22
Bit Name
0
MCLK_CNT_EN
21
LDO_CAP_CHK_TEST_EN
20:19
LDO_CAP_CHK
18
17
ADC_CAL_ERR_EN
ADC_CONV_ERR_EN
16
15
14
13
12
11
ADC_SAT_ERR_EN
AINP_OV_ERR_EN
AINP_UV_ERR_EN
AINM_OV_ERR_EN
AINM_UV_ERR_EN
REF_DET_ERR_EN
10
DLDO_PSM_TRIP_TEST_EN
9
DLDO_PSM_ERR_ERR
8
ALDO_PSM_TRIP_TEST_EN
7
ALDO_PSM_ERR_EN
6
SPI_IGNORE_ERR_EN
Description
This bit must be programmed with a Logic 0 for correct operation.
Master clock counter. When this bit is set, the master clock counter is enabled and the result is
reported via the MCLK_COUNT register. The counter monitors the master clock being used by the
ADC. If an external clock is the clock source, the MCLK counter monitors this external clock.
Similarly, if the on-chip oscillator is selected as the clock source to the ADC, the MCLK counter
monitors the on-chip oscillator.
Test of analog/digital LDO decoupling capacitor check. When this bit is set, the decoupling
capacitor is internally disconnected from the LDO, forcing a fault condition. This allows the user to
test the circuitry that is used for the analog and digital LDO decoupling capacitor check.
Analog/digital LDO decoupling capacitor check. These bits enable the capacitor check. When a
check is enabled, the ADC checks for the presence of the external decoupling capacitor on the
selected supply. When the check is complete, the LDO_CAP_CHK bits are both reset to 0.
00 = check is not enabled.
01 = check the analog LDO capacitor.
10 = check the digital LDO capacitor.
11 = check is not enabled.
When this bit is set, the calibration fail check is enabled.
When this bit is set, the conversions are monitored and the ADC_CONV_ERR bit is set when a
conversion fails.
When this bit is set, the ADC modulator saturation check is enabled.
When this bit is set, the overvoltage monitor on all enabled AINP channels is enabled.
When this bit is set, the undervoltage monitor on all enabled AINP channels is enabled.
When this bit is set, the overvoltage monitor on all enabled AINM channels is enabled.
When this bit is set, the undervoltage monitor on all enabled AINM channels is enabled.
When this bit is set, any external reference being used by the ADC is continuously monitored. An
error is flagged if the external reference is open circuit or has a value of less than 0.7 V.
Checks the test mechanism that monitors the digital LDO. When this bit is set, the input to the test
circuit is tied to DGND instead of the LDO output. Set the DLDO_PSM_ERR bit in the error register.
When this bit is set, the digital LDO voltage is continuously monitored. The DLDO_PSM_ERR bit in
the error register is set if the voltage being output from the digital LDO is outside specification.
Checks the test mechanism that monitors the analog LDO. When this bit is set, the input to the
test circuit is tied to AVSS instead of the LDO output. Set the ALDO_PSM_ERR bit in the error
register.
When this bit is set, the analog LDO voltage is continuously monitored. The ALDO_PSM_ERR bit in
the error register is set if the voltage being output from the analog LDO is outside specification.
When a CRC check of the internal registers is being performed, the on-chip registers cannot be
written to. User write instructions are ignored by the ADC. Set this bit so that the SPI_IGNORE_ERR
bit in the error register informs the user when write operations must not be performed.
Rev. E | Page 86 of 94
Data Sheet
AD7124-8
Bits
5
Bit Name
SPI_SCLK_CNT_ERR_EN
4
SPI_READ_ERR_EN
3
SPI_WRITE_ERR_EN
2
SPI_CRC_ERR_EN
1
MM_CRC_ERR_EN
0
ROM_CRC_ERR_EN
Description
When this bit is set, the SCLK counter is enabled. All read and write operations to the ADC are
multiples of eight bits. For every serial communication, the SCLK counter counts the number of
SCLK pulses. CS must be used to frame each read and write operation. If the number of SCLK
pulses used during a communication is not a multiple of eight, the SPI_SCLK_CNT_ERR bit in the
error register is set. For example, a glitch on the SCLK pin during a read or write operation can be
interpreted as an SCLK pulse. In this case, the SPI_SCLK_CNT_ERR bit is set as there is an excessive
number of SCLK pulses detected. CS_EN in the ADC_CONTROL register must be set to 1 when the
SCLK counter function is being used.
When this bit is set, the SPI_READ_ERR bit in the error register is set when an error occurs during a
read operation. An error occurs if the user attempts to read from invalid addresses.
CS_EN in the ADC_CONTROL register must be set to 1 when the SPI read check function is being
used.
When this bit is set, the SPI_WRITE_ERR bit in the error register is set when an error occurs during a
write operation. An error occurs if the user attempts to write to invalid addresses or write to readonly registers. CS_EN in the ADC_CONTROL register must be set to 1 when the SPI write check
function is being used.
This bit enables a CRC check of all read and write operations. The SPI_CRC_ERR bit in the error
register is set if the CRC check fails. In addition, an 8-bit CRC word is appended to all data read
from the AD7124-8.
When this bit is set, a CRC calculation is performed on the memory map each time that the
registers are written to. Following this, periodic CRC checks are performed on the on-chip
registers. If the register contents have changed, the MM_CRC_ERR bit is set.
When this bit is set, a CRC calculation is performed on the ROM contents on power-on. If the ROM
contents have changed, the ROM_CRC_ERR bit is set.
MCLK_COUNT REGISTER
RS[5:0] = 0, 0, 1, 0, 0, 0
Power-On/Reset = 0x00
The master clock frequency can be monitored using this register.
Table 73 outlines the bit designations for the register. Bit 7 is the first bit of the data stream. The number in parentheses indicates the
power-on/reset default status of that bit.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
MCLK_COUNT (0)
Bit 2
Bit 1
Bit 0
Table 73. MCLK_COUNT Register Bit Descriptions
Bits
7:0
Bit Name
MCLK_COUNT
Description
This register allows the user to determine the frequency of the internal/external oscillator. Internally, a clock
counter increments every 131 pulses of the sampling clock (614.4 kHz in full power mode, 153.6 kHz in mid power
mode, and 768 kHz in low power mode). The 8-bit counter wraps around on reaching its maximum value. The
counter output is read back via this register.
Note that the incrementation of the register is asynchronous to the register read. If a register read coincides with
the register incrementation, it is possible to read an invalid value. To prevent this, read the register four times rather
than once, then read the register four times again at a later point. By reading four values, it is possible to identify the
correct register value at the start and at the end of the timing instants.
Rev. E | Page 87 of 94
AD7124-8
Data Sheet
CHANNEL REGISTERS
RS[5:0] = 0, 0, 1, 0, 0, 1 to 0, 1, 1, 0, 0, 0
Power-On/Reset = 0x8001 for CHANNEL_0; all other channel registers are set to 0x0001
Sixteen channel registers are included on the AD7124-8, CHANNEL_0 to CHANNEL_15. The channel registers begin at Address 0x09
(CHANNEL_0) and end at Address 0x18 (CHANNEL_15). Via each register, the user can configure the channel (AINP input and AINM
input), enable or disable the channel, and select the setup. The setup is selectable from eight different options defined by the user. When
the ADC converts, it automatically sequences through all enabled channels. This allows the user to sample some channels multiple times
in a sequence, if required. In addition, it allows the user to include diagnostic functions in a sequence also.
Table 74 outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the
power-on/reset default status of that bit.
Bit 7
Enable (1)
Bit 6
Bit 5
Bit 4
Setup (0)
Bit 3
(0)
AINP[2:0] (000)
Bit 2
Bit 1
0 (0)
AINM[4:0] (00001)
Bit 0
AINP[4:3] (00)
Table 74. Channel Register Bit Descriptions
Bits
15
Bit Name
Enable
14:12
Setup
11:10
9:5
0
AINP[4:0]
Description
Channel enable bit. Setting this bit enables the device channel for the conversion sequence. By default, only the
enable bit for Channel 0 is set. The order of conversions starts with the lowest enabled channel, then cycles
through successively higher channel numbers, before wrapping around to the lowest channel again.
When the ADC writes a result for a particular channel, the four LSBs of the status register are set to the channel
number, 0 to 15. This allows the channel the data corresponds to be identified. When the DATA_STATUS bit in the
ADC_CONTROL register is set, the contents of the status register are appended to each conversion when it is
read. Use this function when several channels are enabled to determine to which channel the conversion value
read corresponds.
Setup select. These bits identify which of the eight setups are used to configure the ADC for this channel. A setup
comprises a set of four registers: analog configuration, output data rate/filter selection, offset register, and gain
register. All channels can use the same setup, in which case the same 3-bit value must be written to these bits on
all active channels. Alternatively, up to eight channels can be configured differently.
These bits must be programmed with a Logic 0 for correct operation.
Positive analog input AINP input select. These bits select which of the analog inputs is connected to the positive
input for this channel.
00000 = AIN0 (default).
00001 = AIN1.
00010 = AIN2.
00011 = AIN3.
00100 = AIN4.
00101 = AIN5.
00110 = AIN6.
00111 = AIN7.
01000 = AIN8.
01001 = AIN9.
01010 = AIN10.
01011 = AIN11.
01100 = AIN12.
01101 = AIN13.
01110 = AIN14.
01111 = AIN15.
10000 = temperature sensor.
10001 = AVSS.
10010 = internal reference.
10011 = DGND.
10100 = (AVDD − AVSS)/6+. Use in conjunction with (AVDD − AVSS)/6− to monitor supply AVDD − AVSS.
10101 = (AVDD − AVSS)/6−. Use in conjunction with (AVDD − AVSS)/6+ to monitor supply AVDD − AVSS.
10110 = (IOVDD − DGND)/6+. Use in conjunction with (IOVDD − DGND)/6− to monitor IOVDD − DGND.
10111 = (IOVDD − DGND)/6−. Use in conjunction with (IOVDD − DGND)/6+ to monitor IOVDD − DGND.
Rev. E | Page 88 of 94
Data Sheet
Bits
Bit Name
4:0
AINM[4:0]
AD7124-8
Description
11000 = (ALDO − AVSS)/6+. Use in conjunction with (ALDO − AVSS)/6− to monitor the analog LDO.
11001 = (ALDO − AVSS)/6−. Use in conjunction with (ALDO − AVSS)/6+ to monitor the analog LDO.
11010 = (DLDO − DGND)/6+. Use in conjunction with (DLDO − DGND)/6− to monitor the digital LDO.
11011 = (DLDO − DGND)/6−. Use in conjunction with (DLDO − DGND)/6+ to monitor the digital LDO.
11100 = V_20MV_P. Use in conjunction with V_20MV_M to apply a 20 mV p-p signal to the ADC.
11101 = V_20MV_M. Use in conjunction with V_20MV_P to apply a 20 mV p-p signal to the ADC.
11110 = Reserved.
11111 = Reserved.
Negative analog input AINM input select. These bits select which of the analog inputs is connected to the
negative input for this channel.
00000 = AIN0.
00001 = AIN1 (default).
00010 = AIN2.
00011 = AIN3.
00100 = AIN4.
00101 = AIN5.
00110 = AIN6.
00111 = AIN7.
01000 = AIN8.
01001 = AIN9.
01010 = AIN10.
01011 = AIN11.
01100 = AIN12.
01101 = AIN13.
01110 = AIN14.
01111 = AIN15.
10000 = temperature sensor.
10001 = AVSS.
10010 = internal reference.
10011 = DGND.
10100 = (AVDD − AVSS)/6+. Use in conjunction with (AVDD − AVSS)/6− to monitor supply AVDD − AVSS.
10101 = (AVDD − AVSS)/6−. Use in conjunction with (AVDD − AVSS)/6+ to monitor supply AVDD − AVSS.
10110 = (IOVDD − DGND)/6+. Use in conjunction with (IOVDD − DGND)/6− to monitor IOVDD − DGND.
10111 = (IOVDD − DGND)/6−. Use in conjunction with (IOVDD − DGND)/6+ to monitor IOVDD − DGND.
11000 = (ALDO − AVSS)/6+. Use in conjunction with (ALDO − AVSS)/6− to monitor the analog LDO.
11001 = (ALDO − AVSS)/6−. Use in conjunction with (ALDO − AVSS)/6+ to monitor the analog LDO.
11010 = (DLDO − DGND)/6+. Use in conjunction with (DLDO − DGND)/6− to monitor the digital LDO.
11011 = (DLDO − DGND)/6−. Use in conjunction with (DLDO − DGND)/6+ to monitor the digital LDO.
11100 = V_20MV_P. Use in conjunction with V_20MV_M to apply a 20 mV p-p signal to the ADC.
11101 = V_20MV_M. Use in conjunction with V_20MV_P to apply a 20 mV p-p signal to the ADC.
11110 = Reserved.
11111 = Reserved.
Rev. E | Page 89 of 94
AD7124-8
Data Sheet
CONFIGURATION REGISTERS
RS[5:0] = 0, 1, 1, 0, 0, 1 to 1, 0, 0, 0, 0, 0
Power-On/Reset = 0x0860
The AD7124-8 has eight configuration registers, CONFIG_0 to CONFIG_7. Each configuration register is associated with a setup;
CONFIG_x is associated with Setup x. In the configuration register, the reference source, polarity, reference buffers are configured. Table 75
outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the power-on/
reset default status of that bit.
Bit 7
Bit 6
REF_BUFM (0)
Bit 5
0 (0)
AIN_BUFP (1) AIN_BUFM (1)
Bit 4
Bit 3
Bipolar (1)
REF_SEL (0)
Bit 2
Bit 1
Burnout (0)
Bit 0
REF_BUFP (0)
PGA (0)
Table 75. Configuration Register Bit Descriptions
Bits
15:12
11
Bit Name
0
Bipolar
10:9
Burnout
8
REF_BUFP
7
REF_BUFM
6
AIN_BUFP
5
AIN_BUFM
4:3
REF_SEL
2:0
PGA
Description
These bits must be programmed with a Logic 0 for correct operation.
Polarity select bit. When this bit is set, bipolar operation is selected. When this bit is cleared, unipolar operation is
selected.
These bits select the magnitude of the sensor burnout detect current source.
00 = burnout current source off (default).
01 = burnout current source on, 0.5 μA.
10 = burnout current source on, 2 μA.
11 = burnout current source on, 4 μA.
Buffer enable on REFINx(+). When this bit is set, the positive reference input (internal or external) is buffered. When
this bit is cleared, the positive reference input (internal or external) is unbuffered.
Buffer enable on REFINx(−). When this bit is set, the negative reference input (internal or external) is buffered. When
this bit is cleared, the negative reference input (internal or external) is unbuffered.
Buffer enable on AINP. When this bit is set, the selected positive analog input pin is buffered. When this bit is cleared,
the selected positive analog input pin is unbuffered.
Buffer enable on AINM. When this bit is set, the selected negative analog input pin is buffered. When this bit is
cleared, the selected negative analog input pin is unbuffered.
Reference source select bits. These bits select the reference source to use when converting on any channels using
this configuration register.
00 = REFIN1(+)/REFIN1(−).
01 = REFIN2(+)/REFIN2(−).
10 = internal reference.
11 = AVDD.
Gain select bits. These bits select the gain to use when converting on any channels using this configuration register.
PGA
Gain
Input Range When VREF = 2.5 V (Bipolar Mode)
000
1
±2.5 V
001
2
±1.25 V
010
4
± 625 mV
011
8
±312.5 mV
100
16
±156.25 mV
101
32
±78.125 mV
110
64
±39.06 mV
111
128
±19.53 mV
Rev. E | Page 90 of 94
Data Sheet
AD7124-8
FILTER REGISTERS
RS[5:0] = 1, 0, 0, 0, 0, 1 to 1, 0, 1, 0, 0, 0
Power-On/Reset = 0x060180
The AD7124-8 has eight filter registers, FILTER_0 to FILTER_7. Each filter register is associated with a setup; FILTER_x is associated
with Setup x. In the filter register, the filter type and output word rate are set.
Table 76 outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the
power-on/reset default status of that bit.
Bit 7
Bit 6
Filter (0)
Bit 5
Bit 4
REJ60(0)
Bit 3
0(0)
Bit 2
POST_FILTER(0)
Bit 1
Bit 0
SINGLE_CYCLE(0)
FS[10:8](0)
FS[7:0](0)
Table 76. Filter Register Bit Descriptions
Bits
23:21
Bit Name
Filter
20
REJ60
19:17
POST_FILTER
16
SINGLE_CYCLE
15:11
10:0
0
FS[10:0]
Description
Filter type select bits. These bits select the filter type.
000 = sinc4 filter (default).
001 = reserved.
010 = sinc3 filter.
011 = reserved.
100 = fast settling filter using the sinc4 filter. The sinc4 filter is followed by an averaging block, which results
in a settling time equal to the conversion time. In full power and mid power modes, averaging by 16 occurs
whereas averaging by 8 occurs in low power mode.
101 = fast settling filter using the sinc3 filter. The sinc3 filter is followed by an averaging block, which results
in a settling time equal to the conversion time. In full power and mid power modes, averaging by 16 occurs
whereas averaging by 8 occurs in low power mode.
110 = reserved.
111 = post filter enabled. The AD7124-8 includes several post filters, selectable using the POST_FILTER bits.
The post filters have single cycle settling, the settling time being considerably better than a simple
sinc3/sinc4 filter. These filters offer excellent 50 Hz and60 Hz rejection.
When this bit is set, a first order notch is placed at 60 Hz when the first notch of the sinc filter is at 50 Hz.
This allows simultaneous 50 Hz and 60 Hz rejection.
Post filter type select bits. When the filter bits are set to 1, the sinc3 filter is followed by a post filter that
offers good 50 Hz and 60 Hz rejection at output data rates that have zero latency approximately.
POST_FILTER
Output Data Rate (SPS)
Rejection at 50 Hz and 60 Hz ± 1 Hz (dB)
000
Reserved
Not applicable
010
Reserved
Not applicable
010
27.27
47
011
25
62
100
Reserved
Not applicable
101
20
86
110
16.7
92
111
Reserved
Not applicable
Single cycle conversion enable bit. When this bit is set, the AD7124-8 settles in one conversion cycle so that
it functions as a zero latency ADC. This bit has no effect when multiple analog input channels are enabled
or when the single conversion mode is selected. When the fast filters are used, this bit has no effect.
These bits must be programmed with a Logic 0 for correct operation.
Filter output data rate select bits. These bits set the output data rate of the sinc3 filter, sinc4 filter, and fast
settling filters. In addition, they affect the position of the first notch of the sinc filter and the cutoff
frequency. In association with the gain selection, they also determine the output noise and, therefore, the
effective resolution of the device (see noise tables). FS can have a value from 1 to 2047.
Rev. E | Page 91 of 94
AD7124-8
Data Sheet
OFFSET REGISTERS
GAIN REGISTERS
RS[5:0] = 1, 0, 1, 0, 0, 1 to 1, 1, 0, 0, 0, 0
Power-On/Reset = 0x800000
RS[5:0] = 1, 1, 0, 0, 0, 1 to 1, 1, 1, 0, 0, 0
Power-On/Reset = 0x5XXXXX
The AD7124-8 has eight offset registers, OFFSET_0 to OFFSET_7.
Each offset register is associated with a setup; OFFSET_x is
associated with Setup x. The offset registers are 24-bit registers
and hold the offset calibration coefficient for the ADC and its
power-on reset value is 0x800000. Each of these registers is a
read/write register. These registers are used in conjunction with
the associated gain register to form a register pair. The poweron reset value is automatically overwritten if an internal or
system zero-scale calibration is initiated by the user. The ADC
must be placed in standby mode or idle mode when writing to
the offset registers.
The AD7124-8 has eight gain registers, GAIN_0 to GAIN_7. Each
gain register is associated with a setup; GAIN_x is associated
with Setup x. The gain registers are 24-bit registers and hold the
full-scale calibration coefficient for the ADC. The AD7124-8 is
factory calibrated to a gain of 1. The gain register contains this
factory generated value on power-on and after a reset. The gain
registers are read/write registers. However, when writing to the
registers, the ADC must be placed in standby mode or idle
mode. The default value is automatically overwritten if an
internal or system full-scale calibration is initiated by the user
or the full-scale registers are written to.
Rev. E | Page 92 of 94
Data Sheet
AD7124-8
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
32
25
1
24
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
8
17
0.80
0.75
0.70
TOP VIEW
PKG-004570
SEATING
PLANE
9
16
0.20 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
10-20-2017-C
TOP VIEW
0.50
0.40
0.30
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
Figure 132. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
25
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
32
24
1
0.50
BSC
3.70
3.60 SQ
3.50
EXPOSED
PAD
17
TOP VIEW
1.00
0.95
0.85
PKG-004754/005209
SEATING
PLANE
END VIEW
0.50
0.40
0.30
8
9
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-5.
Figure 133. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.95 mm Package Height
(CP-32-30)
Dimensions shown in millimeters
Rev. E | Page 93 of 94
0.20 MIN
01-16-2016-A
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
AD7124-8
Data Sheet
ORDERING GUIDE
Model1
AD7124-8BCPZ
AD7124-8BCPZ-RL
AD7124-8BCPZ-RL7
AD7124-8BBCPZ
AD7124-8BBCPZ-RL
AD7124-8BBCPZ-RL7
EVAL-AD7124-8SDZ
EVAL-SDP-CB1Z
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Evaluation Controller Board
Z = RoHS Compliant Part.
©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13048-0-4/18(E)
Rev. E | Page 94 of 94
Package Option
CP-32-12
CP-32-12
CP-32-12
CP-32-30
CP-32-30
CP-32-30
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