AD7134BCPZ-RL7

厂商：
AD(亚德诺)
封装：
LFCSP-56_8X8MM-EP
描述：
IC ADC 24BIT SIGMA-DELTA 56LFCSP

数据手册：

下载AD7134BCPZ-RL7.pdf

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数据手册
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AD7134BCPZ-RL7 数据手册

24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC AD7134 Data Sheet FEATURES Sinc3 filter with 50 Hz/60 Hz rejection Crosstalk: 130.7 dBFS Daisy-chaining CRC error checking on data and SPI interface Two power modes: high performance mode and low power mode Power supply: 4.5 V to 5.5 V and 1.65 V to 1.95 V 1.8 V IOVDD level External reference: 4.096 V or 5 V Crystal or external CMOS clock of 48 MHz SPI or pin (standalone) configurable operation Operating temperature range: 0°C to 85°C Available in 8 mm × 8 mm, 56-lead LFCSP with exposed pad Alias free: inherent antialias rejection high performance mode 102.5 dB, typical Excellent ac and dc performance 108 dB dynamic range at ODR = 374 kSPS, FIR filter, typical 137 dB dynamic range at ODR = 10 SPS, sinc3 filter, typical THD: −120 dB typical with 1 kHz input tone Offset error drift: 0.7 µV/°C typical Gain drift: 2 ppm/°C typical INL: ±2 ppm of FSR typical Dynamic range enhancement: 4:1 and 2:1 averaging mode 126 dB, A weighted dynamic range Resistive ADC and reference input Easy to sync: asynchronous sample rate converter Multidevice synchronization with one signal line Programmable data rates from 0.01 kSPS to 1496 kSPS with resolution of 0.01 SPS Option to control output data rate by external signal Linear phase digital filter options Low ripple FIR filter: 32 µdB pass-band ripple, dc to 161.942 kHz Low latency sinc3 filter and sinc6 filter, dc to 391.5 kHz APPLICATIONS Electrical test and measurement Audio test 3-phase power quality analysis Control and hardware in loop verification Sonars Condition monitoring for predictive maintenance Acoustic and material science research and development RESET PDN XCLKOUT CLKSEL XTAL2/CLKIN XTAL1 CLKVDD REFIN REFCAP REFGND FUNCTIONAL BLOCK DIAGRAM FORMAT0/CS MODULATOR REFERENCE VCM CLOCK MANAGEMENT 1/2 LDOIN AIN0+ AIN0– LDO MCLK FORMAT1/SCLK DEC1/DCLKMODE ODR DEC0/DCLKIO CTSD MODULATOR ASYNCHRONOUS SAMPLE RATE CONVERTER PROGRAMMABLE DIGITAL FILTER CTSD MODULATOR ASYNCHRONOUS SAMPLE RATE CONVERTER PROGRAMMABLE DIGITAL FILTER CTSD MODULATOR ASYNCHRONOUS SAMPLE RATE CONVERTER PROGRAMMABLE DIGITAL FILTER CTSD MODULATOR ASYNCHRONOUS SAMPLE RATE CONVERTER PROGRAMMABLE DIGITAL FILTER DEC2/SDI DEC3/SDO DCLK AIN1+ AIN1– DIGITAL INTERFACE LOGIC AIN2+ AIN2– AIN3+ AIN3– DIAGNOSTIC ODR DOUT0 DOUT1 DOUT2 DOUT3 PIN/SPI MODE DCLKRATE0/GPIO0 DCLKRATE1/GPIO1 DCLKRATE2/GPIO2 POWER MANAGEMENT AGND1V8 FILTER0/GPIO4 AD7134 IOVDD DVDD5 AVDD5 FRAME1/GPIO7 AVDD1V8 FRAME0/GPIO6 LDO LDOIN DGND5 AGND5 IOGND LDO 22652-001 FILTER1/GPIO5 CLKGND DVDD1V8 DGND1V8 PWRMODE/GPIO3 Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7134 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Programming Output Data Rate and Clock ........................... 46 Applications ....................................................................................... 1 Programming Digital Filter....................................................... 49 Functional Block Diagram .............................................................. 1 Programming Data Interface .................................................... 49 Revision History ............................................................................... 2 Power Modes ............................................................................... 50 General Description ......................................................................... 3 Inherent Antialiasing Filter Modes .......................................... 51 Specifications..................................................................................... 4 Dynamic Range Enhancement, Channel Averaging ................. 52 Timing Specifications ................................................................ 10 Calibration ....................................................................................... 53 Absolute Maximum Ratings.......................................................... 12 Offset Calibration ....................................................................... 53 Thermal Resistance .................................................................... 12 Gain Calibration ......................................................................... 53 ESD Caution ................................................................................ 12 Applications Information .............................................................. 54 Pin Configuration and Function Descriptions ........................... 13 Power Supply............................................................................... 54 Typical Performance Characteristics ........................................... 17 Reference Noise Filtering .......................................................... 54 Terminology .................................................................................... 26 Multidevice Synchronization .................................................... 55 Theory of Operation ...................................................................... 28 Coherent Sampling..................................................................... 55 Continuous Time Sigma-Delta Modulator ............................. 28 Low Latency Digital Control Loop .......................................... 55 Easy to Drive Input and Reference........................................... 28 Automatic Gain Control ............................................................ 56 Inherent Antialiasing Filter (AAF) .......................................... 29 Front-End Design Examples ..................................................... 56 Analog Front-End Design Simplification ............................... 30 Digital Interface .............................................................................. 58 Noise Performance and Resolution .............................................. 31 SPI Interface ................................................................................ 58 Circuit Information ........................................................................ 35 Data Interface.............................................................................. 59 Core Signal Chain....................................................................... 35 Minimum I/O Mode .................................................................. 64 Analog Inputs .............................................................................. 35 Diagnostics ...................................................................................... 65 VCM Output ............................................................................... 35 Internal Fuse Integrity Check ................................................... 65 Reference Input ........................................................................... 36 Analog Input Overrange ........................................................... 66 Clock Input .................................................................................. 36 MCLK Counter ........................................................................... 66 XCLKOUT Output ..................................................................... 36 SPI Interface Monitoring ........................................................... 66 Power Options ............................................................................ 37 Memory Map Integrity Check .................................................. 66 Reset ............................................................................................. 37 ODR Input Frequency Check ................................................... 66 Asynchronous Sample Rate Converter .................................... 37 Digital Filter Overflow and Underflow ................................... 67 Digital Filters ............................................................................... 39 DCLK Error ................................................................................ 67 Quick Start Guide ........................................................................... 42 GPIO Functionality ........................................................................ 68 Standalone Mode ........................................................................ 43 Pin Error Reporting ................................................................... 68 Low Latency Synchronous Data Acquisition ............................. 43 Register Map (SPI Control) ........................................................... 69 Device Control ................................................................................ 44 Register Details ............................................................................... 71 Pin Control Mode ....................................................................... 44 Outline Dimensions ....................................................................... 86 SPI Control Mode ....................................................................... 45 Ordering Guide .......................................................................... 86 Multifunction Pins ..................................................................... 45 Device Configuration..................................................................... 46 REVISION HISTORY 4/2020—Revision 0: Initial Version Rev. 0 | Page 2 of 86 Data Sheet AD7134 GENERAL DESCRIPTION no longer requires a high frequency, low jitter master clock from the digital back end to be routed to each ADC. The AD7134 is a quad channel, low noise, simultaneous sampling, precision analog-to-digital converter (ADC) that delivers on functionality, performance, and ease of use. Based on the continuous time sigma-delta (CTSD) modulation scheme, the AD7134 removes the traditionally required switched capacitor circuitry sampling preceding the Σ-Δ modulator, which leads to a relaxation of the ADC input driving requirement. The CTSD architecture also inherently rejects signals around the ADC aliasing frequency band, giving the device its inherent antialiasing capability, and removes the need for a complex external antialiasing filter. The AD7134 has four independent converter channels in parallel, each with a CTSD modulator and a digital decimation and filtering path. The AD7134 enables simultaneous sampling of four separate signal sources, each supporting a maximum input bandwidth of 391.5 kHz and achieving tight phase matching between these four signal measurements. The high level of channel integration, together with its simplified analog frontend requirement, enables the AD7134 to provide a high density multichannel data acquisition solution in a small form factor. The signal chain simplification property of the AD7134 also improves the system level performance through the reduction of noise, error, mismatch, and distortion that is normally introduced by the analog front-end circuitry. The AD7134 offers excellent dc and ac performance. The bandwidth of each ADC channel ranges from dc to 391.5 kHz, making the device an ideal candidate for universal precision data acquisition solutions supporting a breadth of sensor types, from temperature and pressure to vibration and shock. The AD7134 offers a large number of features and configuration options, giving the user the flexibility to achieve the optimal balance between bandwidth, noise, accuracy, and power for a given application. An integrated asynchronous sample rate converter (ASRC) allows the AD7134 to precisely control the decimation ratio and, in turn, the output data rate (ODR) using interpolation and resampling techniques. The AD7134 supports a wide range of ODR frequencies, from 0.01 kSPS to 1496 kSPS with less than 0.01 SPS adjustment resolution, allowing the user to granularly vary sampling speed to achieve coherent sampling. The ODR value can be controlled through the ODR_VAL_INT_x and ODR_VAL_FLT_x registers (Register 0x16 to Register 0x1C, ASRC master mode), or using an external clock source (ASRC slave mode). The ASRC slave mode operation enables synchronous sampling between multiple AD7134 devices to a single system clock. The ASRC simplifies the clock distribution requirement within a medium bandwidth data acquisition system because it The ASRC acts as a digital filter and decimates the oversampled data from the Σ-Δ modulator to a lower rate to favor higher precision. The ADC data is then further processed by one of the AD7134 user-selectable digital filter profiles to further reject the out of band signals and noises, and reduce the data rate to the final desired ODR value. The AD7134 offers three main digital filter profile options: a wideband low ripple filter with a brick wall frequency profile and an ODR range from 2.5 kSPS to 374 kSPS that is suitable for frequency domain analysis, a fast responding sinc3 filter with an ODR range from 0.01 kSPS to 1496 kSPS that is suitable for low latency time domain analysis and low frequency high dynamic range input types, and a balanced sinc6 filter with an ODR range from 2.5 kSPS to 1.496 MSPS, offering optimal noise performance and response time. The AD7134 is also capable of performing on-board averaging between two or four of its input channels. The result is a near 3 dB, if two channels are combined, or 6 dB, if all four channels are combined, improvement in dynamic range while maintaining the bandwidth. The AD7134 supports two device configuration schemes: serial peripheral interface (SPI) and hardware pin configuration (pin control mode). The SPI control mode offers access to all the features and configuration options available on the AD7134. SPI control mode also enables access to the on-board diagnostic features designed to enable a robust system design. Pin control mode offers the benefit of simplifying the device configuration, enabling the device to operate autonomously after power-up operating in a standalone mode. In addition to the optional SPI, the AD7134 has a flexible and independent data interface for transmitting the ADC output data. The data interface can act as either a bus master or a slave with various clocking options to support multiple communication bus protocols. The data interface also supports daisy-chaining and an optional minimum input/output (I/O) mode designed to minimize the number of digital isolator channels required in isolated applications. The AD7134 has an operating ambient temperature range from 0°C to 85°C. The device is housed in an 8 mm × 8 mm, 56-lead lead frame chip scale package (LFCSP). Note that throughout this data sheet, multifunction pins, such as FORMAT1/SCLK, are referred to either by the entire pin name or by a single function of the pin, for example, SCLK, when only that function is relevant. Rev. 0 | Page 3 of 86 AD7134 Data Sheet SPECIFICATIONS AVDD5 = DVDD5 = 4.5 V to 5.5 V, AVDD1V8 = DVDD1V8 = 1.65 V to 1.95 V, CLKVDD = 1.65 V to 1.95 V, LDOIN = 2.6 V to 5.5 V, IOVDD = 1.65 V to 1.95 V, CLKIN = 48 MHz, AGND5 = DGND5 = AGND1V8 = DGND1V8 = IOGND = CLKGND = 0 V, REFIN voltage (VREF) = 4.096 V, high performance mode, input common-mode voltage (VCM) = 2.048 V, wideband 0.433 Hz × ODR filter, Antialiasing 1 (AA1) mode, unless otherwise noted. Typical values are for TA = 25°C, AVDD5 = DVDD5 = 5 V, AVDD1V8 = DVDD1V8 = CLKVDD = 1.8 V, LDOIN = 5 V, IOVDD = 1.8 V, unless otherwise noted. Table 1. Parameter ADC SPEED AND DATA OUTPUT ODR Wideband 0.10825 Hz × ODR and 0.433 Hz × ODR Filters 1, 2 Sinc6 Filter 3 Sinc3 Filter 4 −3 dB Bandwidth Wideband 0.433 Hz × ODR Filter Wideband 0.10825 Hz × ODR Filter Sinc6 Filter Sinc3 Filter Data Output Coding DYNAMIC PERFORMANCE Dynamic Range (DR) High Performance Mode Low Power Mode Signal-to-Noise Ratio High Performance Mode Low Power Mode Signal-to-Noise-andDistortion Ratio (SINAD) High Performance Mode Low Power Mode Total Harmonic Distortion (THD) High Performance Mode Low Power Mode Spurious-Free Dynamic Range 5 (SFDR) High Performance Mode Low Power Mode INTERMODULATION DISTORTION (IMD) Test Conditions/Comments Min Max Unit 2.5 374 kSPS 2.5 0.01 1496 1496 kSPS kSPS 1.08 161.942 kHz 0.27 40.48 kHz 278.4 391.5 Twos complement, MSB first kHz kHz 0.47 0.003 More information is available in the Noise Performance and Resolution section Shorted input ODR = 374 kSPS ODR = 10 SPS, sinc3 filter A weighted, 1 kHz input, −60 dBFS, ODR = 48 kSPS 2:1 channel averaging, A weighted, 1 kHz input, −60 dBFS, ODR = 48 kSPS 4:1 channel averaging, A weighted, 1 kHz input, −60 dBFS, ODR = 48 kSPS ODR = 187 kSPS 1 kHz, −0.5 dBFS, sine wave input ODR = 374 kSPS ODR = 187 kSPS 1 kHz, −0.5 dBFS, sine wave input ODR = 374 kSPS ODR = 187 kSPS 1 kHz, −0.5 dBFS, sine wave input 105.7 Typ 108 137 120 123 dB dB dB dB 126 dB 102.7 106 dB 105.6 105.3 107 106 dB dB 106.5 105.5 dB dB −120 −119 dB dB 125 125 dBc dBc −122 −125 dB dB 1 kHz, −0.5 dBFS, sine wave input With input tone at 9.7 kHz and 10.3 kHz Second-order Third-order Rev. 0 | Page 4 of 86 Data Sheet Parameter ACCURACY Integral Nonlinearity (INL) Offset Error 6 Offset Error Drift Gain Error6 Gain Drift Voltage Noise ANALOG INPUTS Differential Input Voltage Range (VIN) Input Common-Mode Voltage Range (VCM) Input Current Input Current Drift Differential Input Resistance VCM PIN Output Voltage Load Regulation (∆VOUT/∆IL) Voltage Regulation (∆VOUT/∆VAVDD5V) Short-Circuit Current Loading Capacitance Additive Voltage Noise Density EXTERNAL REFERENCE REFIN Voltage (VREF) REFIN Current REFIN Current Drift REFIN Resistance MODULATOR MAGNITUDE RESPONSE High Performance Mode Low Power Mode AD7134 Test Conditions/Comments Min Typ Max End point method High performance mode ±2 Low power mode ±2 High performance mode Low power mode High performance mode Low power mode High performance mode, master mode ±100 ±100 0.7 0.8 350 ±700 ±700 3.7 2.7 646 Low power mode, master mode 150 390 2 1.01 5.4 0.1 Hz to 10 Hz −VREF is the negative reference voltage and +VREF is the positive reference voltage −VREF VREF/2 ppm of FSR ppm of FSR µV µV µV/°C µV/°C ppm of FSR ppm of FSR ppm/°C µV p-p +VREF V AVDD5/2 V 317 8.3 6.25 VREF/20 Unit µA/V nA/V/°C kΩ AVDD5/2 313 993 45 V µV/mA µV/V 70 mA pF nV/√Hz All channels on One channel on All channels on, low power mode One channel on, low power mode 4.096 or 5 4.096 or 5 5.85 3.22 1.53 0.9 0.5 40 0.7 2.66 1.27 4.79 V V mA mA mA mA µA nA/V/°C kΩ kΩ kΩ kΩ At 100 kHz, ODR = 374 kSPS At 20 kHz, ODR = 374 kSPS At 50 kHz, ODR = 187 kSPS At 20 kHz, ODR = 187 kSPS −0.0202 −0.0024 −0.0122 −0.00189 dB dB dB dB 200 REFIN to REFGND high performance mode REFIN to REFGND low power mode All channels on, high performance mode All channels on, low power mode One channel on, high performance mode One channel on, low power mode REFIN off Rev. 0 | Page 5 of 86 AD7134 Parameter SYNCHRONIZATION Channel to Channel Phase Matching7 Channel to Channel Phase Matching Drift Device to Device Phase Matching 8 DIGITAL FILTER RESPONSE Low Ripple Wideband Group Delay Settling Time Pass-Band Ripple Pass-Band Frequency (fPASS) Wideband 0.433 Hz × ODR Filter Data Sheet Test Conditions/Comments At 20 kHz Min ODR = 1496 kSPS ±32 µdB pass band −0.1 dB pass band −3 dB bandwidth Wideband 0.10825 Hz × ODR Filter ±32 µdB pass band −0.1 dB pass band −3 dB bandwidth Typ Max Unit 1.57 3.3 ns 4.17 ps/°C 10 ns 39.8/ODR 79.6/ODR 32 sec sec µdB 0.4 × ODR 0.401 × ODR 0.433 × ODR 0.1 × ODR 0.101 × ODR 0.10825 × ODR Hz Hz 0.499 × ODR 0.2 × ODR Hz 110 dB Hz Hz Hz Hz Stop Band Frequency (fSTOP) Wideband 0.433 Hz × ODR Filter Wideband 0.10825 Hz × ODR Filter Stop Band Attenuation Sinc6 Group Delay Settling Time Pass Band −3 dB bandwidth Sinc3 Group Delay (GD) Settling Time Pass Band Latency Complete settling −3 dB bandwidth 1.75/ODR 3.5/ODR 0.2617 × ODR sec sec sec 50 SPS, 50 Hz ± 1 Hz 60 SPS, 60 Hz ± 1 Hz 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 50 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz, sinc3 rejection, and 50 Hz/60 Hz rejection filter1 102 106 102 67 dB dB dB dB Attenuation At 50 Hz At 60 Hz At 50 Hz, 60 Hz At 50 Hz, 60 Hz COMBINED RESPONSE Overall Group Delay REJECTION Power Supply Rejection Ratio DC AVDD5 DVDD5 Hz 3.25/ODR 6.5/ODR 0.1861 × ODR Sinc3 filter, slave gated mode Sinc6 filter, slave gated mode High performance mode sec 8/ODR 10.5/ODR 101.8 80.4 Rev. 0 | Page 6 of 86 sec sec dB dB Data Sheet Parameter AVDD1V8 DVDD1V8 IOVDD LDOIN CLKVDD Power Supply Rejection AC AVDD5 DVDD5 AVDD1V8 DVDD1V8 IOVDD CLKVDD Common-Mode Rejection Ratio (CMRR) DC AC Crosstalk Input Signal Alias Rejection (AAREJ) High Performance Mode Low Power Mode EXTERNAL CLOCK INPUT Frequency Duty Cycle Input Voltage High Input Voltage Low Input Capacitance CRYSTAL OSCILLATOR Frequency Start-Up Time CLKSEL INPUT LOGIC Input High Voltage (VINH) Input Low Voltage (VINL) Leakage Currents XCLKOUT PIN Output Frequency Rise Time/Fall Time (20% to 80%) Duty Cycle Output Voltage High Output Voltage Low ODR PIN Output Frequency Output Rise Time/Fall Time (20% to 80%) Output Voltage High AD7134 Test Conditions/Comments Min Typ 87.2 100 102 116.6 61 Max Unit dB dB dB dB dB 100 mV p-p, 1 MHz signal on supply with no decoupling capacitor, value with respect to fullscale input 101 102 104 101 114 103 dB dB dB dB dB dB 78.4 74.5 130.7 dB dB dBFS 85.4 dB 102.5 dB 87.4 dB 97.2 dB 100 mV p-p on VCM with no decoupling capacitor Up to 10 kHz −0.5 dBFS, 1 kHz input on adjacent channels −6 dBFS output of band tone from master clock (MCLK) − 160 kHz to MCLK + 160 kHz, AA1 mode −6 dBFS output of band tone from MCLK − 160 kHz to MCLK + 160 kHz, Antialiasing 2 (AA2) mode −6 dBFS output of band tone from MCLK − 80 kHz to MCLK + 80 kHz, AA1 mode −6 dBFS output of band tone from MCLK − 80 kHz to MCLK + 80 kHz, AA2 mode 47.9 40 0.65 × CLKVDD 48 50:50 48.1 60 10 MHz % V V pF 48 4.4 MHz ms 0.35 × CLKVDD ±100 ppm 0.7 × IOVDD 0.3 × IOVDD +1 −1 45 pF load External clock input duty cycle = 50:50 Source current (ISOURCE) = 100 µA 48 0.85 MHz ps 53.8 % V CLKVDD − 0.2 Sink current (ISINK) = 100 µA 0.01 45 pF load 2.8 ISOURCE = 100 µA IOVDD − 0.2 Rev. 0 | Page 7 of 86 V V µA 0.2 V 1496 kHz ns V AD7134 Parameter Output Voltage Low Input Frequency (fIN) VINH VINL Input Capacitance DCLK PIN Output Frequency Output Rise Time/Fall Time (20% to 80%) Output Duty Cycle Output Voltage High Output Voltage Low fIN VINH VINL Input Capacitance LOGIC INPUTS VINH VINL Leakage Currents LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) INTEGRATED LOW DROPOUT (LDO) REGULATOR Output Voltage Input Voltage POWER SUPPLY VOLTAGE AVDD5 to AGND5 DVDD5 to DGND5 AVDD5 to AGND5 DVDD5 to DGND5 DVDD1V8 to DGND AVDD1V8 to AGND1V8 AVDD1V8 to AGND1V8 DVDD1V8 to DGND IOVDD to IOGND CLKVDD to CLKGND CLKVDD to CLKGND POWER SUPPLY CURRENT High Performance Mode AVDD5 DVDD5 AVDD1V8 DVDD1V8 IOVDD CLKVDD Low Power Mode AVDD5 DVDD5 AVDD1V8 Data Sheet Test Conditions/Comments ISINK = 100 µA Min Typ 0.01 0.7 × IOVDD Max 0.2 1496 0.3 × IOVDD Pin configured as input 10 2.93 45 pF load 48000 2.8 50:50 ISOURCE = 100 µA ISINK = 100 µA IOVDD − 0.2 0.2 50,000 0.7 × IOVDD 0.3 × IOVDD Pin configured as input 10 0.7 × IOVDD 0.2 V V 5.5 V V 5 5 5 5 1.8 1.8 1.85 1.85 1.8 1.8 1.85 5.5 5.5 5.5 5.5 1.95 1.95 1.95 1.95 1.95 1.95 1.95 V V V V V V V V V V V 8.2 38.6 56 60 60.9 90 2.25 2.8 10.3 44.8 73.9 70.6 71.8 105.5 3.17 3.53 mA mA mA mA mA mA mA mA 8.2 14.1 51 10.3 16.5 69 mA mA mA 1.85 2.6 VREF = 5 V VREF = 5 V VREF = 5 V VREF = 5 V VREF = 5 V 4 channels active, internal LDO regulator bypassed, XCLKOUT disabled ODR = 374 kSPS Sinc3 filter, ODR = 1496 kSPS Sinc6 filter, ODR = 1496 kSPS Wideband 0.433 Hz × ODR filter % V V kHz V V pF V V µA IOVDD − 0.2 4.5 4.5 4.7 4.7 1.65 1.65 1.8 1.8 1.65 1.65 1.8 kHz ns 0.2 × IOVDD +10 −10 ISOURCE = 100 µA ISINK = 100 µA Unit V kHz V V pF ODR = 187 kSPS Rev. 0 | Page 8 of 86 Data Sheet Parameter DVDD1V8 IOVDD CLKVDD TOTAL POWER CONSUMPTION High Performance Mode Low Power Mode High Performance Mode Low Power Mode AD7134 Test Conditions/Comments Sinc3 filter, ODR = 1496 kSPS Sinc6 filter, ODR = 1496 kSPS Wideband 0.433 Hz × ODR filter External LDO mode: AVDD5 = DVDD5 = 5 V, AVDD1V8 = DVDD1V8 = CLKVDD = IOVDD = LDOIN = 1.8 V, internal LDO regulator bypassed, XCLKOUT disabled ODR = 374 kSPS, wideband 0.433 Hz × ODR filter 4 channels active 1 channel active 2:1 averaging 4:1 averaging ODR = 2.5 kSPS, 4 channels active ODR = 1496 kSPS, 4 channels active, sinc3 filter ODR = 187 kSPS, wideband 0.433 Hz × ODR filter 4 channels active 1 channel active 2:1 averaging 4:1 averaging ODR = 2.5 kSPS, 4 channels active ODR = 1496 kSPS, 4 channels active, sinc3 filter Internal LDO regulator mode: AVDD5 = DVDD5 = 5 V, LDOIN = 2.6 V, XCLKOUT disabled ODR = 270 kSPS, wideband 0.433 Hz × ODR filter 4 channels active 1 channel active 2:1 averaging 4:1 averaging ODR = 2.5 kSPS, 4 channels active ODR = 1496 kSPS, 4 channels active, sinc3 filter ODR = 187 kSPS, wideband 0.433 Hz × ODR filter 4 channels active 1 channel active 2:1 averaging 4:1 averaging ODR = 2.5 kSPS, 4 channels active ODR = 1496 kSPS, 4 channels active, sinc3 filter Full Power-Down Mode Sleep Mode 1 Min Typ 30.6 38.5 48.5 1.27 1.89 Max 36 45.2 56.8 1.7 2.3 Unit mA mA mA mA mA 504 201 472 450 418 446 540 mW mW mW mW mW mW 297 121 288 254 260 285 386 mW mW mW mW mW mW 593 246 555 530 484 547 mW mW mW mW mW mW 386 147 356 334 316 355 1 15 mW mW mW mW mW mW mW mW For internal LDO regulator mode, the maximum ODR supported for wideband FIR filters is 270 kSPS. For slave mode, the maximum ODR supported for wideband FIR filters is 365 kSPS. 3 For slave mode, the maximum ODR supported for the sinc6 filter is 1460 kSPS. 4 For slave mode, the maximum ODR supported for the sinc3 filter is 1460 kSPS. 5 Excluding the first five harmonics. 6 Following a full system calibration, the offset error and the gain error are in the order of the noise for the programmed output data rate selected. The gain error is a function of the output data rate in slave mode. Therefore, a gain error calibration is needed when the output data rate is changed. It is recommended to perform a periodic system calibration to stop aging related drifts. 7 Between any two channels on the same device. 8 Between any two channels on any two devices. SPI slave mode with DCLK as gated input only with the DIG_IF_RESET SPI write issued simultaneously to both devices. 2 Rev. 0 | Page 9 of 86 AD7134 Data Sheet TIMING SPECIFICATIONS AVDD5 = DVDD5 = 4.5 V to 5.5 V, AVDD1V8 = DVDD1V8 = 1.65 V to 1.95 V, CLKVDD = 1.65 V to 1.95 V, IOVDD = 1.65 V to 1.95 V, CLKIN = 48 MHz, AGND5 = DGND5 = AGND1V8 = DGND1V8 = IOGND = CLKGND = 0 V, TA = 0°C to 85°C, unless otherwise noted. Typical values are at TA = 25°C, unless otherwise noted. Table 2. Device Clock Timing Parameter fSYSCLK MCLK Description System clock frequency Master clock Test Conditions/Comments fDIGCLK fDCLK Internal digital clock (tDIGCLK) = 1/fDIGCLK Data Interface clock (tDCLK) = 1/fDCLK fSCLK SPI clock rate (tSCLK) = 1/fSCLK Min Typ 48 fSYSCLK/2 fSYSCLK/4 fSYSCLK/2 High performance mode Low power mode Max DCLK as output, SPI control mode DCLK as output, pin control mode DCLK as input fSYSCLK fSYSCLK 50 50 Unit MHz Hz Hz Hz MHz MHz MHz MHz The signal on DOUTx is driven out on the rising edge of the DCLK. tODR_PERIOD is 1/ODR. See Figure 2. Table 3. Data Interface Timing with Gated DCLK Parameter t1 Description ODR high time t2 t3 ODR low time ODR falling edge to DCLK rising edge t4 Last data DCLK falling edge to ODR rising edge t5 DCLK rising to DOUTx invalid t6 DCLK rising to DOUTx valid t7 t8 DCLK low time DCLK high time Test Conditions/Comments Master mode, tDCLK > tDIGCLK Master mode, tDCLK ≤ tDIGCLK Slave mode Slave mode Master mode Slave mode Master mode Slave mode Master mode Slave mode Master mode Slave mode Min 2.5 × tDCLK 3 × tDIGCLK 3 × tDIGCLK 3 × tDIGCLK tDCLK − 2 8 0.5 × tDCLK 2 × tDCLK −4 0 0 Typ 3 8.2 tDCLK/2 − 1 tDCLK/2 − 1 t1 t2 ODR tODR_PERIOD t3 t8 t4 DCLK DOUTx LSB (N – 1) t7 MSB t6 LSB Figure 2. Timing Diagram of Data Interface with Gated DCLK Rev. 0 | Page 10 of 86 22652-002 t5 Max 3.5 × tDCLK 3 × tDIGCLK + 4 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Sheet AD7134 Signal on DOUTx is driven out on the rising edge of DCLK. See Figure 3. Table 4. Data Interface Timing with Free Running DCLK Parameter t9 Description ODR high time t10 ODR low time t11 t12 t13 t14 t15 DCLK rising edge to ODR rising edge ODR rising edge to DCLK rising edge ODR sampled high to DOUTx active DCLK rising to DOUTx invalid DCLK rising to DOUTx valid t16 t17 DCLK low time DCLK high time Test Conditions/Comments Master mode, tDCLK > tDIGCLK Master mode, tDCLK ≤ tDIGCLK Slave mode, tDCLK > tDIGCLK Slave mode, tDCLK ≤ tDIGCLK Slave mode, tDCLK > tDIGCLK Slave mode, tDCLK ≤ tDIGCLK Slave mode Slave mode Min 2.5 × tDCLK 3 × tDIGCLK 3 × tDCLK 3 × tDIGCLK 3 × tDCLK 3 × tDIGCLK tDCLK/2 tDCLK/2 3 × tDCLK −4 0 Master mode Master mode Slave mode Typ Max 3.5 × tDCLK – tDIGCLK + 4 3 × tDIGCLK + 4 ns ns ns 3 × tDCLK + 4 ns ns ns ns ns 2 3 tDCLK/2 − 1 tDCLK/2 − 1 t9 Unit ns ns ns t10 ODR t11 t12 t17 DCLK t16 t14 DOUTx t15 22652-003 t13 MSB LSB Figure 3. Timing Diagram of Data Interface with Free Running DCLK SDI is sampled on the rising edge of SCLK. SDO is driven out on the falling edge of SCLK. See Figure 4. Table 5. SPI Interface Timing Description CS falling to data out active SCLK falling edge to SDO valid SCLK low time SDI setup time SDI hold time SDO hold time after SCLK falling SCLK high time Last SCLK rising edge to CS rising edge CS high time CS falling edge to SCLK rising edge Min 0 Typ 7 tSCLK/2 − 1 tSCLK 0.9 × tSCLK/2 9 t26 CS t27 t25 t20 SCLK t22 t24 t21 SDI MSB t18 SDO Max 7 8 tSCLK/2 − 1 2 2 LSB t19 t23 MSB LSB Figure 4. SPI Interface Timing Diagram Rev. 0 | Page 11 of 86 22652-004 Parameter t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 Unit ns ns ns ns ns ns ns ns ns ns AD7134 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter AVDD5 to AGND5 DVDD5 to DGND5 AVDD1V8 to AGND1V8 DVDD1V8 to DGND1V8 CLKVDD to CLKGND IOVDD to IOGND DGND5 to AGND5 AGND1V8 to AGND5 DGND1V8 to AGND5 IOGND to AGND5 CLKGND to AGND5 LDOIN to AGND5 AINx± Inputs to AGND5 REFIN to AGND5 REFCAP to AGND5 REFGND to AGND5 Digital I/O Pins to IOGND XCLKOUT, XTAL2/CLKIN, and XTAL1 to CLKGND Operating Ambient Temperature Range Storage Temperature Range Pb-Free Temperature, Soldering Reflow (10 sec to 30 sec) Junction Temperature Package Classification Temperature Rating −0.3 V to +6 V −0.3 V to +6 V −0.3 V to 2.2 V or LDOIN + 0.3 V (whichever is lower) −0.3 V to 2.2 V or LDOIN + 0.3 V (whichever is lower) −0.3 V to 2.2 V or LDOIN + 0.3 V (whichever is lower) −0.3 V to +2.2 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V AVDD1V8 − 0.3 V to 6 V −0.3 V to AVDD5 + 0.3 V −0.3 V to AVDD5 + 0.3 V −0.3 V to AVDD5 + 0.3 V −0.3 V to +0.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to CLKVDD + 0.3 V Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 7. Thermal Resistance Package Type CP-56-9 2S2P or 1S Test Board 2S2P Test Board with 36 Thermal Vias θJA θJC Unit 371 273 5.42 N/A4 °C/W °C/W Simulated data based on a JEDEC 2S2P test board in a JEDEC natural convection environment. 2 Simulated data based on a JEDEC 1S test board, measured at the exposed pad with a cold plate mounted directly to the package surface. 3 Simulated data based on a JEDEC 2S2P test board with 36 thermal vias in a JEDEC natural convection environment. 4 N/A means not applicable. 1 ESD CAUTION 0°C to 85°C −65°C to +150°C 260°C 150°C 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only, functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 12 of 86 Data Sheet AD7134 1 2 DEC3/SDO DEC2/SDI DEC1/DCLKMODE 3 4 DEC0/DCLKIO DOUT3 DOUT2 DOUT1 6 7 8 9 44 CLKVDD 43 CLKGND 47 CLKSEL 46 XTAL1 45 XTAL2/CLKIN DCLKRATE0/GPIO0 MODE PIN/SPI XCLKOUT 51 50 49 48 52 DCLKRATE1/GPIO1 42 AIN3– 41 AIN3+ 40 AGND5 39 AIN2– 38 AIN2+ 37 REFGND 5 AD7134 TOP VIEW (Not to Scale) DOUT0 10 DCLK 11 ODR 12 IOVDD 13 REFCAP REFIN VCM AIN1– 32 31 30 29 AIN1+ AGND5 AIN0– AIN0+ DNC 28 DVDD5 25 AVDD5 26 AGND5 27 LDOIN 23 DGND5 24 DVDD1V8 20 AVDD1V8 21 AGND1V8 22 DGND1V8 19 FILTER1/GPIO5 16 FRAME0/GPIO6 17 FRAME1/GPIO7 18 FILTER0/GPIO4 15 IOGND 14 36 35 34 33 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AGND5. 22652-005 FORMAT0/CS FORMAT1/SCLK 55 PDN 54 RESET 53 DCLKRATE2/GPIO2 56 PWRMODE/GPIO3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 Mnemonic FORMAT0/CS Type 1 DI 2 FORMAT1/SCLK DI 3 DEC3/SDO DI/O 4 DEC2/SDI DI 5 DEC1/DCLKMODE DI Description ADC Output Data Format Selection Input 0 in Pin Control Mode (FORMAT0). Tie this pin to IOVDD or to IOGND to set the number of DOUTx pins used to output ADC conversion data. See the Output Channel Format section for more details. Chip Select Input in SPI Control Mode (CS). ADC Output Data Format Selection Input 1 in Pin Control Mode (FORMAT1). Tie this pin to IOVDD or to IOGND to set the number of DOUTx pins used to output ADC conversion data. See the Output Channel Format section for more details. Serial Clock Input in SPI Control Mode (SCLK). Decimation Ratio Selection Input 3 in Pin Control Master Mode or PLL Lock Status Output in Pin Control Slave Mode (DEC3). Tie this pin to IOVDD or to IOGND to set the output data rate. See the Programming Output Data Rate and Clock section for more details. In pin control slave mode, this pin is output high to indicate the internal PLL is in lock. Serial Data Output in SPI Control Mode (SDO). Master Mode Decimation Ratio Selection Input 2 in Pin Control Master Mode (DEC2). Tie this pin to IOVDD or to IOGND to set the output data rate. See the Programming Output Data Rate and Clock section for more details. Serial Data Input in SPI Control Mode (SDI). Decimation Ratio Selection Input 1 in Pin Control Master Mode (DEC1). Tie this pin to IOVDD or to IOGND to set the output data rate. See the Programming Output Data Rate and Clock section for more details. DCLK Mode Control in Pin Control Slave Mode and in SPI Control Mode (DCLKMODE). Tie this pin high to IOVDD to set DCLK to operate in free running mode. Tie this pin low to ground to set DCLK to operate in gated mode. Rev. 0 | Page 13 of 86 AD7134 Data Sheet Pin No. 6 Mnemonic DEC0/DCLKIO Type 1 DI 7 8 9 10 11 DOUT3 DOUT2 DOUT1 DOUT0 DCLK DO DO DO DO DI/O 12 ODR DI/O 13 14 15 IOVDD IOGND FILTER0/GPIO4 P GND DI/O 16 FILTER1/GPIO5 DI/O 17 FRAME0/GPIO6 DI/O 18 FRAME1/GPIO7 DI/O 19 20 DGND1V8 DVDD1V8 GND P 21 AVDD1V8 P 22 23 AGND1V8 LDOIN GND P 24 25 26 27 28 29 30 31 32 33 DGND5 DVDD5 AVDD5 AGND5 DNC AIN0+ AIN0− AGND5 AIN1+ AIN1− GND P P GND DNC AI AI GND AI AI Description Decimation Ratio Selection Input 0 in Pin Control Master Mode (DEC0). Tie this pin to IOVDD or to IOGND to set the output data rate. See the Programming Output Data Rate and Clock section for more details. DCLK Pin I/O Direction Control in Pin Control Slave Mode and in SPI Control Mode (DCLKIO). In master mode, tie this pin to IOVDD to configure DCLK as an output. In slave mode, tie this pin low to ground to set DCLK as an input. When the DEC1/DCLKMODE pin is high (DCLK is in free running mode), the DCLKIO input is ignored and the DCLK direction is always the same as the ODR pin. Data Output 3. The output data is synchronous to DCLK and framed by the ODR pin. Data Output 2. The output data is synchronous to DCLK and framed by the ODR pin. Data Output 1. The output data is synchronous to DCLK and framed by the ODR pin. Data Output 0. The output data is synchronous to DCLK and framed by the ODR pin. ADC Conversion Data Clock. Conversion data on the DOUT0 pin to the DOUT3 pin is clocked out synchronously by DCLK. In pin control master mode, DCLK is configured as an output operating in gated mode. In pin control slave mode or in SPI control mode, the DCLK direction and mode of operation are determined by the DEC1/DCLKMODE pin and DCLKIO pin. Refer to Table 29 for details. In master mode, DCLK frequency is programmable through DCLKRATEx in pin control mode or the DATA_PACKET_CONFIG register in SPI control mode. Output Data Rate Control and Framing. The frequency of the ODR signal matches the ADC output data rate. The edges of the ODR signal can be used to frame the conversion output data bit steam. In master mode, the ODR pin is configured as an output with the pin-programmable and registerprogrammable frequency derived from the device master clock. In slave mode, the ODR pin is configured as an input to allow the external clock to control the ADC output data rate. Digital I/O Supply. This pin sets the logic levels for all interface I/O pins. I/O Interface Ground Reference. Digital Filter Type Selection Input 0 in Pin Control Mode (FILTER0). Tie this pin to IOVDD or to IOGND to select the digital filter options. See the Programming Digital Filter section for more details. General-Purpose Input/Output 4 in SPI Control Mode (GPIO4). Digital Filter Type Selection Input 1 in Pin Control Mode (FILTER1). Tie this pin to IOVDD or to IOGND to select the digital filter options. See the Programming Digital Filter section for more details. General-Purpose Input/Output 5 in SPI Control Mode (GPIO5). Conversion Output Data Frame Control Input 0 in Pin Control Mode (FRAME0). Tie this pin to IOVDD or to IOGND to select the conversation output data frame. See the Data Frame section for more details. General-Purpose Input/Output 6 in SPI Control Mode (GPIO6). Conversion Output Data Frame Control Input 1 in Pin Control Mode (FRAME1). Tie this pin to IOVDD or to IOGND to select the conversation output data frame. See the Data Frame section for more details. General-Purpose Input/Output 7 in SPI Control Mode (GPIO7). Ground Reference for Digital Supply Voltage, 1.8 V. Digital Supply Voltage, 1.8 V. The pin is supplied from an external source or the internal LDO regulator. In either case, a decoupling capacitor of 10 µF is required between DVDD1V8 and DGND1V8. Analog Supply Voltage 1.8 V. The pin is supplied from an external source or the internal LDO regulator. In either case, a decoupling capacitor of 10 µF is required between AVDD1V8 and AGND1V8. Ground Reference for Analog Supply Voltage, 1.8 V. Input for Three Internal 1.8 V LDO Regulators Powering AVDD1V8, DVDD1V8, and CLKVDD. Tie this pin to DVDD1V8 if an external power supply is used to power AVDD1V8, DVDD1V8, and CLKVDD. A 10 µF decoupling capacitor is required between LDOIN and DGND1V8. See the On-Board LDO Regulators section for more details. Ground Reference for Digital Supply Voltage, 5 V. Digital Supply Voltage, 5 V. A decoupling capacitor of 10 µF is required between DVDD5 and DGND5. Analog Supply Voltage, 5 V. A decoupling capacitor of 10 µF is required between AVDD5 and AGND5. Ground Reference for Analog Supply Voltage, 5 V. Do Not Connect. Do not connect to this pin. Positive Analog Input to ADC Channel 0. Negative Analog Input to ADC Channel 0. Ground Reference for Analog Supply Voltage, 5 V. Positive Analog Input to ADC Channel 1. Negative Analog Input to ADC Channel 1. Rev. 0 | Page 14 of 86 Data Sheet AD7134 Pin No. 34 Mnemonic VCM Type 1 AO 35 REFIN AI 36 REFCAP AO 37 38 39 40 41 42 43 44 REFGND AIN2+ AIN2− AGND5 AIN3+ AIN3− CLKGND CLKVDD GND AI AI GND AI AI GND P 45 XTAL2/CLKIN DI 46 XTAL1 DI 47 CLKSEL DI 48 XCLKOUT DO 49 PIN/SPI DI 50 MODE DI 51 DCLKRATE0/GPIO0 DI/O 52 DCLKRATE1/GPIO1 DI/O 53 DCLKRATE2/GPIO2 DI/O 54 RESET DI 55 PDN DI Description Common-Mode Voltage Output. The VCM output can be used to provide a common-mode voltage for the analog front-end circuit. The VCM pin provides a buffered voltage output. The level is fixed to 1/2 of the voltage on the REFCAP pin in pin control mode, and is programmable in SPI control mode. When driving capacitive loads larger than 0.2 nF, it is recommended to place a 50 Ω series resistor between the pin and the capacitive load for stability. ADC Reference Filter Input. Use an internal 20 Ω resistor together with an external capacitor on the REFCAP pin to filter the reference source noise. ADC Reference Direct Input. Connect this pin to the external reference source for a direct reference input. Alternatively, connect the reference source to the REFIN pin and place a filter capacitor between the REFCAP pin and REFGND pin to limit the reference noise bandwidth. See the Reference Input section for more details. ADC Reference Ground Reference. Positive Analog Input to ADC Channel 2. Negative Analog Input to ADC Channel 2. Ground Reference for Analog Supply Voltage, 5 V. Positive Analog Input to ADC Channel 3. Negative Analog Input to ADC Channel 3. Clock Management Circuit Ground Reference. Clock Management Circuit Power Supply, 1.8 V. This pin is supplied from an external source or internal LDO regulator. In either case, a decoupling capacitor of 2.2 µF is required between the CLKVDD pin and CLKGND pin. Input 2 for Internal Crystal Oscillator (XTAL2). Connect an external crystal between the XTAL1 pin and XTAL2/CLKIN pin for on-chip clock generation. Clock Input (CLKIN). For operations using an external clock signal, connect this pin to the external clock source. See the Clock Input section for more details. Input 1 for Internal Crystal Oscillator. Connect an external crystal between the XTAL1 pin and XTAL2/CLKIN pin for on-chip clock generation. Leave this pin floating if the device is to operate from a single-ended external clock signal. Clock Source Selection Input. Connect this pin to IOVDD to enable on-chip clock generation from an external crystal. Connect this pin to IOGND if the clock signal is provided externally on the XTAL2/CLKIN pin. Crystal Oscillator Buffered Output. A buffered clock signal generated by the internal crystal oscillator is available on this pin. This signal can be used to drive other AD7134 devices working in parallel. The XCLKOUT output is enabled by default in pin control mode only if the crystal clock option is selected. The XCLKOUT output is disabled by default in SPI control mode. See the XCLKOUT Output section for more details. Device Configuration Mode Control Input. Tie this pin to IOVDD to enable device configuration through register access over the SPI interface. Tie this pin to ground to enable device configuration through the configuration input pins. ASRC Mode Of Operation Control Input. Tie this pin to IOVDD for master mode operation. Tie this pin to IOGND for slave mode operation. DCLK Frequency Control Input 0 in Pin Control Mode (DCLKRATE0). When DCLK is configured as an output, tie this pin to IOVDD or to IOGND to set the frequency ratio between DCLK and the device master clock. See Table 30 for more details. General-Purpose Input/Output 0 in SPI Control Mode (GPIO0). DCLK Frequency Control Input 1 in Pin Control Mode (DCLKRATE1). When DCLK is configured as an output, tie this pin to IOVDD or to IOGND to set the frequency ratio between DCLK and the device master clock. See Table 30 for more details. General-Purpose Input/Output 1 in SPI Control Mode (GPIO1). DCLK Frequency Control Input 2 in Pin Control Mode (DCLKRATE2). When DCLK is configured as an output, tie this pin to IOVDD or to IOGND to set the frequency ratio between DCLK and the device master clock. See Table 30 for more details. General-Purpose Input/Output 2 in SPI Control Mode (GPIO2). Hardware Asynchronous Reset Input, Active Low. Pull this pin to IOVDD through a 10 kΩ pull-up resistor during normal operation. Pull this pin low to IOGND to force the device into reset. See the Reset section for more details. Full Power-Down Mode Control Input, Active Low. Pull this pin to IOVDD through a 10 kΩ pull-up resistor during normal operation. Pull this pin to IOGND to force the device into full power-down mode. See the Power Modes section for more details. Rev. 0 | Page 15 of 86 AD7134 Pin No. 56 Mnemonic PWRMODE/GPIO3 EPAD 1 Data Sheet Type 1 DI/O Description Power Mode Selection Input in Pin Control Mode (PWRMODE). Tie this pin to IOVDD for high performance mode. Tie this pin to IOGND for low power mode. General-Purpose Input/Output 3 in SPI Control Mode (GPIO3). Exposed Pad. Connect the exposed pad to AGND5. DI is digital input, DI/O is bidirectional digital input/output, DO is digital output, P is power, GND is ground, DNC is do not connect, AI is analog input, and AO is analog output. Rev. 0 | Page 16 of 86 Data Sheet AD7134 TYPICAL PERFORMANCE CHARACTERISTICS VREF = 4.096 V, AA1 mode, VCM = 2.048 V, wideband 0.433 × ODR filter, high performance mode, wideband filter plots at ODR = 374 kSPS, sinc3 and sinc6 plots at ODR = 1496 kSPS, unless otherwise noted. 0 0 SNR = 106.26dB THD = –122dB DYNAMIC RANGE = 108dB –50 AMPLITUDE (dB) –100 –150 –200 –100 –150 –200 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) –250 22652-006 –250 Figure 6. Dynamic Range Performance, High Performance Mode, Wideband 0.433 Hz × ODR Filter, ODR = 374 kSPS 1 10 100 1k 10k Figure 9. FFT, High Performance Mode, −0.5 dBFS, Wideband 0.433 Hz × ODR Filter, ODR = 374 kSPS 0 150 SNR = 99.78dB THD = –121.31dB WIDEBAND FILTER SINC3 FILTER SINC6 FILTER 140 100k FREQUENCY (Hz) 22652-007 AMPLITUDE (dB) –50 AMPLITUDE (dB) DYNAMIC RANGE (dB) –50 130 120 110 –100 –150 100 –200 0.1 1 10 100 1k OUTPUT DATA RATE (kSPS) –250 22652-009 80 0.01 Figure 7. Dynamic Range vs. Output Data Rate in High Performance Mode for Wideband FIR, Sinc3 and Sinc6 Filters 1 10 100 1k 10k 1M Figure 10. FFT, High Performance Mode, Sinc6 Filter, −0.5 dBFS, ODR = 1496 kSPS 0 140 SNR = 94.4dB THD = –122dB 4 CHANNELS ACTIVE WITH 2-CHANNEL AVERAGING WITH 4-CHANNEL AVERAGING 135 100k FREQUENCY (Hz) 22652-010 90 –50 AMPLITUDE (dB) DYNAMIC RANGE (dB) 130 125 120 115 –100 –150 110 –200 1 10 INPUT BANDWIDTH (kHz) 100 –250 22652-008 100 Figure 8. Dynamic Range vs. Input Bandwidth, Wideband 0.433 Hz × ODR Filter 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 22652-011 105 Figure 11. FFT, High Performance Mode, Sinc3 Filter, −0.5 dBFS, ODR = 1496 kSPS Rev. 0 | Page 17 of 86 AD7134 Data Sheet 0 0 SNR = 105.6dB THD = –120.95dB –50 AMPLITUDE (dB) –100 –150 –200 –150 –200 –250 1 10 1k 100 10k 100k FREQUENCY (Hz) –300 5k 22652-203 –250 Figure 12. FFT, Low Power Mode, Wideband 0.433 × ODR Filter, −0.5 dBFS, ODR = 187 kSPS 50k FREQUENCY (Hz) Figure 15. IMD with Input Signals at 9.7 kHz and 10.3 kHz, Wideband 0.433 × ODR Filter 0 130 SNR = 97.19dB THD = –118.27dB WIDEBAND 0.433Hz × ODR, HIGH PERFORMANCE MODE WIDEBAND 0.10825Hz × ODR, HIGH PERFORMANCE MODE SINC3 HIGH PERFORMANCE MODE SINC6 HIGH PERFORMANCE MODE 120 POWER PER CHANNEL (mW) –50 AMPILITUDE (dB) –100 –100 –150 –200 22652-013 AMPILITUDE (dB) –50 110 100 90 WIDEBAND 0.433Hz × ODR, LOW POWER MODE WIDEBAND 0.10825Hz × ODR, LOW POWER MODE SINC3 LOW POWER MODE SINC6 LOW POWER MODE 80 70 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 50 0.01 22652-205 –250 0.1 1 10 100 1k 1M OUTPUT DATA RATE (kSPS) Figure 13. FFT, Low Power Mode, Sinc6 Filter, −0.5 dBFS, ODR = 750 kSPS 22652-012 60 Figure 16. Power per Channel vs. Output Data Rate 0 65 SNR = 90.69dB THD = –118.74dB 55 SUPPLY CURRENT (mA) AMPILITUDE (dB) –50 –100 –150 45 35 DVDD1V8 AVDD1V8 DVDD5 AVDD5 REFIN CLKVDD IOVDD 25 15 –200 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M –5 22652-207 –250 Figure 14. FFT, Low Power Mode, Sinc3 Filter, −0.5 dBFS, ODR = 750 kSPS 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 90 22652-035 5 Figure 17. Supply Current vs. Temperature, Wideband 0.433 Hz × ODR Filter Rev. 0 | Page 18 of 86 Data Sheet AD7134 120 4.5 100 4.0 1.5 107.0 –100 106.5 –130 105.0 –140 104.5 –150 10 100 1k 2.4 2.1 1.8 1.5 1.2 0.9 0.6 105.5 10k 100k INPUT FREQUENCY (Hz) 104.0 Figure 19. THD and THD + N vs. Input Frequency, −6 dBFS Input, 0.433 × ODR Filter 0 10 20 30 40 SYSTEM CLOCK JITTER – RMS (ps) 22652-039 SNR (dB) –120 106.0 THD, HIGH PERFORMANCE MODE THD + N, HIGH PERFORMANCE MODE THD, LOW POWER MODE THD + N, LOW POWER MODE 22652-221 THD AND THD + N (dB) Figure 21. THD Histogram –90 –110 0 THD (dB) Figure 18. SNR vs. Input Amplitude, Tone at 1 kHz 22652-274 INPUT AMPLITUDE (dBFS) 22652-017 –96 –102 –108 –114 –120 –72 –78 –84 –90 –48 –54 –60 –66 –42 –24 –30 –36 0 –12 –18 –40 0 0.5 –6 –20 0.3 1.0 –0.3 0 2.0 –0.6 20 2.5 –0.9 40 3.0 –1.2 SNR (dB) 60 3.5 –1.5 NUMBER OF OCCURRENCES WIDEBAND SINC3 HIGH PERFORMANCE SINC6 HIGH PERFORMANCE 80 HIGH PERFORMANCE MODE LOW POWER MODE Figure 22. SNR vs. System Clock Jitter, Wideband 0.433 Hz × ODR Filter –60 106.4 –70 106.3 –90 –100 –110 106.2 SNR (dB) THD AND THD + N (dB) –80 HIGH PERFORMANCE THD HIGH PERFORMANCE THD + N LOW POWER MODE THD LOW POWER MODE THD + N –120 106.1 INPUT FREQUENCY = 1kHz INPUT FREQUENCY = 20kHz 106.0 –130 105.9 –40 –35 –30 –25 –20 –15 INPUT AMPLITUDE (dBFS) –10 –5 0 105.8 2.0 22652-222 –150 –45 Figure 20. THD and THD + N vs. Input Amplitude, Wideband Filter, Tone at 1 kHz 2.1 2.2 2.3 2.4 INPUT COMMON-MODE VOLTAGE (V) 2.5 22652-040 –140 Figure 23. SNR vs. Input Common-Mode Voltage, Wideband 0.433 Hz × ODR Filter Rev. 0 | Page 19 of 86 AD7134 Data Sheet –118.5 200 HIGH PERFORMANCE MODE LOW POWER MODE –119.0 NUMBER OF OCCURRENCES –119.5 THD (dB) –120.0 –120.5 –121.0 INPUT FREQUENCY = 1kHz INPUT FREQUENCY = 20kHz –121.5 –122.0 –122.5 150 100 50 –123.0 5.0 4.3 3.6 2.9 2.2 1.5 SHORTED NOISE (µV) Figure 24. THD vs. Input Common-Mode Voltage, 0.5 dBFS Input Tone, Wideband 0.433 Hz × ODR Filter, Full-Scale Input Tone 22652-212 INPUT COMMON-MODE VOLTAGE (V) 0 0.8 2.5 0.1 2.4 –0.6 2.3 –1.3 2.2 –2.0 2.1 22652-041 –123.5 2.0 Figure 27. Shorted Noise, 0.433 × ODR Filter 50 300 45 NUMBER OF OCCURRENCES 35 RMS NOISE (µV) 250 WIDEBAND SINC6 SINC3 40 30 25 20 15 10 200 150 100 50 5 SHORTED NOISE (µV) Figure 28. Shorted Noise, Sinc3 Filter Figure 25. RMS Noise vs. Temperature, for Wideband 0.433 Hz × ODR, Sinc6 and Sinc3 Filters 90 180 80 160 60 50 40 30 20 10 85°C 25°C 0°C 140 120 100 80 60 40 0 20 40 60 TEMPERATURE (°C) 80 100 Figure 26. RMS Noise vs. Temperature, Low Power Mode for Wideband 0.433 × ODR Filter, Sinc6, Sinc3 Rev. 0 | Page 20 of 86 0 SHORTED NOISE (µV) 22652-215 0 22652-217 20 –2.0 –1.8 –1.6 –1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 RMS NOISE (µV) NUMBER OF OCCURRENCES SINC3 SINC6 WIDEBAND 70 22652-214 10.0 8.5 7.0 5.5 4.0 2.5 1.0 –0.5 –2.0 TEMPERATURE (°C) 0 –3.5 100 –6.5 80 –5.0 60 –8.0 40 –9.5 20 –11.0 0 22652-014 0 Figure 29. Shorted Noise Histogram, 0.433 × ODR Filter at Different Temperatures Data Sheet AD7134 12.4 –10 12.0 11.8 11.6 11.4 VREF = 4V VREF = 5V 0 1 2 3 CHANNEL NUMBER –70 –90 –110 30M Figure 33. Tone Magnitude In Band vs. Input Frequency 15.5 50 VREF = 4V VREF = 5V 0.433 × ODR 0.10825 × ODR 0 AMPLITUDE (dBFS) 15.0 14.5 14.0 13.5 –50 –100 0 1 2 3 CHANNEL 0 –200 22652-219 12.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 NORMALIZED FREQUENCY (fIN/fODR) 22652-029 –150 13.0 Figure 34. Amplitude vs. Normalized Frequency (fIN/fODR) Figure 31. RMS Noise per Channel for Various VREF Values, Low Power Mode 108 0 107 –20 SINC3 FILTER 106 –40 AMPLITUDE (dBFS) 105 104 103 102 –60 –80 –100 –120 101 –140 100 0 5 10 15 20 OUT OF BAND INPUT FREQUENCY (MHz) 25 –160 22652-038 99 Figure 32. In Band Dynamic Range vs. Out of Band Input Frequency of 1 V p-p Input Signal Wideband 0.433 Hz × ODR Filter 0 1 2 3 4 NORMALIZED FREQUENCY (fIN/fODR) 5 22652-032 IN BAND DYNAMIC RANGE (dBFS) 3M INPUT FREQUENCY (Hz) Figure 30. RMS Noise per Channel for Various VREF Values, Wideband 0.433 × ODR Filter RMS NOISE (µV) –50 –130 300k 22652-015 11.2 –30 22652-258 TONE MAGNITUDE IN BAND (dB) RMS NOISE (µV) 12.2 Figure 35. Amplitude vs. Normalized Frequency (fIN/fODR), Sinc Filter Profile Rev. 0 | Page 21 of 86 Data Sheet 10M 5 8M 4 6M 3 4M 2 2M 1 0 0 4 3 VREF = 4V VREF = 5V –2M –1 –4M –2 –6M –3 INL ERROR (ppm) 2 VAIN± (V) DATA OUTPUT (Codes) AD7134 1 0 1 2 3 –4 80 140 120 100 SAMPLES Figure 36. Step Response, Wideband Filter DATA OUTPUT VAIN± 8M 0 +VREF INPUT VOLTAGE Figure 39. INL Error vs. Input Voltage for Various VREF Levels, Low Power Mode 5 10M 4 4 6M 3 4M 2 2M 1 0 0 3 TA = 85°C TA = 25°C TA = 0°C –1 –4M –2 –6M –3 –8M –4 VAIN± (V) –2M INL ERROR (ppm) 2 1 0 –1 –2 285 290 –5 295 –4 –VREF SAMPLES Figure 37. Step Response, Sinc3 Filter 4 3 +VREF Figure 40. INL Error vs. Input Voltage, Wideband 0.433 × ODR Filter 4 5V 4V 3 2 INL ERROR (ppm) 2 1 0 –1 0 1 2 –3 3 +VREF Figure 38. INL Error vs. Input Voltage, Wideband 0.433 × ODR Filter 4 –VREF 22652-018 0 INPUT VOLTAGE HALF SCALE FULL-SCALE 1/4TH SCALE 1 –2 –4 –VREF 0 INPUT VOLTAGE 22652-019 280 0 INPUT VOLTAGE +VREF 22652-226 275 –3 22652-033 –10M 270 INL ERROR (ppm) DATA OUTPUT (Codes) 4 –VREF 22652-031 –5 –10M 60 22652-225 DATA OUTPUT VAIN± –8M Figure 41. INL Error vs. Input Voltage, Full-Scale, Half Scale, and Quarter Scale Inputs Rev. 0 | Page 22 of 86 AD7134 40 50 35 40 25 20 15 10 30 20 10 0 –10 0 –20 ABSOLUTE INL (ppm) 22652-300 5 0 10 20 30 40 50 60 70 Figure 42. INL Distribution 90 Figure 45. Offset Error vs. Temperature 70 250 85°C 25°C 0°C NUMBER OF OCCURRENCES 60 OFFSET ERROR (µV) 80 TEMPERATURE (°C) 22652-177 OFFSET ERROR (µV) 30 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 NUMBER OF OCCURRENCES Data Sheet 50 40 30 20 200 150 100 50 155 95 125 65 500 200 AVDD1V8 = 1.95V AVDD1V8 = 1.8V AVDD1V8 = 1.65V NUMBER OF OCCURRENCES 85°C 25°C 0°C 100 50 0 –50 –100 –150 400 300 200 100 Figure 44. Offset Error vs. AVDD5 Supply Voltage Rev. 0 | Page 23 of 86 22652-229 85 OFFSET ERROR (µV) Figure 47. Offset Error Distribution, Low Power Mode 105 65 45 5 25 –15 –35 –55 –75 –115 0 –135 AVDD5 SUPPLY VOLTAGE (V) 5.5 –155 5.0 –175 –250 4.5 –95 –200 22652-276 OFFSET ERROR (µV) 35 Figure 46. Offset Error Distribution, High Performance Mode Figure 43. Offset Error vs. Input Common-Mode Voltage, Wideband 0.433 Hz × ODR Filter 150 5 OFFSET ERROR (µV) 22652-228 INPUT COMMON-MODE VOLTAGE (V) 0 –25 2.5 –55 2.4 –115 2.3 –145 2.2 –175 2.1 22652-020 0 2.0 –85 10 AD7134 Data Sheet 0 200 HIGH PERFORMANCE MODE LOW POWER MODE 150 CHANNEL OFFSET ERROR (µV) –10 AVDD1V8 = 1.95V AVDD1V8 = 1.8V AVDD1V8 = 1.65V 100 GAIN ERROR (ppm/FSR) –20 –30 –40 –50 –60 50 0 –50 –100 –150 –200 –70 20 0 60 40 80 –300 4.5 22652-232 –80 100 TEMPERATURE (°C) 4.7 5.1 4.9 5.3 5.5 SUPPLY VOLTAGE (V) 22652-275 –250 Figure 51. Gain Error vs. Supply Voltage Figure 48. Channel Offset Error Matching 60 0 50 –200 GAIN ERROR (ppm/FS) GAIN ERROR (ppm/FS) 40 –400 –600 –800 –1000 30 20 10 0 –10 –1200 2.2 2.3 2.4 –30 22652-021 2.1 2.5 INPUT COMMON-MODE VOLTAGE (V) 0 30 40 50 60 70 80 90 Figure 52. Gain Error vs. Temperature –40 85°C 25°C 0°C –60 400 CMRR (dBFS) –80 300 200 –100 –120 –140 100 0 –80 –60 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 –180 1k 10k 100k 1M 10M INPUT FREQUENCY (Hz) Figure 50. Gain Error Distribution Figure 53. CMRR vs. Input Frequency, Wideband 0.433 × ODR Filter Rev. 0 | Page 24 of 86 22652-022 –160 22652-233 NUMBER OF OCCURRENCES 20 TEMPERATURE (°C) Figure 49. Gain Error vs. Input Common-Mode Voltage, Wideband 0.433 × ODR Filter 500 10 22652-178 –20 –1400 2.0 Data Sheet AD7134 –80 500 AVDD5 DVDD5 AVDD1V8 DVDD1V8 CLKVDD IOVDD –90 400 GROUP DELAY (µs) AC PSR (dB) –100 450 –110 –120 –130 350 300 250 200 150 –140 100 –150 500 5k 50k 500k 0 10k 22652-023 –160 50 5M FREQUENCY (Hz) 1M ODR (Hz) Figure 54. AC Power Supply Rejection (PSR) vs. Frequency, Wideband 0.433 × ODR Filter Figure 57. Group Delay vs. ODR, Sinc3 Filter 350 90 CH3 CH2 CH1 80 NUMBER OF OCCURRENCES 300 250 200 DIFFERENTIAL COMPONENT COMMON-MODE COMPONENT 150 100 50 70 60 50 40 30 20 20 40 60 0 22652-034 0 80 TEMPERATURE (°C) PHASE (Degrees) Figure 55. Analog Input Current vs. Temperature, Wideband 0.433 Hz × ODR Filter 22652-256 10 0 –0.020 –0.019 –0.018 –0.017 –0.016 –0.015 –0.014 –0.013 –0.012 –0.011 –0.010 –0.009 –0.008 –0.007 –0.006 –0.005 –0.004 –0.003 –0.002 –0.001 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010 ANALOG INPUT CURRENT (µA/V) 100k 22652-273 50 Figure 58. Channel Phase Matching Distribution for Input Tone at 20 kHz 7 50 85°C 25°C 0°C 45 6 35 PHASE (Degrees) GROUP DELAY (µs) 40 5 4 3 30 25 20 15 2 10 1 10k INPUT FREQUENCY (Hz) 100k Figure 56. Group Delay vs. Input Frequency, Sinc3 Filter ODR = 1250 kSPS Rev. 0 | Page 25 of 86 0 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 TEMPERATURE (°C) Figure 59. Channel Phase Matching vs. Temperature 22652-257 0 1k 22652-042 5 AD7134 Data Sheet TERMINOLOGY AC Common-Mode Rejection Ratio (CMRR) AC CMRR is defined as the ratio of the power in the ADC output at frequency, f, to the power of a 100 mV p-p sine wave applied as the common-mode voltage to the AINx+ pin and AINx− pin at sampling frequency (fS). Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is LSB= 2 × AC CMRR (dB) = 10 log(Pf/PfS) VREFCAP 2N where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. where: VREFCAP is the voltage measured on the REFCAP pin. N = 24 for the AD7134. Integral Nonlinearity (INL) Error INL error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. DC Power Supply Rejection Ratio (DC PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. DC PSRR is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa and nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), and the thirdorder terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7134 is tested using the International Telephonic Consultative Committee (CCIF) standard, where two input frequencies near to each other are used. In this case, the secondorder terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second-order and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Gain Error The first transition (from 100 … 000 to 100 …001) occurs at a level ½ LSB above nominal negative full scale (−4.0959375 V for the ±4.096 V range). The last transition (from 011 … 110 to 011 … 111) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.0959375 V for the ±4.096 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Gain Drift Gain drift is the ratio of the gain error change due to a temperature change of 1°C and the full-scale range (2N). Gain drift is expressed in parts per million. AC Power Supply Rejection (AC PSR) AC PSR is the amplitude of the tone observed when a 100 mV p-p signal is injected on the supply. For example, if a 100 mV p-p signal injected on the supply at a frequency of 1 kHz and a −108 dB tone is observed at 1 kHz in the FFT output, then −108 dB is the ac power supply rejection. Alias Rejection Alias rejection is defined as the ratio of the power in the ADC output at frequency, fIN, to the power of a −6 dBFS input signal at frequency, MCLK ± fIN. Alias rejection = 10 log(PfIN/PMCLK ± fIN) where: PfIN is the power at frequency, fIN, in the ADC output. PMCLK ± fIN is the power at frequency, MCLK ± fIN, in the ADC output. Group Delay Group delay is defined as the difference of phase delays measured at the ADC output and full-scale sine wave ADC input. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the ODR/2 frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the ODR/2 frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal (excluding the first five harmonics). Rev. 0 | Page 26 of 86 Data Sheet AD7134 Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Offset Error Offset error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Offset Error Drift Offset error drift is the ratio of the offset error change due to a temperature change of 1°C. For this calculation, observe the change in output code when the temperature varies over the full range and take the ratio. Offset error drift is expressed in microvolts per degree Celsius. Crosstalk Crosstalk is measured as tone amplitude observed at Frequency X on Channel 1 when Channel 0 and Channel 2 are driven simultaneously with a full-scale tone at Frequency X. Rev. 0 | Page 27 of 86 AD7134 Data Sheet THEORY OF OPERATION Figure 60 illustrates a simplified signal path of one of the four Σ-Δ ADC channels of the AD7134. In a typical operation, the CTSD modulator oversamples the analog input signal at the modulator sampling frequency at MCLK. The ADC quantization noise is modulated to the higher frequency band during this process. The oversampled modulator output is then decimated through an ASRC and digital filter. The decimation removes the additional bandwidth caused by oversampling along with the shaped quantization. The result is a high precision data output from the digital filter at the user defined ODR. MODULATOR ASYNCHRONOUS SAMPLE RATE CONVERTER DIGITAL FILTER LOOP FILTER H(f) ADC ASRC – SAMPLING CLOCK 22652-078 DAC To achieve the required level of accuracy, at the end of each sampling period, the disturbed input signal must settle to the actual source value within 1 LSB of the ADC target effective resolution, which is particularly challenging with a higher precision or higher input bandwidth requirement. A common solution to overcome the input settling challenge is to buffer the input with a high bandwidth amplifier with high output driving capability, as shown in Figure 61. QUANTIZER + phenomenon known as charge injection or charge kickback. In either case, the sudden change of current flow at the input of the ADC reacts with the finite impedance of the driving circuit to create a disturbance in the form of voltage variation. The profile of the variation depends on the bandwidth and the impedance of the driving circuit. MCLK Figure 60. Signal Path Overview CONTINUOUS TIME SIGMA-DELTA MODULATOR SAMPLE/HOLD – Almost all of the contemporary precision ADCs are designed with a switched capacitor-based sample-and-hold circuit. The sampleand-hold circuit is an essential part of the successive approximation register (SAR) ADC architecture, for example, where it is used to reduce the aperture time and maintain a steady input level during conversion. The discrete time Σ-Δ ADCs also use the sample-and-hold circuit in both the input path and the feedback loop, which simplifies the design. Because the analog input signal is converted to a discrete time signal by the sample-andhold circuit, the ADCs with the sample-and-hold circuit are also known as discrete time ADCs. The sample-and-hold circuit offers many benefits to the ADC design. However, some side effects of using the sample-andhold circuit, such as charge kickback and signal aliasing, require additional effort in designing the ADC into a system. SIGNAL IN ADC + DRIVING AMPLIFIER CONVERSION TIME HOLD SETTLING TIME MCLK PERIOD 22652-079 SAMPLE Figure 61. Driving the Input of a Discrete Time ADC The sample-and-hold circuit is also used by the discrete time ADC on the reference input. A high bandwidth amplifier is also required to drive the ADC reference input. The CTSD modulator employs the same Σ-Δ modulation principle, such as oversampling and noise shaping, as the discrete time sigma-delta (DTSD) modulator, with the key difference being the CTSD does not use the sample-and-hold circuit. The drawbacks of using an ADC driving amplifier include the following: The CTSD modulator design used on the AD7134 uses both a continuous time integrator and a continuous time DAC. This architecture offers some unique system benefits to the precision data acquisition systems design over the discrete time ADCs. • EASY TO DRIVE INPUT AND REFERENCE CTSD architecture allows the AD7134 to have a constant resistive input characteristic. This behavior simplifies the frontend circuit design, allowing lower bandwidth, and low power high performance precision amplifiers to directly drive the ADC. The switching action of the sample-and-hold circuit used on the discrete time ADCs creates disturbances on the input node. There are two main impacts of the disturbance. The first is the sudden loading of the input node by the sampling capacitor, for which the magnitude of the disturbance is proportional to the input differential voltage/differential time. The second impact is from the charges stored in the parasitic capacitance of the switches being pushed out to the input node when the switch is closed, a • • The amplifier bandwidth must be much higher than the input signal bandwidth, leading to higher power consumption The additional components in the signal chain lead to more noise and error Additional design complexity to ensure stability when driving the dynamic capacitive load of a discrete time ADC Similarly, due to the continuous time DAC used in the modulator feedback loop, the AD7134 reference input also has a constant resistive input characteristic, making it possible to drive the ADC reference input directly with a voltage reference IC. Rev. 0 | Page 28 of 86 Data Sheet AD7134 INHERENT ANTIALIASING FILTER (AAF) When sampling an analog sinusoid signal at less than twice of its frequency, reconstruction through interpolation results in a lower frequency signal than the original. This phenomenon is known as aliasing. Figure 62 shows an example of signal aliasing viewed in both the time and frequency domains. The example shows the digital discrete time representations of a 3 kHz, 17 kHz, and 23 kHz signal sampled at 20 kHz are identical. When interpolating the result, the output is always a 3 kHz sine wave, which means that, in this sampling system, the frequency component of the input signal at 17 kHz and 23 kHz appear at 3 kHz in the output. The aliasing occurs at the point of sampling of the analog signal. The only way to guarantee the matching between input and output signal frequency is to limit the input signal bandwidth before sampling. In the previous example of the frequency component input signal, if the signal is low-pass filtered with a bandwidth of 10 kHz, the interpolated output always matches the filtered input signal. Because the purpose of the low-pass filter is to prevent high frequency signals from aliasing down, the filter is also known as an antialiasing filter. The signal sampling occurs at the very front of the discrete time ADC in the sample-and-hold circuit. An external antialiasing filter is required in front of the discrete time ADC to protect it against signal aliasing. The antialiasing filter design requires a fine balance between the aliasing rejection level and the phase and magnitude distortion of the input signal. The extra components also introduce error, noise, and additional power consumption to the signal chain. Other than being easy to drive, the other major advantage of the CTSD architecture is its inherent antialiasing property. Without the sample-and-hold circuit, the sampling of the analog signal takes place inside the CTSD modulator at the quantizer, after the integrator. This sampling scheme allows the device to take advantage of the low-pass response of the integrator and intrinsically reject signals around the sampling frequency of the modulator. This property provides an inherent aliasing rejection of up to 102.5 dB for the AD7134. As shown in Figure 63, combining the inherent antialiasing response of the CTSD modulator with the low ripple wideband digital filter, the AD7134 is fully protected from the out of band frequency tones. fIN0 = 3kHz fS = 20kHz x0(t) fIN1 = 17kHz fS = 20kHz x1(t) |H(f)| fIN2 = 23kHz fS = 20kHz fIN1 fS f t Figure 62. Aliasing Explained with an Example Shown in Both Time and Frequency Domains H(f) INHERENT AAF RESPONSE DIGITAL FILTER RESPONSE COMBINED RESPONSE FULL SCALE –85dB IN AA1 MODE –102.5dB IN AA2 MODE –110dB OVER SAMPLING SIGNAL BAND OF INTEREST SAMPLING FREQUENCY ( f S) Figure 63. Combined Magnitude Response of the Inherent Antialiasing Filter and the Digital Filter of the AD7134 Rev. 0 | Page 29 of 86 fIN2 f 22652-080 fIN0 22652-081 x2(t) AD7134 Data Sheet Figure 65 shows the signal chain of the AD7134. For the continuous time-based AD7134, the easy to drive and inherent antialiasing property results in significant simplification of the analog front-end design. Other than the apparent area and cost saving, the front-end simplification also removes the noise, error, and instability introduced by the removed circuit, improving the overall performance of the signal chain. As shown in Figure 65, the instrumentation amplifier can directly drive the resistive inputs of the AD7134, and the bandwidth of the amplifier adds to the antialias rejection, making the signal chain an alias free signal chain. ANALOG FRONT-END DESIGN SIMPLIFICATION The result from the two major benefits of the CTSD architecture described in the Easy to Drive Input and Reference section and the Inherent Antialiasing Filter section is a major simplification of the analog front-end design of the precision medium bandwidth data acquisition signal chain. Figure 64 shows the analog front-end circuit for a discrete time ADC. For discrete time ADC, in between the precision instrumentation amplifier and the ADC is a third-order antialiasing filter plus an ADC driving circuit based on a fully differential ADC driving amplifier. An additional RC circuit is required at the ADC input to ensure stability of the driver and to help further suppress the kickback. A reference driving circuit based on an operation amplifier is placed between the reference IC and the ADC. The circuit incorporates a second-order low-pass filter to help reduce the wideband noise from the reference source. + IN+ – DISCRETE TIME ADC IN-AMP + IN– – REFIN GAIN + REF 22652-083 – Figure 64. Example Analog Front-End Circuit Design of the Discrete Time-Based ADC IN+ AD7134 IN-AMP IN– REFIN REFCAP REF 22652-082 GAIN Figure 65. Example Analog Front-End Circuit Design of the AD7134 Rev. 0 | Page 30 of 86 Data Sheet AD7134 NOISE PERFORMANCE AND RESOLUTION Table 9 to Table 16 contain the data of the noise performance for the wideband 0.433 Hz × ODR filter, wideband 0.10825 Hz × ODR filter, sinc6 filter, and the sinc3 digital filter of the AD7134 for various output data rates and channel averaging settings. The noise values and dynamic range specified are typical for the bipolar input range with an external 4.096 V reference (VREF). The rms noise is measured with shorted analog inputs. The dynamic range is calculated as Dynamic Range (dB) = 20log10((2 × VREF/2√2)/(RMS Noise) The LSB size is calculated as follows: LSB Size = (2 × VREF)/224 where LSB Size is 488 nV with a 4.096 V reference. Table 9. Wideband 0.433 Hz × ODR Filter, High Performance Mode Noise Performance vs. Output Data Rate (VREF = 4.096 V) Output Data Rate (kSPS) 374 325 285 256 235 200 175 128 100 80 64 32 16 10 5 2.5 −3 dB Bandwidth (kHz) 161.94 140.73 123.41 110.85 101.76 86.60 75.78 55.42 43.30 34.64 27.71 13.86 6.93 4.33 2.17 1.08 Single Channel Dynamic RMS Noise Range (dB) (µV) 107.21 12.63 108.09 11.41 108.65 10.69 109.21 10.03 109.71 9.47 110.58 8.57 111.12 8.05 112.72 6.70 113.71 5.97 114.80 5.27 115.83 4.68 118.91 3.28 121.94 2.32 123.80 1.87 126.68 1.34 129.36 0.99 2:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 110.46 8.68 111.21 7.96 111.81 7.43 112.5 6.87 112.79 6.63 113.63 6.02 114.27 5.6 115.66 4.77 116.81 4.17 117.9 3.68 118.87 3.29 121.82 2.34 124.81 1.66 126.67 1.34 129.55 0.96 132.32 0.7 4:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 113.46 6.15 114.25 5.61 114.8 5.27 115.26 4.99 115.85 4.67 116.57 4.29 117.25 3.97 118.68 3.37 119.83 2.95 120.78 2.64 121.87 2.33 124.89 1.65 127.8 1.17 129.76 0.94 132.34 0.69 135.08 0.51 Table 10. Wideband 0.433 Hz × ODR Filter, Low Power Mode Noise Performance vs. Output Data Rate (VREF = 4.096 V) Output Data Rate (kSPS) 374 325 285 256 235 200 175 128 100 80 64 32 16 10 5 2.5 −3 dB Bandwidth (kHz) 161.94 140.73 123.41 110.85 101.76 86.60 75.78 55.42 43.30 34.64 27.71 13.86 6.93 4.33 2.17 1.08 Single Channel Dynamic RMS Noise Range (dB) (µV) 100.42 27.61 102.03 22.93 103.21 20.01 104.08 18.10 104.67 16.91 105.80 14.85 106.64 13.48 108.29 11.15 109.49 9.71 110.58 8.57 111.63 7.59 114.72 5.32 117.69 3.78 119.73 2.99 122.79 2.10 125.64 1.51 2:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 103.41 19.55 105.04 16.21 106.37 13.9 107.12 12.75 107.89 11.68 108.97 10.31 109.79 9.37 111.32 7.87 112.55 6.83 113.54 6.09 114.68 5.34 117.75 3.75 120.78 2.64 122.72 2.11 125.66 1.50 128.58 1.07 Rev. 0 | Page 31 of 86 4:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 106.33 13.96 107.96 11.57 109.21 10.03 110.12 9.03 110.64 8.50 111.76 7.47 112.55 6.82 114.31 5.57 115.51 4.85 116.47 4.34 117.61 3.81 120.64 2.68 123.71 1.88 125.76 1.49 128.61 1.07 131.48 0.77 AD7134 Data Sheet Table 11. Wideband 0.10825 Hz × ODR Filter, High Performance Mode Noise Performance vs. Output Data Rate (VREF = 4.096 V) Output Data Rate (kSPS) 374 325 285 256 235 200 175 128 100 80 64 32 16 10 5 2.5 −3 dB Bandwidth (kHz) 40.49 35.18 30.85 27.71 25.44 21.65 18.94 13.86 10.83 8.66 6.93 3.46 1.73 1.08 40.49 35.18 Single Channel Dynamic RMS Noise Range (dB) (µV) 112.80 6.63 113.57 6.07 114.20 5.65 114.71 5.33 115.14 5.07 115.72 4.74 116.44 4.36 117.76 3.75 118.82 3.32 119.76 2.98 120.85 2.63 123.64 1.91 126.50 1.37 128.44 1.10 130.91 0.83 133.59 0.61 2:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 116.03 4.57 116.84 4.16 117.37 3.91 117.63 3.80 118.13 3.59 118.88 3.29 119.62 3.02 120.88 2.61 121.9 2.32 123.06 2.03 123.78 1.87 126.56 1.36 129.30 0.99 131.23 0.79 133.54 0.60 136.13 0.45 4:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 119.01 3.24 119.67 3.00 120.12 2.85 120.71 2.66 121.16 2.53 121.61 2.40 122.37 2.20 123.85 1.86 124.79 1.66 125.85 1.47 126.78 1.32 129.61 0.95 132.36 0.69 134.15 0.56 136.31 0.44 138.84 0.33 Table 12. Wideband 0.10825 Hz × ODR Filter, Low Power Mode Noise Performance vs. Output Data Rate (VREF = 4.096 V) Output Data Rate (kSPS) 374 325 285 256 235 200 175 128 100 80 64 32 16 10 5 2.5 −3 dB Bandwidth (kHz) 40.49 35.18 30.85 27.71 25.44 21.65 18.94 13.86 10.83 8.66 6.93 3.46 1.73 1.08 40.49 35.18 Single Channel Dynamic RMS Noise Range (dB) (µV) 108.46 10.94 109.29 9.94 110.05 9.11 110.46 8.69 110.80 8.35 111.45 7.75 112.26 7.06 113.51 6.12 114.69 5.34 115.64 4.78 116.73 4.22 119.81 2.96 122.60 2.15 124.75 1.68 127.37 1.24 130.14 0.90 2:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 111.64 7.58 112.34 6.99 113.09 6.41 113.61 6.04 113.97 5.79 114.69 5.33 115.35 4.94 116.6 4.28 117.6 3.81 118.64 3.38 119.66 3.01 122.58 2.15 125.58 1.52 127.41 1.23 130.32 0.88 132.99 0.64 Rev. 0 | Page 32 of 86 4:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 114.53 5.43 115.20 5.03 115.90 4.64 116.42 4.37 116.96 4.01 117.66 3.79 118.24 3.54 119.63 3.02 120.61 2.69 121.76 2.36 122.54 2.16 125.64 1.51 128.61 1.07 130.45 0.86 133.14 0.63 135.84 0.46 Data Sheet AD7134 Table 13. Sinc6 Filter, High Performance Mode Noise Performance vs. Output Data Rate (VREF = 4.096 V) Output Data Rate (kSPS) 1496 1250 1000 750 500 375 325 256 175 128 80 64 32 10 5 2.5 −3 dB Bandwidth (kHz) 278.406 232.63 186.10 139.58 93.05 69.79 60.48 47.64 32.57 23.82 14.89 11.91 5.96 1.86 0.93 0.47 Single Channel Dynamic RMS Noise Range (dB) (µV) 100.66 26.85 102.98 20.56 105.15 16.01 107.33 12.46 109.64 9.54 111.09 8.08 111.94 7.32 113.20 6.34 114.82 5.26 116.32 4.42 118.34 3.50 119.38 3.11 122.38 2.20 126.98 1.30 129.69 0.95 131.97 0.73 2:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 104.13 18.01 106.34 13.95 108.48 10.90 110.57 8.57 112.87 6.57 114.27 5.59 115.02 5.13 116.20 4.48 117.97 3.65 119.35 3.12 121.50 2.43 122.36 2.20 125.33 1.56 129.87 0.92 132.47 0.68 135.31 0.49 4:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 107.07 12.83 109.24 10.00 111.44 7.75 113.52 6.10 115.85 4.66 117.32 3.94 118.02 3.63 119.16 3.19 120.90 2.61 122.29 2.22 124.26 1.77 125.46 1.54 128.24 1.12 132.90 0.65 135.29 0.49 137.57 0.383 Table 14. Sinc6 Filter, Low Power Mode Noise Performance vs. Output Data Rate (VREF = 4.096 V) Output Data Rate (kSPS) 1496 1250 1000 750 500 375 325 256 175 128 80 64 32 10 5 2.5 −3 dB Bandwidth (kHz) 278.406 232.63 186.10 139.58 93.05 69.79 60.48 47.64 32.57 23.82 14.89 11.91 5.96 1.86 0.93 0.47 Single Channel Dynamic RMS Noise Range (dB) (µV) 84.11 180.40 87.78 118.22 92.28 70.43 97.65 37.96 103.33 19.74 101.17 25.32 107.19 12.65 108.60 10.76 110.53 8.62 112.05 7.23 114.25 5.61 115.17 5.05 118.22 3.55 123.03 2.04 125.99 1.45 128.91 1.04 2:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 87.30 124.98 90.93 82.3 95.42 49.04 100.78 26.48 106.53 13.65 103.98 18.32 110.22 8.93 111.58 7.63 113.63 6.03 115.08 5.10 117.28 3.96 118.21 3.56 121.30 2.49 126.15 1.42 129.11 1.01 131.75 0.74 Rev. 0 | Page 33 of 86 4:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 90.05 91.06 93.92 58.31 98.36 34.99 103.61 19.12 109.33 9.89 104.34 17.57 113.13 6.38 114.51 5.44 116.51 4.33 118.06 3.62 120.16 2.84 121.20 2.52 124.23 1.78 129.02 1.02 131.99 0.72 134.57 0.54 AD7134 Data Sheet Table 15. Sinc3 Filter, High Performance Mode Noise Performance vs. Output Data Rate (VREF = 4.096 V) Output Data Rate (kSPS) 1496 1000 750 375 187.5 128 64 32 16 5 2.5 1.25 0.625 0.06 0.05 0.01 −3 dB Bandwidth (kHz) 391.503 261.70 196.28 98.14 49.07 33.50 16.75 8.37 4.19 1.31 0.654 0.327 0.164 0.016 0.013 0.003 Single Channel Dynamic RMS Noise Range (dB) (µV) 95.32 49.64 101.62 24.03 104.72 16.82 109.56 9.63 112.88 6.58 114.76 5.29 117.83 3.72 120.91 2.61 125.74 1.50 128.29 1.11 130.89 0.83 132.91 0.66 134.66 0.54 137.59 0.38 137.46 0.39 137.22 0.40 2:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 98.67 33.74 105.05 16.18 108.01 11.51 112.64 6.76 116.11 4.53 117.81 3.72 120.91 2.60 124.10 1.80 128.66 1.06 131.34 0.78 133.60 0.60 135.52 0.48 137.28 0.39 139.89 0.29 139.49 0.30 140.07 0.28 4:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 101.46 24.48 107.97 11.56 110.97 8.19 115.59 4.81 119.04 3.23 120.72 2.66 123.88 1.85 126.87 1.31 131.54 0.76 134.17 0.56 136.30 0.44 138.08 0.36 139.79 0.29 142.62 0.21 141.81 0.23 141.65 0.23 Table 16. Sinc3 Filter, Low Power Mode Noise Performance vs. Output Data Rate (VREF = 4.096 V) Output Data Rate (kSPS) 1496 1000 750 375 187.5 128 64 32 16 5 2.5 1.25 0.625 0.06 0.05 0.01 −3 dB Bandwidth (kHz) 391.503 261.70 196.28 98.14 49.07 33.50 16.75 8.37 4.19 1.31 0.654 0.327 0.164 0.016 0.013 0.003 Single Channel Dynamic RMS Noise Range (dB) (µV) 76.68 424.32 85.34 156.58 91.30 78.89 98.67 33.77 108.35 11.08 110.49 8.65 113.73 5.96 116.75 4.21 121.75 2.37 124.63 1.70 127.47 1.23 130.07 0.91 132.59 0.68 137.95 0.37 137.87 0.37 138.06 0.36 2:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 79.72 299.01 88.44 109.66 87.19 126.6 101.30 24.94 111.42 7.78 113.50 6.12 116.70 4.23 119.73 2.98 124.65 1.69 127.59 1.20 130.24 0.89 133.05 0.64 135.23 0.50 140.07 0.28 139.98 0.29 140.67 0.26 Rev. 0 | Page 34 of 86 4:1 Channel Averaging Dynamic RMS Noise Range (dB) (µV) 82.62 214.21 91.26 79.17 97.41 39.00 103.42 19.52 114.42 5.50 116.36 4.40 119.69 3.00 122.74 2.11 127.7 1.19 130.54 0.86 133.21 0.63 135.59 0.48 137.85 0.37 141.77 0.23 141.97 0.23 141.78 0.23 Data Sheet AD7134 CIRCUIT INFORMATION CORE SIGNAL CHAIN Each ADC channel on the AD7134 has an identical signal path from the analog input pins to the data interface. Each ADC channel has its own CTSD modulator that oversamples the analog input and passes the digital representation to the digital filter block. The data is filtered, scaled for gain and offset (depending on user settings), and then output on the data interface. Control of the flexible settings for the signal chain is provided by either using the pin control or the SPI control set at power-up by the state of the PIN/SPI input pin. The ADC can use up to a 5 V reference and converts the differential voltage between the analog inputs (AINx+ and AINx−) into a digital output. The analog input accepts only differential input. The ADC converts the voltage difference between the analog input pins into a digital code on the output. Using a commonmode voltage of VREF/2 for the analog inputs, AINx+ and AINx−, maximizes the ADC input range. The 24-bit conversion result is in twos complement, MSB first format. See Table 17 for more details. ANALOG INPUTS Input Structure Due to the CTSD architecture, the AD7134 has a pure resistive input, with a simplified input structure diagram, as shown in Figure 66. The ADC supports only fully differential input signals. The input impedance has a differential resistance value of 6.25 kΩ. Internally, both AINx+ and AINx− are biased to VREF/2 through the internal resistor network. The AD7134 achieves optimal performance with a differential input signal that has a commonmode voltage equal to VREF/2. In Figure 66, CIN means input capacitance and RIN means input resistance. REFCAP AD7134 Input Voltage Range The resistive input structure of the AD7134 allows its input pins to tolerate wide input voltage swings without damaging the device. With the ADC full-scale input being ±VREF, each of the ADC input pins can accept absolute input voltages from 0 V to 5 V. When the individual ADC input channel is powered down, the input is high impedance. Input Common-Mode Range The AD7134 supports an input common-mode range from VREF/2 to AVDD5/2. Optimal performance is achieved with the input common-mode level equal to half of the reference input voltage. VCM OUTPUT The AD7134 provides a buffered common-mode voltage output on the VCM pin. This output can shift the level of the analog input signals. By incorporating the VCM buffer into the ADC, the AD7134 reduces component count and board space. In pin control mode, the VCM potential is fixed to VREF/2 and is enabled by default. In SPI control mode, the user has the option to program the VCM output voltage level from VREF/20 to 19 × VREF/20, or AVDD5/2. The user can also choose to disable the VCM output if not used in SPI control mode. The VCM output level can be configured through the VCMBUF_ REF_DIV_SEL bits and the VCMBUF_REF_SEL bit. The VCM output can be enabled or disabled using the PWRDN_VCMBUF bit. When disabled, the VCM behaves with high impedance. When driving capacitive loads larger than 0.1 µF, it is recommended to place a 50 Ω series resistor between the VCM pin and the capacitive load to ensure the stability of the output buffer. 2 × RIN AINx+ When the device is powered down, with the PDN pin low, in sleep mode, or with the PWRDN_CHx bits, the input behaves with high impedance. RIN 2 × RIN CIN RIN AGND5 2 × RIN 22652-088 2 × RIN AINx– Figure 66. ADC Input Structure Table 17. Output Codes and Ideal Input Voltages Description Full Scale (FS) − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FS + 1 LSB −FS Analog Input (AINx+ − AINx−), VREF = 4.096 V 4.095999512 V 488 nV 0V −488 nV −4.095999512 V −4.096 V Rev. 0 | Page 35 of 86 Digital Output Code, Twos Complement (Hex) 0x7FFFFF 0x000001 0x000000 0xFFFFFF 0x800001 0x800000 AD7134 Data Sheet REFERENCE INPUT Similar to the ADC inputs, the AD7134 reference input is also resistive, which allows the external reference IC to drive the AD7134 directly without the need of a reference buffer. The user can directly connect the external reference source to the REFCAP pin of the AD7134. Tie the CLKSEL pin to the IOVDD pin and connect an external crystal between the XTAL1 pin and the XTAL2/CLKIN pin to enable the crystal clock option. Tie the CLKSEL pin to the IOGND pin and connect an external CMOS clock signal to the XTAL2/CLKIN pin to enable the CMOS clock option. XTAL2/CLKIN AD7134 REFIN 1.8V CLKVDD 20Ω AD7134 MODULATOR REFERENCE OUT 22652-091 CLKSEL REFCAP REFERENCE IC XTAL1 Figure 69. Master Clock Provided by a Crystal GND 48MHz OSCILLATOR 22652-089 REFGND Figure 67. Direct Reference Input Connection to REFCAP Pin The user can reduce the noise on the reference source by filtering the reference signal. An internal 20 Ω resistor between the REFIN pin and the REFCAP pin enables the user to form a first-order RC filter by connecting a capacitor on the REFCAP pin. REFIN MODULATOR REFERENCE REFGND Figure 70. Master Clock Provided by an Oscillator XCLKOUT OUTPUT 22652-090 REFCAP CLKGND When using the crystal clock option, a buffered output from the internal crystal oscillator can be made available on the XCLKOUT pin. Distribute this CMOS clock signal to other AD7134 devices in the same system to allow multiple AD7134 devices to operate from a single external crystal. The XLKCOUT pin can drive 45 pF of load. AD7134 OUT 20Ω GND CLKSEL AD7134 XTAL2/CLKIN Figure 68. Reference Input Connection Using REFIN Pin The series resistor creates a small voltage drop that varies with the device mode of operation. In SPI control mode, the user can configure the device to autocorrect this drop in different operating modes by setting the REFIN_GAIN_CORR_EN bit to 1. The reference input current reduces by 1/4 with the disable of each individual ADC channel. This reduction in current is also accounted for with the reference autocorrection function. AD7134 CLOCK INPUT The AD7134 use an internal oscillator during the initial power-up configuration. After the AD7134 has completed the start-up routine, a clock handover to the externally applied CLKIN occurs. The AD7134 supports two master clock input options. The device can accept an external CMOS clock signal or generate the clock signal using an external crystal. The clock source is determined at power-on by the state of the CLKSEL pin. 1.8V CLKVDD CLKSEL XCLKOUT XTAL2/CLKIN XTAL1 CLKSEL AD7134 The autocorrection function is disabled in pin control mode. The reference input behaves with high impedance when the device is powered down or in power down mode with the PDN pin low. XTAL1 CLKGND 22652-093 REFERENCE IC XTAL1 22652-092 See the Reference Noise Filtering section for examples on how to design the reference filter. XTAL2/CLKIN Figure 71. Provide Master Clock to Multiple Devices from a Single Crystal The XCLKOUT output is enabled by default in pin control mode if the crystal clock options are selected. The XCLKOUT output is disabled in pin control mode if the CMOS clock option is selected. The XCLKOUT output is disabled by default in SPI control mode and can be enabled by writing 1 to the XCLKOUT_EN bit. Rev. 0 | Page 36 of 86 Data Sheet AD7134 POWER OPTIONS The ASRC is placed between the modulator and the digital filter of each ADC channel. The ASRC has the following two inputs: Depending on the bandwidth of interest for the measurement, the AD7134 allows the user to trade measurement bandwidth with power consumption or resolution through its two selectable power modes: high performance and low power. The low power mode operates with half the modulator clock frequency, resulting in comparable noise performance to the high performance mode at half of the output data rate and 40% of power saving. For details of the performance difference between the two modes, see the Noise Performance and Resolution section. • • Data that comes at the MCLK rate from the modulator ODR input, which is either an external asynchronous signal (slave) or a fractional value (master) DATA RATE = MODULATOR SAMPLING FREQUENCY 24MHz FOR HIGH PERFORMANCE MODE DATA RATE = FINAL OUTPUT 12MHz FOR LOW POWER MODE DATA RATE (ODR) CTSD MODULATOR Channel Power-Down ASRC DIGITAL FILTER 22652-094 Operating Power Modes ODR INPUT DATA RATE = ODR × IF RATIO In SPI control mode, the four ADC channels can be individually powered down to save power when not used. Figure 72. Data Rate at Each Stage of Conversion Path The PWRDN_CHx bits control the power-down of each channel. Powering down an ADC channel reduces the supply current and the input current. The input of a powered down channel goes high-Z. The reference input current reduces by 1/4 with the power-down of each ADC channel. The digital PLL present in the ASRC block tracks and locks on the ODR input and generates a fractional ratio. The ASRC works through interpolation and resampling of the modulator output at a fractional ratio to the sampling frequency of the modulator. Sleep Mode The interpolation factor depends on the ODR selected. The fractional sample rate conversion of the ASRC allows the final ODR to be asynchronous to the sampling clock of the modulator. Sleep mode can be activated in SPI control mode by setting the SLEEP_MODE_EN bit to 1. The output of the ASRC is then decimated by an integer in the digital filter to produce the final ODR. In this mode, the device powers down all the blocks except the digital LDO regulator and it retains its on-chip register values. The typical power consumption in this mode is 15 mW. The device can resume full operation within 100 µs after exiting this mode. The ASRC only response depends on the ODR selected and has a notch at the value of interpolation factor × ODR frequency. The interpolation factor values for the various ODRs are shown in Table 18. Both the reference input and input channels go high-Z in sleep mode. Table 18. Interpolation Factor Values for Different ODR Ranges Full Power-Down ODR Range 750 kSPS to 1.496 MSPS 375 kSPS to 749.999 kSPS 366.99 SPS to 374.999 kSPS 10 SPS to 366.99 SPS The full power-down mode is activated by holding the PDN pin low. All internal blocks are powered down in this mode. The typical power consumption in this mode is 1 mW. The device requires a power-up time of 10 ms after exiting this mode. After exiting this mode, the device registers are reset to the default value. Both the reference input and input channels go high-Z in sleep mode. Interpolation Factor Value 8 16 32 1024 For example, the ASRC response for an ODR of 374 kSPS shows a notch at 32 × 374 kHz = 11.968 MHz, as shown in Figure 73. 40 ASRC ONLY RESPONSE PASSBAND EDGE ODR EDGE 20 RESET 0 When reset, the AD7134 restores the internal register values to the default and resets the internal logics and functional blocks. –40 H(f) (dB) Two methods exist for the user to reset the AD7134: through a hard reset by pulling the RESET pin low, or through a software reset by writing 1 to SOFT_RESET (self clears). –20 –60 –80 –100 –120 ASYNCHRONOUS SAMPLE RATE CONVERTER –140 One unique property of the CTSD modulator architecture is having a fixed time constant. As a result, the AD7134 device operates at a fixed modulator clock frequency. –180 0 To facilitate the accurate adjustment of the output data rate, the AD7134 features a digitally programmable ASRC. Rev. 0 | Page 37 of 86 5 10 FREQUENCY (MHz) Figure 73. ASRC Only Response for ODR = 374 kSPS 15 22652-095 –160 AD7134 Data Sheet ASRC Master Mode Similarly, the ASRC response for an ODR of 1496 kSPS shows a notch at 8 × 1496 kHz = 11.968 MHz, as shown in Figure 74. In master mode, the ASRC resamples the interpolated modulator output at a fixed ratio to the modulator clock (see Figure 75). The ratio is internally calculated based on the user setting of the final ODR. The user can configure the ODR through configuration of the ODR pin in pin control mode or through register configuration in SPI control mode. 40 ASRC ONLY RESPONSE PASSBAND EDGE ODR EDGE 20 0 –20 In ASRC master mode, the ODR pin behaves as an output. It produces a pulse train signal in the frequency of the output data rate. The ADC output data is made available for sampling with respect to the ODR signal. –60 –80 –100 –120 For details of the ASRC master mode output data rate setting, see the ASRC Master Mode section. –140 –160 10 20 FREQUENCY (MHz) ASRC Slave Mode In slave mode, the ODR pin behaves as an input (see Figure 76). The user sets the ODR by providing a clock or pulse train at the desired ODR frequency (fODR) to the ODR pin. The AD7134 measures the ODR frequency using the input signal rising edge. An internal digital PLL tracks the ODR pin input signal frequency and uses it to set the resampling rate of the ASRC. The ADC output data is made available for sampling with respect to the ODR signal. Figure 74. Response for ODR of 1496 kSPS The available output data rate range varies based on the digital filter type and the ASRC mode selected (see the Digital Filters section for more information). The ASRC on the AD7134 has the following two modes of operation: • • The user must provide continuous cycles of the ODR signal until the PLL is locked by checking the STAT_PLL_LOCK bit and then reading the data. Any change in the ODR value causes the PLL to unlock and lock back again and requires a wait time before reading data. In master mode, the ODR pin is output and the ODR is set through the pin configuration or a register write. In slave mode, the ODR pin is input to the AD7134 and the ODR is set with an external clock source. The user must also ensure that the jitter on the ODR pin is not more than 100 ns p-p to ensure that the performance is not degraded. XTAL2/CLKIN LOW JITTER 48MHz CLOCK SOURCE AD7134 DIVIDE BY 2 OR 4 ODR IRQ 10Hz TO 1.5MHz PROGRAMMABLE DIVIDER CONTINUOUS TIME Σ-Δ MODULATOR ASRC MICROPROCESSOR/ DSP/FPGA DIGITAL FILTER/ DECIMATOR DATA INTERFACE 22652-097 0 22652-096 –180 Figure 75. ASRC Master Mode Functional Diagram XTAL2/CLKIN LOW JITTER 48MHz CLOCK SOURCE AD7134 DIVIDE BY 2 OR 4 ODR GPO/CLK 10Hz TO 1.5MHz DPLL MICROPROCESSOR/ DSP/FPGA CONTINUOUS TIME Σ-Δ MODULATOR ASRC DIGITAL FILTER/ DECIMATOR DATA INTERFACE Figure 76. ASRC Slave Mode Functional Diagram Rev. 0 | Page 38 of 86 22652-098 H(f) (dB) –40 Data Sheet AD7134 DIGITAL FILTERS 0 The sinc6 filter has a −3 dB bandwidth of 0.1861 × ODR, and the sinc3 filter has a −3 dB bandwidth of 0.2617 × ODR. The Noise Performance and Resolution section contains the noise performance for the sinc filters across power modes and ODR values. –60 –80 –120 0 2 4 6 8 10 12 14 16 NORMALIZED FREQUENCY (fIN/fODR) Figure 78. Sinc3 Filter Frequency Response The settling of the sinc6 filter is 6.5/ODR. For a 374 kSPS ODR, the time to fully settled data is 17.37 µs. DIGITAL FILTER INPUT FILTER SETTLED DIGITAL FILTER OUTPUT 6.5/ODR SETTLING TIME Figure 79. Sinc6 Filter Step Response The settling of the sinc3 filter is 3.5/ODR cycles. Therefore, for a 374 kSPS ODR, the time to fully settled data is 9.35 µs. DIGITAL FILTER INPUT 0 –20 –40 FILTER SETTLED DIGITAL FILTER OUTPUT –80 –100 3.5/ODR SETTLING TIME –120 22652-102 AMPLITUDE (dB) –60 Figure 80. Sinc3 Filter Step Response –140 –160 –180 5 10 15 NORMALIZED FREQUENCY (fIN/fODR) 22652-099 –200 0 Figure 77. Sinc6 Filter Frequency Response Table 19. Digital Filter Options Filter Name Sinc3 Filter −3 dB Bandwidth (Hz) 0.2617 × ODR Sinc3 Filter with 50 Hz/60 Hz Rejection 0.2753 × ODR Sinc6 Filter 0.1861 × ODR Wideband 0.433 Hz × ODR Filter 0.433 × ODR Wideband 0.10825 Hz × ODR Filter (Available Only in SPI Control Mode) 0.108 × ODR 22652-100 –100 Sinc Filters The sinc filters on the AD7134 employ a cascaded integrator comb (CIC) topology to produce a response similar to a sinc function, equivalent to a running averaging operation on the output samples from the ASRC. The sinc filters enable a low latency signal path, useful for applications such as time domain analysis, measurement of dc inputs, and for control loops. Two types of sinc filters are available on the AD7134. The sinc6 filter offers a balance between noise rejection and latency, whereas the sinc3 filter offers the minimum latency path and supports a wide ODR range down to 10 SPS. –40 22652-101 The digital filters available can be operated at any output data rate within the range mentioned in Table 19, allowing the user to choose the optimal input bandwidth and speed of the conversion vs. the desired power mode or resolution. –20 AMPLITUDE (dB) The AD7134 offers four types of digital filters: sinc3, sinc6, and two wideband filters. The sinc3 filter type includes an additional setting with 50 Hz/60 Hz rejection (see Table 19). In SPI control mode, these filters can be chosen on a per channel basis. In pin control mode, only one filter can be selected for all channels. ODR Range 0.01 kSPS to 1496 kSPS 0.01 kSPS to 1496 kSPS 2.5 kSPS to 1.496 MSPS 2.5 kSPS to 374 kSPS 2.5 kSPS to 374 kSPS Rev. 0 | Page 39 of 86 Description Fast settling Fast settling with simultaneous 50 Hz and 60 Hz rejection when ODR = 50 SPS Balancing settling with rejection Wideband low ripple filter Wideband low ripple filter with lower bandwidth AD7134 Data Sheet Simultaneous 50 Hz and 60 Hz Rejection 0 –20 –30 FILTER GAIN (dB) Figure 81 shows the frequency response of the sinc3 filter when the output data rate is programmed to 50 SPS. The sinc3 filter provides 102 dB rejection at 50 Hz ± 1 Hz. –40 –50 –60 –70 –80 –90 –100 –110 –120 0 0 30 60 –10 –20 150 Simultaneous 50 Hz and 60 Hz rejection can also be achieved by selecting the sinc3 and 50 Hz/60 Hz rejection filter path. When the sinc3 filter places a notch at 50 Hz, the 50 Hz/60 Hz rejection postfilter places a first-order notch at 60 Hz. The output data rate is 50 SPS. Figure 84 shows the frequency response of the sinc3 and 50 Hz/60 Hz rejection filter path. The rejection at 50 Hz and 60 Hz (±1 Hz) is in excess of 67 dB. –40 –50 –60 –70 –80 –90 –100 0 –10 25 50 75 100 125 150 FREQUENCY (Hz) –20 –30 Figure 81. Sinc3 and Sinc6 Filter Response (ODR = 50 SPS) Figure 82 shows the frequency response of the sinc3 filter when the output data rate is programmed to 60 SPS. The sinc3 filter provides 106 dB rejection at 60 Hz ± 1 Hz. 0 –40 –50 –60 –70 –80 –10 –90 –20 –100 –30 –110 –40 –120 0 –50 25 75 50 100 FREQUENCY (Hz) –60 125 150 22652-106 0 22652-103 –110 –120 FILTER GAIN (dB) FILTER GAIN (dB) 120 Figure 83. Sinc3 and Sinc6 Filter Response (ODR = 10 SPS) –30 FILTER GAIN (dB) 90 FREQUENCY (Hz) 22652-105 Because the sinc filter rejects signals at the frequency around integer multiples of the ODR, it can be used to reject undesired interference at a specific frequency higher than the input band of interest. Because the sinc3 filter supports an ODR down to 10 SPS, a typical application for the sinc3 filter is to make dc to low bandwidth measurements while rejecting line frequencies at 50 Hz or 60 Hz. –10 Figure 84. Sinc3 and 50 Hz/60 Hz Rejection Filter Response (ODR = 50 SPS) –70 Wideband Low Ripple Filter –80 –90 –100 0 30 60 90 120 150 FREQUENCY (Hz) 22652-104 –110 –120 Figure 82. Sinc3 and Sinc6 Filter Response (ODR = 60 SPS) When the output data rate is 10 SPS, simultaneous 50 Hz and 60 Hz rejection is obtained. The sinc3 filter provides 102 dB rejection at 50 Hz ± 1 Hz and 105 dB at 60 Hz ± 1 Hz. The wideband low ripple filter has a low ripple pass band, narrow transition band, and high stop band rejection. The filter response is close to an ideal brick wall filter, making it ideal for frequency domain measurement and analysis. Two wideband low ripple filter options are available on the AD7134: one filter has a −3 dB corner at 0.433 Hz × ODR, and the other filter has a −3 dB corner at 0.10825 Hz × ODR. Both wideband low ripple filter options offer a pass-band ripple of 32 µdB and a stop band attenuation of −110 dB. For noise performance and resolution, see the Noise Performance and Resolution section. Rev. 0 | Page 40 of 86 AD7134 0 1.2 –20 1.0 –40 0.8 AMPLITUDE (dB) AMPLITUDE (dB) Data Sheet –60 –80 0.6 0.4 0.2 –100 0 0.10825Hz × ODR 0.433Hz × ODR WIDEBAND 0.10825Hz × ODR WIDEBAND 0.433Hz × ODR 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 22652-107 0 –0.2 0.9 NORMALIZED FREQUENCY (fIN/fODR) Figure 85. Low Ripple Wideband 0.433 Hz × ODR Filter and Wideband 0.10825 Hz × ODR Filter Frequency Response 0 0 0.1 0.2 0.3 0.4 NORMALIZED FREQUENCY (fIN/fODR) 0.5 22652-108 AMPLITUDE (dB) 0.10825Hz × ODR 0.433Hz × ODR 0 100 150 Figure 87. Low Ripple Wideband 0.433 Hz × ODR Filter and Wideband 0.10825 Hz × ODR Filter Step Response 1×10–4 –1 50 OUTPUT DATA SAMPLES 22652-109 –120 Figure 86. Low Ripple Wideband 0.433 Hz × ODR Filter and Wideband 0.10825 Hz × ODR Filter Pass-Band Ripple Rev. 0 | Page 41 of 86 AD7134 Data Sheet QUICK START GUIDE The AD7134 offers users a multichannel platform measurement solution for ac and dc signal processing. Flexible filtering allows the AD7134 to be configured to simultaneously sample ac and dc signals on a per channel basis. The ASRC allows users to granularly set the output data rate controlling the input bandwidth of the measurement. This ability, coupled with the flexibility of the digital filter, allows the user to choose the right application settings and meet latency, bandwidth, and performance targets. Key capabilities that allow users to choose the AD7134 as their platform high resolution ADC are highlighted as follows: • • • Four fully differential analog inputs Fast throughput simultaneous sampling ADCs catering for input signals up to 391 kHz Two selectable power modes (high performance and low power) for scaling the current consumption and input bandwidth of the ADC to achieve optimal measurement efficiency • • • • • • • • Wideband, low ripple, digital filter for ac measurement Fast sinc3 filter for precision low frequency, low latency measurement Two ASRC modes (master mode and slave mode) allow user flexibility in digital interface Two antialias modes enabling the user to choose higher levels of alias rejection Choice of SPI or pin strapped configuration option Offset, gain, and phase calibration registers per channel Common-mode voltage output buffer to set the commonmode voltage of the input On-board 1.8 V LDO regulators for single-supply operation Refer to Figure 88 and Table 20 for the typical connections and minimum requirements to start using the AD7134. 5V –IN + +OUT AVDD5 AIN0+ DVDD5 LTC6363-1 SIGNAL – –OUT +IN AIN0– AVDD1V8 IOVDD VOCM GND 1.8V DVDD1V8 CLKVDD AD7134 –IN SIGNAL + +OUT AIN1+ REFIN LTC6363-1 – –OUT REFCAP 4.096V REFERENCE ADR444 AIN1– +IN VCM REFGND VOCM GND CLKIN + +OUT AIN2+ LTC6363-1 SIGNAL – –OUT +IN 48MHz OSCILLATOR CLKGND AIN2– VOCM GND SPI INTERFACE –IN +OUT + SIGNAL LTC6363-1 –OUT AIN3– – +IN VOCM DATA INTERFACE AGND1V8 DGND1V8 IOGND AGND5 DGND5 22652-110 GND AIN3+ MICROPROCESSOR/ DSP/FPGA –IN Figure 88. Typical Connections Diagram Table 20. Requirements to Operate the AD7134 Requirement Power Supplies External Reference Input Stage External Clock FPGA or DSP Description 5 V AVDD5 and DVDD5 supply, 1.8 V − IOVDD, CLKVDD, AVDD1V8, and DVDD1V8 (LT8606, LT8607) 4.096 V or 5 V (ADR444/ADR445) AD8421, ADA4075-2, ADA4945-1, LTC6363 Crystal or a CMOS/LVDS clock for the ADC modulator sampling 1.65 V to 1.95 V digital I/O level Rev. 0 | Page 42 of 86 Data Sheet AD7134 STANDALONE MODE LOW LATENCY SYNCHRONOUS DATA ACQUISITION The user has a digital host without an SPI interface and needs a −3 dB input bandwidth of 102.4 kHz. The user also desires a flat pass-band response with robust data interface. The recommended scheme is pin controlled master mode. The 102.4 kHz input bandwidth with flat pass band can be achieved by using a 0.433 × ODR FIR filter. The minimum ODR needed can be calculated as input bandwidth = 0.433 × ODR. Therefore, the minimum ODR needed is 237 kSPS. From Table 28, the closest ODR value of 256 kSPS can be programmed. The user has an input signal bandwidth of 250 kHz and needs a 24-bit output with minimum latency. There are eight channels and the user needs tight synchronization between the channels. The robust interface calls for using the CRC. Therefore, the frame size is 24 data bits + 8-bit header that includes a 6-bit CRC and a 2-bit status. The DCLK value required is >(Frame Size + 6) × ODR, giving the user a value of 9.7 MHz. From Table 30, the closest DCLK option is 12 MHz. The settings to be configured are pin control mode control, ASRC master, high performance mode, gated DCLK output, 32bit data output, 256 kSPS ODR, 12 MHz DCLK, 0.433 × ODR filter, external LDO regulator, and 4-channel output. Refer to the Device Configuration section for programming these settings. Table 21. Configuration 1 Hardware Settings Supply/Level 5V 1.8 V Comments Supply Supply Low High High Low High Low, low FORMAT1, FORMAT0 High, low FRAME1, FRAME0 PWRMODE High, high High Pin control Crystal input ASRC master Gated DCLK DCLK output 0.433 × ODR filter 4-channel output 32-bit output High performance 12 MHz DCLK Low, low, high Low, low, high, high The 250 kHz input bandwidth with minimum latency can be achieved by the sinc3 filter. The minimum ODR needed can be calculated as input bandwidth = 0.2617 × ODR. Therefore, the ODR required is 956 kSPS. The external DCLK value required is >(Frame Size + 6) × ODR, giving the user a value of 29 MHz. Provide the DCLK and ODR values as per the timing specifications listed in Table 3. The settings to be configured are SPI control mode control, ASRC slave, high performance mode, gated DCLK input, 24-bit data output, 956 kSPS ODR, 29 MHz DCLK, sinc3 filter, external LDO regulator, and 4-channel output. Refer to the Device Configuration section for programming these settings. After power-on, verify the hardware configuration by reading the DEVICE_STATUS register. Table 22. Configuration 2 Hardware Settings Pin Function AVDD5, DVDD5 IOVDD, LDOIN, AVDD1V8, DVDD1V8, CLKVDD PIN/SPI CLKSEL MODE DCLKMODE DCLKIO FILTER1, FILTER0 DCLKRATE2, DCLKRATE1, DCLKRATE0 DEC3, DEC2, DEC1, DEC0 The recommended scheme is to use two devices in SPI controlled slave mode. The external ODR signal can synchronize both devices with a digital interface reset issued simultaneously. See the Multidevice Synchronization section for more details. 256 kSPS ODR Pin Function AVDD5, DVDD5 IOVDD, CLKVDD, AVDD1V8, LDOIN, DVDD1V8 PIN/SPI Supply/Level 5V 1.8 V Comments Supply Supply High CLKSEL High MODE DCLKMODE DCLKIO Low Low Low SPI control mode Crystal input ASRC slave Gated DCLK DCLK input Program the registers in Table 23 with the values listed and leave the all the other registers at their default values. Table 23. Software Settings SPI Register DATA_PACKET_CONFIG DEVICE_CONFIG CHAN_DIG_FILTER_SEL DIGITAL_INTERFACE_CONFIG Rev. 0 | Page 43 of 86 Value 0x20 0x01 0xAA 0x03 Comments 24-bit frame High performance mode Sinc3 filter 4-channel parallel AD7134 Data Sheet DEVICE CONTROL The AD7134 has independent paths for reading data from the ADC conversions and for controlling the device functionality. PIN CONTROL MODE Pin control mode eliminates the need for an SPI communication interface. When a single known configuration is required by the user, or when only limited reconfiguration is required, the number of signals that require routing to the digital host can be reduced using this mode. Pin control mode is useful in digitally isolated applications where minimal adjustment of the configuration is needed. Pin control mode helps save on PCB design and eliminates routing of digital lines. For control, the device can be configured in either of the following two modes: On power-up, the state of the PIN/SPI pin determines the mode used. SPI control mode offers a full set of configurability, including access to the AD7134 internal diagnostic features. Pin control mode offers a subset of selectable features in exchange for easy configurability. The user can choose the mode of operation by the voltage level applied to the PIN/SPI pin Pin control offers a subset of the core functionality and ensures a known state of operation after power-up or reset. Pin control mode selectable options include the following: • • • • • Along with the PIN/SPI pin, four additional pins must be configured to ensure the correct operation of either SPI or pin control mode. Table 24 shows a list of pin controlled functions that are common to pin control mode and SPI control mode operation. The pins listed in Table 24 are sampled only when the AD7134 is powered on. Figure 89 shows pin configurable functions. All the pins except the ones listed in Table 24 can be changed dynamically. Refer to Figure 90 for more details. A limited set of diagnostics are available and CLKOUT is enabled by default in pin control mode only when the crystal option is selected. Table 24. Common Control Pin Function Summary PIN/SPI = LOW PIN/SPI POWER MODE 0 – LOW POWER 1 – HIGH PERFORMANCE PWRMODE/GPIO3 DIGITAL FILTER SELECT 0 0 – WIDEBAND FIR 0.433 × ODR 0 1 – SINC6 1 0 – SINC3 1 1 – SINC3 + 50Hz/60Hz REJECTION FILTER0/GPIO4 FRAME0/GPIO6 DATA FRAME SELECT 0 0 – 16-BIT DATA 0 1 – 16-BIT DATA WITH CRC 1 0 – 24-BIT DATA 1 1 – 24-BIT DATA WITH CRC PIN CONTROL MODE FRAME1/GPIO7 CLKSEL DEC0/DCLKIO DEC1/DCLKMODE Pin Function Controls the mode selection, pin or SPI. ASRC mode of operation selection, master or slave mode operation. Input clock source selection, crystal or CMOS. DCLK direction selection. Gated or Free Running DCLK selection. OUTPUT DATA FORMAT 0 0 – SINGLE-CHANNEL DAISY CHAIN 0 1 – 2-CHANNEL DAISY CHAIN 1 0 – QUAD CHANNEL PARALLEL 1 1 – RESERVED FORMAT1/SCLK FORMAT0/CS DOUT0 DOUT1 AD7134 DOUT2 FILTER1/GPIO5 DEC0/DCLKIO DEC1/DCLKMODE DEC2/SDI DEC3/SDO Pin Mnemonic PIN/SPI MODE Digital filter Frame size Data interface format Decimation rate and DCLK frequency High performance mode or low power mode TO DSP/ FPGA DOUT3 DCLK ODR DCLK OUTPUT FREQUENCY SELECT ODR RATE SELECT Figure 89. Pin Control Mode Configurable Functions Rev. 0 | Page 44 of 86 22652-084 • Pin control mode: pin strapped digital logic inputs (allowing a subset of the configurability options to be used) SPI control mode: over a 3-wire or 4-wire SPI interface (complete configurability) DCLKRATE0/GPIO0 DCLKRATE1/GPIO1 DCLKRATE2/GPIO2 • Data Sheet AD7134 SPI CONTROL MODE The AD7134 has a 4-wire SPI interface that is compatible with QSPI™, MICROWIRE®, and DSPs. Using the SPI interface, the user can access the ADC register map and control the AD7134. To use SPI control mode, the PIN/SPI pin of the AD7134 must be set to logic high. The SPI control operates as a 16-bit, 4-wire interface, allowing read and write access. The SPI serial control interface of the AD7134 is an independent path for controlling and monitoring the AD7134. There is no direct link to the data interface. The timing of ODR and DCLK is not directly related to the timing of the SPI control interface. Refer to the SPI Interface section for more details. The SPI control mode allows the user to configure more features than the pin control mode and use the device fully. The additional features available in SPI control mode are the following: • • • • • • • • • • • • Option for wideband digital filter FIR 0.108 × ODR Digital interface reset Programmable gain, offset, and channel delay Sleep mode 2-channel averaging Additional inherent alias mode (AA2) Programmable ODR, ODR/2, ODR/4, and ODR/8 VCM pin output voltage programmability Per channel phase delay MULTIFUNCTION PINS The AD7134 has multifunction pins where the function of these pins change depending on the selected control mode. Table 25 shows a summary of the multifunction pin functions in each mode of operation. Full suite of diagnostic features More options for ODR select and DCLK frequency select in master mode XCLKOUT disable Table 25. Multifunction Pin Function Summary Pin Mnemonic FORMAT0/CS FORMAT1/SCLK DEC3/SDO DEC2/SDI DEC1/DCLKMODE DEC0/DCLKIO DCLKRATE0/GPIO0 DCLKRATE1/GPIO1 DCLKRATE2/GPIO2 PWRMODE/GPIO3 FILTER0/GPIO4 FILTER1/GPIO5 FRAME0/GPIO6 FRAME1/GPIO7 Pin Function in Pin Control Mode ADC output channel format selection Pin Function in SPI Control Mode SPI interface ASRC master mode decimation ratio selection ASRC master mode: decimation ratio selection ASRC slave mode: DCLK mode selection (free running or gated) ASRC master mode: decimation ratio selection, DCLK is output ASRC slave mode: tie pin low to set it as input DCLK output frequency selection in ASRC master mode Device power mode selection (high performance or low power mode) Digital filter type selection Output data frame selection Rev. 0 | Page 45 of 86 DCLK mode selection (free running or gated) DCLK I/O direction selection (input or output) General-purpose I/O AD7134 Data Sheet DEVICE CONFIGURATION PROGRAMMING OUTPUT DATA RATE AND CLOCK ASRC Slave Mode Output Data Rate In ASRC slave mode, the ODR is controlled by a continuous external pulse signal connected to the ODR pin, with the ODR equal to the pulse frequency. This feature gives the user the flexibility to update the frequency of the external pulse dynamically, which changes the ODR value, but there is a loss of data during a change over time plus the filter settling time. The change over time is dominated by the unlocking and locking of the phase-locked loop (PLL) that tracks the ODR. For ODR values of >10 kSPS, a change of ODR value to less than 500 SPS does not cause the PLL to unlock and lock back again, allowing seamless data. Refer to Table 27 for change over time for ODR ranges for various filters in slave mode. AD7134 can be programmed to any output data rate from 10 SPS to 1496 kSPS. Depending on the MODE pin configuration, the ODR can be generated by the AD7134 or provided externally. When the AD7134 generates the ODR, the mode is called master mode, and when ODR is provided externally, the mode is called slave mode. Table 26. Mode Pin Configuration MODE Pin 0 1 ASRC Mode of Operation Slave Master ODR Pin Direction Input Output For Example 1, if the user changes the ODR value from 300 kSPS to 2500 SPS while using the digital FIR filter, the change over time is 22 ms + 512/2500 = 226.8 ms. For Example 2, if the user changes the ODR value from 1 MSPS to 500 kSPS while using a sinc3 digital filter, the change over time is 11 ms + 512/500,000 = 12 ms. The supported ODR range varies by the power mode and the digital filter type selected (see Table 19 for more details). Table 27. ODR Change Over Time in Slave Mode ODR Range 750 kHz to 1.46 MHz 374 kHz to 750 kHz 365 kHz to 374 kHz 1.46 kHz to 365 kHz 1.46 kHz to 2.5 kHz 732 SPS to 1.46 kHz 366 SPS to 732 SPS 183 SPS to 366 SPS 91.5 SPS to 183 SPS 45.7 SPS to 97.5 SPS 22.8 SPS to 45.7 SPS 11.4 SPS to 22.8 SPS 10 SPS to 11.4 SPS FIR Not applicable Not applicable ODR range not supported in slave mode 22 ms + 512/ODR Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Rev. 0 | Page 46 of 86 Sinc6 5.5 ms + 512/ODR 11 ms + 512/ODR 22 ms + 512/ODR 22 ms + 512/ODR 22 ms + 512/ODR Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Sinc3 5.5 ms + 512/ODR 11 ms + 512/ODR 22 ms + 512/ODR 22 ms + 512/ODR 22 ms + 512/ODR 44 ms + 512/ODR 88 ms + 512/ODR 6 sec + 512/ODR 12 sec + 512/ODR 24 sec + 512/ODR 48 sec + 512/ODR 96 sec + 512/ODR 192 sec + 512/ODR Data Sheet AD7134 ASRC Master Mode Program ODR_VAL_FLT, Bits[31:0] with 0x2F4103E5. In ASRC master mode, the AD7134 device generates the output data at a programmable decimation ratio. The user can program the decimation ratio in both pin control and SPI control mode to achieve the desired output date rate. In Example 2, for an ODR to be 375 kSPS, calculate the decimation rate as follows: In pin control mode, the decimation rate is fixed as per the predefined pin control options. Sixteen decimation ratio options are available through the configuration of the DEC0/DCLKIO pin to DEC3/SDO pin. The final ODR value also depends on the digital filter type. Table 28 summarizes the ODR values available in master mode. Program ODR_VAL_INT, Bits[23:0] with 0x000040. In SPI control mode, the ODR is available at the full range described in Table 19. The ODR can be programmed via the ODR_VAL_INT, Bits[23:0] bits and ODR_VAL_FLT, Bits[31:0] bits with a resolution of 0.01 SPS. In Example 1, for an ODR to be 187.23 kSPS, calculate the decimation rate as follows: Decimation Rate = MCLK/375 kHz = 24 MHz/375 kHz = 64 = 0x00004000000000 Program ODR_VAL_FLT, Bits[31:0] with 0x00000000. Every time the ODR_VAL_INT, Bits[23:0] and ODR_VAL_FLT, Bits[31:0] are changed, the MASTER_SLAVE_TX_BIT in the TRANSFER_REGISTER must be set to update the ODR to the new value. The user has the flexibility to change the ODR value, but that means a loss of data of about 2 µs plus the filter settling time. The 2 µs time, tDELAY, is constant across the ODR range. See Figure 90 for more details. The SPI control mode also allows the user to set a different ODR rate for each of the four ADC channels using the ODR_RATE_SEL_CHx bits. The ODR options are limited to 1, ½, ¼, or ⅛ of the ODR frequency. Decimation Rate = MCLK/187.23 kHz = 24 MHz/187.23 kHz = 128.1846 = 0x0000802F4103E5 Program ODR_VAL_INT, Bits[23:0] with 0x80. Table 28. Output Data Rate Configuration in Pin Control Master Mode DEC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DEC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DEC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Wideband 0.433 Hz × ODR Filter (kSPS) 374 325 285 256 235 200 175 128 100 80 64 32 16 10 5 2.5 tODR_PERIOD Sinc6 Filter (kSPS) 1496 1250 1000 750 500 375 325 256 175 128 80 64 32 10 5 2.5 Sinc3 Filter (kSPS) 1496 1000 750 375 187.5 128 64 32 16 5 2.5 1.25 0.625 0.06 0.05 0.01 tODR_PERIOD tODR_PERIOD ODR SPI WRITE DELAY tDELAY = 2µs t = FILTER_SETTLE FILTER SETTLED Figure 90. Master Mode ODR Change Over Rev. 0 | Page 47 of 86 DATA READY 22652-085 DEC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AD7134 Data Sheet Data Clock (DCLK) mode of operation is controlled by the DEC1/DCLKMODE pin and DEC0/DCLKIO pin, as shown in Table 29. The data clock can be either an input or an output depending on the direction of the ODR pin. When ODR is output for master mode, set the DEC0/DCLKIO pin high to configure DCLK as an output. When ODR is input for slave mode, tie the DEC0/DCLKIO pin low to configure DCLK as an input. The data clock can be operated in gated mode or free running mode controlled by the DEC1/DCLKMODE pin. In master mode, the DCLK pin is configured as an output. The DCLK frequency is derived from the AD7134 device master clock and can be configured using the DCLKRATE0/GPIO0 pin to DCLKRATE2/GPIO2 pin in pin control mode, or DCLK_ FREQ_SEL (Bits[3:0]) in Register 0x11 in SPI control mode. SPI control mode offers 16 DCLK output frequency options, and pin control mode offers eight. Table 30 lists all the DCLK output frequency options. When operated in pin control mode with the ASRC set to master mode, the DCLK operation is limited to gated output only. When operating in pin control mode with the ASRC set to slave mode, or when operating in SPI control mode, the DCLK In slave mode, the DCLK pin is an external signal. Table 29. DCLK Mode of Operation in Pin Control Mode or in SPI Control Mode DEC1/DCLKMODE 0 0 0 0 1 1 1 1 DEC0/DCLKIO 0 0 1 1 0 0 1 1 MODE 0 1 0 1 0 1 0 1 DCLK Direction Input Reserved Reserved Output Input Reserved Reserved Output DCLK Mode Gated Reserved Reserved Gated Free running Reserved Reserved Free running Table 30. DCLK Output Frequency Configuration DCLKRATE2 or Register 0x11, Bit 3 0 DCLKRATE1 or Register 0x11, Bit 2 0 DCLKRATE0 or Register 0x11, Bit 1 0 Register 0x11, Bit 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 Not available in pin control mode. Rev. 0 | Page 48 of 86 DCLK Output Frequency Options 48 MHz (SPI/pin control mode default) 24 MHz 1 12 MHz 6 MHz1 3 MHz 1.5 MHz1 750 kHz 375 kHz1 187.5 kHz 93.75 kHz1 46.875 kHz 234.375 kHz1 11.71875 kHz 5.859375 kHz1 2.929688 kHz 1.464844 kHz1 Data Sheet AD7134 PROGRAMMING DIGITAL FILTER PROGRAMMING DATA INTERFACE In pin control mode, four digital filter types are available through the configuration of the FILTER1/GPIO5 pin and FILTER0/GPIO4 pin. All four ADC channels share the same digital filter type. The digital interface consists of setting up the format, the frame, and the averaging options. Output Channel Format The data interface format is determined by setting the FORMAT0/CS pin and FORMAT1/SCLK pin. The logic state of the FORMAT0/CS pin and FORMAT1/SCLK pin is read on power-up and determine how many data lines (DOUTx) the ADC conversions are output on. One additional digital filter type, wideband 0.10825 Hz × ODR filter, is available only in SPI control mode. In SPI control mode, the digital filter type can be configured independently for each ADC channel via the DIGFILTER_SEL_CHx bits and the additional digital filter type (wideband 0.10825 Hz × ODR filter or wideband 0.433 Hz × ODR filter) via the WB_FILTER_ SEL_CHx bits, where x is the channel number from 0 to 3. Table 31 lists all the digital filter options. Because the FORMAT0/CS pin and FORMAT1/SCLK pin are read on power-up of the AD7134 and the device remains in this output configuration, this function must always be hardwired and cannot be altered dynamically. Figure 91 and Figure 92 show the formatting configuration for the digital output pins on the AD7134. To configure the digital filter dynamically, change the digital filter first and then change the output data rate to ensure proper operation. Table 31. Digital Filter Configuration FILTER1 or DIGFILTER_SEL_CHx, Bit 1 0 0 FILTER0 or DIGFILTER_SEL_CHx, Bit 0 0 0 WB_FILTER_SEL_CHx, Bit 0 0 1 0 1 1 1 0 1 X2 X2 X2 Available in SPI control mode only. X means don’t care. AD7134 ODR DCLK IOVDD EACH ADC HAS A 1 DEDICATED DOUTx PIN 0 DOUT0 CH 0 DOUT1 CH 1 DOUT2 CH 2 DOUT3 CH 3 FORMAT1/SCLK FORMAT0/CS DGND DAISY-CHAINING IS NOT POSSIBLE IN THIS FORMAT 22652-086 2 Figure 91. FORMAT1, FORMAT0 = 10, Four Data Output Pins AD7134 CHANNEL0 TO CHANNEL3 OUTPUT ON DOUT0 ODR DCLK 0 FORMAT0/CS 0 FORMAT1/SCLK DOUT0 SINGLE-CHANNEL DAISY CHAIN Figure 92. FORMAT1, FORMAT0 = 00, One Data Output Pin Rev. 0 | Page 49 of 86 22652-087 1 Digital Filter Type Wideband 0.433 Hz × ODR filter Wideband 0.10825 Hz × ODR filter 1 Sinc6 Sinc3 Sinc3 with additional 60 Hz rejection AD7134 Data Sheet Calculate the minimum required DCLK rate for a given data interface configuration as follows: DCLK (Minimum) = Output Data Rate × Channels per DOUTx × (Frame Size + 6) and filtering. This feature gives the user flexibility to match the delays on different channels and thus achieving tight phase matching between channels. POWER MODES For example, if data size = 24 and 6-bit CRC is enabled with one DOUTx line, single-channel daisy-chaining, DCLK (Minimum) = 374 kSPS × 4 Channels per DOUTx × (24 + 8 + 6) = 44.88 Mbps The AD7134 can output the data from four ADC channels in parallel using four output pins, or serialize the data and output them using fewer pins. Paralleling the output enables a higher output data rate for a given DCLK frequency. In addition to using fewer I/Os, serializing the data allows data from multiple AD7134 devices to be daisy-chained. The output channel format is controlled by the FORMAT0/CS pin and FORMAT1/SCLK pin in pin control mode and the format bits in the DIGITAL_INTERFACE_CONFIG register in SPI control mode. Table 33 lists all the output channel format options. Data Frame The frame of each ADC sample output data consists of the data followed by an optional status/CRC header. The AD7134 supports two data length options: 16-bit and 24-bit. The AD7134 also supports one CRC-6 header option. Table 34 lists all the output data frame options. Data Delay The data output of each channel of the AD7134 can be individually delayed by 0, 1, or 2 MCLK cycles using the MPC_CONFIG register. The front-end signal chain components can add varying amounts of phase delay depending on factors like gain setting The AD7134 offers two power modes, high performance mode and low power mode. These modes are available in both pin control mode and SPI control mode. In pin control mode, the PWRMODE/GPIO3 pin controls the AD7134 operating power mode. In SPI control mode, the POWER_MODE bit controls the power mode. Additional sleep mode is available in SPI control mode. Table 32 summarizes the power mode configurations. In both pin control mode and SPI control mode, a full device power-down can be initiated through the PDN pin. Table 32. Power Mode Configuration PWRMODE/GPIO3 or POWER_MODE Bit 0 1 SLEEP_MODE_EN 0 0 X 1 Device Power Mode Low power mode High performance mode Sleep mode To operate the device correctly in low power mode, the user must toggle the setting from low power mode to high performance mode and back to low power mode. In pin control mode, to set the AD7134 in low power mode, toggle the PWRMODE/GPIO3 pin to high and after a delay of 10 ms toggle it back to low. In SPI control mode after power up, change the POWER_MODE bit from low to high and after a delay of 10 ms change it back to low. Also, in pin slave mode, first provide the ODR signal and then change the power mode to ensure dynamic sampling of the PWRMODE/GPIO3 pin. Table 33. Output Channel Format Configuration FORMAT1/SCLK Pin or Bit 1, DIGITAL_INTERFACE_ CONFIG Register 0 FORMAT0/CS Pin or Bit 0, DIGITAL_INTERFACE_ CONFIG Register 0 0 1 1 1 0 1 Output Channel Format Single-channel daisy-chain mode. DOUT0 acts as an output and DOUT2 acts as a daisychain input. DOUT1 and DOUT3 are disabled. Data from all four ADC channels are serialized and output on DOUT0 (SPI default mode). Dual-channel daisy-chain mode. DOUT0 and DOUT1 act as outputs, and DOUT2 and DOUT3 act as daisy-chain inputs. Data from Channel 0 and Channel 1 are serialized and output on DOUT0. Data from Channel 2 and Channel 3 are serialized and output on DOUT1. Quad-channel parallel output mode. Each ADC channel has a dedicated data output pin. Channel data averaging mode. In pin control mode, data from all four channels are averaged and output on DOUT0. DOUT2 acts as daisy-chain input. DOUT1 and DOUT3 are disabled. In SPI control mode, the averaging operation is defined by the AVG_SEL bits in Register 0x12. Table 34. Data Frame Options FRAME1/GPIO7 Pin or Bit 1, DATA_ PACKET_CONFIG Register 0 0 1 1 FRAME0/GPIO6 Pin or Bit 0, DATA_ PACKET_CONFIG Register 0 1 0 1 Rev. 0 | Page 50 of 86 Data Frame 16-bit ADC data 16-bit data with CRC-6 24-bit ADC data 24-bit data with CRC-6 Frame Length 16 24 24 32 Data Sheet AD7134 INHERENT ANTIALIASING FILTER MODES The CTSD architecture allows the AD7134 to reject signals around the integer multiples of the modulator sampling frequency, protecting its input band of interest from aliasing. The AD7134 offers two antialiasing modes. The default antialiasing mode, AA1, offers a typical 85 dB of aliasing rejection. The other antialiasing mode, AA2, improves the rejection to 102.5 dB with the cost of a higher offset drift of 1.03 µV/°C, additional power consumption of 3 mW per channel, and higher noise level with dynamic range reduction. Table 35 shows typical performance differences in inherent antialias modes. The filter is wideband 0.433 × ODR FIR filter, and the ODR value is ODR = 374 kSPS. Table 35. Performance Difference in Inherent Antialias Modes Parameter Dynamic Range SNR Alias Rejection Offset Drift Power per Channel The AA2 mode is only available in SPI control mode and can be enabled by setting the AA_MODE bit to 1. Rev. 0 | Page 51 of 86 AA1 Mode 107.4 dB 106.6 dB 85 dB 0.5 µV/°C 126 mW AA2 Mode 105.9 dB 105.4 dB 102.5 dB 1.03 µV/°C 129 mW AD7134 Data Sheet DYNAMIC RANGE ENHANCEMENT, CHANNEL AVERAGING The AD7134 is equipped with built in 4-channel and 2-channel averaging functions that increase the performance by 6 dB and 3 dB. The device performs on-board averaging of the output data from two or four of its ADC channels to improve the dynamic range. AIN0+ AIN0– INPUT SIGNAL AIN1+ AIN1– AIN2+ Averaging is a digital postprocessing option after the digital filter, which performs averaging of the output data from multiple ADC channels. This averaging feature allows the user to measure a signal with multiple ADC channels and average the result to achieve higher dynamic range. AIN2– AIN3– AD7134 22652-117 AIN3+ Figure 93. 4:1 Channel Averaging In 4:1 averaging mode, a single input signal is applied to all four input channels, as shown in Figure 93. In this mode with averaging enabled, the AD7134 is a single-channel device with the dynamic range improved by 6 dB. AIN0+ AIN0– INPUT SIGNAL 1 AIN1+ AIN1– In 2:1 averaging mode, a single input signal is applied to two input channels, as shown in Figure 94. In this mode with averaging enabled, the AD7134 behaves as a 2-channel device with each channel dynamic range improved by 3 dB. AIN2+ AIN2– INPUT SIGNAL 2 For noise performance of channel averaging, see the Noise Performance and Resolution section. AIN3– AD7134 22652-118 AIN3+ Figure 94. 2:1 Channel Averaging Figure 93 and Figure 94 show the connection diagrams for using these functions. For 4:1 channel averaging, short all four inputs together, but for 2:1 channel averaging short two inputs together. In pin control mode, only 4:1 averaging is available through the configuration of the FORMAT0/CS pin and FORMAT1/SCLK pin, as shown in Table 33. In SPI control mode, set the format bits, Bits[1:0] in Register 0x12 to 11 to enable the output averaging function. Then use Bits[3:2] in Register 0x12 to select the channel averaging options. Rev. 0 | Page 52 of 86 Data Sheet AD7134 CALIBRATION In SPI control mode, the AD7134 offers the ability to calibrate offset and gain individually for each channel. The user can alter the gain and offset of the AD7134 and subsystem. VREF/222. An LSB of offset register adjustment changes the digital output by 2 LSBs. For example, changing the offset register from 0 to 100 changes the digital output by 200 LSBs. Each channel of the ADC has an associated gain and offset coefficient that is stored for each ADC after factory programming. The user can overwrite these gain and offset coefficients using the gain and offset correction registers. However, after a reset or power cycle, the gain and offset register values revert to the hard coded, programmed factory setting. For additional register information, see the OFFSET_CAL_ EN_CHx bit descriptions in Table 81, Table 87, Table 93, and Table 99. These options are available in SPI control mode only. OFFSET CALIBRATION The offset correction registers provide 23-bit, signed, twos complement registers for channel offset adjustment. The offset setting for each channel is enabled using the OFFSET_CAL_ EN_CHx bits. The offset range is ±VREF with a step size of GAIN CALIBRATION The gain register is 20 bits with a range of ±50% and the LSB applying a gain of 0.95 ppm. The gain setting for each channel is enabled using the GAIN_CAL_SEL_CHx bits. For additional register information, see the GAIN_CAL_ SEL_CHx bit descriptions in Table 78, Table 84, Table 90, and Table 96. Rev. 0 | Page 53 of 86 AD7134 Data Sheet POWER SUPPLY DVDD5 The AD7134 has a total of seven power supply input pins: AVDD5, DVDD5, LDOIN, AVDD1V8, DVDD1V8, CLKVDD, and IOVDD. IOVDD Refer to the power supply voltages in Table 1 for operating supply voltage values for 4.096 V and 5 V reference inputs. LDOIN Figure 97. Power Sequencing in Internal LDO Mode If the internal LDO regulators are not used, tie the LDOIN pin to DVDD1V8, as shown in Figure 98. To simplify the power supply design, the user can supply the AVDD5 pin and DVDD5 pin together with a single, low noise 5 V supply, and supply the AVDD1V8, DVDD1V8, CLKVDD, and IOVDD pins together with a single low noise 1.8 V supply. 5V SUPPLY 1.8V SUPPLY LDOIN AVDD5 DVDD5 10µF CLKVDD 10µF AD7134 2.2µF To simplify the power supply design, the AD7134 provides three internal LDO regulators to generate the 1.8 V required for the AVDD1V8, DVDD1V8, and CLKVDD pins from a single 2.6 V to 5.5 V supply connected to the LDOIN pin, as shown in Figure 95. AVDD1V8 If AVDD1V8, DVDD1V8, and CLKVDD are powered from a separate external supply, take caution on the supply sequencing. All three supplies are connected internally through the back diode of the regulator. If one supply powers up first, it can supply power to other supplies through the back diode and the other LDO regulators. REFERENCE NOISE FILTERING REGULATOR The user can reduce the noise contribution of the reference source to the overall ADC conversion accuracy by filtering the reference signal. An internal 20 Ω resistor between the REFIN pin and the REFCAP pin enables the user to form a first-order RC filter by connecting a capacitor on the REFCAP pin. DVDD1V8 REGULATOR 22652-111 CLKVDD REGULATOR Figure 98. External Power Mode Connections REFERENCE IC Figure 95. Internal LDO Regulator Connections AD7134 20Ω If the internal LDO regulators are used, the AVDD1V8, DVDD1V8, and CLKVDD pins must be decoupled with a 10 µF, 10 µF, and 2.2 µF capacitor, respectively, to their respective grounds, as shown in Figure 96. GND 5V SUPPLY REFCAP MODULATOR REFERENCE REFGND Figure 99. Reference Input Connection Using REFIN pin LDOIN AVDD5 DVDD5 IOVDD REFIN OUT 22652-116 LDOIN The equivalent noise bandwidth of a first-order filter is 0.25/RC in Hz. 1.8V SUPPLY DVDD1V8 AD7134 2.2µF 22652-112 CLKVDD 10µF 1.8V SUPPLY DVDD1V8 On-Board LDO Regulators 10µF IOVDD AVDD1V8 22652-115 To generate 5 V and 1.8 V rails, the power circuits using LT8606 or LT8607 provide a low EMI, small size solution supporting a wide range of input voltages. AVDD1V8 22652-114 APPLICATIONS INFORMATION Figure 96. Internal LDO Regulator Mode Power Connections The noise contribution of the reference source is proportional to the ADC input signal. The reference noise contribution is at the highest when the input signal is at full scale. The reference noise has no impact on the output when the ADC inputs are shorted. The internal LDO regulators are enabled only when the IOVDD supply is powered up first by an external 1.8 V supply. As a general rule, limit the reference noise to ¼ of the noise of the ADC to have a minimal effect on the overall SNR. The internal LDO regulators work properly if the power supply sequence in Figure 97 is followed. Ensure that the IOVDD and LDOIN pins are powered after DVDD5, as shown in Figure 97. The total reference noise is the root sum square of its 1/f noise and its wideband noise. Rev. 0 | Page 54 of 86 Data Sheet AD7134 Consider the AD7134 device that is operating in high performance mode, ODR = 374 kSPS, and wideband 0.433 Hz × ODR filter with a reference voltage of 4.096 V. According to Table 9, the ADC noise in this setup is 12.63 µV rms. The reference noise is ¼, equal to 3.16 µV rms. An ADR444 reference IC is chosen to provide the reference voltage for the AD7134. The ADR444 has a 0.1 Hz to 10 Hz peak noise of 1.8 µV p-p, and a noise spectrum density of 78.6 nV/√Hz. The ADR444 1/f noise is 1.8 µV p-p or 1.8/6.6 = 0.273 µV rms. The total reference noise is the root sum square of its 1/f noise and its wideband noise. Therefore, To achieve tight synchronization, the user must configure all the devices in slave mode and use the SPI to set the DIG_IF_RESET bit to reset the digital interface before the data capture. This DIG_IF_RESET command must be given to all the slaves simultaneously using one single SPI write command. XTAL2/ CLKIN ASYNCHRONOUS SAMPLE RATE CONVERTER AD7134 SLAVE MODE ISOLATION XTAL2/ CLKIN MICROPROCESSOR/ DSP/FPGA INPUT/ OUTPUT SPI AND DATA INTERFACE XTAL1 ASYNCHRONOUS SAMPLE RATE CONVERTER √(0.2732 + n2WB) < 3.16 Solving the equation yields the wideband noise, nWB, of the ADR444, which must be less than 3.14 µV rms. XTAL1 AD7134 SLAVE MODE The wideband noise of the ADR444 can be calculated by multiplying its noise spectrum density by the square root of the noise bandwidth. 78.6 nV/√Hz × √NBW < 3.14 µV rms where NBW is the noise bandwidth. The calculation shows that the noise bandwidth must be less than 1.6 kHz. The equivalent noise bandwidth of a first-order filter is 0.25/RC, in Hz. The AD7134 has an internal 20 Ω resister between the REFIN pin and the REFCAP pin. By connecting the output of the ADR444 to the REFIN input, a capacitor > 7.9 µF on the REFCAP pin is sufficient to limit the reference noise to the desired value. It is recommended to place a 10 µF capacitor on the REFCAP pin. MULTIDEVICE SYNCHRONIZATION The integrated ASRC of the AD7134 helps achieve multidevice synchronization with a single low speed ODR line, giving less than 10 ns of phase matching between channels on different devices, which makes it easy to synchronize. Applications like conditionbased monitoring, power quality analyzer, and sonar system demand tight phase matching across high numbers of channels, making the digital interface design complex. The devices can be clocked with their own local clock sources yet can achieve tight phase matching without the need of routing high speed clock lines that adds to EMI issues. This clocking also means that for applications demanding isolation, the user can pass fewer low speed lines across the isolation barrier, as shown in Figure 100. 22652-119 An example to calculate the reference noise requirement based on the ADC mode of operation follows. The AD7134 does not require the system clock across isolation to synchronize isolated devices, which enables higher ODR in isolated simultaneous sampling applications. ISOLATION The 1/f noise of the reference can be estimated by its peak-topeak noise specification over the 0.1 Hz to 10 Hz frequency range. The wideband noise can be calculated from the voltage noise density specification of the reference and the reference noise bandwidth. Figure 100. Simplified Clocking in AD7134 COHERENT SAMPLING The integrated ASRC of the AD7134 allows the user to set granular sampling speeds from 0.01 kSPS to 1496 kSPS with a resolution of 0.01 SPS. The ASRC allows the user to detect the line frequency and change the ODR so that there is a rational relationship between the input signal frequency and the sampling speed. Mathematically, coherent sampling is expressed as fIN/fODR = number of cycles in sampling window ÷ number of data points for FFT. For example, fODR is 32 kSPS, fIN is 1 kHz, and the number of samples is 512. Number of cycles in the sampling window = 512 × 1000/32 kSPS = 16. If the input frequency is 1.01 kHz, the ODR change is 4096 × 1010/16 = 258.56 kSPS to achieve coherent sampling. In applications like power metering and analysis, it is necessary to achieve the required accuracy on the harmonic data and metering parameters and ensure coherency between the ADC sampling rate and the power line frequency. LOW LATENCY DIGITAL CONTROL LOOP The control loop demands low latency, but the antialias filter for noise reduction adds significant delay, increasing the loop latency. The inherent antialias rejection of the AD7134 removes the need of the antialias filter, significantly reducing the signal chain latency. The AD7134 supports throughput rates up to 1496 kSPS, making it an optimal choice for low latency, 24-bit digital control loops. Rev. 0 | Page 55 of 86 AD7134 Data Sheet AUTOMATIC GAIN CONTROL The AD7134 has additional GPIO functionality when operated in SPI control mode. One of the diagnostic features of the AD7134 enables GPIO7 to report any of the diagnostic errors by enabling the ERR_PIN_OUT_EN bit. do not need to have a high bandwidth and a strong output drive to overcome kickbacks from traditional ADCs. The ADA4610-2 is an optimal choice because it offers wide input range, low noise, suitable bandwidth, and high linearity. The AD8605 is another optimal choice for rail to rail, low voltage, single-supply operation. +6V The user can use GPIO7 to report any input overrange detection, and based on the report the user can control the gain of the front-end amplifier. Configure GPIO7 as an output and set the ERR_PIN_EN_OR_AIN bit, which enables errors from input overrange and enables error reporting on GPIO7. Wire the FRAME1/GPIO7 pin to gain control of the amplifier. +5V AD7134 AINx+ RG RF 22652-121 +5V Figure 102. Buffered Input with Gain and No Additional Common-Mode Rejection VCC Differential Input with Unregulated Common-Mode Voltage Low Impedance Source AD7134 OUT– AINx+ FORMAT1/SCLK DEC2/SDI AINx– IN– DEC3/SDO If a wider input common-mode range is required, a fully differential amplifier can be used, as shown in Figure 103. DIGITAL ISOLATOR (OPTIONAL) FORMAT0/CS RF FRAME1/ GPIO7 IN– 22652-120 GAIN CONTROL VEE Figure 101. Automatic Gain Control IN+ AD7134 RG AINx+ ADC FDA VCM RG AINx– VCM RF FRONT-END DESIGN EXAMPLES 22652-122 OUT+ PGA SENSOR AINx– VCM –4V Any input overrange above ±VREF on the input lines causes GPIO7 to go high, which brings down gain of the PGA, which reduces its output below ±VREF. This control happens automatically without any intervention of the digital host. IN+ ADC RF VCM The analog front-end circuit of the AD7134 must perform the following sequence: Figure 103. Use a Fully Differential Amplifier to Extend Input Common-Mode Voltage and Signal Gain/Attenuation 1. 2. This circuit can also provide gain or attenuation of the signal and is responsible for rejecting the input common mode. 4. The following low noise amplifiers are recommended for various types of system challenges. Example operational amplifiers include the ADA4625-2, ADA4610-2, AD8605, and the ADA4075-2. Examples of fully differential amplifiers include the ADA4940-2, LTC6363, and the ADA4945-1. Example instrumentation amplifiers include the AD8421. Fully differential amplifiers such as the ADA4940-2, ADA4945-1, and LTC6363 are all suitable choices. Devices such as the LTC6363-0.5, LTC6363-1, and LTC6363-2 with a highly matched integrated resistor network offer unmatched CMRR at 94 dB minimum. Fully Differential Amplifier with Single Unipolar Supply The circuit in Figure 104 has no passive components, but it offers fixed gain for single-ended or differential inputs having a low impedance source. Single unipolar 5 V supply operation relaxes the power design. 2V Differential Input Signal with Controlled Common-Mode and High Impedance Source An example of a high impedance source includes a Wheatstone bridge type of configuration for strain and pressure monitoring. 4.5V VREF = 4V 5V –2V 0.5V +IN Rev. 0 | Page 56 of 86 AINx+ LTC6363-1 SIGNAL The input common mode is well controlled, needing no commonmode rejection, and a dual op amp configuration works properly. The circuit in Figure 102 can also provide gain to the signal. Because of the easy to drive nature of the AD7134, the op amps +OUT –OUT –IN VOCM AINx– 2.5V VCM AD7134 Figure 104. Fully Differential Amplifier with Single Supply 22652-123 3. Provide adequate input impedance to match the source. Provide reasonably low output impedance to drive the 6 kΩ differential input resistance of the ADC. Convert the input signal to a balanced, fully differential signal with fixed common-mode voltage of 2 V to 2.5 V. Provide the necessary gain or attenuation to match the maximum source signal amplitude to the full-scale input range of the ADC. Data Sheet AD7134 Single-Ended or Pseudo Differential Input with High Source Impedance Precision Dual Amplifier The circuit in Figure 106 is suitable for a high impedance source, which can add gain or attenuation. Example operational amplifiers are the ADA4941-1, LT6350, ADA4805-2, and ADA4004-2. R AINx+ R R R IN+ R A number of other circuits can be used to perform single-ended to differential conversions. R VCM Figure 106. Dual Operation Amplifier Configuration Instrumentation Amplifier with Single-Ended to Differential Output Conversion Operational Amplifier and Fully Differential Amplifier VREF = 4V The circuit in Figure 107 is a low input bias operational amplifier with a fully differential amplifier, like the ADA4945-1, is suitable for high impedance sources. The fully differential amplifier circuit can add gain or attenuation. RF1 AD7134 RG1 RG2 VCM RF2 AINx+ IN+ FDA SIGNAL AD8421 REF AINx+ AINx– RG2 RF2 22652-124 AINx– AD7134 VCM Figure 105. Instrumentation Amplifier in Differential Output Configuration Rev. 0 | Page 57 of 86 Figure 107. Op Amp and Fully Differential Amplifier 22652-126 The circuit configuration in Figure 105 is suitable for singleended input signal, high common-mode range, and low input current suitable for a high impedance source for gain ≥ 1. 2V AD7134 AINx– 22652-125 The single-ended or pseudo differential input signals must be converted into fully differential signals before driving into the AD7134. All the circuit examples given in the Front-End Design Examples section for interfacing with differential signals can work with interfacing with single-ended or pseudo differential signals. Connect the second input to signal ground or a common-mode voltage source. AD7134 Data Sheet DIGITAL INTERFACE DIGITAL HOST AD7134 SPI_SEL SCLK MOSI MISO FORMAT0/CS FORMAT1/SCLK DEC2/SDI DEC3/SDO DRIVING EDGE GPIO DCLK IRQ/IO ODR SAMPLING EDGE Figure 109. SCLK Edges GPI GPI GPI GPI DOUT0 DOUT1 DOUT2 DOUT3 DATA INTERFACE FOR ADC DATA READBACK SCLK The SPI interface uses a 7-bit addressing scheme and supports three modes of operation: 3-wire mode, 4-wire mode, and minimum I/O mode. An optional CRC function is also available for improving communication robustness. 22652-127 SPI INTERFACE FOR REGISTER ACCESS the falling edge of the SCLK is the driving edge, and the rising edge of the SCLK is the sampling edge. The output data on the SDO pin is clocked out on the falling edge of SCLK and the input data on the SDI pin is sampled on the rising edge of SCLK. 22652-128 The AD7134 digital interface consists of two independent parts: an SPI interface for register access and device configuration, and a data interface for sending out conversion data. 3-Wire Mode Figure 108. Communication Interface of AD7134 SPI INTERFACE The SPI control mode is one of the two control modes supported on the AD7134. The other mode is pin control mode. The user can choose which mode to operate the device in by setting the logic level on the PIN/SPI pin. Set the PIN/SPI pin high to enable the SPI control mode, which enables the SPI interface of the device. In this mode, SDO is disabled and read data is available on the DEC2/SDI pin. SDO is high impedance in the command, and the data is shorted to SDI (see Figure 110). 4-Wire Mode The standard SPI interface consists of four signals, as shown in Figure 111. The AD7134 has a 4-wire SPI interface that is compatible with QSPI, MICROWIRE, and DSPs. The interface operates in SPI Control Mode 0. In SPI Control Mode 0, the SCLK idles low, SCLK SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 22652-129 CS Figure 110. 3-Wire Mode Write/Read Command CS 3-WIRE READ/WRITE SDI R/W ADDRESS ENTITY [CRC] ENTITY [CRC] SDI W ADDRESS ENTITY [CRC] ENTITY [CRC] PADDING [CRC] PADDING [CRC] PADDING [CRC] ENTITY [CRC] 4-WIRE WRITE [STATUS] SDO SDI R ADDRESS PADDING 4-WIRE READ [STATUS] INSTRUCTION PHASE ENTITY DATA PHASE (1 OR MORE ENTITIES) Figure 111. 3-Wire and 4-Wire SPI Transaction Protocols Rev. 0 | Page 58 of 86 [CRC] 22652-131 SDO Data Sheet AD7134 SPI CRC The SPI CRC code is an optional feature. Enabling it allows the user to improve transaction robustness on the SPI bus, for example, in a noisy environment. The SPI CRC is calculated with the x8 + x2 + x + 1 polynomial with an initial seed value of 0xA5. The SPI CRC achieves a Hamming distance of 4 with a maximum word length of 119 bits. 3-Wire Isolated Mode The AD7134 powers up in 3-wire isolated mode and a toggle on the chip select line makes the AD7134 exit this mode. The chip select line is not used and must be connected to ground. The SPI packet is 24 bits, consisting of an 8-bit command and address, 8-bit data (entity), and 8-bit CRC. See Figure 112 for 3-wire isolated mode. Also note that a streaming register read or write is not supported in this mode. SDI 3-WIRE ISOLATED WRITE 3-WIRE ISOLATED READ ADDRESS W STATUS SDO SDI ADDRESS R STATUS SDO INSTRUCTION DATA CRC PADDING CRC PADDING CRC DATA CRC DATA PACKET 22652-133 CS Figure 112. 3-Wire Isolated Mode Additional SPI Features The AD7134 provides the user several options to control the SPI interface. Some of the features are listed in the following sections. Single Instruction Mode When the SINGLE_INSTR bit is set, streaming is disabled and only one read or write operation is performed regardless of the state of the CS line. If this bit is set and CS remains asserted, the state machine resets after the data byte as if CS was deasserted and awaits the next instruction. Single instruction mode forces each data byte to be preceded with a new instruction even though the CS line has not been deasserted. Single instruction mode also allows additional flexibility in the usage of the CS pin if it is required for an application. The default for this bit is set, resulting in streaming being enabled. SDI SPI LOCK CODE 24 1s SPI LOCKED SPI UNLOCK CODE 23 1s AND ONE 0 22652-301 SPI Interface Lock/Unlock Figure 113. SPI Lock/Unlock and Reset The AD7134 provides the user an option to lock the SPI interface by performing an SPI write of 24 consecutive 1s. This write blocks the SPI read/write access to registers. To unlock and reset, the user must perform an SPI write of 23 1s and one 0. The status of the SPI interface can be read by completing an SPI read to an SPI register whose value is known. If the SPI interface is out of sync, the user initiates an unlock and resets the SPI interface. At any point, if the SPI interface is not responding, execute a lock and unlock. This unlock/lock does not affect any data transaction in progress on the data interface and does not affect the SDO behavior. Stream Mode Stream mode allows the user to consecutively access one or more registers repeatedly without having to carry the overhead associated with setting up the address each cycle. At the end of the loop, the autogenerated address resets to the beginning address and resumes counting until the last address is reached again. The process continues as long as the CS is not deactivated. When CS is deactivated, stream mode is terminated until started again by the user. The STREAM_MODE register is used to tell the device how many consecutive registers are to be accessed in the stream mode. If this register is 0x00, the default, streaming is not enabled. If the value in this register is not zero, when streaming is initiated, the value in this register tells the address generator how many consecutive addresses are to be written to or read from before looping back to the beginning address. If the value in this address is 0x01, the same address is written to or read from for the duration of the stream event. If the value is 0x02, two consecutive addresses are written (or read) for the duration. If, for example, the stream entry point is Address 0x10, Address 0x10 is the first address. Address 0x11 is the second address. After this loop is complete, the next autogenerated address is 0x10 and so on. This cycle continues until terminated by the user by deasserting the CS line. To initiate stream mode, the user must first set this register, 0x000E, with a nonzero value indicating how many addresses are to be accessed. Any value between 0x01 and 0xFF is valid. Take care that all addresses within this scope are suitable for streaming because some addresses may be specified as do not change. Next, begin the read or write cycle as usual. Master Slave Transfer Bit Bit 0 of the TRANSFER_REGISTER is used as the master slave transfer bit, which is useful when a register is composed of multiple bytes that must all be written simultaneously to prevent erroneous device operation. In master mode, the ODR_VAL_INT_x and ODR_VAL_FLT_x registers need this implementation. When this bit is set, multiple bytes of data that have been transferred using the SPI are written at one time to the slave. Upon completion of the transfer, the slave device clears this bit (autoclear), indicating to the SPI master that the transfer completed and the slave data can be read back if desired by the control program. DATA INTERFACE The AD7134 has a flexible data interface designed to support the different digital host types and applications requirements. The AD7134 can act as the data interface master or slave. The data interface supports both gated and free running clock signals, parallel or serial output data steaming modes, and daisy-chain configuration. Rev. 0 | Page 59 of 86 AD7134 Data Sheet The data interface consists of three signal types: clock, data, and data framing signal. Data Interface Clock The AD7134 supports both gated and free running DCLK signals. The ADC output data is clocked out on the DCLK rising edge. SAMPLING EDGE DRIVING EDGE The direction of the ODR signal depends on the choice of the ASRC mode of operation. See the Asynchronous Sample Rate Converter section for more information on the ASRC. Data Interface Status and CRC Header The user has the option to append a byte width header to each output data sample for additional status information and/or error checking. The header consists of 6-bit CRC code with two status bits, as shown in Table 36. 22652-132 DCLK Choosing the Data Interface Mode of Operation Figure 114. DCLK Edges DCLK is a bidirectional pin. The AD7134 can act as an interface master and generate the DCLK signal, or act as an interface slave and clock out data based on a received DCLK signal. When the DCLK pin is configured as an output, the user can choose the DCLK output frequency through the DATA_ PACKET_CONFIG register or configuration of the DCLKRATEx/GPIOx pins in pin control mode. Refer to the Programming Output Data Rate and Clock section for more information on how to configure the DCLK frequency. Data Bus The ADC output data appears on the DOUTx pins. Each AD7134 device has four data output pins: DOUT0, DOUT1, DOUT2, and DOUT3. The user has the option to parallel output the ADC conversion result on the four DOUTx pins or to serialize the data from multiple channels and output them using one or two of the DOUTx pins. Parallel output configuration allows a high data rate at a low DCLK frequency. A serialized output configuration requires fewer I/Os from the digital host and can reduce the number of digital isolator channels required in an isolation application. The daisy-chain mode is available only with a serialized output configuration. Data Framing Signal Table 36. Details of the Header Bit 7 6 [5:0] Bit Description Chip error Filter settled and PLL locked 6-bit CRC Bit 7 is set if an error is detected by the on-chip diagnostic circuitry of the AD7134. See the Diagnostics section for more details of the diagnostic features of the device. Bit 6 is set if the digital filter on the corresponding channel is fully settled and, when operating in ASRC slave mode, the PLL is locked after an ODR input frequency change. The data sample value does not reflect the correct conversion result when Bit 6 of the header has a value of zero. Data CRC Calculation The CRC is calculated with the polynomial and initial seed value as shown in Table 37. Table 37. Data CRC Calculation CRC Mode CRC-6 Polynomial x6 + x5 + x2 + x + 1 Default Seed Value 0x25 Alternative CRC Mode of Operation The AD7134 uses a linear feedback shift register (LFSR) to calculate the CRC. In pin control mode and in SPI control mode, by default, the LFSR is reset after each data sample with the default seed value (see Table 37). In SPI control mode, the user has the option to alter the LFSR resetting behavior. Configure CRC_ POLY_RST_SEL to 1 to disable the reset of the LFSR after each sample, making the current CRC result in the seed value of the next calculation. This mode allows the processor-based digital host to check the CRC less frequently and still be able to detect an error in the bit transfer. The ODR control signal is dual purposed to act as the framing signal for the AD7134 data interface. The ODR pin is bidirectional with its signal direction dependent on the ASRC mode of operation. The output data can be driven out with respect to the ODR falling or rising edge depending on the mode of DCLK used. DOUTx CRC-6 DATA 16/24 BITS DATA DATA STATUS CRC Figure 115. Data CRC Options Rev. 0 | Page 60 of 86 DATA STATUS CRC 22652-134 ODR DOUTx NO CRC Data Sheet AD7134 ASRC Master Mode Data Interface Daisy-Chaining When the ASRC is in master mode, the ODR pin behaves as an output. The user has the choice to operate the DCLK pin in gated mode or in free running mode. Daisy-chaining allows numerous devices to use the same data interface lines by cascading the outputs of multiple ADCs from separate AD7134 devices. The data interface of only one ADC device is in direct connection with the digital host. With the DCLK pin configured as an output, the AD7134 acts as the data interface master, providing the DCLK signals and the output data steam synchronously to the ODR signal. ODR DCLK DOUTx This feature is especially useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. DIGITAL HOST INPUT/ OUTPUT INPUT/ OUTPUT INPUT/ OUTPUT When daisy-chaining with two channels, DOUT2 and DOUT3 become serial data inputs, and DOUT0 and DOUT1 remain as serial data outputs. ASRC MASTER Figure 118 shows an example of daisy-chaining the AD7134 devices with two channels. In this case, the DOUT0 pin and DOUT1 pin of the AD7134 devices are cascaded to the DOUT2 and DOUT3 pins of the next device in the chain. Data readback is analogous to clocking a shift register. INTERFACE SLAVE AD7134 ODR 22652-135 DCLK DOUTx ASRC SLAVE Figure 116. Data Interface Example 1, First AD7134 Device in ASRC Master Mode with the Digital Host as Interface Slave ASRC Slave Mode Data Interface The scheme operates by passing the output data of the DOUT0 pin and DOUT1 pin of an AD7134 downstream device to the DOUT2 and DOUT3 inputs of the next AD7134 device upstream in the chain. The data then continues through the chain until it is clocked onto the DOUT0 pin and DOUT1 pin of the final upstream device in the chain. When the ASRC is in slave mode, the ODR pin behaves as an input. The user has the choice to operate the DCLK pin in gated mode or in free running mode. AD7134 DOUT0 DOUT1 With the DCLK pin configured as an input, the AD7134 acts as the data interface slave, providing the output data stream on the input DCLK driving edge. DOUT2 DOUT3 If the DCLK pin is configured as a free running input, the user must ensure that the DCLK pin is synchronized to the ODR signal for proper data framing. AD7134 ODR DCLK DOUTx AD7134 DOUT0 DOUT1 DOUT2 DIGITAL HOST DOUT3 22652-141 AD7134 For the AD7134, implement this connection by cascading DOUT0 and DOUT1 through a number of devices, or using only DOUT0. Figure 118. Data Interface Connection with 2-Channel Daisy-Chaining Configuration INPUT/ OUTPUT INPUT/ OUTPUT INPUT/ OUTPUT AD7134 ASRC MASTER DOUT0 INTERFACE SLAVE DOUT1 DOUT2 AD7134 DOUT3 ODR DCLK DOUT0 DOUT1 Figure 117. Data interface Example 2, Two AD7134 Devices in ASRC Slave Mode with Digital Host as Interface Master DOUT2 DOUT3 22652-142 ASRC SLAVE AD7134 22652-139 DOUTx Figure 119. Data Interface Connection with 1-Channel Daisy-Chaining Configuration Rev. 0 | Page 61 of 86 AD7134 Data Sheet Daisy-chaining can be achieved in a similar manner on the AD7134 when using only the DOUT0 pin. In this case, only the DOUT2 pin is used as the serial data input pin, as shown in Figure 119. If the AD7134 is used in the chain as a master for generating the ODR and DCLK, the user must program the DAISY_CHAIN_ DEV_NUM bits to let the device know how many devices are connected to it. Programming the DAISY_CHAIN_DEV_NUM bits ensures that the AD7134 generates a sufficient number of DCLK cycles to clock the data out from all the devices in the chain. For example, in Figure 120, program the DAISY_CHAIN_ DEV_NUM bits in the master device to 0x01 so that the AD7134 can generate the number of DCLK cycles to clock out data from both the devices. AD7134 ODR DOUT0 DOUT1 It is optional to include a status or CRC header byte with each conversion result to improve the communication robustness and to receive real-time error status. The user can choose to parallel or serialize the output data. Serializing the output data from four ADC channels to one DOUTx pin increases the data frame length by 4×. If multiple devices are daisy-chained, the total data frame length is equal to the sum of the data frame length of the individual devices on the chain. Frame Length Examples In Case 1, the following conditions apply: • • • • • 16-bit output format No status or CRC header Parallel output on all four DOUTx pins No daisy chain Averaging disabled The output data frame length is 16/8 = 2 bytes per ODR period on each of the four DOUTx pins. DOUT2 DOUT3 In Case 2, the following conditions apply: DCLK • • • • • MASTER AD7134 ODR DOUT0 24-bit data format Status and CRC header enabled Output on two DOUTx pins Daisy chain three devices Averaging disabled DOUT1 The output data frame length is (24/8 + 1) × 2 × 3 = 24 bytes per ODR period on each of the two DOUTx pins. DOUT2 DOUT3 In Case 3, the following conditions apply: 22652-143 DCLK SLAVE Figure 120. Single Channel Daisy Chain for Master Slave Configuration The number of devices supported on a chain is limited by the DCLK frequency chosen for a given output data rate. The maximum usable DCLK frequency allowed when daisychaining devices is limited by the combination of timing specifications and the DCLK mode of operation. Data Interface Frame Length The AD7134 data interface operates with the byte-based transfer scheme. That is, the transactions are in multiples of eight bits. The data frame length, defined as the number of data bytes per ODR cycle per DOUTx pin, depends on the following factors: • • • • • Conversion output word size Status or CRC header Data output format configuration Daisy-chain configuration Data averaging The conversion output word size can be 16 bits or 24 bits. • • • • • 24-bit output format Status/CRC header enabled Output on one DOUTx pins Daisy-chain two devices 4:1 averaging The output data frame length is (24/8 + 1) × 4 × 2/4 = 8 bytes per ODR period. DCLK Frequency Selection The user must ensure an adequate DCLK frequency is used to clock out the full length of the data frame in time. The maximum supported DCLK frequency on the AD7134 is 48 MHz as an output and 50 MHz as an input. Gated DCLK Output Cycles When DCLK is configured as a gated output, the AD7134 uses an internal counter to control the number of DCLK cycles to output after each ODR pulse. The device automatically adjusts the number of DCLK cycles to output according to its data frame and format configuration. However, in daisy-chain mode, the device has no inherent knowledge of the number of devices connected on the chain. Rev. 0 | Page 62 of 86 Data Sheet AD7134 In pin control mode, unless the device is configured to operate in quad channel parallel output mode, it assumes a daisy-chain configuration. If the DCLK pin is configured as a gated output, the device assumes that four devices are on the daisy chain. The number of DCLK cycles it generates after each ODR pulse is equal to four times the data frame length of the devices. • • • In SPI control mode, the user has the flexibility to program the number of devices on the daisy chain through the DAISY_ CHAIN_DEV_NUM bits. The value acts as a multiplier to the number of DCLK cycles the device outputs after each ODR pulse when the DCLK is configured as a gated output. Channel Dependent ODR Gated DCLK Output Cycles Examples The device outputs (24 + 8) × 2 × 3 = 192 DCLK cycles after each ODR pulse. In SPI control mode, the AD7134 supports the configuration of different ODR rates on each channel using the CHANNEL_ODR_SELECT register. The rate must be a power of two fraction of the signal frequency on the ODR pin and is limited to a minimum of 1/8 of the main ODR frequency. Each channel updates its conversion output based on the ODR rate of the channel. For example, if a channel is configured to have an output data rate of ODR/4, its output data updates once every four ODR cycles. Figure 121 shows an example of the data interface timing of a device with different output data rate settings on each channel. In Case 1, the following conditions apply: • • • • • Averaging disabled SPI control mode operation DAISY_CHAIN_DEV_NUM = 3 (decimal) 16-bit output format No status or CRC header Single-channel daisy-chain mode Pin control mode operation DCLK configured as gated output The device outputs 16 × 4 = 64 DCLK cycles after each ODR pulse. In Case 2, the following conditions apply: 24-bit output format Status and CRC header enabled Dual-channel daisy-chain mode ODR DOUT0 RATE = ODR SAMPLE N SAMPLE N + 1 SAMPLE N + 2 SAMPLE N + 3 SAMPLE N + 4 DOUT1 RATE = ODR/2 SAMPLE N SAMPLE N SAMPLE N + 1 SAMPLE N + 1 SAMPLE N + 2 DOUT2 RATE = ODR/4 SAMPLE N SAMPLE N SAMPLE N SAMPLE N SAMPLE N + 1 DOUT3 RATE = ODR/8 SAMPLE N SAMPLE N SAMPLE N SAMPLE N SAMPLE N Figure 121. Data Interface Timing Example of a Device with Different ODR Settings on Each Channel Rev. 0 | Page 63 of 86 22652-144 • • • AD7134 Data Sheet Bit 1 of the INTERFACE_CONFIG_B register (DIG_IF_RESET) resets the data interface. In multidevice configuration, this bit synchronizes data channel outputs to achieve device to device channel phase matching. This bit is self clearing and only available for use in SPI slave mode operation. Refer to the Multidevice Synchronization section. MINIMUM I/O MODE Certain applications require a minimum number of I/O lines to be used for interfacing with the AD7134. This requirement may be due to the limited number of I/Os available on the digital host, or for cost reasons, to minimize the number of digital isolation channels required in an isolated application. The AD7134 is designed to support both register and data access using as few as only four unidirectional I/O lines. cannot be disabled. All SPI packets must be 24 bits, which is R/W + Address (8-bit), data (8-bit), and CRC (8-bit), as described in Figure 114. To configure the AD7134 to operate with a minimum number of IO lines, perform the following sequence: Connect the FORMAT0/CS pin to ground. Externally connect DCLK to the FORMAT1/SCLK pin. Configure DCLK to be a gated input. Set ASRC slave mode. Set FORMATx to 00 wherein data from all four ADC channels are converged and output through DOUT0. Set the SDO_PIN_SRC_SEL bit to 1. 1. 2. 3. 4. 5. 6. AD7134 DCLK FORMAT1/SCLK DEC2/SDI The minimum I/O mode configuration essentially combines the register and data access interface on the AD7134 and allows the digital host to interface with the AD7134 with only one SPI port as master. The trade-off of minimizing the number of I/O ports is more complicated firmware design and a potentially higher CPU processing load. On power-on, the AD7134 boots up in minimum I/O mode and a toggle on CS pin makes the device exit the minimum I/O mode. Also, SPI CRC is enabled in minimum I/O mode and DEC3/SDO ODR FORMAT0/CS DIGITAL ISOLATOR (OPTIONAL) MICROPROCESSOR/ DSP SCLK SPI PORT (MASTER) MOSI REGISTER AND DATA MISO ACCESS I/O 22652-145 Digital Interface Reset Figure 122. Signal Connection Diagram of Minimum I/O Configuration In minimum I/O mode, the user can use the DEC3/SDO pin for both register content and ADC conversion data readback. Only one of the SDO and DOUT0 outputs are allowed to be enabled at any given time. Setting the SDO_PIN_SRC_SEL bit to 1 causes the signal on DOUT0 to be duplicated on the DEC3/SDO pin. Rev. 0 | Page 64 of 86 Data Sheet AD7134 DIAGNOSTICS As shown in Figure 123, the NO_CHIP_ERR bit in the device configuration register is the master error status bit. This bit is cleared if any of the other status error bits are set. This bit sets back to 1 when all the status bits are cleared, indicating no chip error. The AD7134 has numerous diagnostic functions on chip that monitor and report errors for the following functional blocks: Internal fuses Analog input range MCLK frequency SPI communication Memory map value ODR input frequency Digital filters INTERNAL FUSE INTEGRITY CHECK The AD7134 uses a fuse type memory to store the factory programmed calibration values that are unique to each device. When leaving the factory, a CRC code is calculated based on the final fuse values of the device and is stored in the device memory. On each power-up, the device reads the fuse memory for self configuration. The device also performs a CRC calculation based on the fuse values read and compares the calculation against the factory programmed value to detect a fuse reading error. In SPI control mode, the user can enable or disable the following diagnostic features through the diagnostic control register: • • • • • Fuse cyclic redundancy check (CRC) Memory map CRC SPI CRC MCLK counter Analog input range The device sets the ERR_FUSE_CRC bit if a fuse CRC error is detected. Figure 123 shows all the different types of blocks monitored, as well as blocks that are enabled using the diagnostic control register. The remaining diagnostic features run continuously on the device and all the bits except the NO_CHIP_ERR bit are cleared on a read. DIAGNOSTIC CONTROL ERR_MM_CRC_EN FUSE_CRC_CHECK ERR_OR_AIN_EN ERR_SPI_CRC_EN MCLK_CNT_EN The user can also initiate a fuse check by using the FUSE_ CRC_CHECK bit in the diagnostic control register. This bit is cleared when the check is complete. When this check is executed, the data output is interrupted. The fuse CRC supports 1-bit error correction. The device tries to correct the error when detected. The AD7134 sets the STAT_FUSE_ECC bit if the error is corrected and sets the ERR_FUSE_CRC bit if the fuse CRC error correction is not completed. ERR_MM_CRC ERR_FUSE_CRC ERR_OR_AINx ERR_SPI_CRC MCLK_COUNTER NO_CHIP_ERR ERR_ASRC ERR_DCLK ERR_OFUF_CHx ERR_SPI_READ ERR_SPI_WRITE ERR_SPI_SCLK_CNT Figure 123. Errors Rev. 0 | Page 65 of 86 22652-146 • • • • • • • AD7134 Data Sheet Four overvoltage flags in the AIN_OR_ERROR register corresponding to the four input channels are cleared on a read. MCLK COUNTER A stable MCLK is important because the output data rate, filter settling time, and the filter notch frequencies are dependent on the master clock. The AD7134 allows the user to monitor the master clock. When the MCLK_CNT_EN bit in the diagnostic control register is set, the MCLK_COUNTER register increments by one every 12,000 master clock cycles. The user can monitor this register over a fixed period by running a timer in the controller, and the master clock frequency can be determined from the result in the MCLK_COUNTER register. MCLK = Register Data × 12,000/Timer Value where Register Data is in decimal format. For example, if MCLK is 24 MHz and the timer is set to 100 ms, the expected MCLK_COUNTER value is 0xC8. This register wraps around after it reaches its maximum value. For write or read operation, the host sends the R/W bit, the address (eight bits), the data (eight bits), and the 8-bit CRC (on R/W, address, and data). In a write operation, while the host is sending the CRC on the SDI line, the slave simultaneously transmits the CRC calculated on the write + address + data that the slave has received. The slave executes a write operation only when the received CRC sent by the host matches with its calculated CRC. The slave sends a 1-bit status followed by 15 zeros and the 8-bit CRC (see Figure 124). SDI SDO W + ADDRESS 1-BIT STATUS DATA 15 ZEROES CRC ON W + ADDRESS + READ DATA CRC ON W + ADDRESS + READ DATA 22652-147 An on-chip, full-scale overrange detection monitor flags a bit on detection of a positive full-scale input voltage between the AINx+ pins and AINx− pins. This detection is enabled on each channel by using the ERR_OR_AIN_EN bit in the diagnostic control register, and an overvoltage bit corresponding to the particular channel is set if the voltage exceeds the full scale corresponding to that channel. transaction is calculated using the 8-bit command word and data. For a read transaction, the checksum is calculated using the command word and the data output. Figure 124. SPI Write with CRC In a read operation, while the host is sending the CRC on the SDI line, the slave simultaneously transmits the CRC calculated on the command and the read data. The slave sends a 1-bit status followed by seven zeros, 8-bit read data, and 8-bit CRC (see Figure 125). The 1-bit status sent by the slave is the error bit, which indicates that the previous frame had a read, write, or CRC error. SDI SDO R + ADDRESS 1-BIT STATUS DON’T CARE 7 ZEROES + READ DATA CRC ON R + ADDRESS + READ DATA CRC ON R + ADDRESS + READ DATA 22652-148 ANALOG INPUT OVERRANGE Figure 125. SPI Read with CRC SPI INTERFACE MONITORING MEMORY MAP INTEGRITY CHECK The AD7134 supports a number of diagnostic measures to improve the robustness of its SPI interface. Accessing Undefined Register Address When the user tries to access an undefined register address, the device ignores the instruction and flags an error in the ERR_ SPI_READ bit or the ERR_SPI_WRITE bit. These bits are cleared on a read. SCLK Counter The AD7134 uses an SCLK counter to count the number of SCLK cycles supplied in each of the read and write transactions framed by the CS signal. The device flags an error in the ERR_SPI_ SCLK_CNT bit if the number of SCLK cycles at the end of each SPI transaction is not an integer multiple of 8. This bit is cleared on a read. The SCLK counter is not available in minimum I/O mode. SPI CRC When the ERR_SPI_CRC_EN bit in the diagnostic control register is set, a CRC check for all SPI read and write operations is enabled. The ERR_SPI_CRC bit in the SPI error register is set if the CRC check fails. This bit is cleared on a read. For CRC checksum calculations, the polynomial used is x + x + x+ 1 and has a reset seed of 0xA5. 8 2 When the ERR_MM_CRC_EN bit is set in the diagnostic control register, a CRC of the data from all the on-board registers with write access is calculated and the results are stored in memory. The device then continuously performs the CRC calculation at a frequency of 2.4 kHz, and compares each output with the CRC value stored in memory. The device sets the ERR_MM_CRC bit if the two values are different. This bit is cleared on a read. The CRC value stored in the memory is also recalculated after each SPI write transaction. This feature is useful for detecting a soft error in the memory map. ODR INPUT FREQUENCY CHECK An ODR input frequency check applies only to device operation in ASRC slave mode. The device checks the input ODR signal frequency after the PLL locks and sets the ERR_ASRC bit if the ODR frequency detected is outside the range for the particular type of filter selected as specified in Table 19. This bit is cleared on a read. For example, if the ODR input is set to 600 kSPS and the type of filter set is wideband, this error is flagged. There is no data output in this scenario. The 8-bit checksum is appended to the end of each read and write transaction. The checksum calculation for the write Rev. 0 | Page 66 of 86 Data Sheet AD7134 DIGITAL FILTER OVERFLOW AND UNDERFLOW DCLK ERROR The digital filter overflow/underflow occurs when the input is overrange or due to an incorrect setting of the gain and calibration register. The AD7134 monitors the digital filter path and sets the corresponding channel bit in the DIG_FILTER_OFUF register when an overflow or underflow condition is detected. The device has a built in feature to flag insufficient numbers of data clocks needed to clock out the complete frame. For proper usage of this diagnostic feature, it is recommended to read back these flags after power-up. ODR Time > tDCLK × Frame Size + 6 × tDCLK/tDIGCLK (whichever is higher) The user must program or provide a data clock that is fast enough to clock out the complete frame for the given ODR and ensure that for the gated mode, And for free mode, ODR Time > tDCLK × Frame Size + 4 × tDCLK/tDIGCLK (whichever is higher) (1) The ERR_DCLK flag sets if the programmed or provided DCLK frequency is such that Equation 1 is not met, resulting in an insufficient number of data clocks to clock out the entire frame. This bit is cleared on a read. Rev. 0 | Page 67 of 86 AD7134 Data Sheet GPIO FUNCTIONALITY PIN ERROR REPORTING The AD7134 has additional GPIO functionality when operated in SPI control mode. This fully configurable mode allows the device to operate eight GPIOs, thus making the AD7134 work as an SPI-based GPIO expander. The GPIO pins can be set as inputs or outputs (read or write) on a per pin basis. Additionally, GPIO7 can be used as an output to report any of the diagnostic errors by enabling Bit ERR_PIN_OUT_EN. Register ERROR_PIN_SRC_CONTROL controls the type of errors that can be reported on this pin. If multiple types are selected, the output is a logical OR of all the selected errors. In write mode, these GPIO pins can be used to control other circuits such as switches, amplifiers, multiplexers, and buffers over the same SPI interface as the AD7134. Sharing the SPI interface in this way allows the user to use a lower overall number of data lines from the controller, compared to a system where multiple control signals are required. This sharing is especially useful in systems where reducing the number of control lines across an isolation barrier is important. Similarly, a GPIO read is a useful feature because it allows a peripheral device to send information to the input GPIO and then this information can be read from the SPI interface of the AD7134. GPIO6 can be used as an error input from any other device by enabling the ERR_PIN_IN_EN bit. The status of this bit can be read using the ERR_PIN_IN_STATUS bit. The GPIO7 output is a logical OR of all the selected errors, as per the ERROR_PIN_SRC_CONTROL register and the ERR_PIN_IN_STATUS bit. The GPIO pins can be used as general-purpose inputs or outputs. The GPIO_DIR_CTRL register configures the individual pin as an input or output. The GPIO_DATA register reflects the status of the pins when configured as inputs or the user can write to this register to set the pins when configured as outputs (see Figure 126). DCLKRATE0/GPIO0 DCLKRATE1/GPIO1 PWRMODE/GPIO3 DEC2/SDI FILTER0/GPIO4 DEC3/SDO FILTER1/GPIO5 FORMAT0/CS DIGITAL ISOLATOR (OPTIONAL) MICROPROCESSOR/ DSP SCLK SPI PORT MOSI (MASTER) MISO CS FRAME0/GPIO6 FRAME1/GPIO7 AD7134 Figure 126. AD7134 as SPI GPIO Expander Rev. 0 | Page 68 of 86 22652-149 SWITCHES AMPLIFIERS MULTIPLEXERS BUFFERS DCLKRATE2/GPIO2 FORMAT1/SCLK Data Sheet AD7134 REGISTER MAP (SPI CONTROL) See Table 38 for the register map for the device (SPI control). Table 38. Register Map Reg 0x0 Name INTERFACE_ CONFIG_A Bit 7 SOFT_ RESET Bit 6 Reserved Bit 5 ADDRESS_ ASCENSION_BIT 0x1 INTERFACE_ CONFIG_B SINGLE_ INSTR Reserved 0x2 DEVICE_CONFIG Reserved MASTER_ SLAVE_ RD_CTRL OP_IN_ PROGRESS 0x3 0x4 0x5 0x6 0x7 0xA 0xB 0xC 0xD 0xE 0xF CHIP_TYPE PRODUCT_ID_LSB PRODUCT_ID_MSB CHIP_GRADE SILICON_REV SCRATCH_PAD SPI_REVISION VENDOR_ID_LSB VENDOR_ID_MSB STREAM_MODE TRANSFER_REGISTER 0x10 DEVICE_CONFIG_1 0x11 DATA_PACKET_ CONFIG 0x12 DIGITAL_INTERFACE_ CONFIG POWER_DOWN_ CONTROL RESERVED DEVICE_STATUS 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F ODR_VAL_INT_LSB ODR_VAL_INT_MID ODR_VAL_INT_MSB ODR_VAL_FLT_LSB ODR_VAL_FLT_MID0 ODR_VAL_FLT_MID1 ODR_VAL_FLT_MSB CHANNEL_ODR_ SELECT CHAN_DIG_FILTER_ SEL FIR_BW_SEL 0x20 0x21 0x22 GPIO_DIR_CTRL GPIO_DATA ERROR_PIN_SRC_ CONTROL 0x23 0x24 ERROR_PIN_ CONTROL VCMBUF_CTRL 0x25 Diagnostic Control Bit 4 SDO_ ACTIVE_ BIT Bit 3 SDO_ ACTIVE_ BIT_ MIRROR Reserved NO_CHIP_ ERR CHIP_TYPE PRODUCT_ID[7:0] PRODUCT_ID[15:8] Bit 2 ADDRESS_ ASCENSION_ BIT_MIRROR Bit 1 Reserved Bit 0 SOFT_ RESET_ MIRROR Reset 0x18 RW R/W DIG_IF_ RESET Reserved 0x80 R/W POWER_ MODE 0xD0 R/W 0x07 N/A1 N/A1 0x00 0x02 0x00 0x02 0x56 0x04 0x00 0x00 R R R R R R/W R R R R/W R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 0x00 R/W R ODR_RATE_SEL_CH0 0x40 0x00 0x00 0x72 0xB7 0xCE 0x2B 0x00 R/W R/W R/W R/W R/W R/W R/W R/W DIGFILTER_SEL_CH0 0x00 R/W 0x00 R/W 0x00 0x00 0x00 R/W R/W R/W 0x00 R/W 0x00 R/W 0x00 R/W Reserved PRODUCT_GRADE DEVICE_VERSION SILICON_REVISION_ID SCRATCH_PAD SPI_REVSION_NUMBER VENDOR_ID[7:0] VENDOR_ID[15:8] STREAM_MODE_BITS Reserved Reserved CRC_ POLY_ RST_SEL Reserved AA_MODE Reserved PWRDN_ CH3 Reserved ODR_RATE_SEL_CH3 DIGFILTER_SEL_CH3 PWRDN_CH2 AVG_SEL PWRDN_ CH1 DIGFILTER_SEL_CH2 ERR_PIN_ EN_OR_AIN Reserved Reserved PWRDN_ VCMBUF Reserved REFIN_ GAIN_ CORR_EN DCLK_FREQ_SEL Reserved PWRDN_ CH0 Reserved STAT_ STAT_ STAT_ STAT_ DCLKMODE DCLKIO MODE CLKSEL ODR_VAL_INT[7:0] ODR_VAL_INT[15:8] ODR_VAL_INT[23:16] ODR_VAL_FLT[7:0] ODR_VAL_FLT[15:8] ODR_VAL_FLT[23:16] ODR_VAL_FLT[31:24] ODR_RATE_SEL_CH2 ODR_RATE_SEL_CH1 Reserved Reserved SDO_PIN_ SRC_SEL Frame DAISY_CHAIN_DEV_NUM ERR_OR_ AIN_EN DIGFILTER_SEL_CH1 WB_ FILTER_ SEL_CH3 GPIO_IO_CONTROL GPIO_DATA ERR_PIN_ ERR_PIN_ EN_ EN_SPI INTERNAL WB_FILTER_ SEL_CH2 MCLK_ CNT_EN Rev. 0 | Page 69 of 86 Format PWRDN_ LDO SLEEP_ MODE_EN STAT_ FUSE_ECC STAT_ PLL_LOCK WB_FILTER_ SEL_CH1 WB_ FILTER_ SEL_CH0 Reserved ERR_PIN_ IN_STATUS VCMBUF_REF_DIV_SEL Reserved MASTER_ SLAVE_ TX_BIT XCLKOUT_ EN ERR_SPI_ CRC_EN ERR_PIN_ IN_EN ERR_MM_ CRC_EN ERR_PIN_ OUT_EN VCMBUF_ REF_SEL FUSE_ CRC_CHECK AD7134 Data Sheet Reg 0x26 Name MPC_CONFIG 0x27 0x28 0x29 CH0_GAIN_LSB CH0_GAIN_MID CH0_GAIN_MSB 0x2A 0x2B 0x2C CH0_OFFSET_LSB CH0_OFFSET_MID CH0_OFFSET_MSB 0x2D 0x2E 0x2F CH1_GAIN_LSB CH1_GAIN_MID CH1_GAIN_MSB 0x30 0x31 0x32 CH1_OFFSET_LSB CH1_OFFSET_MID CH1_OFFSET_MSB 0x33 0x34 0x35 CH2_GAIN_LSB CH2_GAIN_MID CH2_GAIN_MSB 0x36 0x37 0x38 CH2_OFFSET_LSB CH2_OFFSET_MID CH2_OFFSET_MSB 0x39 0x3A 0x3B CH3_GAIN_LSB CH3_GAIN_MID CH3_GAIN_MSB 0x3C 0x3D 0x3E CH3_OFFSET_LSB CH3_OFFSET_MID CH3_OFFSET_MSB 0x3F 0x40 MCLK_COUNTER DIG_FILTER_OFUF Reserved 0x41 DIG_FILTER_SETTLED Reserved 0x42 INTERNAL_ERROR Reserved 0x47 SPI Error Reserved 0x48 AIN_OR_ERROR Reserved 1 Bit 7 Bit 6 MPC_CLKDEL_EN_ CH3 Bit 5 Bit 4 MPC_CLKDEL_EN_CH2 Reserved OFFSET_ CAL_ EN_CH0 Reserved OFFSET_ CAL_ EN_CH1 Reserved OFFSET_ CAL_ EN_CH2 Reserved OFFSET_ CAL_ EN_CH3 Bit 3 Bit 2 MPC_CLKDEL_EN_CH1 GAIN_CH0[7:0] GAIN_CH0[15:8] GAIN_ CAL_ SEL_CH0 OFFSET_CH0[7:0] OFFSET_CH0[15:8] OFFSET_CH0[22:16] GAIN_CH1[7:0] GAIN_CH1[15:8] GAIN_ CAL_ SEL_CH1 OFFSET_CH1[7:0] OFFSET_CH1[15:8] OFFSET_CH1[22:16] GAIN_CH2[7:0] GAIN_CH2[15:8] GAIN_ CAL_ SEL_CH2 OFFSET_CH2[7:0] OFFSET_CH2[15:8] OFFSET_CH2[22:16] GAIN_CH3[7:0] GAIN_CH3[15:8] GAIN_ CAL_ SEL_CH3 OFFSET_CH3[7:0] OFFSET_CH3[15:8] OFFSET_CH3[22:16] MCLK_COUNT ERR_ OFUF_ CH3 CH3_ SETTLED ERR_DCLK ERR_SPI_ CRC ERR_OR_ AIN3 N/A means not applicable. The reset value is time stamp dependent and programmed in production. Rev. 0 | Page 70 of 86 Bit 1 Bit 0 MPC_CLKDEL_EN_CH0 GAIN_CH0[19:16] GAIN_CH1[19:16] GAIN_CH2[19:16] GAIN_CH3[19:16] ERR_OFUF_ CH2 ERR_OFUF_ CH1 ERR_OFUF_ CH0 CH2_ SETTLED ERR_FUSE_ CRC ERR_SPI_ SCLK_CNT ERR_OR_ AIN2 CH1_ SETTLED ERR_ASRC CH0_ SETTLED ERR_MM_ CRC ERR_SPI_ READ ERR_OR_ AIN0 ERR_SPI_ WRITE ERR_OR_ AIN1 Reset 0x00 RW R/W 0x00 0x00 0x00 R/W R/W R/W 0x00 0x00 0x00 R/W R/W R/W 0x00 0x00 0x00 R/W R/W R/W 0x00 0x00 0x00 R/W R/W R/W 0x00 0x00 0x00 R/W R/W R/W 0x00 0x00 0x00 R/W R/W R/W 0x00 0x00 0x00 R/W R/W R/W 0x00 0x00 0x00 R/W R/W R/W 0x00 0x00 R R 0x00 R 0x00 R 0x00 R 0x00 R Data Sheet AD7134 REGISTER DETAILS Address: 0x0, Reset: 0x18, Name: INTERFACE_CONFIG_A Table 39. Bit Descriptions for INTERFACE_CONFIG_A Bits 7 Bit Name SOFT_RESET Settings 0 1 6 5 Reserved ADDRESS_ASCENSION_BIT 0 1 4 SDO_ACTIVE_BIT 0 1 3 2 1 0 SDO_ACTIVE_BIT_MIRROR ADDRESS_ASCENSION_BIT_MIRROR Reserved SOFT_RESET_MIRROR 0 1 Description Soft Reset of the Device. This bit is cleared on completion of a reset. Default. Initiates a soft reset. Reserved. Register Map Address Ascension/Descend Control. Used in conjunction with streaming mode, address ascension causes sequential register addresses to ascend in order. Disabling causes sequential register addresses to descend in order. Sequential register address in descending order. Sequential register address in ascending order. SDO Control. SDO disabled, exhibit high impedance. SDO enabled. Mirror Image of SDO_ACTIVE_BIT. Mirror Image of ADDRESS_ASCENTION_BIT. Reserved. Mirror Image of SOFT_RESET. Default. Initiates a soft reset. Reset 0x0 Access R/W 0x0 0x0 R R/W 0x1 R/W 0x1 0x0 0x0 0x0 R R R R/W Reset 0x1 Access R/W 0x0 0x0 R R/W 0x0 0x0 0x0 R R/W R/W Reset 0x3 0x0 Access R R Address: 0x1, Reset: 0x80, Name: INTERFACE_CONFIG_B Table 40. Bit Descriptions for INTERFACE_CONFIG_B Bits 7 Bit Name SINGLE_INSTR Settings 0 1 6 5 Reserved MASTER_SLAVE_RD_CTRL 0 1 [4:2] 1 0 Reserved DIG_IF_RESET Reserved Description Single Instruction Mode Control. When set, this bit disables streaming regardless of the state of CS. When clear, streaming is enabled. Disable. Enable. Reserved. Master Slave Readback Control. Determines the data to read back from the master or slave buffered bits (ODR_VAL_INT_x and ODR_VAL_FLT_x). Set to 1 to read back from master output. Clear this bit to read back from slave output. Readback of the slave flip flop outputs. Readback of the master flip flop outputs. Reserved. Digital Interface Reset. Reserved. Address: 0x2, Reset: 0xD0, Name: DEVICE_CONFIG Table 41. Bit Descriptions for DEVICE_CONFIG Bits [7:6] 5 Bit Name Reserved OP_IN_PROGRESS Settings 0 1 Description Reserved. Operation in Progress Indicator. A readback value of 0 indicates that the device is busy. Some operation in progress. No operation in progress. Rev. 0 | Page 71 of 86 AD7134 Bits 4 Data Sheet Bit Name NO_CHIP_ERR Settings Description Error Flag for all of the Enabled Status Errors. This bit is the OR of all the enabled error bits and continues to stay clear as long as any error flag is set. Device has a chip error. No chip error. Reserved. Device Power Mode Control. Low power mode. High performance mode. 0 1 [3:1] 0 Reserved POWER_MODE 0 1 Reset 0x1 Access R 0x0 0x0 R R/W Reset 0x7 Access R Address: 0x3, Reset: 0x07, Name: CHIP_TYPE Table 42. Bit Descriptions for CHIP_TYPE Bits [7:0] Bit Name CHIP_TYPE Settings Description Code to Indicate the Type of Device. Read 0x07 to confirm for precision ADC. Address: 0x4, Reset: 0x00, Name: PRODUCT_ID_LSB Table 43. Bit Descriptions for PRODUCT_ID_LSB Bits [7:0] 1 Bit Name PRODUCT_ID[7:0] Settings Description Product ID. Reset Not applicable 1 Access R Reset Not applicable 1 Access R Reset value is time stamp dependent and programmed in production. Address: 0x5, Reset: 0x00, Name: PRODUCT_ID_MSB Table 44. Bit Descriptions for PRODUCT_ID_MSB Bits [7:0] 1 Bit Name PRODUCT_ID[15:8] Settings Description Product ID. Reset value is time stamp dependent and programmed in production. Address: 0x6, Reset: 0x00, Name: CHIP_GRADE Table 45. Bit Descriptions for CHIP_GRADE Bits [7:4] [3:0] Bit Name PRODUCT_GRADE DEVICE_VERSION Settings Description Grade of the Device. Device Version. Reset 0x0 0x0 Access R R Address: 0x7, Reset: 0x02, Name: SILICON_REV Table 46. Bit Descriptions for SILICON_REV Bits [7:0] Bit Name SILICON_REVISION_ID Settings Description Stores the Revision Number of the Current Silicon. Reset 0x2 Access R Reset 0x0 Access R/W Reset 0x2 Access R Address: 0xA, Reset: 0x00, Name: SCRATCH_PAD Table 47. Bit Descriptions for SCRATCH_PAD Bits [7:0] Bit Name SCRATCH_PAD Settings Description Scratch Pad for Checking SPI Read and Write Operation. Address: 0xB, Reset: 0x02, Name: SPI_REVISION Table 48. Bit Descriptions for SPI_REVISION Bits [7:0] Bit Name SPI_REVSION_NUMBER Settings Description Indicate the Revision Number of the SPI Protocol. Address: 0xC, Reset: 0x56, Name: VENDOR_ID_LSB Table 49. Bit Descriptions for VENDOR_ID_LSB Bits [7:0] Bit Name VENDOR_ID[7:0] Settings Description Vendor ID. Rev. 0 | Page 72 of 86 Reset 0x56 Access R Data Sheet AD7134 Address: 0xD, Reset: 0x04, Name: VENDOR_ID_MSB Table 50. Bit Descriptions for VENDOR_ID_MSB Bits [7:0] Bit Name VENDOR_ID[15:8] Settings Description Vendor ID. Reset 0x4 Access R Address: 0xE, Reset: 0x00, Name: STREAM_MODE Table 51. Bit Descriptions for STREAM_MODE Bits [7:0] Bit Name STREAM_MODE_BITS Settings Description Defines the Depth of the Loop for User Stream Mode. Reset 0x0 Access R/W Address: 0xF, Reset: 0x00, Name: TRANSFER_REGISTER Table 52. Bit Descriptions for TRANSFER_REGISTER Bits [7:1] 0 Bit Name Reserved MASTER_SLAVE_TX_BIT Settings Description Reserved. Master Slave Transfer Bit. When this bit is set, data is entered into the master registers transferred to the slave. Upon completion of the transfer, the slave device clears this bit (autoclears), indicating to the SPI master that the transfer was complete and the slave data can be read back if desired by the control program. Prior to a transfer, an attempted readback views the prior data unless Bit 5 of Register 0x1 (MASTER_SLAVE_RD_CTRL) is set. In that case, the master data is accessed. Another method to invoke the transfer is to use the CS low to high transition. Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R/W R/W 0x0 R/W 0x0 R/W 0x0 R/W Reset 0x0 Access R/W 0x0 R Address: 0x10, Reset: 0x00, Name: DEVICE_CONFIG_1 Table 53. Bit Descriptions for DEVICE_CONFIG_1 Bits [7:4] 3 Bit Name Reserved AA_MODE Settings 0 1 2 SDO_PIN_SRC_SEL 0 1 1 REFIN_GAIN_CORR_EN 0 1 0 XCLKOUT_EN 0 1 Description Reserved, is always zero. Sets Inherent Antialiasing Mode. AA1 mode. AA2 mode. DEC3/SDO Pin Signal Source Selection. In minimum I/O mode, the user can use the DEC3/SDO pin for both register content and ADC conversion data readback. DEC3/SDO pin acts as SPI serial data output. Signal on DOUT0 is duplicated on DEC3/SDO pin. Enables Reference Gain Correction. Reference gain correction disabled. Reference gain correction enabled. XCLKOUT Output Enable Control. XCLKOUT disabled. XCLKOUT enabled. Address: 0x11, Reset: 0x00, Name: DATA_PACKET_CONFIG Table 54. Bit Descriptions for DATA_PACKET_CONFIG Bits 7 Bit Name CRC_POLY_RST_SEL Settings 0 1 6 Reserved Description Data Interface CRC Reset Method Selection. The data interface CRC is reset with default seed value at the end of every data frame. The data interface CRC does not reset at the end of each data frame. The CRC value calculated from the proceeding data frame seeds the CRC calculation of the current data frame. Reserved Rev. 0 | Page 73 of 86 AD7134 Bits [5:4] Bit Name Frame Data Sheet Settings 0 1 10 11 [3:0] DCLK_FREQ_SEL 0 1 10 11 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111 Description ADC Conversion Data Output Frame Control. 16-bit ADC data only. 16-bit ADC data followed by 6-bit CRC. 24-bit ADC data only. 24-bit ADC data followed by 6-bit CRC. Controls DCLK Output Frequency. fDCLK = 48 MHz. fDCLK = 24 MHz. fDCLK = 12 MHz. fDCLK = 6 MHz. fDCLK = 3 MHz. fDCLK = 1.5 MHz. fDCLK = 750 kHz. fDCLK = 375 kHz. fDCLK = 187.5 kHz. fDCLK = 93.75 kHz. fDCLK = 46.875 kHz. fDCLK = 23.4375 kHz. fDCLK = 11.71875 kHz. fDCLK = 5.859 kHz. fDCLK = 2.929 kHz. fDCLK = 1.464 kHz. Reset 0x0 Access R/W 0x0 R/W Reset 0x0 Access R/W Address: 0x12, Reset: 0x00, Name: DIGITAL_INTERFACE_CONFIG Table 55. Bit Descriptions for DIGITAL_INTERFACE_CONFIG Bits [7:4] Bit Name DAISY_CHAIN_DEV_NUM Settings 0 1 10 11 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111 Description Sets the Number of Devices Connected in a Daisy-Chain Configuration. This register is only applicable to a device set to output DCLK to other devices in a daisy-chain configuration. The register value acts as a clock cycle multiplier in DCLK output configuration. For example, setting the daisychain device number to two doubles the number of DCLK cycles output per ODR cycle. Only one device is used. 2 devices are in daisy-chain configuration. 3 devices are in daisy-chain configuration. 4 devices are in daisy-chain configuration. 5 devices are in daisy-chain configuration. 6 devices are in daisy-chain configuration. 7 devices are in daisy-chain configuration. 8 devices are in daisy-chain configuration. 9 devices are in daisy-chain configuration. 10 devices are in daisy-chain configuration. 11 devices are in daisy-chain configuration. 12 devices are in daisy-chain configuration. 13 devices are in daisy-chain configuration. 14 devices are in daisy-chain configuration. 15 devices are in daisy-chain configuration. 16 devices are in daisy-chain configuration. Rev. 0 | Page 74 of 86 Data Sheet Bits [3:2] Bit Name AVG_SEL AD7134 Settings 0 1 10 11 [1:0] Format 0 1 10 11 Description Multichannel ADC Conversion Data Averaging Control. Data from all four channels are averaged and output on DOUT0. DOUT2 acts as daisy-chain input. DOUT1 and DOUT3 are disabled. Data from Channel 0 and Channel 1 are averaged and output on DOUT0. DOUT1 is disabled. Channel 2 and Channel 3 are under normal operation. Data from Channel 2 and Channel 3 are averaged and output on DOUT2. DOUT3 is disabled. Channel 0 and Channel 1 are under normal operation. Data from Channel 0 and Channel 1 are averaged and output on DOUT0. Data from Channel 2 and Channel 3 are averaged and output on DOUT1. DOUT2 and DOUT3 act as daisy-chain inputs. DOUTx Output Format Configuration. Single-channel daisy-chain mode. DOUT0 acts as an output and DOUT2 acts as a daisy-chain input. DOUT1 and DOUT3 are disabled. Data from all four ADC channels are output on DOUT0. Dual-channel daisy-chain mode. DOUT0 and DOUT1 act as output and DOUT2 and DOUT3 act as daisy-chain input. Data from Channel 0 and Channel 1 are output on DOUT0. Data from Channel 2 and Channel 3 are output on DOUT1. Quad channel parallel output mode. Each ADC channel has a dedicated data output pin. Channel data averaging mode, averaging operation is defined by AVG_SEL. Reset 0x0 Access R/W 0x0 R/W Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W Address: 0x13, Reset: 0x00, Name: POWER_DOWN_CONTROL Table 56. Bit Descriptions for POWER_DOWN_CONTROL Bits 7 6 Bit Name Reserved PWRDN_CH3 Settings 0 1 5 PWRDN_CH2 0 1 4 PWRDN_CH1 0 1 3 PWRDN_CH0 0 1 2 1 Reserved PWRDN_LDO 0 1 0 SLEEP_MODE_EN 0 1 Description Reserved. Powers Down Analog Input Channel 3. Power up. Power down. Powers Down Analog Input Channel 2. Power up. Power down. Powers Down Analog Input Channel 1. Power up. Power down. Powers Down Analog Input Channel 0. Power up. Power down. Reserved. Powers Down the Internal Analog and Clock LDO Regulators. Internal LDO regulators powered. Internal LDO regulators powered down. All Blocks Except Digital LDO Regulator are Turned Off. On-chip register contents remain the same. Sleep mode disabled. Sleep mode enabled. Address: 0x14, Reset: 0x00, Name: RESERVED Table 57. Bit Descriptions for RESERVED Bits [7:0] Bit Name Reserved Settings Description Reserved. Always zero. Rev. 0 | Page 75 of 86 Reset 0x0 Access R/W AD7134 Data Sheet Address: 0x15, Reset: 0x00, Name: DEVICE_STATUS Table 58. Bit Descriptions for DEVICE_STATUS Bits [7:6] 5 Bit Name Reserved STAT_DCLKMODE Settings 0 1 4 STAT_DCLKIO 0 1 3 STAT_MODE 0 1 2 STAT_CLKSEL 0 1 1 STAT_FUSE_ECC 0 1 0 STAT_PLL_LOCK 0 1 Description Reserved. DEC1/DCLKMODE Pin Status Indicates if DCLK is in Free Running or Gated Mode. DCLK is in gated mode. Compatible with SPI interface. DCLK is in free running mode. DEC0/DCLKIO Pin Status Indicates DCLK Pin Direction. DCLK is input. DCLK is output. MODE Pin Status Indicates Whether Device is Master or Slave. Slave mode: ODR is input. Master mode: ODR is output. CLKSEL Pin Status Indicates the Clock Source. CMOS input clock is connected. Crystal input is connected. Status Bit that Indicates Application of Fuse Error Correction Code. This bit is cleared on is read. Error code correction not applied. Error code correction applied. PLL Status in Slave Mode. Indicates if PLL has locked or not. Setting this bit indicates PLL is locked. PLL not locked. PLL locked. Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Reset 0x40 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x72 Access R/W Address: 0x16, Reset: 0x40, Name: ODR_VAL_INT_LSB Table 59. Bit Descriptions for ODR_VAL_INT_LSB Bits [7:0] Bit Name ODR_VAL_INT[7:0] Settings Description Integer Portion of Decimation Rate. Decimation rate is the ratio of MCLK to ODR. In master mode, the user can program this register to set the ODR output frequency based on the MCLK frequency. Address: 0x17, Reset: 0x00, Name: ODR_VAL_INT_MID Table 60. Bit Descriptions for ODR_VAL_INT_MID Bits [7:0] Bit Name ODR_VAL_INT[15:8] Settings Description Integer Portion of Decimation Rate. Decimation rate is the ratio of MCLK to ODR. In master mode, the user can program this register to set the ODR output frequency based on the MCLK frequency. Address: 0x18, Reset: 0x00, Name: ODR_VAL_INT_MSB Table 61. Bit Descriptions for ODR_VAL_INT_MSB Bits [7:0] Bit Name ODR_VAL_INT[23:16] Settings Description Integer Portion of Decimation Rate. Decimation rate is the ratio of MCLK to ODR. In master mode, the user can program this register to set the ODR output frequency based on the MCLK frequency. Address: 0x19, Reset: 0x72, Name: ODR_VAL_FLT_LSB Table 62. Bit Descriptions for ODR_VAL_FLT_LSB Bits [7:0] Bit Name ODR_VAL_FLT[7:0] Settings Description Fractional Portion of Decimation Rate. Decimation rate is the ratio of MCLK to ODR. In master mode, the user can program this register to set the ODR output frequency based on the MCLK frequency. Rev. 0 | Page 76 of 86 Data Sheet AD7134 Address: 0x1A, Reset: 0xB7, Name: ODR_VAL_FLT_MID0 Table 63. Bit Descriptions for ODR_VAL_FLT_MID0 Bits [7:0] Bit Name ODR_VAL_FLT[15:8] Settings Description Fractional Portion of Decimation Rate. Decimation rate is the ratio of MCLK to ODR. In master mode, the user can program this register to set the ODR output frequency based on the MCLK frequency. Reset 0xB7 Access R/W Reset 0xCE Access R/W Reset 0x2B Access R/W Address: 0x1B, Reset: 0xCE, Name: ODR_VAL_FLT_MID1 Table 64. Bit Descriptions for ODR_VAL_FLT_MID1 Bits [7:0] Bit Name ODR_VAL_FLT[23:16] Settings Description Fractional Portion of Decimation Rate. Decimation rate is the ratio of MCLK to ODR. In master mode, the user can program this register to set the ODR output frequency based on the MCLK frequency. Address: 0x1C, Reset: 0x2B, Name: ODR_VAL_FLT_MSB Table 65. Bit Descriptions for ODR_VAL_FLT_MSB Bits [7:0] Bit Name ODR_VAL_FLT[31:24] Settings Description Fractional Portion of Decimation Rate. Decimation rate is the ratio of MCLK to ODR. In master mode, the user can program this register to set the ODR output frequency based on the MCLK frequency. Address: 0x1D, Reset: 0x00, Name: CHANNEL_ODR_SELECT Table 66. Bit Descriptions for CHANNEL_ODR_SELECT Bits [7:6] Bit Name ODR_RATE_SEL_CH3 Settings Description Select Output Data Rate to ODR Frequency Ratio for Channel 3. Output data rate = ODR. Output data rate = ODR/2. Output data rate = ODR/4. Output data rate = ODR/8. Select Output Data Rate to ODR Frequency Ratio for Channel 2. Output data rate = ODR. Output data rate = ODR/2. Output data rate = ODR/4. Output data rate = ODR/8. Select Output Data Rate to ODR Frequency Ratio for Channel 1. Output data rate = ODR. Output data rate = ODR/2. Output data rate = ODR/4. Output data rate = ODR/8. Select Output Data Rate to ODR Frequency Ratio for Channel 0. Output data rate = ODR. Output data rate = ODR/2. Output data rate = ODR/4. Output data rate = ODR/8. 0 1 10 11 [5:4] ODR_RATE_SEL_CH2 0 1 10 11 [3:2] ODR_RATE_SEL_CH1 0 1 10 11 [1:0] ODR_RATE_SEL_CH0 0 1 10 11 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W Reset 0x0 Access R/W 0x0 R/W Address: 0x1E, Reset: 0x00, Name: CHAN_DIG_FILTER_SEL Table 67. Bit Descriptions for CHAN_DIG_FILTER_SEL Bits [7:6] Bit Name DIGFILTER_SEL_CH3 Settings 0 01 10 11 [5:4] DIGFILTER_SEL_CH2 0 01 Description Channel 3 Digital Filter Type Selection. Wideband filter. Sinc6 filter. Sinc3 filter. Sinc3 filter with simultaneous 50 Hz and 60 Hz rejection. Channel 2 Digital Filter Type Selection. Wideband filter. Sinc6 filter. Rev. 0 | Page 77 of 86 AD7134 Data Sheet Bits Bit Name Settings 10 11 [3:2] DIGFILTER_SEL_CH1 Description Sinc3 filter. Sinc3 filter with simultaneous 50 Hz and 60 Hz rejection. Channel 1 Digital Filter Type Selection. Wideband filter. Sinc6 filter. Sinc3 filter. Sinc3 filter with simultaneous 50 Hz and 60 Hz rejection. Channel 0 Digital Filter Type Selection. Wideband filter. Sinc6 filter. Sinc3 filter. Sinc3 filter with simultaneous 50 Hz and 60 Hz rejection. 0 01 10 11 [1:0] DIGFILTER_SEL_CH0 0 01 10 11 Reset Access 0x0 R/W 0x0 R/W Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W Address: 0x1F, Reset: 0x00, Name: FIR_BW_SEL Table 68. Bit Descriptions for FIR_BW_SEL Bits [7:4] 3 Bit Name Reserved WB_FILTER_SEL_CH3 Settings 0 1 2 WB_FILTER_SEL_CH2 0 1 1 WB_FILTER_SEL_CH1 0 1 0 WB_FILTER_SEL_CH0 0 1 Description Reserved. Channel 3 Wideband Filter Bandwidth Selection. Wideband filter has a bandwidth of 0.433 Hz × ODR. Wideband filter has a bandwidth of 0.10825 Hz × ODR. Channel 2 Wideband Filter Bandwidth Selection. Wideband filter has a bandwidth of 0.433 Hz × ODR. Wideband filter has a bandwidth of 0.10825 Hz × ODR. Channel 1 Wideband Filter Bandwidth Selection. Wideband filter has a bandwidth of 0.433 Hz × ODR. Wideband filter has a bandwidth of 0.10825 Hz × ODR. Channel 0 Wideband Filter Bandwidth Selection. Wideband filter has a bandwidth of 0.433 Hz × ODR. Wideband filter has a bandwidth of 0.10825 Hz × ODR. Address: 0x20, Reset: 0x00, Name: GPIO_DIR_CTRL Table 69. Bit Descriptions for GPIO_DIR_CTRL Bits [7:0] Bit Name GPIO_IO_CONTROL Settings Description GPIO I/O Direction Control. Each bit controls the direction of a GPIO pin. A value of 0 sets the GPIO pin as an input. A value of 1 sets the GPIO pin as an output. Bit 0 is associated with GPIO0. Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 0x0 Access R R/W Address: 0x21, Reset: 0x00, Name: GPIO_DATA Table 70. Bit Descriptions for GPIO_DATA Bits [7:0] Bit Name GPIO_DATA Settings Description GPIO Data Value. If a GPIO pin is configured as an input, the corresponding bit is read only and its value reflects the input logic status of the pin. If a GPIO pin is configured as an output, write to the corresponding bit to control the output logic of the pin. Bit 0 is associated with GPIO0. 1 = logic high and 0 = logic low. Address: 0x22, Reset: 0x00, Name: ERROR_PIN_SRC_CONTROL Table 71. Bit Descriptions for ERROR_PIN_SRC_CONTROL Bits [7:6] 5 Bit Name Reserved ERR_PIN_EN_OR_AIN Settings 0 1 Description Reserved. Enables Error Reporting on GPIO7 for Input Overrange Errors. Disables pin toggle for overvoltage error. Enables pin toggle for overvoltage error. Rev. 0 | Page 78 of 86 Data Sheet Bits 4 Bit Name ERR_PIN_EN_INTERNAL AD7134 Settings 0 1 3 ERR_PIN_EN_SPI 0 1 [2:0] Reserved Description Enables Error Reporting on GPIO7 for Any Internal Errors. Internal error can be digital overflow or underflow error, memory map CRC error, ASRC error, fuse CRC error, or DCLK counter error. Make sure to enable the corresponding error in the diagnostic control register to enable this reporting. Disables pin toggle for internal errors. Enables pin toggle for internal errors. Enables error reporting on GPIO7 if there are any SPI errors such as read, write, CRC check, and clock counter errors. Make sure to enable SPI CRC error for reporting those errors on the pin. Disables pin toggle for SPI related errors. Enables pin toggle for SPI related errors. Reserved. Reset 0x0 Access R/W 0x0 R/W 0x0 R Reset 0x0 0x0 Access R R 0x0 R/W 0x0 R/W Reset 0x0 0x0 Access R R/W 0x0 R/W Address: 0x23, Reset: 0x00, Name: ERROR_PIN_CONTROL Table 72. Bit Descriptions for ERROR_PIN_CONTROL Bits [7:3] 2 Bit Name Reserved ERR_PIN_IN_STATUS 1 ERR_PIN_IN_EN 0 ERR_PIN_OUT_EN Settings Description Reserved. This bit is the readback of the latched status of the error input, GPIO6, when it is enabled using the ERR_PIN_IN_EN bit. Enables GPIO6 as an error input. This bit allows error to be daisy-chained from a digital host and is OR’ed with internal errors. Enables GPIO7 as an error output pin. The source of this error is defined by the ERROR_PIN_SRC_CONTROL register. Address: 0x24, Reset: 0x00, Name: VCMBUF_CTRL Table 73. Bit Descriptions for VCMBUF_CTRL Bits 7 6 Bit Name Reserved PWRDN_VCMBUF Settings 0 1 [5:1] VCMBUF_REF_DIV_SEL 0 1 10 11 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111 10000 10001 10010 10011 11101 11110 11111 Description Reserved. VCM Buffer Power Control. VCM buffer powered on. VCM buffer powered down. VCM Output Voltage Level Selection when VCMBUF_REF_SEL = 0. VCM = VREF × 10/20. Reserved. VCM = VREF × 19/20. VCM = VREF × 18/20. VCM = VREF × 17/20. VCM = VREF × 16/20. VCM = VREF × 15/20. VCM = VREF × 14/20. VCM = VREF × 13/20. VCM = VREF × 12/20. VCM = VREF × 11/20. VCM = VREF × 9/20. VCM = VREF × 8/20. VCM = VREF × 7/20. VCM = VREF × 6/20. VCM = VREF × 5/20. VCM = VREF × 4/20. VCM = VREF × 3/20. VCM = VREF × 2/20. VCM = VREF × 1/20. VCM = VREF × 10/20. VCM = VREF × 10/20. VCM = VREF × 10/20. Rev. 0 | Page 79 of 86 AD7134 Bits 0 Data Sheet Bit Name VCMBUF_REF_SEL Settings 0 1 Description VCM Output Source Selection. VCM as a ratio of VREF. The VCM output level is VREF divided by the ratio set with VCMBUF_REF_DIV_SEL. VCM is fixed to AVDD5/2. Reset 0x0 Access R/W Reset 0x0 0x0 Access R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W Address: 0x25, Reset: 0x00, Name: Diagnostic Control Table 74. Bit Descriptions for Diagnostic Control Bits [7:6] 5 Bit Name Reserved ERR_OR_AIN_EN Settings 0 1 4 3 Reserved MCLK_CNT_EN 0 1 2 ERR_SPI_CRC_EN 0 1 1 ERR_MM_CRC_EN 0 1 0 FUSE_CRC_CHECK 0 1 Description Reserved. Enables Overrange Monitor on all Enabled Analog Input Channels. Input overvoltage monitor is disabled. Input overvoltage monitor is enabled. Reserved Enables Master Clock Counter. Starts the MCLK counter, which monitors the external clock being used by the ADC. Disables MCLK counter. Enables MCLK counter. Enables CRC Check on SPI Read and Write Operations. The ERR_SPI_CRC bit in the SPI error register is set if the CRC check fails. In addition, an 8-bit CRC word is appended to all SPI read operations. SPI CRC disabled. SPI CRC enabled. Enables Memory Map CRC Calculation. CRC calculation is performed on the memory map each time the registers are written to. Following this write, periodic CRC checks are performed on the on-chip registers. If the register contents have changed, the ERR_MM_CRC bit is set. Disables memory map CRC check. Enables memory map CRC check. Initiates a CRC Calculation on the Fuse Contents. If the fuse contents have changed, the ERR_FUSE_CRC bit is set. This bit is cleared on completion of the check. CRC calculation disabled. CRC calculation enabled. Address: 0x26, Reset: 0x00, Name: MPC_CONFIG Table 75. Bit Descriptions for MPC_CONFIG Bits [7:6] Bit Name MPC_CLKDEL_EN_CH3 Settings 00 01 10 11 [5:4] MPC_CLKDEL_EN_CH2 00 01 10 11 [3:2] MPC_CLKDEL_EN_CH1 00 01 10 11 [1:0] MPC_CLKDEL_EN_CH0 00 01 Description Magnitude and Phase Matching Calibration Clock Delay Enable for Channel 3. Magnitude and phase clock delay: 0 clock delays. Magnitude and phase clock delay: 1 clock delay. Magnitude and phase clock delay: 2 clock delays. Magnitude and phase clock delay: 0 clock delays. Magnitude and Phase Matching Calibration Clock Delay Enable for Channel 2. Magnitude and phase clock delay: 0 clock delays. Magnitude and phase clock delay: 1 clock delay. Magnitude and phase clock delay: 2 clock delays. Magnitude and phase clock delay: 0 clock delays. Magnitude and Phase Matching Calibration Clock Delay Enable for Channel 1. Magnitude and phase clock delay: 0 clock delays. Magnitude and phase clock delay: 1 clock delay. Magnitude and phase clock delay: 2 clock delays. Magnitude and phase clock delay: 0 clock delay. Magnitude and Phase Matching Calibration Clock Delay Enable for Channel 0. Magnitude and phase clock delay: 0 clock delays. Magnitude and phase clock delay: 1 clock delay. Rev. 0 | Page 80 of 86 Data Sheet Bits Bit Name AD7134 Settings 10 11 Description Magnitude and phase clock delay: 2 clock delays. Magnitude and phase clock delay: 0 clock delay. Reset Access Address: 0x27, Reset: 0x00, Name: CH0_GAIN_LSB Table 76. Bit Descriptions for CH0_GAIN_LSB Bits [7:0] Bit Name GAIN_CH0[7:0] Settings Description Channel 0 Gain Calibration Value. Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x28, Reset: 0x00, Name: CH0_GAIN_MID Table 77. Bit Descriptions for CH0_GAIN_MID Bits [7:0] Bit Name GAIN_CH0[15:8] Settings Description Channel 0 Gain Calibration Value. Address: 0x29, Reset: 0x00, Name: CH0_GAIN_MSB Table 78. Bit Descriptions for CH0_GAIN_MSB Bits [7:5] 4 [3:0] Bit Name Reserved GAIN_CAL_SEL_CH0 GAIN_CH0[19:16] Settings Description Reserved. Enables Gain Calibration on Channel 0. Channel 0 Gain Calibration Value. Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x2A, Reset: 0x00, Name: CH0_OFFSET_LSB Table 79. Bit Descriptions for CH0_OFFSET_LSB Bits [7:0] Bit Name OFFSET_CH0[7:0] Settings Description Channel 0 Offset Calibration Value. Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x2B, Reset: 0x00, Name: CH0_OFFSET_MID Table 80. Bit Descriptions for CH0_OFFSET_MID Bits [7:0] Bit Name OFFSET_CH0[15:8] Settings Description Channel 0 Offset Calibration Value. Address: 0x2C, Reset: 0x00, Name: CH0_OFFSET_MSB Table 81. Bit Descriptions for CH0_OFFSET_MSB Bits 7 [6:0] Bit Name OFFSET_CAL_EN_CH0 OFFSET_CH0[22:16] Settings Description Enables Offset Calibration on Channel 0. Channel 0 Offset Calibration Value. Reset 0x0 0x0 Access R/W R/W Address: 0x2D, Reset: 0x00, Name: CH1_GAIN_LSB Table 82. Bit Descriptions for CH1_GAIN_LSB Bits [7:0] Bit Name GAIN_CH1[7:0] Settings Description Channel 1 Gain Calibration Value. Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x2E, Reset: 0x00, Name: CH1_GAIN_MID Table 83. Bit Descriptions for CH1_GAIN_MID Bits [7:0] Bit Name GAIN_CH1[15:8] Settings Description Channel 1 Gain Calibration Value. Address: 0x2F, Reset: 0x00, Name: CH1_GAIN_MSB Table 84. Bit Descriptions for CH1_GAIN_MSB Bits [7:5] 4 [3:0] Bit Name Reserved GAIN_CAL_SEL_CH1 GAIN_CH1[19:16] Settings Description Reserved. Enables Gain Calibration on Channel 1. Channel 1 Gain Calibration Value. Rev. 0 | Page 81 of 86 Reset 0x0 0x0 0x0 Access R R/W R/W AD7134 Data Sheet Address: 0x30, Reset: 0x00, Name: CH1_OFFSET_LSB Table 85. Bit Descriptions for CH1_OFFSET_LSB Bits [7:0] Bit Name OFFSET_CH1[7:0] Settings Description Channel 1 Offset Calibration Value. Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x31, Reset: 0x00, Name: CH1_OFFSET_MID Table 86. Bit Descriptions for CH1_OFFSET_MID Bits [7:0] Bit Name OFFSET_CH1[15:8] Settings Description Channel 1 Offset Calibration Value. Address: 0x32, Reset: 0x00, Name: CH1_OFFSET_MSB Table 87. Bit Descriptions for CH1_OFFSET_MSB Bits 7 [6:0] Bit Name OFFSET_CAL_EN_CH1 OFFSET_CH1[22:16] Settings Description Enables Offset Calibration on Channel 1. Channel 1 Offset Calibration Value. Reset 0x0 0x0 Access R/W R/W Address: 0x33, Reset: 0x00, Name: CH2_GAIN_LSB Table 88. Bit Descriptions for CH2_GAIN_LSB Bits [7:0] Bit Name GAIN_CH2[7:0] Settings Description Channel 2 Gain Calibration Value. Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x34, Reset: 0x00, Name: CH2_GAIN_MID Table 89. Bit Descriptions for CH2_GAIN_MID Bits [7:0] Bit Name GAIN_CH2[15:8] Settings Description Channel 2 Gain Calibration Value. Address: 0x35, Reset: 0x00, Name: CH2_GAIN_MSB Table 90. Bit Descriptions for CH2_GAIN_MSB Bits [7:5] 4 [3:0] Bit Name Reserved GAIN_CAL_SEL_CH2 GAIN_CH2[19:16] Settings Description Reserved. Enables Gain Calibration on Channel 2. Channel 2 Gain Calibration Value. Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x36, Reset: 0x00, Name: CH2_OFFSET_LSB Table 91. Bit Descriptions for CH2_OFFSET_LSB Bits [7:0] Bit Name OFFSET_CH2[7:0] Settings Description Channel 2 Offset Calibration Value. Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x37, Reset: 0x00, Name: CH2_OFFSET_MID Table 92. Bit Descriptions for CH2_OFFSET_MID Bits [7:0] Bit Name OFFSET_CH2[15:8] Settings Description Channel 2 Offset Calibration Value. Address: 0x38, Reset: 0x00, Name: CH2_OFFSET_MSB Table 93. Bit Descriptions for CH2_OFFSET_MSB Bits 7 [6:0] Bit Name OFFSET_CAL_EN_CH2 OFFSET_CH2[22:16] Settings Description Enables Offset Calibration on Channel 2. Channel 2 Offset Calibration Value. Reset 0x0 0x0 Access R/W R/W Address: 0x39, Reset: 0x00, Name: CH3_GAIN_LSB Table 94. Bit Descriptions for CH3_GAIN_LSB Bits [7:0] Bit Name GAIN_CH3[7:0] Settings Description Channel 3 Gain Calibration Value. Rev. 0 | Page 82 of 86 Reset 0x0 Access R/W Data Sheet AD7134 Address: 0x3A, Reset: 0x00, Name: CH3_GAIN_MID Table 95. Bit Descriptions for CH3_GAIN_MID Bits [7:0] Bit Name GAIN_CH3[15:8] Settings Description Channel 3 Gain Calibration Value. Reset 0x0 Access R/W Address: 0x3B, Reset: 0x00, Name: CH3_GAIN_MSB Table 96. Bit Descriptions for CH3_GAIN_MSB Bits [7:5] 4 [3:0] Bit Name Reserved GAIN_CAL_SEL_CH3 GAIN_CH3[19:16] Settings Description Reserved. Enables Gain Calibration on Channel 3. Channel 3 Gain Calibration Value. Reset 0x0 0x0 0x0 Access R R/W R/W Address: 0x3C, Reset: 0x00, Name: CH3_OFFSET_LSB Table 97. Bit Descriptions for CH3_OFFSET_LSB Bits [7:0] Bit Name OFFSET_CH3[7:0] Settings Description Channel 3 Offset Calibration Value. Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x3D, Reset: 0x00, Name: CH3_OFFSET_MID Table 98. Bit Descriptions for CH3_OFFSET_MID Bits [7:0] Bit Name OFFSET_CH3[15:8] Settings Description Channel 3 Offset Calibration Value. Address: 0x3E, Reset: 0x00, Name: CH3_OFFSET_MSB Table 99. Bit Descriptions for CH3_OFFSET_MSB Bits 7 [6:0] Bit Name OFFSET_CAL_EN_CH3 OFFSET_CH3[22:16] Settings Description Enables Offset Calibration on Channel 3. Channel 3 Offset Calibration Value. Reset 0x0 0x0 Access R/W R/W Address: 0x3F, Reset: 0x00, Name: MCLK_COUNTER Table 100. Bit Descriptions for MCLK_COUNTER Bits [7:0] Bit Name MCLK_COUNT Settings Description 8-Bit Counter that Increments Once Every 12,000 MCLK Cycles. The counter output is read back, which enables the user to determine the frequency of the external clock. The MCLK counter starts when MCLK_CNT_EN is set, and ends when it reaches 255 MCLK cycles. Reset 0x0 Access R Address: 0x40, Reset: 0x00, Name: DIG_FILTER_OFUF Table 101. Bit Descriptions for DIG_FILTER_OFUF Bits [7:4] 3 Bit Name Reserved ERR_OFUF_CH3 Settings 0 1 2 ERR_OFUF_CH2 0 1 1 ERR_OFUF_CH1 0 1 0 ERR_OFUF_CH0 0 1 Description Reserved. Channel 3 Digital Filter Overflow or Underflow Error. No overflow or underflow error. Overflow or underflow error. Channel 2 Digital Filter Overflow or Underflow Error. No overflow or underflow error. Overflow or underflow error. Channel 1 Digital Filter Overflow or Underflow Error. No overflow or underflow error. Overflow or underflow error. Channel 0 Digital Filter Overflow or Underflow Error. No overflow or underflow error. Overflow or underflow error. Rev. 0 | Page 83 of 86 Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R AD7134 Data Sheet Address: 0x41, Reset: 0x00, Name: DIG_FILTER_SETTLED Table 102. Bit Descriptions for DIG_FILTER_SETTLED Bits [7:4] 3 Bit Name Reserved CH3_SETTLED Settings 0 1 2 CH2_SETTLED 0 1 1 CH1_SETTLED 0 1 0 CH0_SETTLED 0 1 Description Reserved. Channel 3 Digital Filter Status. Digital filter not settled. Digital filter is settled. Channel 2 Digital Filter Status. Digital filter not settled. Digital filter is settled. Channel 1 Digital Filter Status. Digital filter not settled. Digital filter is settled. Channel 0 Digital Filter Status. Digital filter not settled. Digital filter is settled. Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R Address: 0x42, Reset: 0x00, Name: INTERNAL_ERROR Table 103. Bit Descriptions for INTERNAL_ERROR Bits [7:4] 3 Bit Name Reserved ERR_DCLK Settings 0 1 2 ERR_FUSE_CRC 0 1 1 ERR_ASRC 0 1 0 ERR_MM_CRC 0 1 Description Reserved. DCLK Error Flag Indicates that the DCLK Programmed or Provided is Low to Clock Out the Complete Frame. No DCLK error. DCLK error. Fuse Error Flag Indicates a CRC Error in Fuse Contents. When enabled, a CRC calculation is performed on the fuse contents. If the contents have changed, this bit is set. No fuse CRC error. Fuse CRC error. ASRC Error Flag Indicates if ODR is Out of Range of the Filter Selected. No ASRC error. ASRC error. Memory Map Error Flag Indicates CRC Error in On-Chip Register Contents. When enabled, a CRC calculation is performed on the memory map each time the registers are written to. Following this calculation, periodic CRC checks are performed on the on-chip registers. If the register contents have changed, an error is flagged. No memory map error. Memory map error. Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R Reset 0x0 0x0 Access R R 0x0 R 0x0 R Address: 0x47, Reset: 0x00, Name: SPI Error Table 104. Bit Descriptions for SPI Error Bits [7:4] 3 Bit Name Reserved ERR_SPI_CRC Settings 0 1 2 ERR_SPI_SCLK_CNT 0 1 1 ERR_SPI_WRITE 0 1 Description Reserved. SPI CRC Error Flag Indicates CRC Error During SPI Communications. This error reporting is enabled using the ERR_SPI_CRC_EN bit in the diagnostic control register. No CRC error. CRC error detected. SCLK counter error flag indicates that the number of SCLK cycles during SPI communication is not a multiple of eight. No error. SCLK counter error detected. SPI Write Error Flag Indicates Error During SPI Write Operation. No error. SPI write error. Rev. 0 | Page 84 of 86 Data Sheet Bits 0 Bit Name ERR_SPI_READ AD7134 Settings 0 1 Description SPI Read Error Flag Indicates Error During SPI Read Operation. No error. Read error detected. Reset 0x0 Access R Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R Address: 0x48, Reset: 0x00, Name: AIN_OR_ERROR Table 105. Bit Descriptions for AIN_OR_ERROR Bits [7:4] 3 Bit Name Reserved ERR_OR_AIN3 Settings 0 1 2 ERR_OR_AIN2 0 1 1 ERR_OR_AIN1 0 1 0 ERR_OR_AIN0 0 1 Description Reserved. Input Overvoltage Flag on Channel 3. When enabled, this bit detects the input voltage exceeding the absolute value of VREF. No overvoltage input detected. Overvoltage input detected. Input Overvoltage Flag on Channel 2. When enabled, this bit detects the input voltage exceeding the absolute value of VREF. No overvoltage input detected. Overvoltage input detected. Input Overvoltage Flag on Channel 1. When enabled, this bit detects the input voltage exceeding the absolute value of VREF. No overvoltage input detected. Overvoltage input detected. Input Overvoltage Flag on Channel 0. When enabled, this bit detects the input voltage exceeding the absolute value of VREF. No overvoltage input detected. Overvoltage input detected. Rev. 0 | Page 85 of 86 AD7134 Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR AREA DETAIL A (JEDEC 95) 8.10 8.00 SQ 7.90 0.30 0.25 0.18 P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 56 43 1 42 0.50 BSC *6.70 EXPOSED PAD 6.60 SQ 6.50 29 0.80 0.75 0.70 END VIEW PKG-004323 SEATING PLANE 0.45 0.40 0.35 14 15 28 BOTTOM VIE W 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.20 MIN 6.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WLLD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION 10-24-2018-B TOP VIEW Figure 127. 56-Lead Lead Frame Chip Scale Package [LFCSP] 8 mm × 8 mm Body and 0.75 mm Package Height (CP-56-9) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7134BCPZ AD7134BCPZ-RL7 EVAL-AD7134FMCZ EVAL-SDP-CH1Z 1 Temperature Range 0°C to 85°C 0°C to 85°C Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP] 56-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Controller Board Z = RoHS Compliant Part. ©2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D22652-4/20(0) Rev. 0 | Page 86 of 86 Package Option CP-56-9 CP-56-9

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