AD7142

Programmable Capacitance-to-Digital Converter with Environmental Compensation AD7142 FEATURES Programmable capacitance-to-digital converter 36 ms update rate (@ maximum sequence length) Better than 1 fF resolution 14 capacitance sensor input channels No external RC tuning components required Automatic conversion sequencer On-chip automatic calibration logic Automatic compensation for environmental changes Automatic adaptive threshold and sensitivity levels On-chip RAM to store calibration data SPI®-compatible serial interface (AD7142) I2C®-compatible serial interface (AD7142-1) Separate VDRIVE level for serial interface Interrupt output and GPIO 32-lead, 5 mm x 5 mm LFCSP_VQ 2.6 V to 3.6 V supply voltage Low operating current Full power mode: less than 1 mA Low power mode: 50 μA FUNCTIONAL BLOCK DIAGRAM VREF– VREF+ 29 28 TEST 27 CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 CIN11 CIN12 CIN13 30 31 32 1 2 3 POWER-ON RESET LOGIC 13 14 AVCC AGND SWITCH MATRIX 4 5 6 7 8 9 10 11 16-BIT Σ-Δ CDC CALIBRATION ENGINE 17 DVCC DGND1 DGND2 CALIBRATION RAM CONTROL AND DATA REGISTERS 18 19 CSHIELD SRC SRC 12 15 16 250kHz EXCITATION SOURCE VDRIVE 20 SERIAL INTERFACE AND CONTROL LOGIC INTERRUPT AND GPIO LOGIC 26 GPIO APPLICATIONS Personal music and multimedia players Cell phones Digital still cameras Smart hand-held devices Television, A/V, and remote controls Gaming consoles 21 22 23 24 25 SDO/ SDA SDI/ SCLK CS/ ADD0 ADD1 INT Figure 1. GENERAL DESCRIPTION The AD7142 and AD7142-1 are integrated capacitance-todigital converters (CDCs) with on-chip environmental calibration for use in systems requiring a novel user input method. The AD7142 and AD7142-1 can interface to external capacitance sensors implementing functions such as capacitive buttons, scroll bars, or wheels. The CDC has 14 inputs channeled through a switch matrix to a 16-bit, 250 kHz sigma-delta (∑-Δ) capacitance-to-digital converter. The CDC is capable of sensing changes in the capacitance of the external sensors and uses this information to register a sensor activation. The external sensors can be arranged as a series of buttons, as a scroll bar or wheel, or as a combination of sensor types. By programming the registers, the user has full control over the CDC setup. High resolution sensors require minor software to run on the host processor. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. The AD7142 and AD7142-1 have on-chip calibration logic to account for changes in the ambient environment. The calibration sequence is performed automatically and at continuous intervals, while the sensors are not touched. This ensures that there are no false or nonregistering touches on the external sensors due to a changing environment. The AD7142 has an SPI-compatible serial interface, and the AD7142-1 has an I2C-compatible serial interface. Both parts have an interrupt output, as well as a general-purpose input/ output (GPIO). The AD7142 and AD7142-1 are available in a 32-lead, 5 mm × 5 mm LFCSP_VQ and operate from a 2.6 V to 3.6 V supply. The operating current consumption is less than 1 mA, falling to 50 μA in low power mode (conversion interval of 400 ms). One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. 05702-001 AD7142 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 SPI Timing Specifications (AD7142)......................................... 5 I2C Timing Specifications (AD7142-1) ..................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 11 Capacitance Sensing Theory..................................................... 11 Operating Modes........................................................................ 12 Capacitance Sensor Input Configuration.................................... 13 CIN Input Multiplexer Setup .................................................... 13 Capacitiance-to-Digital Converter............................................... 14 Oversampling the CDC Output ............................................... 14 Capacitance Sensor Offset Control.......................................... 14 Conversion Sequencer ............................................................... 14 CDC Conversion Sequence Time ............................................ 15 CDC Conversion Results........................................................... 16 Noncontact Proximity Detection ................................................. 17 Recalibration ............................................................................... 17 Proximity Sensitivity .................................................................. 17 FIFO Control .............................................................................. 20 Environmental Calibration ........................................................... 22 Capacitance Sensor Behavior Without Calibration............... 22 Capacitance Sensor Behavior with Calibration...................... 23 Adaptive Threshold and Sensitivity ............................................. 24 Interrupt Output............................................................................. 25 CDC Conversion Complete Interrupt..................................... 25 Sensor Touch Interrupt.............................................................. 25 GPIO INT Output Control ....................................................... 27 Outputs ............................................................................................ 29 Excitation Source........................................................................ 29 CSHIELD Output ............................................................................. 29 GPIO ............................................................................................ 29 Using the GPIO to turn on/off an LED................................... 29 Serial Interface ................................................................................ 30 SPI Interface ................................................................................ 30 I2C Compatible Interface........................................................... 32 VDRIVE Input ................................................................................. 34 PCB Design Guidelines ................................................................. 35 Capacitive Sensor Board Mechanical Specifications ............. 35 Chip Scale Packages ................................................................... 35 Power-Up Sequence ....................................................................... 36 Typical Application Circuits ......................................................... 37 Register Map ................................................................................... 38 Detailed Register Descriptions ..................................................... 39 Bank 1 Registers ......................................................................... 39 Bank 2 Registers ......................................................................... 48 Bank 3 Registers ......................................................................... 54 Outline Dimensions ....................................................................... 66 Ordering Guide .......................................................................... 66 REVISION HISTORY 6/06—Revision 0: Initial Version Rev. 0 | Page 2 of 68 AD7142 SPECIFICATIONS AVCC, DVCC = 2.6 V to 3.6 V, TA = −40oC to +85°C, unless otherwise noted. Table 1. Parameter CAPACITANCE-TO-DIGITAL CONVERTER Update Rate Resolution CIN Input Range1 No Missing Codes CIN Input Leakage Total Unadjusted Error Output Noise (Peak-to-Peak) Output Noise (RMS) Parasitic Capacitance CBULK Offset Range 1 CBULK Offset Resolution Low Power Mode Delay Accuracy EXCITATION SOURCE Frequency Output Voltage Short-Circuit Source Current Short-Circuit Sink Current Maximum Output Load CSHIELD Output Drive CSHIELD Bias Level LOGIC INPUTS (SDI, SCLK, CS, SDA, GPI TEST) VIH Input High Voltage VIL Input Low Voltage IIH Input High Voltage IIL Input Low Voltage Hysteresis OPEN-DRAIN OUTPUTS (SCLK, SDA, INT) VOL Output Low Voltage IOH Output High Leakage Current LOGIC OUTPUTS (SDO, GPO) VOL Output Low Voltage VOH Output High Voltage SDO Floating State Leakage Current GPO Floating State Leakage Current ±20 156.25 4 240 250 20 50 250 10 AVCC/2 0.7 x VDRIVE 0.4 −1 1 150 0.4 ±1 0.4 VDRIVE − 0.6 ±1 −5 +2 260 AVCC Min 35.45 Typ 36.86 16 ±2 16 25 ±20 7 3 0.8 0.5 40 Max 38.4 Unit ms Bit pF Bit nA % Codes Codes Codes Codes pF pF fF % kHz V mA mA pF μA V V V μA μA mV V μA V V μA μA Test Conditions/Comments 12 conversion stages in sequencer, decimation = 256 Guaranteed by design, but not production tested Decimation rate = 128 Decimation rate = 256 Decimation rate = 128 Decimation rate = 256 Parasitic capacitance to ground, per CIN input guaranteed by characterization % of 200 ms, 400 ms, 600 ms, or 800 ms Capacitance load on source to ground VIN = VDRIVE VIN = DGND +0.1 ISINK = −1 mA VOUT = VDRIVE ISINK = 1 mA, VDRIVE = 1.65 V to 3.6 V ISOURCE = 1 mA, VDRIVE = 1.65 V to 3.6 V Pin three-state, leakage measured to GND and DVCC Pin three-state, leakage measured to GND and DVCC Rev. 0 | Page 3 of 68 AD7142 Parameter POWER AVCC, DVCC VDRIVE ICC Min 2.6 1.65 Typ 3.3 0.9 16 2.25 1 Max 3.6 3.6 1 20 33 4.5 18 Unit V V mA μA μA μA μA Test Conditions/Comments Serial interface operating voltage In full power mode Low power mode, converter idle, TA = 25°C Low power mode, converter idle Full shutdown, TA = 25°C Full shutdown CIN and CBULK are defined as follows: CIN PLASTIC OVERLAY SENSOR BOARD CAPACITIVE SENSOR CBULK 05702-054 Table 2. Typical Average Current in Low Power Mode, AVCC, DVCC = 3.6 V, T= 25°C, Load of 50 pF on SRC Pin, No Load on SRC Number of Conversion Stages, Current Values Expressed in μA Low Power Mode Delay 200 ms 400 ms 600 ms 800 ms Decimation Rate = 128 256 128 256 128 256 128 256 1 26.4 35.6 21.3 26 19.6 22.7 18.7 21.1 2 33.3 49.1 24.8 32.9 21.9 27.4 20.5 24.6 3 40.1 62.2 28.3 39.7 24.3 32 22.2 28.1 4 46.9 74.9 31.7 46.5 26.6 36.6 24 31.5 5 53.5 87.3 35.2 53.1 28.9 41.1 25.7 35 6 60 99.3 38.6 59.6 31.2 45.6 27.5 38.4 7 66.5 111 42 66.1 33.5 50 29.2 41.8 8 72.8 122.3 45.4 72.4 35.8 54.4 31 45.2 9 79.1 133.4 48.7 78.7 38.1 58.8 32.7 48.5 10 85.2 144.2 52 84.9 40.4 63.1 34.4 51.8 11 91.3 154.7 55.3 91 42.6 67.4 36.1 55.1 12 97.3 164.9 58.6 97 44.8 71.6 37.8 58.4 Table 3. Maximum Average Current in Low Power Mode, AVCC, DVCC = 3.6 V, Load of 50 pF on SRC Pin, No Load on SRC Number of Conversion Stages, Current Values Expressed in μA Low Power Mode Delay 200 ms 400 ms 600 ms 800 ms Decimation Rate = 128 256 128 256 128 256 128 256 1 45.4 56.2 39.5 45 37.5 41.2 36.5 39.3 2 53.6 72 43.6 53.1 40.3 46.7 38.6 43.4 3 61.5 87.2 47.7 61.1 43 52.1 40.7 47.5 4 69.4 102 51.8 68.9 45.8 57.4 42.7 51.5 5 77.1 116.3 55.8 76.7 48.5 62.7 44.8 55.6 6 84.7 130.2 59.8 84.3 51.2 67.9 46.8 59.5 7 92.2 143.7 63.7 91.8 53.9 73.1 48.8 63.5 8 99.6 156.8 67.6 99.1 56.5 78.2 50.9 67.4 9 106.8 169.5 71.5 106.4 59.2 83.3 52.9 71.3 10 113.9 181.8 75.4 113.6 61.8 88.3 54.9 75.2 11 121 193.8 79.2 120.6 64.5 93.3 56.9 79 12 127.9 205.5 83 127.5 67.1 98.2 58.9 82.8 Rev. 0 | Page 4 of 68 AD7142 SPI TIMING SPECIFICATIONS (AD7142) TA = −40°C to +85°C; VDRIVE = 1.65 V to 3.6 V; AVCC, DVCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. Table 4. SPI Timing Specifications Parameter fSCLK t1 t2 t3 t4 t5 t6 t7 t8 Limit at TMIN, TMAX 5 5 20 20 15 15 20 16 15 Unit MHz max ns min ns min ns min ns min ns min ns max ns max ns min Description CS falling edge to first SCLK falling edge SCLK high pulse width SCLK low pulse width SDI setup time SDI hold time SDO access time after SCLK falling edge CS rising edge to SDO high impedance SCLK rising edge to CS high CS t1 t2 1 2 t3 3 15 16 1 2 15 t8 16 SCLK t4 SDI t5 LSB MSB t6 SDO MSB LSB t7 05702-002 Figure 2. SPI Detailed Timing Diagram Rev. 0 | Page 5 of 68 AD7142 I2C TIMING SPECIFICATIONS (AD7142-1) TA = −40°C to +85°C; VDRIVE = 1.65 V to 3.6 V; AVCC, DVCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals timed from a voltage level of 1.6 V. Table 5. I2C Timing Specifications 1 Parameter fSCLK t1 t2 t3 t4 t5 t6 t7 t8 tR tF 1 Limit 400 0.6 1.3 0.6 100 300 0.6 0.6 1.3 300 300 Unit kHz max μs min μs min μs min ns min ns min μs min μs min μs min ns max ns max Description Start condition hold time, tHD; STA Clock low period, tLOW Clock high period, tHIGH Data setup time, tSU; DAT Data hold time, tHD; DAT Stop condition setup time, tSU; STO Start condition setup time, tSU; STA Bus free time between stop and start conditions, tBUF Clock/data rise time Clock/data fall time Guaranteed by design, not production tested. 200µA IOL TO OUTPUT PIN 1.6V CL 50pF 200µA IOH 05702-004 Figure 3. Load Circuit for Digital Output Timing Specifications Rev. 0 | Page 6 of 68 AD7142 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVCC to AGND, DVCC to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Input Current to Any Pin Except Supplies1 ESD Rating (Human Body Model) Operating Temperature Range Storage Temperature Range Junction Temperature LFCSP_VQ Power Dissipation θJA Thermal Impedance IR Reflow Peak Temperature Lead Temperature (Soldering 10 sec) 1 Rating −0.3 V to +3.6 V −0.3 V to AVCC + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VDRIVE + 0.3 V 10 mA 2.5 kV −40°C to +150°C −65°C to +150°C 150°C 450 mW 135.7°C/W 260°C (±0.5°C) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 68 AD7142 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS CIN2 CIN1 CIN0 VREF– VREF+ TEST GPIO INT 32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 25 CIN2 CIN1 CIN0 VREF– VREF+ TEST GPIO INT CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 1 2 3 4 5 6 7 8 PIN 1 INDICATOR TOP VIEW AD7142 24 23 22 21 20 19 18 17 CS SCLK SDI SDO VDRIVE DGND2 DGND1 DVCC CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 1 2 3 4 5 6 7 8 PIN 1 INDICATOR AD7142-1 TOP VIEW 24 23 22 21 20 19 18 17 ADD1 SCLK ADD0 SDA VDRIVE DGND2 DGND1 DVCC CIN11 9 CIN12 10 CIN13 11 CSHIELD 12 AVCC 13 AGND 14 SRC 15 SRC 16 CIN11 9 CIN12 10 CIN13 11 CSHIELD 12 AVCC 13 AGND 14 SRC 15 SRC 16 Figure 4. AD7142 Pin Configuration 05702-005 Figure 5. AD7142-1 Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mnemonic CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 CIN11 CIN12 CIN13 CSHIELD AVCC AGND SRC SRC DVCC DGND1 DGND2 VDRIVE SDO SDA SDI ADD0 SCLK CS ADD1 INT GPIO TEST VREF+ VREF− CIN0 CIN1 CIN2 Description Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. CDC Shield Potential Output. Requires 10 nF capacitor to ground. Connect to external shield. CDC Supply Voltage. Analog Ground Reference Point for All CDC Circuitry. Tie to analog ground plane. CDC Excitation Source Output. Inverted Excitation Source Output. Digital Core Supply Voltage. Digital Ground. Digital Ground. Serial Interface Operating Voltage Supply. AD7142 SPI Serial Data Output. AD7142-1 I2C Serial Data Input/Output. SDA requires pull-up resistor. AD7142 SPI Serial Data Input. AD7142-1 I2C Address Bit 0. Clock Input for Serial Interface. AD7142 SPI Chip Select Signal. AD7142-1 I2C Address Bit 1. General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor. Programmable GPIO. Factory Test Pin. Tie to ground. CDC Positive Reference Input. Normally tied to analog power. CDC Negative Reference Input. Tie to analog ground. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Rev. 0 | Page 8 of 68 05702-044 AD7142 TYPICAL PERFORMANCE CHARACTERISTICS 1000 980 DEVICE 1 960 SHUTDOWN ICC (µA) 2.45 2.30 2.15 2.00 DEVICE 1 1.85 1.70 1.55 1.40 2.7 DEVICE 3 DEVICE 2 940 DEVICE 3 DEVICE 2 ICC (µA) 920 900 880 860 840 820 2.7 05702-053 2.8 2.9 3.0 3.1 3.2 VCC (V) 3.3 3.4 3.5 3.6 2.8 2.9 3.0 3.1 3.2 VCC (V) 3.3 3.4 3.5 3.6 Figure 6. Supply Current vs. Supply Voltage (VCC = AVCC + DVCC, ICC = AICC + DICC) 180 160 140 120 100 80 LP_CONV_DELAY = 600ms 05702-051 Figure 9. Shutdown Supply Current vs. Supply Voltage (VCC = AVCC + DVCC, ICC = AICC + DICC) 1.10 LP_CONV_DELAY = 200ms 1.05 DEVICE 1 1.00 ICC (mA) ICC (µA) 0.95 DEVICE 3 0.90 DEVICE 2 LP_CONV_DELAY = 400ms LP_CONV_DELAY = 800ms 40 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 0.80 0 50 100 150 200 250 300 350 400 450 500 VCC (V) CAPACITANCE LOAD ON SOURCE (pF) Figure 7. Low Power Supply Current vs. Supply Voltage, Decimation Rate = 256 (VCC = AVCC + DVCC, ICC = AICC + DICC) 120 Figure 10. Supply Current vs. Capacitive Load on SRC (ICC = AICC + DICC) 16015 16010 16005 DEVICE 2 16000 15995 DEVICE 3 15990 15985 15980 DEVICE 1 100 LP_CONV_DELAY = 200ms ICC (µA) 80 60 LP_CONV_DELAY = 400ms 40 LP_CONV_DELAY = 800ms 20 2.7 2.8 2.9 3.0 3.10 3.2 3.3 3.4 3.5 05702-050 0 50 100 150 200 250 300 350 400 450 500 CAPACITANCE LOAD ON SOURCE (pF) 3.6 VCC (V) Figure 11. Output Code vs. Capacitive Load on SRC Figure 8. Low Power Supply Current vs. Supply Voltage Decimation Rate = 128 (VCC = AVCC + DVCC, ICC = AICC + DICC) Rev. 0 | Page 9 of 68 05702-048 LP_CONV_DELAY = 600ms CDC OUTPUT CODE 05702-049 60 0.85 05702-052 AD7142 960 940 3.6V 920 SUPPLY CURRENT (µA) 2.5 100mV 200mV CDC PEAK-TO-PEAK NOISE (Codes) 300mV 400mV 500mV 2.0 900 3.3V 880 860 840 820 05702-056 1.5 1.0 0.5 05702-059 800 780 –40 –20 0 20 40 60 2.7V 80 100 120 0 10 1k 100k FREQUENCY (Hz) 10M TEMPERATURE (°C) Figure 12. Supply Current vs. Temperature (Supply Current = AICC + DICC) 12 180 160 140 120 100 80 60 40 20 0 100 Figure 14. Power Supply Sine Wave Rejection 10 SUPPLY CURRENT (µA) 8 CDC PEAK-TO-PEAK NOISE (Codes) 6 3.6V 4 3.3V 300mV 200mV 100mV 05702-060 2 2.7V 0 –40 –20 0 20 40 60 80 100 05702-057 50mV 25mV 1k 10k 100k 1M 120 10M TEMPERATURE (°C) SQUARE WAVE FREQUENCY (Hz) Figure 13. Shutdown Supply Current vs. Temperature (Supply Current = AICC + DICC) Figure 15. Power Supply Square Wave Rejection Rev. 0 | Page 10 of 68 AD7142 THEORY OF OPERATION The AD7142 and AD7142-1 are capacitance-to-digital converters (CDCs) with on-chip environmental compensation, intended for use in portable systems requiring high resolution user input. The internal circuitry consists of a 16-bit, ∑-Δ converter that converts a capacitive input signal into a digital value. There are 14 input pins on the AD7142 and AD7142-1, CIN0 to CIN13. A switch matrix routes the input signals to the CDC. The result of each capacitance-to-digital conversion is stored in on-chip registers. The host subsequently reads the results over the serial interface. The AD7142 contains an SPI interface and the AD7142-1 has an I2C interface ensuring that the parts are compatible with a wide range of host processors. Because the AD7142 and AD7142-1 are identical parts, with the exception of the serial interface, AD7142 refers to both the AD7142 and AD7142-1 throughout this data sheet. The AD7142 interfaces with up to 14 external capacitance sensors. These sensors can be arranged as buttons, scroll bars, wheels, or as a combination of sensor types. The external sensors consist of electrodes on a 2- or 4-layer PCB that interfaces directly to the AD7142. The AD7142 can be set up to implement any set of input sensors by programming the on-chip registers. The registers can also be programmed to control features such as averaging, offsets, and gains for each of the external sensors. There is a sequencer on-chip to control how each of the capacitance inputs is polled. Rx The AD7142 has an interrupt output, INT, to indicate when new data has been placed into the registers. INT is used to interrupt the host on sensor activation. The AD7142 operates from a 2.6 V to 3.6 V supply, and is available in a 32-lead, 5 mm × 5 mm LFCSP_VQ. CAPACITANCE SENSING THEORY The AD7142 uses a method of sensing capacitance known as the shunt method. Using this method, an excitation source is connected to a transmitter generating an electric field to a receiver. The field lines measured at the receiver are translated into the digital domain by a ∑-Δ converter. When a finger, or other grounded object, interferes with the electric field, some of the field lines are shunted to ground and do not reach the receiver (see Figure 16). Therefore, the total capacitance measured at the receiver decreases when an object comes close to the induced field. PLASTIC COVER PCB LAYER 1 PCB LAYER 2 16-BIT DATA Tx The AD7142 has on-chip digital logic and 528 words of RAM that are used for environmental compensation. The effects of humidity, temperature, and other environmental factors can effect the operation of capacitance sensors. Transparent to the user, the AD7142 performs continuous calibration to compensate for these effects, allowing the AD7142 to give error-free results at all times. The AD7142 requires some minor companion software that runs on the host or other microcontroller to implement high resolution sensor functions such as a scroll bar or wheel. However, no companion software is required to implement buttons, including 8-way button functionality. Button sensors are implemented completely in digital logic on-chip. The AD7142 can be programmed to operate in either full power mode, or in low power automatic wake-up mode. The automatic wake-up mode is particularly suited for portable devices that require low power operation giving the user significant power savings coupled with full functionality. Σ-Δ ADC EXCITATION SIGNAL 240kHz 05702-007 AD7142 Figure 16. Sensing Capacitance Method In practice, the excitation source and ∑-Δ ADC are implemented on the AD7142, while the transmitter and receiver are constructed on a PCB that makes up the external sensor. Registering a Sensor Activation When a sensor is approached, the total capacitance associated with that sensor, measured by the AD7142, changes. When the capacitance changes to such an extent that a set threshold is exceeded, the AD7142 registers this as a sensor touch. Preprogrammed threshold levels are used to determine if a change in capacitance is due to a button being activated. If the capacitance exceeds one of the threshold limits, the AD7142 registers this as a true button activation. The same thresholds principle is used to determine if other types of sensors, such as sliders or scroll wheels, are activated. Rev. 0 | Page 11 of 68 AD7142 Complete Solution for Capacitance Sensing Analog Devices provides a complete solution for capacitance sensing. The two main elements to the solution are the sensor PCB and the AD7142. If the application requires high resolution sensors such as scroll bars or wheels, software is required that runs on the host processor. (No software is required for button sensors.) The memory requirements for the host depend on the sensor, and are typically 10 kB of code and 600 bytes of data memory. SENSOR PCB Full Power Mode In full power mode, all sections of the AD7142 remain fully powered at all times. While a sensor is being touched, the AD7142 processes the sensor data. If no sensor is touched, the AD7142 measures the ambient capacitance level and uses this data for the on-chip compensation routines. In full power mode, the AD7142 converts at a constant rate. See the CDC Conversion Sequence Time section for more information. Low Power Mode When in low power mode, the AD7142 POWER_MODE bits are set to 10 upon device initialization. If the external sensors are not touched, the AD7142 reduces its conversion frequency, thereby greatly reducing its power consumption. The part remains in a low power state while the sensors are not touched. Every 400 ms, the AD7142 performs a conversion and uses this data to update the compensation logic. When an external sensor is touched, the AD7142 begins a conversion sequence every 40 ms to read back data from the sensors. In low power mode, the total current consumption of the AD7142 is an average of the current used during a conversion, and the current used while the AD7142 is waiting for the next conversion to begin. For example, when the low power mode conversion interval is 400 ms, the AD7142 typically uses 0.9 mA current for 40 ms, and 15 μA for 400 ms of the conversion interval. (Note that these conversion timings can be altered through the register settings. See the CDC Conversion Sequence Time section for more information.) AD7142 SETUP AND INITIALIZATION POWER_MODE = 10 AD7142 SPI OR I2C Figure 17. Three Part Capacitance Sensing Solution Analog Devices supplies the sensor PCB design to the customer based on the customer’s specifications, and supplies any necessary software on an open-source basis. Standard sensor designs are also available as PCB library components. OPERATING MODES The AD7142 has three operating modes. Full power mode, where the device is always fully powered, is suited for applications where power is not a concern (for example, game consoles that have an ac power supply). Low power mode, where the part automatically powers down, is tailored to give significant power savings over full power mode, and is suited for mobile applications where power must be conserved. In shutdown mode, the part shuts down completely. The POWER_MODE bits (Bit 0 and Bit 1) of the control register set the operating mode on the AD7142. The control register is at Address 0x000. Table 8 shows the POWER_MODE settings for each operating mode. To put the AD7142 into shutdown mode, set the POWER_MODE bits to either 01 or 11. Table 8. POWER_MODE Settings POWER_MODE Bits 00 01 10 11 Operating Mode Full power mode Full shutdown mode Low power mode Full shutdown mode 05702-008 HOST PROCESSOR 1 MIPS 10kB ROM 600 BYTES RAM NO ANY SENSOR TOUCHED? YES CONVERSION SEQUENCE EVERY LP_CONV_DELAY ms UPDATE COMPENSATION LOGIC DATA PATH CONVERSION SEQUENCE EVERY 36ms FOR SENSOR READBACK YES ANY SENSOR TOUCHED? NO 05702-009 PROXIMITY TIMER COUNT DOWN TIMEOUT Figure 18. Low Power Mode Operation The power-on default setting of the POWER_MODE bits is 00, full power mode. Rev. 0 | Page 12 of 68 AD7142 CAPACITANCE SENSOR INPUT CONFIGURATION Each stage of the AD7142 capacitance sensors can be uniquely configured by using the registers in Table 45 and Table 46. These registers are used to configure input pin connection setups, sensor offsets, sensor sensitivities, and sensor limits for each stage. Each sensor can be individually optimized. For example, a button sensor connected to STAGE0 can require a different sensitivity and offset values than a button with a different function that is connected to a different stage. The AD7142 has an on-chip multiplexer to route the input signals from each pin to the input of the converter. Each input pin can be tied to either the negative or the positive input of the CDC, or it can be left floating. Each input can also be internally connected to the CSHIELD signal to help prevent cross coupling. If an input is not used, always connect it to CSHIELD. For each input pin, CIN0 to CIN13, the multiplexer settings can be set on a per sequencer stage basis. For example, CIN0 is connected to the negative CDC input for conversion STAGE1, left floating for sequencer STAGE1, and so on for all twelve conversion stages. Two bits in each register control the mux setting for the input pin. CIN INPUT MULTIPLEXER SETUP The CIN_CONNECTION_SETUP registers in Table 45 list the different options that are provided for connecting the sensor input pin to the CDC converter. CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 CIN11 CIN12 CIN13 CIN_CONNECTION _SETUP BITS 00 01 10 11 CIN SETTING CINX FLOATING CINX CONNECTED TO NEGATIVE CDC INPUT CINX CONNECTED TO POSITIVE CDC INPUT CINX CONNECTED TO CSHIELD + – CDC 05702-010 Figure 19. Input Mux Configuration Options Rev. 0 | Page 13 of 68 AD7142 CAPACITIANCE-TO-DIGITAL CONVERTER The capacitance-to-digital converter on the AD7142 has a Σ-Δ architecture with 16-bit resolution. There are 14 possible inputs to the CDC that are connected to the input of the converter through a switch matrix. The sampling frequency of the CDC is 250 kHz. This process is only required once during the initial capacitance sensor characterization. +DAC (20pF RANGE) 7 POS_AFE_OFFSET REGISTER OVERSAMPLING THE CDC OUTPUT The decimation rate, or oversampling ratio, is determined by Bits[9:8] of the control register, as listed in Table 9. Table 9. CDC Decimation Rate Decimation Bit Value 00 01 101 111 1 POS_AFE_OFFSET_SWAP REGISTER CIN + 16-BIT _ CDC 16 Decimation Rate 256 128 – – CDC Output Rate Per Stage 1.536 ms 3.072 ms – – SENSOR NEG_AFE_OFFSET_SWAP REGISTER EXT –DAC (20pF RANGE) CIN_CONNECTION_SETUP REGISTER 7 NEG_AFE_OFFSET REGISTER 05702-011 Do not use this setting. The decimation process on the AD7142 is an averaging process where a number of samples are taken and the averaged result is output. Due to the architecture of the digital filter employed, the amount of samples taken (per stage) is equal to 3× the decimation rate. So 3 × 256 or 3 × 128 samples are averaged to obtain each stage result. The decimation process reduces the amount of noise present in the final CDC result. However, the higher the decimation rate, the lower the output rate per stage, thus, a trade-off is possible between a noise free signal and speed of sampling. Figure 21. Analog Front End Offset Control CONVERSION SEQUENCER The AD7142 has an on-chip sequencer to implement conversion control for the input channels. Up to 12 conversion stages can be performed in sequence. By using the Bank 2 registers, each stage can be uniquely configured to support multiple capacitance sensor interface requirements. For example, a slider sensor can be assigned to STAGE1 with a button sensor assigned to STAGE2. The AD7142 on-chip sequence controller provides conversion control beginning with STAGE0. Figure 22 shows a block diagram of the CDC conversion stages and CIN inputs. A conversion sequence is defined as a sequence of CDC conversions starting at STAGE0 and ending at the stage determined by the value programmed in the SEQUENCE_STAGE_NUM register. Depending on the number and type of capacitance sensors that are used, not all conversion stages are required. Use the SEQUENCE_STAGE_NUM register to set the number of conversions in one sequence, depending on the sensor interface requirements. For example, this register would be set to 5 if the CIN inputs were mapped to only six stages. In addition, set the STAGE_CAL_EN registers according to the number of stages that are used. CAPACITANCE SENSOR OFFSET CONTROL There are two programmable DACs on board the AD7142 to null any capacitance sensor offsets. These offsets are associated with printed circuit board capacitance or capacitance due to any other source, such as connectors. In Figure 20, CIN is the capacitance of the input sensors, while CBULK is the capacitance between layers of the sensor PCB. CBULK can be offset using the on-board DACs. PLASTIC OVERLAY SENSOR BOARD CAPACITIVE SENSOR CIN CBULK 05702-054 Figure 20. Capacitances Around the Sensor PCB A simplified block diagram in Figure 21 shows how to apply the STAGE_OFFSET registers to null the offsets. The 7-bit POS_AFE_OFFSET and NEG_AFE_OFFSET registers program the offset DAC to provide 0.16 pF resolution offset adjustment over a range of ±20 pF. Apply the positive and negative offsets to either the positive or the negative CDC input using the NEG_AFE_OFFSET register and POS_AFE_OFFSET register. Rev. 0 | Page 14 of 68 AD7142 STAGE 11 STAGE 10 STAGE 9 STAGE 8 STAGE 7 STAGE 6 STAGE 5 STAGE 4 STAGE 3 STAGE 2 STAGE 1 STAGE 0 CIN0 CIN1 CIN2 SWITCH MATRIX A scroll bar sensor requires eight stages. The result from each stage is used by the host software to determine the user’s position on the scroll bar. The algorithm that performs this process is available from Analog Devices free of charge, on signing a software license. Scroll wheels also require eight stages. The 8-way switch is made from two pairs of differential buttons. It, therefore, requires two conversion stages, one for each of the differential button pairs. It also requires a stage to measure whether the sensor is active. The buttons are orientated so that one pair makes up the top and bottom portions of the 8-way switch; the other pair makes up the left and right portions of the 8-way switch. CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 CIN1 1 CIN12 CIN13 SE Q UE NC E Σ-Δ 16-BIT ADC CDC CONVERSION SEQUENCE TIME The time required for one complete measurement for all 12 stages by the CDC is defined as the CDC conversion sequence time. The SEQUENCE_STAGE_NUM register and DECIMATION register determine the conversion time as listed in Table 10. Table 10. CDC Conversion Times for Full Power Mode Conversion Time (ms) DECIMATION DECIMATION = 128 = 256 1.536 3.072 3.072 6.144 4.608 9.216 6.144 12.288 7.68 15.36 9.216 18.432 10.752 21.504 12.288 24.576 13.824 27.648 15.36 30.72 16.896 33.792 18.432 36.864 CO NV ER SIO N Figure 22. CDC Conversion Stages The number of required conversion stages depends completely on the number of sensors attached to the AD7142. Figure 23 shows how many conversion stages are required for each sensor, and how many inputs each sensor requires to the AD7142. AD7142 SEQUENCER STAGEX + CDC – SCROLL BAR STAGEX + CDC – BUTTONS 05702-012 AD7142 SEQUENCER STAGEX + – CDC STAGEX + CDC – STAGEX + CDC – STAGEX + CDC – SEQUENCE_STAGE_NUM 0 1 2 3 4 5 6 7 8 9 10 11 STAGEX + CDC – AD7142 SEQUENCER 8-WAY SWITCH STAGEX + CDC – STAGEX + CDC – STAGEX + – CDC For example, while operating with a decimation rate of 128, if the SEQUENCE_STAGE_NUM register is set to 5 for the conversion of six stages in a sequence, the conversion sequence time is 9.216 ms. STAGEX + – CDC STAGEX + – STAGEX + CDC – CDC Full Power Mode CDC Conversion Sequence Time The full power mode CDC conversion sequence time for all 12 stages is set by configuring the SEQUENCE_STAGE_NUM register, and DECIMATION register as outlined in Table 10. Figure 24 shows a simplified timing diagram of the full power CDC conversion time. The full power mode CDC conversion time tCONV_FP is set using Table 10. Figure 23. Sequencer Setup for Sensors A button sensor generally requires one sequencer stage; however, it is possible to configure two button sensors to operate differentially. Only one button from the pair can be activated at a time; pressing both buttons together results in neither button being activated. This configuration requires one conversion stage. Rev. 0 | Page 15 of 68 05702-014 AD7142 tCONV_FP CDC CONVERSION CONVERSION SEQUENCE N CONVERSION SEQUENCE N+1 CONVERSION SEQUENCE N+2 05702-015 tCONV_LP CDC CONVERSION CONVERSION SEQUENCE N CONVERSION SEQUENCE N+1 05702-016 NOTES 1. tCONV_FP = VALUE SET FROM TABLE 10. NOTES 1. tCONV_LP = tCONV_FP + LP_CONV_DELAY Figure 24. Full Power Mode CDC Conversion Sequence Time Figure 25. Low Power Mode CDC Conversion Sequence Time Low Power Mode CDC Conversion Sequence Time with Delay The frequency of each CDC conversion while operating in the low power automatic wake up mode is controlled by using the LP_CONV_DELAY register located at Address 0x000[3:2], in addition to the registers listed in Table 10. This feature provides some flexibility for optimizing the conversion time to meet system requirements vs. AD7142 power consumption. For example, maximum power savings is achieved when the LP_CONV_DELAY register is set to 3. With a setting of 3, the AD7142 automatically wakes up, performing a conversion every 800 ms. Table 11. LP_CONV_DELAY Settings LP_CONV_DELAY Bits 00 01 10 11 Delay Between Conversions 200 ms 400 ms 600 ms 800 ms CDC CONVERSION RESULTS Certain high resolution sensors require the host to read back the CDC conversion results for processing. The registers required for host processing are located in the Bank 3 registers. The host processes the data readback from these registers using a software algorithm, to determine position information. In addition to the results registers in the Bank 3 registers, the AD7142 provides the 16-bit CDC output data directly, starting at Address 0x00B of Bank 1. Reading back the CDC 16-bit conversion data register allows for customer-specific application data processing. Figure 25 shows a simplified timing example of the low power CDC conversion time. As shown, the low power CDC conversion time is set by tCONV_FP and the LP_CONV_DELAY register. Rev. 0 | Page 16 of 68 AD7142 NONCONTACT PROXIMITY DETECTION The AD7142 internal signal processing continuously monitors all capacitance sensors for noncontact proximity detection. This feature provides the ability to detect when a user is approaching a sensor, at which time all internal calibration is immediately disabled while the AD7142 is automatically configured to detect a valid contact. The proximity control register bits are described in Table 12. The FP_PROXIMITY_CNT register bits and LP_PROXIMITY_CNT register bits control the length of the calibration disable period after proximity is detected. The calibration is disabled during this time and enabled again at the end of this period provided that the user is no longer approaching, or in contact with, the sensor. Figure 26 and Figure 27 show examples of how these registers are used to set the full and low power mode calibration disable periods. LP_PROXIMITY_RECAL register bits to force a recalibration while operating in the full and low power modes. These figures show a user approaching a sensor followed by the user leaving the sensor while the proximity detection remains active after the user leaves the sensor. This situation could occur if the user interaction creates some moisture on the sensor causing the new sensor value to be different from the expected value. In this case, the internal recalibration is applied to automatically recalibrate the sensor. The force recalibration event takes two interrupt cycles, therefore it should not be set again during this interval. PROXIMITY SENSITIVITY Figure 30 describes the two conditions that set the internal proximity detection signal using Comparator 1 and Comparator 2. Comparator 1 detects when a user is approaching a sensor. The PROXIMITY_DETECTION_RATE register controls the sensitivity of Comparator 1. For example, if PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1 signal is set when the absolute difference between WORD1 and WORD3 exceeds four LSB codes. Comparator 2 detects when a user hovers over a sensor or approaches a sensor very slowly. The PROXIMITY_RECAL_LVL register (Address 0x003) controls the sensitivity of Comparator 2. For example, if PROXIMITY_RECAL_LVL is set to 75, the Proximity 2 signal is set when the absolute difference between the fast filter average value and the ambient value exceeds 75 LSB codes. RECALIBRATION In the event of a very long proximity detection event, such as a user hovering over a sensor for a long period of time, the FP_PROXIMITY_RECAL Bits[9:0] and LP_PROXIMITY_RECAL Bits[15:10] in Register 0x004 can be applied to force a recalibration. This ensures that the ambient values are recalibrated regardless of how long the user hovers over a sensor. A recalibration ensures maximum AD7142 sensor performance. Figure 28 and Figure 29 show examples of using the FP_PROXIMITY_RECAL and Table 12. Proximity Control Registers (See Figure 30) Register FP_PROXIMITY_CNT LP_PROXIMITY_CNT FP_PROXIMITY_RECAL LP_PROXIMITY_RECAL PROXIMITY_RECAL_LVL PROXIMITY_DETECTION_RATE Length 4 bits 4 bits 8 bits 6 bits 8 bits 6 bits Register Address 0x002 0x002 0x004 0x004 0x003 0x003 Description Full power mode proximity control Low power mode proximity control Full power mode proximity recalibration control Low power mode proximity recalibration control Proximity recalibration level Proximity detection rate USER APPROACHES SENSOR HERE USER LEAVES SENSOR AREA HERE tCONV_FP CDC CONVERSION SEQUENCE (INTERNAL) 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 tCALDIS PROXIMITY DETECTION (INTERNAL) CALIBRATION (INTERNAL) CALIBRATION DISABLED CALIBRATION ENABLED Figure 26. Full Power Mode Proximity Detection Example with FP_PROXIMITY = 1 Rev. 0 | Page 17 of 68 05702-017 AD7142 USER APPROACHES SENSOR HERE USER LEAVES SENSOR AREA HERE tCONV_LP CDC CONVERSION SEQUENCE (INTERNAL) 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 tCALDIS PROXIMITY DETECTION (INTERNAL) CALIBRATION (INTERNAL) CALIBRATION DISABLED CALIBRATION ENABLED Figure 27. Low Power Mode Proximity Detection with LP_PROXIMITY = 4 and LP_CONV_DELAY = 0 USER APPROACHES SENSOR HERE USER LEAVES SENSOR AREA HERE CDC CONVERSION VALUES EXCEED PROXIMITY_RECALIBRATION _LVL USER IN CONTACT WITH SENSOR 16 CDC CONVERSION SEQUENCE (INTERNAL) 30 70 tCONV_FP tDISCA L PROXIMITY DETECTION (INTERNAL) CALIBRATION (INTERNAL) CALIBRATION DISABLED RECALIBRATION PERIOD CALIBRATION ENABLED NOTES 1. SEQUENCE CONVERSION TIME tCONV_FP DETERMINED FROM TABLE 10 2. tDISCAL = tCONV_FP × FP_PROXIMITY_CNT 3. tRECAL = tCONV_FP × FP_PROXIMITY_RECAL Figure 28. Full Power Mode Proximity Detection with Forced Recalibration Example with FP_PROXIMITY = 1 and FP_PROXIMITY_RECAL = 40 Rev. 0 | Page 18 of 68 05702-019 RECALIBRATION (INTERNAL) tRECAL 05702-018 NOTES 1. SEQUENCE CONVERSION TIME tCONV_LP = tCONV_FP + LP_CONV_DELAY 2. PROXIMITY IS SET WHEN USER APPROACHES THE SENSOR AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED. 3. tCALDIS = (tCONV_LP × LP_PROXIMITY_CNT × 4) + LP_CONV_DELAY AD7142 USER APPROACHES SENSOR HERE USER LEAVES SENSOR AREA HERE CDC CONVERSION VALUES EXCEED PROXIMITY_RECALIBRATION _LVL USER IN CONTACT WITH SENSOR 16 CDC CONVERSION SEQUENCE (INTERNAL) 30 70 tCONV_LP tDISCAL PROXIMITY DETECTION (INTERNAL) CALIBRATION (INTERNAL) CALIBRATION DISABLED RECALIBRATION PERIOD CALIBRATION ENABLED RECALIBRATION (INTERNAL) tRECAL Figure 29. Low Power Mode Proximity Detection with Forced Recalibration Example with LP_PROXIMITY = 4 and LP_PROXIMITY_RECAL = 10 Rev. 0 | Page 19 of 68 05702-020 NOTES 1. SEQUENCE CONVERSION TIME tCONV_LP = tCONV_HP + LP_CONV_DELAY 2. tDISCAL = tCONV_LP × (16 × LP_PROXIMITY_CNT) 3. tRECAL = tCONV_LP × (LP_PROXIMITY_RECAL × 4) AD7142 FIFO CONTROL As shown in Figure 30, there are a number of FIFOs implemented on the AD7142. These FIFOs are located in Bank 3 of the on-chip memory. The FIFOs are used by the onchip logic to run the environmental calibration, adaptive threshold, and proximity algorithms. Determining the AVG_FP_SKIP and AVG_LP_SKIP value is only required once during the initial setup of the capacitance sensor interface. Recommended values for these settings when using all 12 conversion stages on the AD7142 are: AVG_FP_SKIP = 11 = skip 31 samples AVG_LP_SKIP = 11 = skip 3 samples AVG_FP_SKIP and AVG_LP_SKIP In Register 0x001, Bits[13:12]are the slow FIFO skip control for full power mode, AVG_FP_SKIP. Bits[15:14] in the same register are the slow FIFO skip control for low power mode, AVG_LP_SKIP. These values determine which CDC samples are not used (skipped) in the slow FIFO. Changing theses values slows down or speeds up the rate at which the ambient capacitance value tracks the measured capacitance value read by the converter. The slow FIFO is used by the on-chip logic to track the ambient capacitance value. The slow FIFO expects to receive samples from the converter at a rate of 33 ms to 40 ms. AVG_FP_SKIP and AVG_LP_SKIP are used to normalize the frequency of the samples going into the FIFO, regardless of how many conversion stages are in a sequence. FF_SKIP_CNT In Register 0x02, Bits[3:0] are the fast filter skip control, FF_SKIP_CNT. This value determines which CDC samples are not used (skipped) in the proximity detection fast FIFO. The proximity detection fast FIFO is used by the on-chip logic to determine if proximity is detected . The fast FIFO expects to receive samples from the converter at a set rate. FF_SKIP_CNT is used to normalize the frequency of the samples going into the FIFO, regardless of how many conversion stages are in a sequence. Determining the FF_SKIP_CNT value is required only once during the initial setup of the capacitance sensor interface. Table 13 shows how FF_SKIP_CNT controls the update rate to the fast FIFO. Recommended value for this setting when using all 12 conversion stages on the AD7142 is: FF_SKIP_CNT = 0000 = no samples skipped Table 13. FF_SKIP_CNT Settings FF_SKIP_CNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FAST FIFO Update Rate DECIMATION = 128 1.536 × (SEQUENCE_STAGE_NUM + 1) ms 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 4.608 × (SEQUENCE_STAGE_NUM + 1) ms 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 7.68 × (SEQUENCE_STAGE_NUM + 1) ms 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 10.752 × (SEQUENCE_STAGE_NUM + 1) ms 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 13.824 × (SEQUENCE_STAGE_NUM + 1) ms 15.36 × (SEQUENCE_STAGE_NUM + 1) ms 16.896 × (SEQUENCE_STAGE_NUM + 1) ms 18.432 × (SEQUENCE_STAGE_NUM + 1) ms 19.968 × (SEQUENCE_STAGE_NUM + 1) ms 21.504 × (SEQUENCE_STAGE_NUM + 1) ms 23.04 × (SEQUENCE_STAGE_NUM + 1) ms 24.576 × (SEQUENCE_STAGE_NUM + 1) ms DECIMATION = 256 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 15.36 × (SEQUENCE_STAGE_NUM + 1) ms 18.432 × (SEQUENCE_STAGE_NUM + 1) ms 21.504 × (SEQUENCE_STAGE_NUM + 1) ms 24.576 × (SEQUENCE_STAGE_NUM + 1) ms 27.648 × (SEQUENCE_STAGE_NUM + 1) ms 30.72 × (SEQUENCE_STAGE_NUM + 1) ms 33.792 × (SEQUENCE_STAGE_NUM + 1) ms 36.864 × (SEQUENCE_STAGE_NUM + 1) ms 39.936 × (SEQUENCE_STAGE_NUM + 1) ms 43.008 × (SEQUENCE_STAGE_NUM + 1) ms 46.08 × (SEQUENCE_STAGE_NUM + 1) ms 49.152 × (SEQUENCE_STAGE_NUM + 1) ms Rev. 0 | Page 20 of 68 AD7142 STAGE_MAX_WORD0 STAGE_MAX_WORD1 STAGE_MAX_WORD2 STAGE_MAX_WORD3 Σ-Δ 16-BIT CDC 16 BANK 3 REGISTERS MAX LEVEL DETECTION LOGIC STAGE_MAX_AVG BANK 3 REGISTERS STAGE_MAX_TEMP BANK 3 REGISTERS STAGE_HIGH_THRESHOLD BANK 3 REGISTERS STAGE_MIN_WORD0 STAGE_MIN_WORD1 STAGE_MIN_WORD2 STAGE_MIN_WORD3 BANK 3 REGISTERS MIN LEVEL DETECTION LOGIC CONTROL LOGIC SW SLOW_FILTER_UPDATE_LVL REGISTER 0x003 STAGE_FF_WORD0 STAGE_FF_WORD1 STAGE_FF_WORD2 STAGE_FF_WORD3 STAGE_FF_WORD4 STAGE_FF_WORD5 STAGE_FF_WORD6 STAGE_FF_WORD7 STAGE_MIN_AVG BANK 3 REGISTER3 STAGE_MIN_TEMP BANK 3 REGISTERS STAGE_LOW_THRESHOLD BANK 3 REGISTERS FP_PROXIMITY_CNT REGISTER 0x002 LP_PROXIMITY_CNT REGISTER 0X002 COMPARATOR 3 WORD0 – WORD3 COMPARATOR 1 WORD0 – WORD3 PROXIMITY 1 PROXIMITY PROXIMITY TIMING CONTROL LOGIC PROXIMITY SLOW FILTER EN PROXIMITY_DETECTION_RATE REGISTER 0x003 FP_PROXIMITY_RECAL REGISTER 0x004 LP_PROXIMITY_RECAL REGISTER 0X004 Σ=WORD(N) N0 8 SW1 COMPARATOR 2 STAGE_FF_AVG BANK 3 REGISTERS AVERAGE – AMBIENT 7 PROXIMITY 2 BANK 3 REGISTERS STAGE_FF_WORDX STAGE_SF_WORD0 STAGE_SF_WORD1 STAGE_SF_WORD2 STAGE_SF_WORD3 STAGE_SF_WORD4 STAGE_SF_WORD5 STAGE_SF_WORD6 STAGE_SF_WORD7 BANK 3 REGISTERS PROXIMITY_RECAL_LVL REGISTER 0x003 CDC OUTPUT CODE AMBIENT VALUE STAGE_SF_WORDX SENSOR CONTACT TIME STAGE_SF_AMBIENT BANK 3 REGISTERS NOTES 1. SLOW FILTER EN IS SET AND SW1 IS CLOSED WHEN |WORD 0–WORD 3| EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE_LVL REGISTER PROVIDING PROXIMITY IS NOT SET. 2. PROXIMITY 1 IS SET WHEN |WORD 0–WORD 3| EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_DETECTION_RATE REGISTER. 3. PROXIMITY 2 IS SET WHEN |AVERAGE–AMBIENT| EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER. 4. DESCRIPTION OF COMPARATOR FUNCTIONS: COMPARATOR 1: USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR. COMPARATOR 2: USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR, OR APPROACHING A SENSOR VERY SLOWLY. ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF THE USER INTERACTION. FOR EXAMPLE, HUMIDITY OR DIRT LEFT BEHIND ON SENSOR. COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW FILTER EN IS SET AND PROXIMITY IS NOT SET. Figure 30. AD7142 Proximity Detection and Environmental Calibration Rev. 0 | Page 21 of 68 05702-021 AD7142 ENVIRONMENTAL CALIBRATION The AD7142 provides on-chip capacitance sensor calibration to automatically adjust for environmental conditions that have an effect on the capacitance sensor ambient levels. Capacitance sensor output levels are sensitive to temperature, humidity, and in some cases, dirt. The AD7142 achieves optimal and reliable sensor performance by continuously monitoring the CDC ambient levels and correcting for any changes by adjusting the STAGE_HIGH_THRESHOLD and STAGE_LOW_ THRESHOLD register values. The CDC ambient level is defined as the capacitance sensor output level during periods when the user is not approaching or in contact with the sensor. The compensation logic runs automatically on every conversion after configuration when the AD7142 is not being touched. This allows the AD7142 to account for rapidly changing environmental conditions. The ambient compensation control registers give the host access to general setup and controls for the compensation algorithm. The RAM stores the compensation data for each conversion stage, as well as setup information specific to each stage. Figure 31 shows an example of an ideal capacitance sensor behavior where the CDC ambient level remains constant regardless of the environmental conditions. The CDC output shown is for a pair of differential button sensors, where one sensor caused an increase, and the other a decrease in measured capacitance when activated. The positive and negative sensor threshold levels are calculated as a percentage of the STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values based on the threshold sensitivity settings and the ambient value. These values are sufficient to detect a sensor contact, resulting with the AD7142 asserting the INT output when the threshold levels are exceeded. SENSOR 1 INT ASSERTED STAGE_HIGH_THRESHOLD CAPACITANCE SENSOR BEHAVIOR WITHOUT CALIBRATION Figure 32 shows the typical behavior of a capacitance sensor with no applied calibration. This figure shows ambient levels drifting over time as environmental conditions change. The ambient level drift has resulted in the detection of a missed user contact on Sensor 2. This is a result of the initial low offset level remaining constant while the ambient levels drifted upward beyond the detection range. The Capacitance Sensor Behavior with Calibration section describes how the AD7142 adaptive calibration algorithm prevents errors such as this from occurring. SENSOR 1 INT ASSERTED STAGE_HIGH_THRESHOLD CDC OUTPUT CODES CCDC AMBIENT VALUE DRIFTING STAGE_LOW_THRESHOLD SENSOR 2 INT NOT ASSERTED t CHANGING ENVIRONMENTAL CONDITIONS 05702-023 Figure 32. Typical Sensor Behavior Without Calibration Applied CDC OUTPUT CODES CDC AMBIENT VALUE STAGE_LOW_THRESHOLD SENSOR 2 INT ASSERTED t CHANGING ENVIRONMENTAL CONDITIONS 05702-022 Figure 31. Ideal Sensor Behavior with a Constant Ambient Level Rev. 0 | Page 22 of 68 AD7142 CAPACITANCE SENSOR BEHAVIOR WITH CALIBRATION The AD7142 on-chip adaptive calibration algorithm prevents sensor detection errors such as the one shown in Figure 32. This is achieved by monitoring the CDC ambient levels and internally adjusting the initial offset level register values according to the amount of ambient drift measured on each sensor. This closed loop routine ensures the reliability and repeatable operation of every sensor connected to the AD7142 under dynamic environmental conditions. Figure 33 shows a simplified example of how the AD7142 applies the adaptive calibration process resulting in no interrupt errors under changing CDC ambient levels due to environmental conditions. 1 SENSOR 1 INT ASSERTED 2 3 STAGE_HIGH_THRESHOLD (POST CALIBRATED REGISTER VALUE) CDC OUTPUT CODES CDCAMBIENT VALUE DRIFTING 6 5 4 SENSOR 2 INT ASSERTED CHANGING ENVIRONMENTAL CONDITIONS t STAGE_LOW_THRESHOLD (POST CALIBRATED REGISTER VALUE) NOTES 1. INITIAL STAGE_OFFSET_HIGH REGISTER VALUE 2. POST CALIBRATED REGISTER STAGE_HIGH_THRESHOLD 3. POST CALIBRATED REGISTER STAGE_HIGH_THRESHOLD 4. INITIAL STAGE_LOW_THRESHOLD 5. POST CALIBRATED REGISTER STAGE_LOW_THRESHOLD 6. POST CALIBRATED REGISTER STAGE_LOW_THRESHOLD Figure 33. Typical Sensor Behavior with Calibration Applied on the Data Path Rev. 0 | Page 23 of 68 05702-024 AD7142 ADAPTIVE THRESHOLD AND SENSITIVITY The AD7142 provides an on-chip self-learning adaptive threshold and sensitivity algorithm. This algorithm continuously monitors the output levels of each sensor and automatically rescales the threshold levels proportionally to the sensor area covered by the user. As a result, the AD7142 maintains optimal threshold and sensitivity levels for all types of users regardless of their finger sizes. The threshold level is always referenced from the ambient level and is defined as the CDC converter output level that must be exceeded for a valid sensor contact. The sensitivity level is defined as how sensitive the sensor is before a valid contact is registered. Figure 34 provides an example of how the adaptive threshold and sensitivity algorithm works. The positive and negative sensor threshold levels are calculated as a percentage of the STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values based on the threshold sensitivity settings and the ambient value. On configuration, initial estimates are supplied for both STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW after which the calibration engine automatically adjusts the STAGE_HIGH_THRESHOLD and STAGE_LOW _THRESHOLD values for sensor response. Reference A in Figure 34 shows an under sensitive threshold level for a small finger user, demonstrating the disadvantages of a fixed threshold level. By enabling the adaptive threshold and sensitivity algorithm, the positive and negative threshold levels are determined by the POS_ THRESHOLD_SENSITIVITY and NEG_THRESHOLD_ SENSITIVITY register values and the most recent average maximum sensor output value. These registers can be used to select 16 different positive and negative sensitivity levels ranging between 25% and 95.32% of the most recent average maximum output level referenced from the ambient value. The smaller the sensitivity percentage setting, the easier it is to trigger a sensor activation. Reference B shows that the positive adaptive threshold level is set at almost midsensitivity with a 62.51% threshold level by setting POS_THRESHOLD_ SENSITIVITY = 1000. Figure 34 also provides a similar example for the negative threshold level with NEG_ THRESHOLD_SENSITIVITY = 0001. AVERAGE MAX VALUE 95.32% STAGE_OFFSET_HIGH IS UPDATED AVERAGE MAX VALUE STAGE_OFFSET_HIGH 95.32% STAGE_OFFSET_HIGH IS UPDATED HERE 62.51% = POS ADAPTIVE THRESHOLD LEVEL 25% 25% B A CDC OUTPUT CODES 62.51% = POS ADAPTIVE THRESHOLD LEVEL AMBIENT LEVEL 25% NEG ADAPTIVE THRESHOLD LEVEL = 39.08% STAGE_OFFSET_LOW 95.32% STAGE_OFFSET_LOW IS UPDATED HERE 25% NEG ADAPTIVE THRESHOLD LEVEL = 39.08% STAGE_OFFSET_LOW IS UPDATED HERE 95.32% SENSOR CONTACTED BY SMALL FINGER SENSOR CONTACTED BY LARGE FINGER 05702-025 Figure 34. Threshold Sensitivity Example with POS_THRESHOLD_SENSITIVITY = 1000 and NEG_THRESHOLD_SENSITIVITY = 0011 Rev. 0 | Page 24 of 68 AD7142 INTERRUPT OUTPUT The AD7142 has an interrupt output that triggers an interrupt service routine on the host processor. The INT signal is on Pin 25, and is an open-drain output. There are three types of interrupt events on the AD7142: a CDC conversion complete interrupt, a sensor threshold interrupt, and a GPIO interrupt. Each interrupt has enable and status registers. The conversion complete and sensor threshold interrupts can be enabled on a per conversion stage basis. The status registers indicate what type of interrupt triggered the INT pin. Status registers are cleared, and the INT signal is reset high, during a read operation. The signal returns high as soon as the read address has been set up. SENSOR TOUCH INTERRUPT The sensor touch interrupt mode is implemented when the host processor requires an interrupt only when a sensor is contacted. Configuring the AD7142 into this mode results in the interrupt being asserted when the user makes contact with the sensor and again when the user lifts off the sensor. The second interrupt is required to alert the host processor that the user is no longer contacting the sensor. The registers located at Address 0x005 and Address 0x006 are used to enable the interrupt output for each stage. The registers located at Address 0x008 and Address 0x009 are used to read back the interrupt status for each stage. Figure 35 shows the interrupt output timing during contact with one of the sensors connected to STAGE0 while operating in the sensor touch interrupt mode. For a low limit configuration, the interrupt output is asserted as soon as the sensor is contacted and again after the user has stopped contacting the sensor. Note: The interrupt output remains low until the host processor reads back the interrupt status registers located at Address 0x008 and Address 0x009. The interrupt output is asserted when there is a change in the threshold status bits. This could indicate that a user is now touching the sensor(s) for the first time, the number of sensors being touched has changed, or the user is no longer touching the sensor(s). Reading the status bits in the interrupt status register shows the current sensor activations. CONVERSION STAGE STAGE0 STAGE1 CDC CONVERSION COMPLETE INTERRUPT The AD7142 interrupt signal asserts low to indicate the completion of a conversion stage, and new conversion result data is available in the registers. The interrupt can be independently enabled for each conversion stage. Each conversion stage complete interrupt can be enabled via the STAGE_COMPLETE_EN register (Address 0x007). This register has a bit that corresponds to each conversion stage. Setting this bit to 1 enables the interrupt for that stage. Clearing this bit to 0 disables the conversion complete interrupt for that stage. In normal operation, the AD7142’s interrupt is enabled only for the last stage in a conversion sequence. For example, if there are five conversion stages, the conversion complete interrupt for STAGE4 is enabled. INT only asserts when all five conversion stages are complete, and the host can read new data from all five result registers. The interrupt is cleared by reading the STAGE_COMPLETE_STATUS_INT register located at Address 0x00A. Register 0x00A is the conversion complete interrupt status register. Each bit in this register corresponds to a conversion stage. If a bit is set, it means that the conversion complete interrupt for the corresponding stage was triggered. This register is cleared on a read, provided the underlying condition that triggered the interrupt has gone away. 2 SERIAL READ BACK 4 INT OUTPUT NOTES: 1. USER TOUCHING DOWN ON SENSOR 2. ADDRESS 0X008 READ BACKTO CLEAR INTERRUPT 3. USER LIFTING OFF OF SENSOR 4. ADDRESS 0X008 READ BACK TO CLEAR INTERRUPT Figure 35. Example of Sensor Touch Interrupt Rev. 0 | Page 25 of 68 05702-055 AD7142 CONVERSIONS STAGE0 STAGE1 STAGE2 STAGE3 STAGE4 STAGE5 STAGE6 STAGE7 STAGE8 STAGE9 STAGE10 STAGE11 INT 1 SERIAL READS NOTES THIS IS AN EXAMPLE OF A CDC CONVERSION COMPLETE INTERRUPT. 2 3 THIS TIMING EXAMPLE SHOWS THAT THE INTERRUPT OUTPUT HAS BEEN ENABLED TO BE ASSERTED AT THE END OF A CONVERSION CYCLE FOR STAGE0, STAGE5, AND STAGE9. THE INTERRUPTS FOR ALL OTHER STAGES HAVE BEEN DISABLED. STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE5, AND STAGE9 (x = 0, 5, 9) STAGEx_LOW_INT_EN (ADDRESS 0x005) = 0 STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0 STAGEx_COMPLETE_EN (ADDRESS 0x007) = 1 STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE 1 THROUGH STAGE 8, STAGE10, AND STAGE11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10, 11) STAGEx_LOW_INT_EN (ADDRESS 0x005) = 0 STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0 STAGEx_COMPLETE_EN (ADDRESS 0x007) = 0 SERIAL READBACK REQUIREMENTS FOR STAGE0, STAGE5 AND STAGE9. THIS READBACK OPERATION IS REQUIRED TO CLEAR THE INTERRUPT OUTPUT. 1. READ THE STAGE0_COMPLETE_STATUS_INT (ADDRESS 0x00A) REGISTER 2. READ THE STAGE5_COMPLETE_STATUS_INT (ADDRESS 0x00A) REGISTER 3. READ THE STAGE9_COMPLETE_STATUS_INT (ADDRESS 0x00A) REGISTER 05702-026 Figure 36. Example of Configuring the Registers for End of Conversion Interrupt Setup CONVERSIONS STAGE0 STAGE1 STAGE2 STAGE3 STAGE4 STAGE5 STAGE6 STAGE7 STAGE8 STAGE9 STAGE10 STAGE11 INT 1 SERIAL READS 4 2 NOTES THIS IS AN EXAMPLE OF A SENSOR THRESHOLD INTERRUPT FOR A CASE WHERE THE LOW THRESHOLD LEVELS WERE EXCEEDED. FOR EXAMPLE: THE SENSOR CONNECTED TO STAGE0 AND STAGE9 WERE CONTACTED AND THE LOW THRESHOLD LEVELS WERE EXCEEDED RESULTING IN THE INTERRUPT BEING ASSERTED. THE STAGE6 INTERRUPT WAS NOT ASSERTED BECAUSE THE USER DID NOT CONTACT THE SENSOR CONNECTED TO STAGE6. STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE 0, STAGE6, AND STAGE9 (x = 0, 6, 9) STAGEx_LOW_INT_EN (ADDRESS 0x005) = 1 STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0 STAGEx_COMPLETE_EN (ADDRESS 0x007) = 0 STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE 1 THROUGH STAGE7, STAGE8, STAGE10, AND STAGE11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10, 11) STAGEx_LOW_INT_EN (ADDRESS 0x005) = 0 STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0 STAGEx_COMPLETE_EN (ADDRESS 0x007) = 0 SERIAL READBACK REQUIREMENTS FOR STAGE0 AND STAGE9. THIS READBACK OPERATION IS REQUIRED TO CLEAR THE INTERRUPT OUTPUT. 1. READ THE STAGE0_LOW_LIMIT_INT (ADDRESS 0x008) REGISTER 2. READ THE STAGE5_LOW_LIMIT_INT (ADDRESS 0x008) REGISTER Figure 37. Example of Configuring the Registers for Sensor Interrupt Setup Rev. 0 | Page 26 of 68 05702-027 AD7142 GPIO INT OUTPUT CONTROL The INT output signal can be controlled by the GPIO pin when the GPIO is configured as an input. The GPIO is configured as an input by setting the GPIO_SETUP bits in the interrupt configuration register to 01. See the GPIO section for more information on how to configure the GPIO. Enable the GPIO interrupt by setting the GPIO_INT_EN bit in Register 0x007 to 1, or disable the GPIO interrupt by clearing this bit to 0. The GPIO status bit in the conversion complete interrupt status register reflects the status of the GPIO interrupt. This bit is set to 1 when the GPIO has triggered INT. The bit is cleared on readback from the register, provided the condition that caused the interrupt has gone away. The GPIO interrupt can be set to trigger on a rising edge, falling edge, high level, or low level at the GPIO input pin. Table 14 shows how the settings of the GPIO_INPUT_CONFIG bits in the interrupt enable register affect the behavior of INT. Figure 38 to Figure 41 show how the interrupt output is cleared on a read from the CDC conversion complete interrupt status register. 1 SERIAL READBACK GPIO INPUT HIGH WHEN REGISTER IS READ BACK GPIO INPUT SERIAL READBACK GPIO INPUT HIGH WHEN REGISTER IS READ BACK GPIO INPUT INT OUTPUT 1 INT OUTPUT GPIO INPUT LOW WHEN REGISTER IS READ BACK GPIO INPUT GPIO INPUT LOW WHEN REGISTER IS READ BACK GPIO INPUT INT OUTPUT INT OUTPUT 05702-028 Figure 38. INT Output Controlled by the GPIO Input Example, GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 00 Figure 39. INT Output Controlled by the GPIO Input Example, GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 01 Rev. 0 | Page 27 of 68 05702-029 NOTES 1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT. NOTES 1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT. AD7142 1 SERIAL READBACK GPIO INPUT LOW WHEN REGISTER IS READBACK GPIO INPUT 1 SERIAL READBACK GPIO INPUT LOW WHEN REGISTER IS READBACK GPIO INPUT INT OUTPUT INT OUTPUT GPIO INPUT HIGH WHEN REGISTER IS READBACK GPIO INPUT GPIO INPUT HIGH WHEN REGISTER IS READBACK GPIO INPUT INT OUTPUT INT OUTPUT NOTES 1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT. 05702-030 NOTES 1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT. Figure 41. INT Output Controlled by the GPIO Input Example, GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 11 Figure 40. INT Output Controlled by the GPIO Input Example, GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 10 Table 14. GPIO Interrupt Behavior GPIO_INPUT_CONFIG 00 = Negative Level Triggered 00 = Negative Level Triggered 01 = Positive Edge Triggered 01 = Positive Edge Triggered 10 = Negative Edge Triggered 10 = Negative Edge Triggered 11 = Positive Level Triggered 11 = Positive Level Triggered GPIO Pin 1 0 1 0 1 0 1 0 GPIO_STATUS 0 1 1 0 0 1 1 0 INT 1 0 0 1 1 0 0 1 INT Behavior Not triggered Asserted while signal on GPIO pin is low Pulses low at low-to-high GPIO transition Not triggered Pulses low at high-to-low GPIO transition Not triggered Asserted while signal on GPIO pin is high Not triggered Rev. 0 | Page 28 of 68 05702-031 AD7142 OUTPUTS EXCITATION SOURCE The excitation source on board the AD7142 is a square wave source with a frequency of 240 kHz. This excitation source forms the electric field between the transmitter and receiver in the external capacitance sensor PCB. The source is output from the AD7142 on two pins, the SRC pin and the SRC pin (outputs an inverted version of the source square wave). The SRC signal offsets large external sensor capacitances. SRC is not used in the majority of applications. The source output can be disabled from both output pins separately by writing to the control register bits (Address 0x000[13:12]). Setting Bit 12 in this register to 1 disables the source output on the SRC pin. Setting Bit 13 in this register to 1 disables the inverted source output on the SRC pin. GPIO The AD7142 has one GPIO pin located at Pin 26. It can be configured as an input or an output. The GPIO_SETUP Bits[13:12] in the interrupt enable register determine how the GPIO pin is configured. Table 15. GPIO_SETUP Bits GPIO_SETUP 00 01 10 11 GPIO Configuration GPIO disabled Input Output low Output high When the GPIO is configured as an output, the voltage level on the pin is set to either a low level or a high level, as defined by the GPIO_SETUP bits shown in Table 15. When the GPIO is configured as an input, the GPIO_INPUT_CONFIG bits in the interrupt enable register determine the response of the AD7142 to a signal on the GPIO pin. The GPIO can be configured as either active high or active low, as well as either edge triggered or level triggered, as listed in Table 16. Table 16. GPIO_INPUT_CONFIG Bits GPIO_INPUT_CONFIG 00 01 10 11 GPIO Configuration Triggered on negative level (active low) Triggered on positive edge (active high) Triggered on negative edge (active low) Triggered on positive level (active high) CSHIELD OUTPUT To prevent leakage from the external capacitance sensors, the sensor traces are shielded. The AD7142 has a voltage output that can be used as the potential for any shield traces, CSHIELD. The CSHIELD voltage is equal to AVDD/2. The CSHIELD potential is derived from the output of the AD7142 internal amplifier, and is of equal potential to the CIN input lines. Because the shield is at the same potential as the sensor traces, no leakage to ground occurs. To eliminate any ringing on the CSHIELD output, connect a 10 nF capacitor between the CSHIELD pin and ground. For 4-layer sensors, CSHIELD is connected to a copper plane around the sensors on layers 2, 3, and 4. A ground copper plane is used on Layer 1 around the source electrodes. On a 2-layer sensor, CSHIELD is connected to a copper plane around the sensors on the bottom layer. A ground copper plane is used on the top layer around the source electrodes. Figure 42 shows how the sensor traces are shielded by running traces connected to the shield potential around the sensor traces. When GPIO is configured as an input, it triggers the interrupt output on the AD7142. Table 14 lists the interrupt output behavior for each of the GPIO configuration setups. USING THE GPIO TO TURN ON/OFF AN LED The GPIO on the AD7142 can be used to turn on and off LEDs by setting the GPIO as either output high or low. Setting the GPIO output high turns on the LED; setting the GPIO output low turns off the LED. The GPIO pin connects to a transistor that provides the drive current for the LED. Suitable transistors include the KTC3875. VCC KTC3875 OR SIMILAR AD7142 SENSOR PCB CSHIELD 10nF 05702-032 AD7142 GPIO Figure 42. Shielding the Sensor Traces 05702-061 Figure 43. Controlling LEDs Using the GPIO Rev. 0 | Page 29 of 68 AD7142 SERIAL INTERFACE The AD7142 is available with an SPI serial interface. The AD7142-1 is available with an I2C-compatible interface. Both parts are the same, with the exception of the serial interface. Bits[15:11] of the command word must be set to 11100 to successfully begin a bus transaction. Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a write. Bits[9:0] contain the target register address. When reading or writing to more than one register, this address indicates the address of the first register to be written to or read from. SPI INTERFACE The AD7142 has a 4-wire serial peripheral interface (SPI). The SPI has a data input pin (SDI) for inputting data to the device, a data output pin (SDO) for reading data back from the device, and a data clock pin (SCLK) for clocking data into and out of the device. A chip select pin (CS) enables or disables the serial interface. CS is required for correct operation of the SPI interface. Data is clocked out of the AD7142 on the negative edge of SCLK, and data is clocked into the device on the positive edge of SCLK. Writing Data Data is written to the AD7142 in 16-bit words. The first word written to the device is the command word, with the read/write bit set to 0. The master then supplies the 16-bit input data-word on the SDI line. The AD7142 clocks the data into the register addressed in the command word. If there is more than one word of data to be clocked in, the AD7142 automatically increments the address pointer, and clocks the next data-word into the next register. The AD7142 continues to clock in data on the SDI line until either the master finishes the write transition by pulling CS high, or until the address pointer reaches its maximum value. The AD7142 address pointer does not wrap around. When it reaches its maximum value, any data provided by the master on the SDI line is ignored by the AD7142. SPI Command Word All data transactions on the SPI bus begin with the master taking CS from high to low and sending out the command word. This indicates to the AD7142 whether the transaction is a read or a write, and gives the address of the register from which to begin the data transfer. The following bit map shows the SPI command word. MSB 15 14 1 1 LSB 13 1 12 0 11 0 10 R/W 9:0 Register address 16-BIT COMMAND WORD ENABLE WORD SDI CW 15 CW 14 CW 13 CW 12 CW 11 R/W CW 10 CW 9 CW 8 CW 7 REGISTER ADDRESS CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 D15 D14 D13 16-BIT DATA D2 D1 D0 t2 SCLK 1 2 t3 3 4 5 t4 6 7 8 t5 9 10 11 12 13 14 15 16 17 18 19 30 31 32 t1 CS t8 Figure 44. Single Register Write SPI Timing Rev. 0 | Page 30 of 68 05702-033 NOTES 1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR CONTROL WORD AND 16 BITS FOR DATA. 3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS) AD7142 16-BIT COMMAND WORD ENABLE WORD SDI CW 15 CW 14 CW 13 CW 12 CW 11 R/W CW 10 CW 9 CW 8 STARTING REGISTER ADDRESS CW 7 CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 D15 DATA FOR STARTING REGISTER ADDRESS D14 D1 D0 D15 DATA FOR NEXT REGISTER ADDRESS D14 D1 D0 D15 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 31 32 33 34 47 48 49 CS NOTES 1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN). 4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS) Figure 45. Sequential Register Write SPI Timing 16-BIT COMMAND WORD ENABLE WORD SDI CW 15 CW 14 CW 13 CW 12 CW 11 R/W CW 10 CW 9 CW 8 CW 7 REGISTER ADDRESS CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 X X X X X X t2 SCLK 1 2 3 4 5 t4 6 7 8 t5 9 10 11 12 13 14 15 16 17 18 19 30 31 32 t1 CS t3 t8 t6 SDO XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14 D13 D2 D1 t7 D0 XXX 16-BIT READBACK DATA NOTES 1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE REGISTER DATA IS READ BACK ON THE SDO PIN. 4. X DENOTES DON’T CARE. 5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS) Figure 46. Single Register Readback SPI Timing Reading Data A read transaction begins when the master writes the command word to the AD7142 with the read/write bit set to 1. The master then supplies 16 clock pulses per data-word to be read, and the AD7142 clocks out data from the addressed register on the SDO line. The first data-word is clocked out on the first falling edge of SCLK following the command word, as shown in Figure 46. The AD7142 continues to clock out data on the SDO line provided the master continues to supply the clock signal on SCLK. The read transaction finishes when the master takes CS high. If the AD7142 address pointer reaches its maximum value, then the AD7142 repeatedly clocks out data from the addressed register. The address pointer does not wrap around. Rev. 0 | Page 31 of 68 05702-035 05702-034 AD7142 16-BIT COMMAND WORD ENABLE WORD SDI CW 15 CW 14 CW 13 CW 12 CW 11 R/W CW 10 CW 9 CW 8 CW 7 REGISTER ADDRESS CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 X X X X X X X X X SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 31 32 33 34 47 48 49 CS SDO XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14 D1 D0 D15 D14 D1 D0 D15 READBACK DATA FOR STARTING REGISTER ADDRESS READBACK DATA FOR NEXT REGISTER ADDRESS Figure 47. Sequential Register Readback SPI Timing I2C COMPATIBLE INTERFACE The AD7142-1 supports the industry standard 2-wire I C serial interface protocol. The two wires associated with the I2C timing are the SCLK and the SDA inputs. The SDA is an I/O pin that allows both register write and register readback operations. The AD7142-1 is always a slave device on the I2C serial interface bus. It has a 7-bit device address, Address 0101 1XX. The lower two bits are set by tying the ADD0 and ADD1 pins high or low. The AD7142-1 responds when the master device sends its device address over the bus. The AD7142-1 cannot initiate data transfers on the bus. Table 17. AD7142-1 I2C Device Address ADD1 0 0 1 1 ADD0 0 1 0 1 I C Address 0101 100 0101 101 0101 110 0101 111 2 2 All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit that determines the direction of the data transfer. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from, or written to it. If the R/W bit is a zero, the master writes to the slave device. If the R/W bit is a one, the master reads from the slave device. Data is sent over the serial bus in a sequence of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, since a low-to-high transition when the clock is high can be interpreted as a stop signal. The number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. When all data bytes are read or written, a stop condition is established. A stop condition is defined by a low-to-high transition on SDA while SCLK remains high. If the AD7142 encounters a stop condition, it returns to its idle condition, and the address pointer register resets to Address 0x00. Data Transfer Data is transferred over the I2C serial interface in 8-bit bytes. The master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, SDA, while the serial clock line, SCLK, remains high. This indicates that an address/data stream follows. Rev. 0 | Page 32 of 68 05702-036 NOTES 1. MULTIPLE REGISTERS CAN BE READ BACK CONTINUOUSLY. 2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDO PIN. 4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 5. X DENOTES DON’T CARE. 6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS) AD7142 START AD7142 DEVICE ADDRESS SDA DEV A6 DEV A5 DEV A4 DEV A3 DEV DEV A2 A1 DEV A0 R/W ACK REGISTER ADDRESS[A15:A8] A15 A14 A9 A8 ACK A7 REGISTER ADDRESS[A7:A0] A6 A1 A0 t1 SCLK 1 2 3 4 5 6 t3 7 8 9 10 11 16 17 18 19 20 25 26 t2 STOP REGISTER DATA[D15:D8 ] ACK D15 D14 D9 D8 ACK D7 REGISTER DATA[D7:D0] D6 D1 D0 ACK START t8 AD7142 DEVICE ADDRESS DEV A6 DEV A5 DEV A4 t4 27 28 29 34 35 36 37 t5 38 43 44 45 t6 46 t7 1 2 3 NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE X ARE DON'T CARE BITS. 4. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X ARE DON’T CARE BITS. 5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE AWAYS SEPARATED BY A LOW ACK BIT. 6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. Figure 48. Example of I2C Timing for Single Register Write Operation Writing Data over the I2C Bus The process for writing to the AD7142-1 over the I C bus is shown in Figure 48 and Figure 50. The device address is sent over the bus followed by the R/W bit set to 0. This is followed by two bytes of data that contain the 10-bit address of the internal data register to be written. The following bit map shows the upper register address bytes. Note that Bit 7 to Bit 2 in the upper address byte are don’t care bits. The address is contained in the 10 LSBs of the register address bytes. MSB 7 X 6 X 5 X 4 X 3 X 2 X 1 Register Address Bit 9 LSB 0 Register Address Bit 8 2 Any data written to the AD7142-1 after the address pointer has reached its maximum value is discarded. All registers on the AD7142-1 are 16-bit. Two consecutive 8-bit data bytes are combined and written to the 16-bit registers. To avoid errors, all writes to the device must contain an even number of data bytes. To finish the transaction, the master generates a stop condition on SDO, or generates a repeat start condition if the master is to maintain control of the bus. Reading Data over the I2C Bus To read from the AD7142-1, the address pointer register must first be set to the address of the required internal register. The master performs a write transaction, and writes to the AD7142-1 to set the address pointer. The master then outputs a repeat start condition to keep control of the bus, or if this is not possible, ends the write transaction with a stop condition. A read transaction is initiated, with the R/W bit set to 1. The AD7142-1 supplies the upper eight bits of data from the addressed register in the first readback byte, followed by the lower eight bits in the next byte. This is shown in Figure 49 and Figure 50. Because the address pointer automatically increases after each read, the AD7142-1 continues to output readback data until the master puts a no acknowledge and stop condition on the bus. If the address pointer reaches its maximum value, and the master continues to read from the part, the AD7142-1 repeatedly sends data from the last register addressed. The following bit map shows the lower register address bytes. MSB 7 Reg Add Bit 7 6 Reg Add Bit 6 5 Reg Add Bit 5 4 Reg Add Bit 4 3 Reg Add Bit 3 2 Reg Add Bit 2 1 Reg Add Bit 1 LSB 0 Reg Add Bit 0 The third data byte contains the 8 MSBs of the data to be written to the internal register. The fourth data byte contains the 8 LSBs of data to be written to the internal register. The AD7142-1 address pointer register automatically increments after each write. This allows the master to sequentially write to all registers on the AD7142-1 in the same write transaction. However, the address pointer register does not wrap around after the last address. Rev. 0 | Page 33 of 68 05702-037 AD7142 START AD7142-1 DEVICE ADDRESS SDA DEV A6 DEV A5 DEV A4 DEV A3 DEV DEV A2 A1 DEV A0 R/W ACK REGISTER ADDRESS[A15:A8] A15 A14 A9 A8 ACK A7 REGISTER ADDRESS[A7:A0] A6 A1 A0 ACK t1 SCLK 1 2 3 4 5 6 t3 7 8 9 10 11 16 17 18 19 20 25 26 27 t2 P SR DEV A6 USING REPEATED START 28 29 30 34 AD7142-1 DEVICE ADDRESS DEV A5 DEV A1 DEV A0 R/W ACK D7 REGISTER DATA[D7:D0] D6 D1 D0 ACK t8 AD7142 DEVICE ADDRESS DEV A6 DEV A5 DEV A4 t4 35 36 37 38 t5 39 44 45 46 t6 t7 1 2 3 P S DEV A6 AD7142-1 DEVICE ADDRESS DEV A5 DEV A1 DEV A0 R/W ACK D7 REGISTER DATA[D7:D0] D6 D1 D0 ACK P SEPARATE READ AND WRITE TRANSACTIONS 28 29 30 34 t4 35 36 37 38 t5 39 44 45 46 Figure 49. Example of I2C Timing for Single Register Readback Operation WRITE S 6-BIT DEVICE ADDRESS W REGISTER ADDR [15:8] REGISTER ADDR [7:0] WRITE DATA HIGH BYTE [15:8] WRITE DATA LOW BYTE [7:0] WRITE DATA HIGH BYTE [15:8] WRITE DATA LOW BYTE [7:0] ACK ACK ACK ACK ACK ACK P READ (USING REPEATED START) S 6-BIT DEVICE ADDRESS W REGISTER ADDR HIGH BYTE REGISTER ADDR LOW BYTE 6-BIT DEVICE ADDRESS READ DATA HIGH BYTE [15:8] READ DATA LOW BYTE [7:0] READ DATA HIGH BYTE [15:8] READ DATA LOW BYTE [7:0] ACK ACK ACK SR R ACK ACK ACK ACK P READ (WRITE TRANSACITON SETS UP REGISTER ADDRESS) R ACK ACK S P ACK 6-BIT DEVICE ADDRESS W REGISTER ADDR HIGH BYTE REGISTER ADDR LOW BYTE S 6-BIT DEVICE ADDRESS READ DATA HIGH BYTE [15:8] READ DATA LOW BYTE [7:0] READ DATA HIGH BYTE [15:8] READ DATA LOW BYTE [7:0] ACK ACK ACK ACK P 05702-039 OUTPUT FROM MASTER OUTPUT FROM AD7142 S = START BIT P = STOP BIT SR = REPEATED START BIT ACK = ACKNOWLEDGE BIT ACK = NO ACKNOWLEDGE BIT Figure 50. Example of Sequential I2C Write and Readback Operation VDRIVE INPUT The supply voltage to all pins associated with both the I C and SPI serial interfaces (SDO, SDI, SCLK, SDA, and CS) is separate from the main VCC supplies and is connected to the VDRIVE pin. 2 This allows the AD7142 to be connected directly to processors whose supply voltage is less than the minimum operating voltage of the AD7142 without the need for external levelshifters. The VDRIVE pin can be connected to voltage supplies as low as 1.65 V and as high as DVCC. Rev. 0 | Page 34 of 68 05702-038 NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA. 4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB X's ARE DON'T CARE BITS. 5. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB X’s ARE DON’T CARE BITS. 6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BITS. 7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION. AD7142 PCB DESIGN GUIDELINES CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS Table 18. Parameter Distance from Edge of Any Sensor to Edge of Metal Object Distance Between Sensor Edges 1 Distance Between Bottom of Sensor Board and Controller Board or Metal Casing 2 (4-Layer, 2-Layer, and Flex Circuit) 1 Symbol D1 D2 = D3 = D4 D5 Min 1.0 0 Typ Max 1.0 Unit mm mm mm The distance is dependent on the application and the positioning of the switches relative to each other and with respect to the user’s finger positioning and handling. Adjacent sensors, with 0 minimum space between them, are implemented differentially. 2 The 1.0 mm specification is meant to prevent direct sensor board contact with any conductive material. This specification does not guarantee no EMI coupling from the controller board to the sensors. Address potential EMI coupling issues by placing a grounded metal shield between the capacitive sensor board and the main controller board as shown in Figure 53. CAPACITIVE SENSOR BOARD METAL OBJECT D5 CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING 05702-047 CAPACITIVE SENSOR PRINTED CIRCUIT 8-WAY SWITCH Figure 53. Capacitive Sensor Board with Grounded Shield CHIP SCALE PACKAGES D4 SLIDER The lands on the chip scale package (CP-32-3) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width. Center the land on the pad to maximize the solder joint size. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. To avoid shorting, provide a clearance of at least 0.25 mm between the thermal pad and the inner edges of the land pattern on the printed circuit board. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. Connect the printed circuit board thermal pad to GND. BUTTONS D3 D2 D1 05702-045 Figure 51. Capacitive Sensor Board Mechanicals Top View CAPACITIVE SENSOR BOARD D5 GROUNDED METAL SHIELD CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING Figure 52. Capacitive Sensor Board Mechanicals Side View Rev. 0 | Page 35 of 68 05702-046 AD7142 POWER-UP SEQUENCE When the AD7142 is powered up, the following sequence is recommended when initially developing the AD7142 and μP serial interface: 1. 2. Turn on the power supplies to the AD7142. Write to the Bank 2 registers at Address 0x080 through Address 0x0DF. These registers are contiguous so a sequential register write sequence can be applied. Note: The Bank 2 register values are unique for each application. Register values are provided by Analog Devices after the sensor board has been developed. 3. Write to the Bank 1 registers at Address 0x000 through Address 0x007 as outlined below. These registers are contiguous so a sequential register write sequence can be applied (see Figure 45 and Figure 50). Caution: At this time, Address 0x001 must remain set to default value 0x0000 during this contiguous write operation. Register values: Address 0x000 = 0x00B2 Address 0x001 = 0x0000 Address 0x002 = 0x0690 Address 0x003 = 0x0664 6. Address 0x004 = 0x290F Address 0x005 = 0x0000 Address 0x006 = 0x0000 Address 0x007 = 0x0001 (The AD7142 interrupt is asserted approximately every 37 ms.) 4. 5. Write to the Bank 1 register, Address 0x001 = 0x0FFF. Read back the corresponding interrupt status register at Address 0x008, Address 0x009, or Address 0x00A. This is determined by the interrupt output configuration as explained in the Interrupt Output section. Note: The specific registers required to be readback depend on each application. Analog Devices provides this information after the sensor board has been developed. Repeat Step 5 every time INT is asserted. CONVERSION STAGE CONVERSION STAGES DISABLED 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 9 10 11 0 1 2 9 10 11 0 1 FIRST CONVERSION SEQUENCE SECOND CONVERSION SEQUENCE THIRD CONVERSION SEQUENCE Figure 54. Recommended Start-Up Sequence Rev. 0 | Page 36 of 68 05702-040 AD7142 TYPICAL APPLICATION CIRCUITS AVCC, DVCC VDRIVE 2.2kΩ CIN2 32 CIN1 31 CIN0 30 VREF– 29 VREF+ 28 TEST 27 GPIO 26 INT 25 INT SS SCK MOSI MISO SENSOR PCB LAYER 1 1 CIN3 2 CIN4 CS 24 SCLK 23 SDI 22 SDO 21 VDRIVE 20 DGND2 19 HOST WITH SPI INTERFACE SENSOR PCB LAYER 2 3 CIN5 SLIDER 4 CIN6 5 CIN7 6 CIN8 7 CIN9 AD7142 VHOST 1.8V DGND1 18 12 CSHIELD 14 AGND 11 CIN13 10 CIN12 CIN11 13 AVCC 15 SRC 16 SRC 8-WAY SWITCH 8 CIN10 DVCC 17 AVCC, DVCC 2.7V TO 3.6V 0.1µF 1µF TO 10µF (OPTIONAL) 9 10nF Figure 55. Typical Application Circuit with SPI Interface VDRIVE VDRIVE AVCC, DVCC 2.2kΩ 2.2kΩ CIN2 32 CIN1 31 CIN0 30 VREF– 29 VREF+ 28 TEST 27 GPIO 26 INT 25 INT 1 2 3 4 CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 ADD1 24 SCLK 23 ADD0 22 HOST WITH I2C INTERFACE SCK SENSOR PCB LAYER 2 AD7142-1 SDA 21 V DRIVE DGND2 DGND1 20 19 18 SDO SLIDER BUTTONS 5 6 7 8 CSHIELD CIN11 CIN12 AVCC AGND CIN10 CIN13 SRC SRC DVCC 17 16 10 11 12 13 14 15 9 AVCC, DVCC 2.7V TO 3.6V 0.1µF 1µF TO 10µF (OPTIONAL) SENSOR PCB LAYER 1 10nF 05702-042 Figure 56. Typical Application Circuit with I2C Interface Rev. 0 | Page 37 of 68 05702-041 AD7142 REGISTER MAP The AD7142 address space is divided into three different register banks, referred to as Bank 1, Bank 2, and Bank 3. Figure 57 illustrates the division of these three banks. Bank 1 registers contain control registers, CDC conversion control registers, interrupt enable registers, interrupt status registers, CDC 16-bit conversion data registers, device ID registers, and proximity status registers. Bank 2 registers contain the configuration registers used for uniquely configuring the CIN inputs for each conversion stage. Initialize the Bank 2 configuration registers immediately after power-up to obtain valid CDC conversion result data. Bank 3 registers contain the results of each conversion stage. These registers automatically update at the end of each conversion sequence. Although these registers are primarily used by the AD7142 internal data processing, they are accessible by the host processor for additional external data processing, if desired. Default values are undefined for Bank 2 registers and Bank 3 registers until after power up and configuration of the Bank 2 registers. REGISTER BANK 1 ADDR 0x000 ADDR 0x001 SET UP CONTROL (1 REGISTER) CALIBRATION AND SET UP (4 REGISTERS) ADDR 0x005 ADDR 0x080 ADDR 0x088 ADDR 0x090 ADDR 0x098 INTERRUPT ENABLE (3 REGISTERS) ADDR 0x008 ADDR 0x0A0 REGISTER BANK 2 STAGE 0 CONFIGURATION (8 REGISTERS) STAGE 1 CONFIGURATION (8 REGISTERS) STAGE 2 CONFIGURATION (8 REGISTERS) STAGE 3 CONFIGURATION (8 REGISTERS) ADDR 0x0E0 ADDR 0x088 ADDR 0x090 ADDR 0x098 ADDR 0x0A0 REGISTER BANK 3 STAGE 0 RESULTS (36 REGISTERS) STAGE 1 RESULTS (36 REGISTERS) STAGE 2 RESULTS (36 REGISTERS) STAGE 3 RESULTS (36 REGISTERS) STAGE 4 RESULTS (36 REGISTERS) STAGE 5 RESULTS (36 REGISTERS) STAGE 6 RESULTS (36 REGISTERS) STAGE 7 RESULTS (36 REGISTERS) STAGE 8 RESULTS (36 REGISTERS) STAGE 9 RESULTS (36 REGISTERS) STAGE 10 RESULTS (36 REGISTERS) STAGE 11 RESULTS (36 REGISTERS) 05702-043 24 REGISTERS 96 REGISTERS INTERRUPT STATUS (3 REGISTERS) ADDR 0x00B CDC 16-BIT CONVERSION DATA (12 REGISTERS) ADDR 0x017 ADDR 0x018 ADDR 0x042 PROXIMITY STATUS REGISTER ADDR 0x043 DEVICE ID REGISTER INVALID DO NOT ACCESS ADDR 0x0A8 ADDR 0x0B0 ADDR 0x0B8 ADDR 0x0C0 ADDR 0x0C8 ADDR 0x0D0 432 REGISTERS STAGE 4 CONFIGURATION (8 REGISTERS) STAGE 5 CONFIGURATION (8 REGISTERS) STAGE 6 CONFIGURATION (8 REGISTERS) STAGE 7 CONFIGURATION (8 REGISTERS) STAGE 8 CONFIGURATION (8 REGISTERS) STAGE 9 CONFIGURATION (8 REGISTERS) STAGE 10 CONFIGURATION (8 REGISTERS) STAGE 11 CONFIGURATION (8 REGISTERS) ADDR 0x0A8 ADDR 0x0B0 ADDR 0x0B8 ADDR 0x0C0 ADDR 0x0C8 ADDR 0x0D0 ADDR 0x28F INVALID DO NOT ACCESS ADDR 0x0D8 ADDR 0x7F0 Figure 57. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers Rev. 0 | Page 38 of 68 AD7142 DETAILED REGISTER DESCRIPTIONS BANK 1 REGISTERS All addresses and default values are expressed in hexadecimal. Table 19. PWR_CONTROL Register Address 0x000 Data Bit [1:0] Default Value 0 Type R/W Name POWER_MODE Description Operating modes 00 = full power mode (normal operation, CDC conversions approximately every 36 ms) 01 = full shutdown mode (no CDC conversions) 10 = low power mode (automatic wake up operation) 11 = full shutdown mode (no CDC conversions) Low power mode conversion delay 00 = 200 ms 01 = 400 ms 10 = 600 ms 11 = 800 ms Number of stages in sequence (N + 1) 0000 = 1 conversion stage in sequence 0001 = 2 conversion stages in sequence …… Maximum value = 1011 = 12 conversion stages per sequence ADC decimation factor 00 = decimate by 256 01 = decimate by 128 10 = do not use this setting 11 = do not use this setting Software reset control (self-clearing) 1 = resets all registers to default values Interrupt polarity control 0 = active low 1 = active high Excitation source control for Pin 15 0 = enable output 1 = disable output Excitation source control for Pin 16 0 = enable output 1 = disable output CDC bias current control 00 = normal operation 01 = normal operation + 20% 10 = normal operation + 35% 11 = normal operation + 50% [3:2] 0 LP_CONV_DELAY [7:4] 0 SEQUENCE_STAGE_NUM [9:8] 0 DECIMATION [10] [11] 0 0 SW_RESET INT_POL [12] 0 EXCITATION_SOURCE [13] 0 SRC [15:14] 0 CDC_BIAS Rev. 0 | Page 39 of 68 AD7142 Table 20. STAGE_CAL_EN Register Address 0x001 Data Bit [0] Default Value 0 Type R/W Name STAGE0_CAL_EN Description STAGE0 calibration enable 0 = disable 1 = enable STAGE1 calibration enable 0 = disable 1 = enable STAGE2 calibration enable 0 = disable 1 = enable STAGE3 calibration enable 0 = disable 1 = enable STAGE4 calibration enable 0 = disable 1 = enable STAGE5 calibration enable 0 = disable 1 = enable STAGE6 calibration enable 0 = disable 1 = enable STAGE7 calibration enable 0 = disable 1 = enable STAGE8 calibration enable 0 = disable 1 = enable STAGE9 calibration enable 0 = disable 1 = enable STAGE10 calibration enable 0 = disable 1 = enable STAGE11 calibration enable 0 = disable 1 = enable Full power mode skip control 00 = skip 3 samples 01 = skip 7 samples 10 = skip 15 samples 11 = skip 31 samples Low power mode skip control 00 = use all samples 01 = skip 1 sample 10 = skip 2 samples 11 = skip 3 samples [1] 0 STAGE1_CAL_EN [2] 0 STAGE2_CAL_EN [3] 0 STAGE3_CAL_EN [4] 0 STAGE4_CAL_EN [5] 0 STAGE5_CAL_EN [6] 0 STAGE6_CAL_EN [7] 0 STAGE7_CAL_EN [8] 0 STAGE8_CAL_EN [9] 0 STAGE9_CAL_EN [10] 0 STAGE10_CAL_EN [11] 0 STAGE11_CAL_EN [13:12] 0 AVG_FP_SKIP [15:14] 0 AVG_LP_SKIP Rev. 0 | Page 40 of 68 AD7142 Table 21. AMB_COMP_CTRL0 Register Address 0x002 Data Bit [3:0] Default Value 0 Type R/W Name FF_SKIP_CNT Description Fast filter skip control (N+1) 0000 = no sequence of results are skipped 0001 = one sequence of results is skipped for every one allowed into Fast FIFO 0010 = two sequences of results are skipped for every one allowed into Fast FIFO 1011 = maximum value = 12 sequences of results are skipped for every one allowed into Fast FIFO Full power mode proximity period Low power mode proximity period Full power to low power mode time out control 00 = 1.25 × (FP_PROXIMITY_CNT) 01 = 1.50 × (FP_PROXIMITY_CNT) 10 = 1.75 × (FP_PROXIMITY_CNT) 11 = 2.00 × (FP_PROXIMITY_CNT) Forced calibration control 0 = normal operation 1 = forces all conversion stages to recalibrate Conversion reset control (self-clearing) 0 = normal operation 1 = resets the conversion sequence back to STAGE0. [7:4] [11:8] [13:12] F F 0 FP_PROXIMITY_CNT LP_PROXIMITY_CNT PWR_DOWN_TIMEOUT [14] 0 FORCED_CAL [15] 0 CONV_RESET Table 22. AMB_COMP_CTRL1 Register Address 0x003 Data Bit [7:0] [13:8] [15:14] Default Value 64 1 0 Type R/W Name PROXIMITY_RECAL_LVL PROXIMITY_DETECTION_RATE SLOW_FILTER_UPDATE_LVL Description Proximity recalibration level Proximity detection rate Slow filter update level Table 23. AMB_COMP_CTRL2 Register Address 0x004 Data Bit [9:0] [15:10] Default Value 3FF 3F Type R/W Name FP_PROXIMITY_RECAL LP_PROXIMITY_RECAL Description Full power mode proximity recalibration time control Low power mode proximity recalibration time control Table 24. STAGE_LOW_INT_EN Register Address 0x005 Data Bit [0] Default Value 0 Type R/W Name STAGE0_LOW_INT_EN Description STAGE0 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE1 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE2 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE3 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded [1] 0 STAGE1_LOW_INT_EN [2] 0 STAGE2_LOW_INT_EN [3] 0 STAGE3_LOW_INT_EN Rev. 0 | Page 41 of 68 AD7142 Address Data Bit [4] Default Value 0 Type Name STAGE4_LOW_INT_EN Description STAGE4 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE5 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE6 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE7 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE8 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE9 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE10 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded STAGE11 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded GPIO setup 00 = disable GPIO pin 01 = configure GPIO as an input 10 = configure GPIO as an active low output 11 = configure GPIO as an active high output GPIO input configuration 00 = triggered on negative level 01 = triggered on positive edge 10 = triggered on negative edge 11 = triggered on positive level [5] 0 STAGE5_LOW_INT_EN [6] 0 STAGE6_LOW_INT_EN [7] 0 STAGE7_LOW_INT_EN [8] 0 STAGE8_LOW_INT_EN [9] 0 STAGE9_LOW_INT_EN [10] 0 STAGE10_LOW_INT_EN [11] 0 STAGE11_LOW_INT_EN [13:12] 0 GPIO_SETUP [15:14] 0 GPIO_INPUT_CONFIG Table 25. STAGE_HIGH_INT_EN Register Address 0x006 Data Bit [0] Default Value 0 Type R/W Name STAGE0_HIGH_INT_EN Description STAGE0 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded STAGE1 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded STAGE2 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded STAGE3 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded [1] 0 STAGE1_HIGH_INT_EN [2] 0 STAGE2_HIGH_INT_EN [3] 0 STAGE3_HIGH_INT_EN Rev. 0 | Page 42 of 68 AD7142 Address Data Bit [4] Default Value 0 Type Name STAGE4_HIGH_INT_EN Description STAGE4 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded STAGE5 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded STAGE6 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded STAGE7 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded STAGE8 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded STAGE9 sensor interrupt low limit control 0 = interrupt source disabled 1 = INT asserted if STAGE10_LOW is exceeded STAGE10 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded STAGE11 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded Set unused register bits = 0 [5] 0 STAGE5_HIGH_INT_EN [6] 0 STAGE6_HIGH_INT_EN [7] 0 STAGE7_HIGH_INT_EN [8] 0 STAGE8_HIGH_INT_EN [9] 0 STAGE9_HIGH_INT_EN [10] 0 STAGE10_HIGH_INT_EN [11] 0 STAGE11_HIGH_INT_EN [15:12] Unused Table 26. STAGE_COMPLETE_INT_EN Register Address 0x007 Data Bit [0] Default Value 0 Type R/W Name STAGE0_COMPLETE_EN Description STAGE0 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE0 conversion STAGE1 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE1 conversion STAGE2 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE2 conversion STAGE3 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE3 conversion STAGE4 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE4 conversion STAGE5 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE5 conversion STAGE6 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE6 conversion [1] 0 STAGE1_COMPLETE_EN [2] 0 STAGE2_COMPLETE_EN [3] 0 STAGE3_COMPLETE_EN [4] 0 STAGE4_COMPLETE_EN [5] 0 STAGE5_COMPLETE_EN [6] 0 STAGE6_COMPLETE_EN Rev. 0 | Page 43 of 68 AD7142 Address Data Bit [7] Default Value 0 Type Name STAGE7_COMPLETE_EN Description STAGE7 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE7 conversion STAGE8 conversion complete interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE8 conversion STAGE9 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE9 conversion STAGE10 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE10 conversion STAGE11 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE11 conversion Interrupt control when GPIO input pin changes level 0 = disabled 1 = enabled Set unused register bits = 0 [8] 0 STAGE8_COMPLETE_EN [9] 0 STAGE9_COMPLETE_EN [10] 0 STAGE10_COMPLETE_EN [11] 0 STAGE11_COMPLETE_EN [12] 0 GPIO_INT_EN [15:13] Unused Table 27. STAGE_LOW_LIMIT_INT Register 1 Address 0x008 Data Bit [0] Default Value 0 Type R Name STAGE0_LOW_LIMIT_INT Description STAGE0 CDC conversion low limit interrupt result 1 = indicates STAGE0_LOW_THRESHOLD value was exceeded STAGE1 CDC conversion low limit interrupt result 1 = indicates STAGE1_LOW_THRESHOLD value was exceeded STAGE2 CDC conversion low limit interrupt result 1 = indicates STAGE2_LOW_THRESHOLD value was exceeded STAGE3 CDC conversion low limit interrupt result 1 = indicates STAGE3_LOW_THRESHOLD value was exceeded STAGE4 CDC conversion low limit interrupt result 1 = indicates STAGE4_LOW_THRESHOLD value was exceeded STAGE5 CDC conversion low limit interrupt result 1 = indicates STAGE5_LOW_THRESHOLD value was exceeded STAGE6 CDC conversion low limit interrupt result 1 = indicates STAGE6_LOW_THRESHOLD value was exceeded STAGE7 CDC conversion low limit interrupt result 1 = indicates STAGE7_LOW_THRESHOLD value was exceeded STAGE8 CDC conversion low limit interrupt result 1 = indicates STAGE8_LOW_THRESHOLD value was exceeded STAGE9 CDC conversion low limit interrupt result 1 = indicates STAGE9_LOW_THRESHOLD value was exceeded [1] 0 STAGE1_LOW_LIMIT_INT [2] 0 STAGE2_LOW_LIMIT_INT [3] 0 STAGE3_LOW_LIMIT_INT [4] 0 STAGE4_LOW_LIMIT_INT [5] 0 STAGE5_LOW_LIMIT_INT [6] 0 STAGE6_LOW_LIMIT_INT [7] 0 STAGE7_LOW_LIMIT_INT [8] 0 STAGE8_LOW_LIMIT_INT [9] 0 STAGE9_LOW_LIMIT_INT Rev. 0 | Page 44 of 68 AD7142 Address Data Bit [10] Default Value 0 Type Name STAGE10_LOW_LIMIT_INT Description STAGE10 CDC Conversion Low Limit Interrupt result 1 = indicates STAGE10_LOW_THRESHOLD value was exceeded STAGE11 CDC conversion low limit interrupt result 1 = indicates STAGE11_LOW_THRESHOLD value was exceeded Set unused register bits = 0 [11] 0 STAGE11_LOW_LIMIT_INT [15:12] 1 Unused Registers self-clear to 0 after readback, provided that the limits are not exceeded. Table 28. STAGE_HIGH_LIMIT_INT Register 1 Address 0x009 Data Bit [0] Default Value 0 Type R Name STAGE0_HIGH_LIMIT_INT Description STAGE0 CDC conversion high limit interrupt result 1 = indicates STAGE0_HIGH_THRESHOLD value was exceeded STAGE1 CDC conversion high limit interrupt result 1 = indicates STAGE1_HIGH_THRESHOLD value was exceeded Stage2 CDC conversion high limit interrupt result 1 = indicates STAGE2_HIGH_THRESHOLD value was exceeded STAGE3 CDC conversion high limit interrupt result 1 = indicates STAGE3_HIGH_THRESHOLD value was exceeded STAGE4 CDC conversion high limit interrupt result 1 = indicates STAGE4_HIGH_THRESHOLD value was exceeded STAGE5 CDC conversion high limit interrupt result 1 = indicates STAGE5_HIGH_THRESHOLD value was exceeded STAGE6 CDC conversion high limit interrupt result 1 = indicates STAGE6_HIGH_THRESHOLD value was exceeded STAGE7 CDC conversion high limit interrupt result 1 = indicates STAGE7_HIGH_THRESHOLD value was exceeded STAGE8 CDC conversion high limit interrupt result 1 = indicates STAGE8_HIGH_THRESHOLD value was exceeded STAGE9 CDC conversion high limit interrupt result 1 = indicates STAGE9_HIGH_THRESHOLD value was exceeded STAGE10 CDC conversion high limit interrupt result 1 = indicates STAGE10_HIGH_THRESHOLD value was exceeded STAGE11 CDC conversion high limit interrupt result 1 = indicates STAGE11_HIGH_THRESHOLD value was exceeded Set unused register bits = 0 [1] 0 STAGE1_HIGH_LIMIT_INT [2] 0 STAGE2_HIGH_LIMIT_INT [3] 0 STAGE3_HIGH_LIMIT_INT [4] 0 STAGE4_HIGH_LIMIT_INT [5] 0 STAGE5_HIGH_LIMIT_INT [6] 0 STAGE6_HIGH_LIMIT_INT [7] 0 STAGE7_HIGH_LIMIT_INT [8] 0 STAGE8_HIGH_LIMIT_INT [9] 0 STAGE9_HIGH_LIMIT_INT [10] 0 STAGE10_HIGH_LIMIT_INT [11] 0 STAGE11_HIGH_LIMIT_INT [15:12] 1 Unused Registers self-clear to 0 after readback, provided that the limits are not exceeded. Rev. 0 | Page 45 of 68 AD7142 Table 29. STAGE_COMPLETE_LIMIT_INT Register 7 Address 0x00A Data Bit [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [15:13] 7 Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 Type R Name STAGE0_COMPLETE_STATUS_INT STAGE1_COMPLETE_STATUS_INT STAGE2_COMPLETE_STATUS_INT STAGE3_COMPLETE_STATUS_INT STAGE4_COMPLETE_STATUS_INT STAGE5_COMPLETE_STATUS_INT STAGE6_COMPLETE_STATUS_INT STAGE7_COMPLETE_STATUS_INT STAGE8_COMPLETE_STATUS_INT STAGE9_COMPLETE_STATUS_INT STAGE10_COMPLETE_STATUS_INT STAGE11_COMPLETE_STATUS_INT GPIO_STATUS Unused Description STAGE0 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed STAGE1 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed STAGE2 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed STAGE3 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed STAGE4 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed STAGE5 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed STAGE6 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed STAGE7 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed STAGE8 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed STAGE9 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed STAGE10 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed STAGE11 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed GPIO input pin status 1 = indicates level on GPIO pin has changed Set unused register bits = 0 Registers self-clear to 0 after readback, provided that the limits are not exceeded. Table 30. CDC 16-Bit Conversion Data Registers Address 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value 0 0 0 0 0 0 0 0 0 0 0 0 Type R R R R R R R R R R R R Name ADC_RESULT_S0 ADC_RESULT_S1 ADC_RESULT_S2 ADC_RESULT_S3 ADC_RESULT_S4 ADC_RESULT_S5 ADC_RESULT_S6 ADC_RESULT_S7 ADC_RESULT_S8 ADC_RESULT_S9 ADC_RESULT_S10 ADC_RESULT_S11 Description STAGE0 CDC 16-bit conversion data STAGE1 CDC 16-bit conversion data STAGE2 CDC 16-bit conversion data STAGE3 CDC 16-bit conversion data STAGE4 CDC 16-bit conversion data STAGE5 CDC 16-bit conversion data STAGE6 CDC 16-bit conversion data STAGE7 CDC 16-bit conversion data STAGE8 CDC 16-bit conversion data STAGE9 CDC 16-bit conversion data STAGE10 CDC 16-bit conversion data STAGE11 CDC 16-bit conversion data Rev. 0 | Page 46 of 68 AD7142 Table 31. Device ID Register Address 0x017 Data Bit [3:0] [15:4] Default Value 3 E62 Type R Name REVISION_CODE DEVID Description AD7142 revision code AD7142 device ID = 110110100010 Table 32. Proximity Status Register Address 0x042 Data Bit [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [15:0] Default Value 0 0 0 0 0 0 0 0 0 0 0 0 Type R R R R R R R R R R R R Name STAGE0_PROXIMITY_STATUS STAGE1_PROXIMITY_STATUS STAGE2_PROXIMITY_STATUS STAGE3_PROXIMITY_STATUS STAGE4_PROXIMITY_STATUS STAGE5_PROXIMITY_STATUS STAGE6_PROXIMITY_STATUS STAGE7_PROXIMITY_STATUS STAGE8_PROXIMITY_STATUS STAGE9_PROXIMITY_STATUS STAGE10_PROXIMITY_STATUS STAGE11_PROXIMITY_STATUS Unused Description STAGE0 proximity status register 1 = indicates proximity has been detected on STAGE0 STAGE1 proximity status register 1 = indicates proximity has been detected on STAGE1 STAGE2 proximity status register 1 = indicates proximity has been detected on STAGE2 STAGE3 proximity status register 1 = indicates proximity has been detected on STAGE3 STAGE4 proximity status register 1 = indicates proximity has been detected on STAGE4 STAGE5 proximity status register 1 = indicates proximity has been detected on STAGE5 STAGE6 proximity status register 1 = indicates proximity has been detected on STAGE6 STAGE7 proximity status register 1 = indicates proximity has been detected on STAGE7 STAGE8 proximity status register 1 = indicates proximity has been detected on STAGE8 STAGE9 proximity status register 1 = indicates proximity has been detected on STAGE9 STAGE10 proximity status register 1 = indicates proximity has been detected on STAGE10 STAGE11 proximity status register 1 = indicates proximity has been detected on STAGE11 Set unused register bits = 0 Rev. 0 | Page 47 of 68 AD7142 BANK 2 REGISTERS All address values are expressed in hexadecimal. Table 33. STAGE0 Configuration Registers Address 0x080 0x081 0x082 0x083 0x084 0x085 0x086 0x087 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE0_CONNECTION[6:0] STAGE0_CONNECTION[13:7] STAGE0_AFE_OFFSET STAGE0_SENSITIVITY STAGE0_OFFSET_LOW STAGE0_OFFSET_HIGH STAGE0_OFFSET_HIGH_CLAMP STAGE0_ OFFSET_LOW_CLAMP Description STAGE0 CIN(6:0) connection setup (see Table 45) STAGE0 CIN(13:7) connection setup (see Table 46) STAGE0 AFE offset control (see Table 47) STAGE0 sensitivity control (see Table 48) STAGE0 initial offset low value STAGE0 initial offset high value STAGE0 offset high clamp value STAGE0 offset low clamp value Table 34. STAGE1 Configuration Registers Address 0x088 0x089 0x08A 0x08B 0x08C 0x08D 0x08E 0x08F Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE1_CONNECTION[6:0] STAGE1_CONNECTION[13:7] STAGE1_AFE_OFFSET STAGE1_SENSITIVITY STAGE1_OFFSET_LOW STAGE1_OFFSET_HIGH STAGE1_OFFSET_HIGH_CLAMP STAGE1_OFFSET_LOW_CLAMP Description STAGE1 CIN(6:0) connection setup (see Table 45) STAGE1 CIN(13:7) connection setup (see Table 46) STAGE1 AFE offset control (see Table 47) STAGE1 sensitivity control (see Table 48) STAGE1 initial offset low value STAGE1 initial offset high value STAGE1 offset high clamp value STAGE1 offset low clamp value Table 35. STAGE2 Configuration Registers Address 0x090 0x091 0x092 0x093 0x094 0x095 0x096 0x097 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE2_CONNECTION[6:0] STAGE2_CONNECTION[13:7] STAGE2_AFE_OFFSET STAGE2_SENSITIVITY STAGE2_OFFSET_LOW STAGE2_OFFSET_HIGH STAGE2_OFFSET_HIGH_CLAMP STAGE2_OFFSET_LOW_CLAMP Description STAGE2 CIN(6:0) connection setup (see Table 45) STAGE2 CIN(13:7) connection setup (see Table 46) STAGE2 AFE offset control (see Table 47) STAGE2 sensitivity control (see Table 48) STAGE2 initial offset low value STAGE2 initial offset high value STAGE2 offset high clamp value STAGE2 offset low clamp value Rev. 0 | Page 48 of 68 AD7142 Table 36. STAGE3 Configuration Registers Address 0x098 0x099 0x09A 0x09B 0x09C 0x09D 0x09E 0x09F Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE3_CONNECTION[6:0] STAGE3_CONNECTION[13:7] STAGE3_AFE_OFFSET STAGE3_SENSITIVITY STAGE3_OFFSET_LOW STAGE3_OFFSET_HIGH STAGE3_OFFSET_HIGH_CLAMP STAGE3_OFFSET_LOW_CLAMP Description STAGE3 CIN(6:0) connection setup (see Table 45) STAGE3 CIN(13:7) connection setup (see Table 46) STAGE3 AFE offset control (see Table 47) STAGE3 sensitivity control (see Table 48) STAGE3 initial offset low value STAGE3 initial offset high value STAGE3 offset high clamp value STAGE3 offset low clamp value Table 37. STAGE4 Configuration Registers Address 0x0A0 0x0A1 0x0A2 0x0A3 0x0A4 0x0A5 0x0A6 0x0A7 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE4_CONNECTION[6:0] STAGE4_CONNECTION[13:7] STAGE4_AFE_OFFSET STAGE4_SENSITIVITY STAGE4_OFFSET_LOW STAGE4_OFFSET_HIGH STAGE4_OFFSET_HIGH_CLAMP STAGE4_OFFSET_LOW_CLAMP Description STAGE4 CIN(6:0) connection setup (see Table 45) STAGE4 CIN(13:7) connection setup (see Table 46) STAGE4 AFE offset control (see Table 47) STAGE4 sensitivity control (see Table 48) STAGE4 initial offset low value STAGE4 initial offset high value STAGE4 offset high clamp value STAGE4 offset low clamp value Table 38. STAGE5 Configuration Registers Address 0x0A8 0x0A9 0x0AA 0x0AB 0x0AC 0x0AD 0x0AE 0x0AF Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE5_CONNECTION[6:0] STAGE5_CONNECTION[13:7] STAGE5_AFE_OFFSET STAGE5_SENSITIVITY STAGE5_OFFSET_LOW STAGE5_OFFSET_HIGH STAGE5_OFFSET_HIGH_CLAMP STAGE5_OFFSET_LOW_CLAMP Description STAGE5 CIN(6:0) connection setup (see Table 45) STAGE5 CIN(13:7) connection setup (see Table 46) STAGE5 AFE offset control (see Table 47) STAGE5 sensitivity control (see Table 48) STAGE5 initial offset low value STAGE5 initial offset high value STAGE5 offset high clamp value STAGE5 offset low clamp value Rev. 0 | Page 49 of 68 AD7142 Table 39. STAGE6 Configuration Registers Address 0x0B0 0x0B1 0x0B2 0x0B3 0x0B4 0x0B5 0x0B6 0x0B7 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE6_CONNECTION[6:0] STAGE6_CONNECTION[13:7] STAGE6_AFE_OFFSET STAGE6_SENSITIVITY STAGE6_OFFSET_LOW STAGE6_OFFSET_HIGH STAGE6_OFFSET_HIGH_CLAMP STAGE6_OFFSET_LOW_CLAMP Description STAGE6 CIN(6:0) connection setup (see Table 45) STAGE6 CIN(13:7) connection setup (see Table 46) STAGE6 AFE offset control (see Table 47) STAGE6 sensitivity control (see Table 48) STAGE6 initial offset low value STAGE6 initial offset high value STAGE6 offset high clamp value STAGE6 offset low clamp value Table 40. STAGE7 Configuration Registers Address 0x0B8 0x0B9 0x0BA 0x0BB 0x0BC 0x0BD 0x0BE 0x0BF Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE7_CONNECTION[6:0] STAGE7_CONNECTION[13:7] STAGE7_AFE_OFFSET STAGE7_SENSITIVITY STAGE7_OFFSET_LOW STAGE7_OFFSET_HIGH STAGE7_OFFSET_HIGH_CLAMP STAGE7_OFFSET_LOW_CLAMP Description STAGE7 CIN(6:0) connection setup (see Table 45) STAGE7 CIN(13:7) connection setup (see Table 46) STAGE7 AFE offset control (see Table 47) STAGE7 sensitivity control (see Table 48) STAGE7 initial offset low value STAGE7 initial offset high value STAGE7 offset high clamp value STAGE7 offset low clamp value Table 41. STAGE8 Configuration Registers Address 0x0C0 0x0C1 0x0C2 0x0C3 0x0C4 0x0C5 0x0C6 0x0C7 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE8_CONNECTION[6:0] STAGE8_CONNECTION[13:7] STAGE8_AFE_OFFSET STAGE8_SENSITIVITY STAGE8_OFFSET_LOW STAGE8_OFFSET_HIGH STAGE8_OFFSET_HIGH_CLAMP STAGE8_OFFSET_LOW_CLAMP Description STAGE8 CIN(6:0) connection setup (see Table 45) STAGE8 CIN(13:7) connection setup (see Table 46) STAGE8 AFE offset control (see Table 47) STAGE8 sensitivity control (see Table 48) STAGE8 initial offset low value STAGE8 initial offset high value STAGE8 offset high clamp value STAGE8 offset low clamp value Table 42. STAGE9 Configuration Registers Address 0x0C8 0x0C9 0x0CA 0x0CB 0x0CC 0x0CD 0x0CE 0x0CF Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE9_CONNECTION[6:0] STAGE9_CONNECTION[13:7] STAGE9_AFE_OFFSET STAGE9_SENSITIVITY STAGE9_OFFSET_LOW STAGE9_OFFSET_HIGH STAGE9_OFFSET_HIGH_CLAMP STAGE9_OFFSET_LOW_CLAMP Description STAGE9 CIN(6:0) connection setup (see Table 45) STAGE9 CIN(13:7) connection setup (see Table 46) STAGE9 AFE offset control (see Table 47) STAGE9 sensitivity control (see Table 48) STAGE9 initial offset low value STAGE9 initial offset high value STAGE9 offset high clamp value STAGE9 offset low clamp value Rev. 0 | Page 50 of 68 AD7142 Table 43. STAGE10 Configuration Registers Address 0x0D0 0x0D1 0x0D2 0x0D3 0x0D4 0x0D5 0x0D6 0x0D7 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE10_CONNECTION[6:0] STAGE10_CONNECTION[13:7] STAGE10_AFE_OFFSET STAGE10_SENSITIVITY STAGE10_OFFSET_LOW STAGE10_OFFSET_HIGH STAGE10_OFFSET_HIGH_CLAMP STAGE10_OFFSET_LOW_CLAMP Description STAGE10 CIN(6:0) connection setup (see Table 45) STAGE10 CIN(13:7) connection setup (see Table 46) STAGE10 AFE offset control (see Table 47) STAGE10 sensitivity control (see Table 48) STAGE10 initial offset low value STAGE10 initial offset high value STAGE10 offset high clamp value STAGE10 offset low clamp value Table 44. STAGE11 Configuration Registers Address 0x0D8 0x0D9 0x0DA 0x0DB 0x0DC 0x0DD 0x0DE 0x0DF Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE11_CONNECTION[6:0] STAGE11_CONNECTION[13:7] STAGE11_AFE_OFFSET STAGE11_SENSITIVITY STAGE11_OFFSET_LOW STAGE11_OFFSET_HIGH STAGE11_OFFSET_HIGH_CLAMP STAGE11_OFFSET_LOW_CLAMP Description STAGE11 CIN(6:0) connection setup (see Table 45) STAGE11 CIN(13:7) connection setup (see Table 46) STAGE11 AFE offset control (see Table 47) STAGE11 sensitivity control (see Table 48) STAGE11 initial offset low value STAGE11 initial offset high value STAGE11 offset high clamp value STAGE11 offset low clamp value Table 45. STAGEX Detailed CIN (0:6) Connection Setup Description (X = 0 to 11) Data Bit [1:0] Default Value X Type R/W Name CIN0_CONNECTION_SETUP Description CIN0 connection setup 00 = CIN0 not connected to CDC inputs 01 = CIN0 connected to CDC negative input 10 = CIN0 connected to CDC positive input 11 = CIN0 connected to BIAS (connect unused CIN inputs) CIN1 connection setup 00 = CIN1 not connected to CDC inputs 01 = CIN1 connected to CDC negative input 10 = CIN1 connected to CDC positive input 11 = CIN1 connected to BIAS (connect unused CIN inputs) CIN2 connection setup 00 = CIN2 not connected to CDC inputs 01 = CIN2 connected to CDC negative input 10 = CIN2 connected to CDC positive input 11 = CIN2 connected to BIAS (connect unused CIN inputs) CIN3 connection setup 00 = CIN3 not connected to CDC inputs 01 = CIN3 connected to CDC negative input 10 = CIN3 connected to CDC positive input 11 = CIN3 connected to BIAS (connect unused CIN inputs) CIN4 connection setup 00 = CIN4 not connected to CDC inputs 01 = CIN4 connected to CDC negative input 10 = CIN4 connected to CDC positive input 11 = CIN4 connected to BIAS (connect unused CIN inputs) [3:2] X R/W CIN1_CONNECTION_SETUP [5:4] X R/W CIN2_CONNECTION_SETUP [7:6] X R/W CIN3_CONNECTION_SETUP [9:8] X R/W CIN4_CONNECTION_SETUP Rev. 0 | Page 51 of 68 AD7142 Data Bit [11:10] Default Value X Type R/W Name CIN5_CONNECTION_SETUP Description CIN5 connection setup 00 = CIN5 not connected to CDC inputs 01 = CIN5 connected to CDC negative input 10 = CIN5 connected to CDC positive input 11 = CIN5 connected to BIAS (connect unused CIN inputs) CIN6 connection setup 00 = CIN6 not connected to CDC inputs 01 = CIN6 connected to CDC negative input 10 = CIN6 connected to CDC positive input 11 = CIN6 connected to BIAS (connect unused CIN inputs) [13:12] X R/W CIN6_CONNECTION_SETUP [15:14] X Unused Table 46. STAGEX Detailed CIN (7:13) Connection Setup Description (X = 0 to 11) Data Bit [1:0] Default Value X Type R/W Name CIN7_CONNECTION_SETUP Description CIN7 connection setup 00 = CIN7 not connected to CDC inputs 01 = CIN7 connected to CDC negative input 10 = CIN7 connected to CDC positive input 11 = CIN7 connected to BIAS (connect unused CIN inputs) CIN8 connection setup 00 = CIN8 not connected to CDC inputs 01 = CIN8 connected to CDC negative input 10 = CIN8 connected to CDC positive input 11 = CIN8 connected to BIAS (connect unused CIN inputs) CIN9 connection setup 00 = CIN9 not connected to CDC inputs 01 = CIN9 connected to CDC negative input 10 = CIN9 connected to CDC positive input 11 = CIN9 connected to BIAS (connect unused CIN inputs) CIN10 connection setup 00 = CIN10 not connected to CDC inputs 01 = CIN10 connected to CDC negative input 10 = CIN10 connected to CDC positive input 11 = CIN10 connected to BIAS (connect unused CIN inputs) CIN11 connection setup 00 = CIN11 not connected to CDC inputs 01 = CIN11 connected to CDC negative input 10 = CIN11 connected to CDC positive input 11 = CIN11 connected to BIAS (connect unused CIN inputs) CIN12 connection setup 00 = CIN12 not connected to CDC inputs 01 = CIN12 connected to CDC negative input 10 = CIN12 connected to CDC positive input 11 = CIN12 connected to BIAS (connect unused CIN inputs) [3:2] X R/W CIN8_CONNECTION_SETUP [5:4] X R/W CIN9_CONNECTION_SETUP [7:6] X R/W CIN10_CONNECTION_SETUP [9:8] X R/W CIN11_CONNECTION_SETUP [11:10] X R/W CIN12_CONNECTION_SETUP Rev. 0 | Page 52 of 68 AD7142 Data Bit [13:12] Default Value X Type R/W Name CIN13_CONNECTION_SETUP Description CIN13 connection setup 00 = CIN13 not connected to CDC inputs 01 = CIN13 connected to CDC negative input 10 = CIN13 connected to CDC positive input 11 = CIN13 connected to BIAS (connect unused CIN inputs) Negative AFE offset enable control 0 = enable 1 = disable Positive AFE offset enable control 0 = enable 1 = disable [14] X NEG_AFE_OFFSET_DISABLE [15] X POS_AFE_OFFSET_DISABLE Table 47. STAGEX Detailed Offset Control Description (X = 0 to 11) Data Bit [6:0] [7] Default Value X X Type R/W R/W Name NEG_AFE_OFFSET NEG_AFE_OFFSET_SWAP Description Negative AFE offset setting (20 pF range) 1 LSB value = 0.16 pF of offset Negative AFE offset swap control 0 = NEG_AFE_OFFSET applied to CDC negative input 1 = NEG_AFE_OFFSET applied to CDC positive input Positive AFE offset setting (20 pF range) 1 LSB value = 0.16 pF of offset Positive AFE offset swap control 0 = POS_AFE_OFFSET applied to CDC positive input 1 = POS_AFE_OFFSET applied to CDC negative input [14:8] [15] X X R/W R/W POS_AFE_OFFSET POS_AFE_OFFSET_SWAP Table 48. STAGEX Detailed Sensitivity Control Description (X = 0 to 11) Data Bit [3:0] Default Value X Type R/W Name NEG_THRESHOLD_SENSITIVITY Description Negative threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% Negative peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level Positive threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% Positive peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [6:4] X R/W NEG_PEAK_DETECT [7] [11:8] X X R/W R/W Unused POS_THRESHOLD_SENSITIVITY [14:12] X R/W POS_PEAK_DETECT [15] X R/W Unused Rev. 0 | Page 53 of 68 AD7142 BANK 3 REGISTERS All address values are expressed in hexadecimal. Table 49. STAGE0 Results Registers Address 0x0E0 0x0E1 0x0E2 0x0E3 0x0E4 0x0E5 0x0E6 0x0E7 0x0E8 0x0E9 0x0EA 0x0EB 0x0EC 0x0ED 0x0EE 0x0EF 0x0F0 0x0F1 0x0F2 0x0F3 0x0F4 0x0F5 0x0F6 0x0F7 0x0F8 0x0F9 0x0FA 0x0FB 0x0FC 0x0FD 0x0FE 0x0FF 0x100 0x101 0x102 0x103 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE0_CONV_DATA STAGE0_FF_WORD0 STAGE0_FF_WORD1 STAGE0_FF_WORD2 STAGE0_FF_WORD3 STAGE0_FF_WORD4 STAGE0_FF_WORD5 STAGE0_FF_WORD6 STAGE0_FF_WORD7 STAGE0_SF_WORD0 STAGE0_SF_WORD1 STAGE0_SF_WORD2 STAGE0_SF_WORD3 STAGE0_SF_WORD4 STAGE0_SF_WORD5 STAGE0_SF_WORD6 STAGE0_SF_WORD7 STAGE0_SF_AMBIENT STAGE0_FF_AVG STAGE0_PEAK_DETECT_WORD0 STAGE0_PEAK_DETECT_WORD1 STAGE0_MAX_WORD0 STAGE0_MAX_WORD1 STAGE0_MAX_WORD2 STAGE0_MAX_WORD3 STAGE0_MAX_AVG STAGE0_HIGH_THRESHOLD STAGE0_MAX_TEMP STAGE0_MIN_WORD0 STAGE0_MIN_WORD1 STAGE0_MIN_WORD2 STAGE0_MIN_WORD3 STAGE0_MIN_AVG STAGE0_LOW_THRESHOLD STAGE0_MIN_TEMP Unused Description STAGE0 CDC 16-bit conversion data (copy of data in STAGE0_CONV_DATA register) STAGE0 fast FIFO WORD0 STAGE0 fast FIFO WORD1 STAGE0 fast FIFO WORD2 STAGE0 fast FIFO WORD3 STAGE0 fast FIFO WORD4 STAGE0 fast FIFO WORD5 STAGE0 fast FIFO WORD6 STAGE0 fast FIFO WORD7 STAGE0 slow FIFO WORD0 STAGE0 slow FIFO WORD1 STAGE0 slow FIFO WORD2 STAGE0 slow FIFO WORD3 STAGE0 slow FIFO WORD4 STAGE0 slow FIFO WORD5 STAGE0 slow FIFO WORD6 STAGE0 slow FIFO WORD7 STAGE0 slow FIFO ambient value STAGE0 fast FIFO average value STAGE0 peak FIFO WORD0 value STAGE0 peak FIFO WORD1 value STAGE0 maximum value FIFO WORD0 STAGE0 maximum value FIFO WORD1 STAGE0 maximum value FIFO WORD2 STAGE0 maximum value FIFO WORD3 STAGE0 average maximum FIFO value STAGE0 high threshold value STAGE0 temporary maximum value STAGE0 minimum value FIFO WORD0 STAGE0 minimum value FIFO WORD1 STAGE0 minimum value FIFO WORD2 STAGE0 minimum value FIFO WORD3 STAGE0 average minimum FIFO value STAGE0 low threshold value STAGE0 temporary minimum value Rev. 0 | Page 54 of 68 AD7142 Table 50. STAGE1 Results Registers Address 0x104 0x105 0x106 0x107 0x108 0x109 0x10A 0x10B 0x10C 0x10D 0x10E 0x10F 0x110 0x111 0x112 0x113 0x114 0x115 0x116 0x117 0x118 0x119 0x11A 0x11B 0x11C 0x11D 0x11E 0x11F 0x120 0x121 0x122 0x123 0x124 0x125 0x126 0x127 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE1_CONV_DATA STAGE1_FF_WORD0 STAGE1_FF_WORD1 STAGE1_FF_WORD2 STAGE1_FF_WORD3 STAGE1_FF_WORD4 STAGE1_FF_WORD5 STAGE1_FF_WORD6 STAGE1_FF_WORD7 STAGE1_SF_WORD0 STAGE1_SF_WORD1 STAGE1_SF_WORD2 STAGE1_SF_WORD3 STAGE1_SF_WORD4 STAGE1_SF_WORD5 STAGE1_SF_WORD6 STAGE1_SF_WORD7 STAGE1_SF_AMBIENT STAGE1_FF_AVG STAGE1_CDC_WORD0 STAGE1_CDC_WORD1 STAGE1_MAX_WORD0 STAGE1_MAX_WORD1 STAGE1_MAX_WORD2 STAGE1_MAX_WORD3 STAGE1_MAX_AVG STAGE1_HIGH_THRESHOLD STAGE1_MAX_TEMP STAGE1_MIN_WORD0 STAGE1_MIN_WORD1 STAGE1_MIN_WORD2 STAGE1_MIN_WORD3 STAGE1_MIN_AVG STAGE1_LOW_THRESHOLD STAGE1_MIN_TEMP Unused Description STAGE1 CDC 16-bit conversion data (copy of data in STAGE1_CONV_DATA register) STAGE1 fast FIFO WORD0 STAGE1 fast FIFO WORD1 STAGE1 fast FIFO WORD2 STAGE1 fast FIFO WORD3 STAGE1 fast FIFO WORD4 STAGE1 fast FIFO WORD5 STAGE1 fast FIFO WORD6 STAGE1 fast FIFO WORD7 STAGE1 slow FIFO WORD0 STAGE1 slow FIFO WORD1 STAGE1 slow FIFO WORD2 STAGE1 slow FIFO WORD3 STAGE1 slow FIFO WORD4 STAGE1 slow FIFO WORD5 STAGE1 slow FIFO WORD6 STAGE1 slow FIFO WORD7 STAGE1 slow FIFO ambient value STAGE1 fast FIFO average value STAGE1 CDC FIFO WORD0 STAGE1 CDC FIFO WORD1 STAGE1 maximum value FIFO WORD0 STAGE1 maximum value FIFO WORD1 STAGE1 maximum value FIFO WORD2 STAGE1 maximum value FIFO WORD3 STAGE1 average maximum FIFO value STAGE1 high threshold value STAGE1 temporary maximum value STAGE1 minimum value FIFO WORD0 STAGE1 minimum value FIFO WORD1 STAGE1 minimum value FIFO WORD2 STAGE1 minimum value FIFO WORD3 STAGE1 average minimum FIFO value STAGE1 low threshold value STAGE1 temporary minimum value Rev. 0 | Page 55 of 68 AD7142 Table 51. STAGE2 Results Registers Address 0x128 0x129 0x12A 0x12B 0x12C 0x12D 0x12E 0x12F 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138 0x139 0x13A 0x13B 0x13C 0x13D 0x13E 0x13F 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14A 0x14B Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE2_CONV_DATA STAGE2_FF_WORD0 STAGE2_FF_WORD1 STAGE2_FF_WORD2 STAGE2_FF_WORD3 STAGE2_FF_WORD4 STAGE2_FF_WORD5 STAGE2_FF_WORD6 STAGE2_FF_WORD7 STAGE2_SF_WORD0 STAGE2_SF_WORD1 STAGE2_SF_WORD2 STAGE2_SF_WORD3 STAGE2_SF_WORD4 STAGE2_SF_WORD5 STAGE2_SF_WORD6 STAGE2_SF_WORD7 STAGE2_SF_AMBIENT STAGE2_FF_AVG STAGE2_CDC_WORD0 STAGE2_CDC_WORD1 STAGE2_MAX_WORD0 STAGE2_MAX_WORD1 STAGE2_MAX_WORD2 STAGE2_MAX_WORD3 STAGE2_MAX_AVG STAGE2_HIGH_THRESHOLD STAGE2_MAX_TEMP STAGE2_MIN_WORD0 STAGE2_MIN_WORD1 STAGE2_MIN_WORD2 STAGE2_MIN_WORD3 STAGE2_MIN_AVG STAGE2_LOW_THRESHOLD STAGE2_MIN_TEMP Unused Description STAGE2 CDC 16-bit conversion data (copy of data in STAGE2_CONV_DATA register) STAGE2 fast FIFO WORD0 STAGE2 fast FIFO WORD1 STAGE2 fast FIFO WORD2 STAGE2 fast FIFO WORD3 STAGE2 fast FIFO WORD4 STAGE2 fast FIFO WORD5 STAGE2 fast FIFO WORD6 STAGE2 fast FIFO WORD7 STAGE2 slow FIFO WORD0 STAGE2 slow FIFO WORD1 STAGE2 slow FIFO WORD2 STAGE2 slow FIFO WORD3 STAGE2 slow FIFO WORD4 STAGE2 slow FIFO WORD5 STAGE2 slow FIFO WORD6 STAGE2 slow FIFO WORD7 STAGE2 slow FIFO ambient value STAGE2 fast FIFO average value STAGE2 CDC FIFO WORD0 STAGE2 CDC FIFO WORD1 STAGE2 maximum value FIFO WORD0 STAGE2 maximum value FIFO WORD1 STAGE2 maximum value FIFO WORD2 STAGE2 maximum value FIFO WORD3 STAGE2 average maximum FIFO value STAGE2 high threshold value STAGE2 temporary maximum value STAGE2 minimum value FIFO WORD0 STAGE2 minimum value FIFO WORD1 STAGE2 minimum value FIFO WORD2 STAGE2 minimum value FIFO WORD3 STAGE2 average minimum FIFO value STAGE2 low threshold value STAGE2 temporary minimum value Rev. 0 | Page 56 of 68 AD7142 Table 52. STAGE3 Results Registers Address 0x14C 0x14D 0x14E 0x14F 0x150 0x151 0x152 0x153 0x154 0x155 0x156 0x157 0x158 0x159 0x15A 0x15B 0x15C 0x15D 0x15E 0x15F 0x160 0x161 0x162 0x163 0x164 0x165 0x166 0x167 0x168 0x169 0x16A 0x16B 0x16C 0x16D 0x16E 0x16F Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE3_CONV_DATA STAGE3_FF_WORD0 STAGE3_FF_WORD1 STAGE3_FF_WORD2 STAGE3_FF_WORD3 STAGE3_FF_WORD4 STAGE3_FF_WORD5 STAGE3_FF_WORD6 STAGE3_FF_WORD7 STAGE3_SF_WORD0 STAGE3_SF_WORD1 STAGE3_SF_WORD2 STAGE3_SF_WORD3 STAGE3_SF_WORD4 STAGE3_SF_WORD5 STAGE3_SF_WORD6 STAGE3_SF_WORD7 STAGE3_SF_AMBIENT STAGE3_FF_AVG STAGE3_CDC_WORD0 STAGE3_CDC_WORD1 STAGE3_MAX_WORD0 STAGE3_MAX_WORD1 STAGE3_MAX_WORD2 STAGE3_MAX_WORD3 STAGE3_MAX_AVG STAGE3_HIGH_THRESHOLD STAGE3_MAX_TEMP STAGE3_MIN_WORD0 STAGE3_MIN_WORD1 STAGE3_MIN_WORD2 STAGE3_MIN_WORD3 STAGE3_MIN_AVG STAGE3_LOW_THRESHOLD STAGE3_MIN_TEMP Unused Description STAGE3 CDC 16-bit conversion data (copy of data in STAGE3_CONV_DATA register) STAGE3 fast FIFO WORD0 STAGE3 fast FIFO WORD1 STAGE3 fast FIFO WORD2 STAGE3 fast FIFO WORD3 STAGE3 fast FIFO WORD4 STAGE3 fast FIFO WORD5 STAGE3 fast FIFO WORD6 STAGE3 fast FIFO WORD7 STAGE3 slow FIFO WORD0 STAGE3 slow FIFO WORD1 STAGE3 slow FIFO WORD2 STAGE3 slow FIFO WORD3 STAGE3 slow FIFO WORD4 STAGE3 slow FIFO WORD5 STAGE3 slow FIFO WORD6 STAGE3 slow FIFO WORD7 STAGE3 slow FIFO ambient value STAGE3 fast FIFO average value STAGE3 CDC FIFO WORD0 STAGE3 CDC FIFO WORD1 STAGE3 maximum value FIFO WORD0 STAGE3 maximum value FIFO WORD1 STAGE3 maximum value FIFO WORD2 STAGE3 maximum value FIFO WORD3 STAGE3 average maximum FIFO value STAGE3 high threshold value STAGE3 temporary maximum value STAGE3 minimum value FIFO WORD0 STAGE3 minimum value FIFO WORD1 STAGE3 minimum value FIFO WORD2 STAGE3 minimum value FIFO WORD3 STAGE3 average minimum FIFO value STAGE3 low threshold value STAGE3 temporary minimum value Rev. 0 | Page 57 of 68 AD7142 Table 53. STAGE4 Results Registers Address 0x170 0x171 0x172 0x173 0x174 0x175 0x176 0x177 0x178 0x179 0x17A 0x17B 0x17C 0x17D 0x17E 0x17F 0x180 0x181 0x182 0x183 0x184 0x185 0x186 0x187 0x188 0x189 0x18A 0x18B 0x18C 0x18D 0x18E 0x18F 0x190 0x191 0x192 0x193 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE4_CONV_DATA STAGE4_FF_WORD0 STAGE4_FF_WORD1 STAGE4_FF_WORD2 STAGE4_FF_WORD3 STAGE4_FF_WORD4 STAGE4_FF_WORD5 STAGE4_FF_WORD6 STAGE4_FF_WORD7 STAGE4_SF_WORD0 STAGE4_SF_WORD1 STAGE4_SF_WORD2 STAGE4_SF_WORD3 STAGE4_SF_WORD4 STAGE4_SF_WORD5 STAGE4_SF_WORD6 STAGE4_SF_WORD7 STAGE4_SF_AMBIENT STAGE4_FF_AVG STAGE4_CDC_WORD0 STAGE4_CDC_WORD1 STAGE4_MAX_WORD0 STAGE4_MAX_WORD1 STAGE4_MAX_WORD2 STAGE4_MAX_WORD3 STAGE4_MAX_AVG STAGE4_HIGH_THRESHOLD STAGE4_MAX_TEMP STAGE4_MIN_WORD0 STAGE4_MIN_WORD1 STAGE4_MIN_WORD2 STAGE4_MIN_WORD3 STAGE4_MIN_AVG STAGE4_LOW_THRESHOLD STAGE4_MIN_TEMP Unused Description STAGE4 CDC 16-bit conversion data (copy of data in STAGE4_CONV_DATA register) STAGE4 fast FIFO WORD0 STAGE4 fast FIFO WORD1 STAGE4 fast FIFO WORD2 STAGE4 fast FIFO WORD3 STAGE4 fast FIFO WORD4 STAGE4 fast FIFO WORD5 STAGE4 fast FIFO WORD6 STAGE4 fast FIFO WORD7 STAGE4 slow FIFO WORD0 STAGE4 slow FIFO WORD1 STAGE4 slow FIFO WORD2 STAGE4 slow FIFO WORD3 STAGE4 slow FIFO WORD4 STAGE4 slow FIFO WORD5 STAGE4 slow FIFO WORD6 STAGE4 slow FIFO WORD7 STAGE4 slow FIFO ambient value STAGE4 fast FIFO average value STAGE4 CDC FIFO WORD0 STAGE4 CDC FIFO WORD1 STAGE4 maximum value FIFO WORD0 STAGE4 maximum value FIFO WORD1 STAGE4 maximum value FIFO WORD2 STAGE4 maximum value FIFO WORD3 STAGE4 average maximum FIFO value STAGE4 high threshold value STAGE4 temporary maximum value STAGE4 minimum value FIFO WORD0 STAGE4 minimum value FIFO WORD1 STAGE4 minimum value FIFO WORD2 STAGE4 minimum value FIFO WORD3 STAGE4 average minimum FIFO value STAGE4 low threshold value STAGE4 temporary minimum value Rev. 0 | Page 58 of 68 AD7142 Table 54. STAGE5 Results Registers Address 0x194 0x195 0x196 0x197 0x198 0x199 0x19A 0x19B 0x19C 0x19D 0x19E 0x19F 0x1A0 0x1A1 0x1A2 0x1A3 0x1A4 0x1A5 0x1A6 0x1A7 0x1A8 0x1A9 0x1AA 0x1AB 0x1AC 0x1AD 0x1AE 0x1AF 0x1B0 0x1B1 0x1B2 0x1B3 0x1B4 0x1B5 0x1B6 0x1B7 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE5_CONV_DATA STAGE5_FF_WORD0 STAGE5_FF_WORD1 STAGE5_FF_WORD2 STAGE5_FF_WORD3 STAGE5_FF_WORD4 STAGE5_FF_WORD5 STAGE5_FF_WORD6 STAGE5_FF_WORD7 STAGE5_SF_WORD0 STAGE5_SF_WORD1 STAGE5_SF_WORD2 STAGE5_SF_WORD3 STAGE5_SF_WORD4 STAGE5_SF_WORD5 STAGE5_SF_WORD6 STAGE5_SF_WORD7 STAGE5_SF_AMBIENT STAGE5_FF_AVG STAGE5_CDC_WORD0 STAGE5_CDC_WORD1 STAGE5_MAX_WORD0 STAGE5_MAX_WORD1 STAGE5_MAX_WORD2 STAGE5_MAX_WORD3 STAGE5_MAX_AVG STAGE5_HIGH_THRESHOLD STAGE5_MAX_TEMP STAGE5_MIN_WORD0 STAGE5_MIN_WORD1 STAGE5_MIN_WORD2 STAGE5_MIN_WORD3 STAGE5_MIN_AVG STAGE5_LOW_THRESHOLD STAGE5_MIN_TEMP Unused Description STAGE5 CDC 16-bit conversion data (copy of data in STAGE5_CONV_DATA register) STAGE5 fast FIFO WORD0 STAGE5 fast FIFO WORD1 STAGE5 fast FIFO WORD2 STAGE5 fast FIFO WORD3 STAGE5 fast FIFO WORD4 STAGE5 fast FIFO WORD5 STAGE5 fast FIFO WORD6 STAGE5 fast FIFO WORD7 STAGE5 slow FIFO WORD0 STAGE5 slow FIFO WORD1 STAGE5 slow FIFO WORD2 STAGE5 slow FIFO WORD3 STAGE5 slow FIFO WORD4 STAGE5 slow FIFO WORD5 STAGE5 slow FIFO WORD6 STAGE5 slow FIFO WORD7 STAGE5 slow FIFO ambient value STAGE5 fast FIFO average value STAGE5 CDC FIFO WORD0 STAGE5 CDC FIFO WORD1 STAGE5 maximum value FIFO WORD0 STAGE5 maximum value FIFO WORD1 STAGE5 maximum value FIFO WORD2 STAGE5 maximum value FIFO WORD3 STAGE5 average maximum FIFO value STAGE5 high threshold value STAGE5 temporary maximum value STAGE5 minimum value FIFO WORD0 STAGE5 minimum value FIFO WORD1 STAGE5 minimum value FIFO WORD2 STAGE5 minimum value FIFO WORD3 STAGE5 average minimum FIFO value STAGE5 low threshold value STAGE5 temporary minimum value Rev. 0 | Page 59 of 68 AD7142 Table 55. STAGE6 Results Registers Address 0x1B8 0x1B9 0x1BA 0x1BB 0x1BC 0x1BD 0x1BE 0x1BF 0x1C0 0x1C1 0x1C2 0x1C3 0x1C4 0x1C5 0x1C6 0x1C7 0x1C8 0x1C9 0x1CA 0x1CB 0x1CC 0x1CD 0x1CE 0x1CF 0x1D0 0x1D1 0x1D2 0x1D3 0x1D4 0x1D5 0x1D6 0x1D7 0x1D8 0x1D9 0x1DA 0x1DB Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE6_CONV_DATA STAGE6_FF_WORD0 STAGE6_FF_WORD1 STAGE6_FF_WORD2 STAGE6_FF_WORD3 STAGE6_FF_WORD4 STAGE6_FF_WORD5 STAGE6_FF_WORD6 STAGE6_FF_WORD7 STAGE6_SF_WORD0 STAGE6_SF_WORD1 STAGE6_SF_WORD2 STAGE6_SF_WORD3 STAGE6_SF_WORD4 STAGE6_SF_WORD5 STAGE6_SF_WORD6 STAGE6_SF_WORD7 STAGE6_SF_AMBIENT STAGE6_FF_AVG STAGE6_CDC_WORD0 STAGE6_CDC_WORD1 STAGE6_MAX_WORD0 STAGE6_MAX_WORD1 STAGE6_MAX_WORD2 STAGE6_MAX_WORD3 STAGE6_MAX_AVG STAGE6_HIGH_THRESHOLD STAGE6_MAX_TEMP STAGE6_MIN_WORD0 STAGE6_MIN_WORD1 STAGE6_MIN_WORD2 STAGE6_MIN_WORD3 STAGE6_MIN_AVG STAGE6_LOW_THRESHOLD STAGE6_MIN_TEMP Unused Description STAGE6 CDC 16-bit conversion data (copy of data in STAGE6_CONV_DATA register) STAGE6 fast FIFO WORD0 STAGE6 fast FIFO WORD1 STAGE6 fast FIFO WORD2 STAGE6 fast FIFO WORD3 STAGE6 fast FIFO WORD4 STAGE6 fast FIFO WORD5 STAGE6 fast FIFO WORD6 STAGE6 fast FIFO WORD7 STAGE6 slow FIFO WORD0 STAGE6 slow FIFO WORD1 STAGE6 slow FIFO WORD2 STAGE6 slow FIFO WORD3 STAGE6 slow FIFO WORD4 STAGE6 slow FIFO WORD5 STAGE6 slow FIFO WORD6 STAGE6 slow FIFO WORD7 STAGE6 slow FIFO ambient value STAGE6 fast FIFO average value STAGE0 CDC FIFO WORD0 STAGE6 CDC FIFO WORD1 STAGE6 maximum value FIFO WORD0 STAGE6 maximum value FIFO WORD1 STAGE6 maximum value FIFO WORD2 STAGE6 maximum value FIFO WORD3 STAGE6 average maximum FIFO value STAGE6 high threshold value STAGE6 temporary maximum value STAGE6 minimum value FIFO WORD0 STAGE6 minimum value FIFO WORD1 STAGE6 minimum value FIFO WORD2 STAGE6 minimum value FIFO WORD3 STAGE6 average minimum FIFO value STAGE6 low threshold value STAGE6 temporary minimum value Rev. 0 | Page 60 of 68 AD7142 Table 56. STAGE7 Results Registers Address 0x1DC 0x1DD 0x1DE 0x1DF 0x1E0 0x1E1 0x1E2 0x1E3 0x1E4 0x1E5 0x1E6 0x1E7 0x1E8 0x1E9 0x1EA 0x1EB 0x1EC 0x1ED 0x1EE 0x1EF 0x1F0 0x1F1 0x1F2 0x1F3 0x1F4 0x1F5 0x1F6 0x1F7 0x1F8 0x1F9 0x1FA 0x1FB 0x1FC 0x1FD 0x1FE 0x1FF Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE7_CONV_DATA STAGE7_FF_WORD0 STAGE7_FF_WORD1 STAGE7_FF_WORD2 STAGE7_FF_WORD3 STAGE7_FF_WORD4 STAGE7_FF_WORD5 STAGE7_FF_WORD6 STAGE7_FF_WORD7 STAGE7_SF_WORD0 STAGE7_SF_WORD1 STAGE7_SF_WORD2 STAGE7_SF_WORD3 STAGE7_SF_WORD4 STAGE7_SF_WORD5 STAGE7_SF_WORD6 STAGE7_SF_WORD7 STAGE7_SF_AMBIENT STAGE7_FF_AVG STAGE7_CDC_WORD0 STAGE7_CDC_WORD1 STAGE7_MAX_WORD0 STAGE7_MAX_WORD1 STAGE7_MAX_WORD2 STAGE7_MAX_WORD3 STAGE7_MAX_AVG STAGE7_HIGH_THRESHOLD STAGE7_MAX_TEMP STAGE7_MIN_WORD0 STAGE7_MIN_WORD1 STAGE7_MIN_WORD2 STAGE7_MIN_WORD3 STAGE7_MIN_AVG STAGE7_LOW_THRESHOLD STAGE7_MIN_TEMP Unused Description STAGE7 CDC 16-bit conversion data (copy of data in STAGE7_CONV_DATA register) STAGE7 fast FIFO WORD0 STAGE7 fast FIFO WORD1 STAGE7 fast FIFO WORD2 STAGE7 fast FIFO WORD3 STAGE7 fast FIFO WORD4 STAGE7 fast FIFO WORD5 STAGE7 fast FIFO WORD6 STAGE7 fast FIFO WORD7 STAGE7 slow FIFO WORD0 STAGE7 slow FIFO WORD1 STAGE7 slow FIFO WORD2 STAGE7 slow FIFO WORD3 STAGE7 slow FIFO WORD4 STAGE7 slow FIFO WORD5 STAGE7 slow FIFO WORD6 STAGE7 slow FIFO WORD7 STAGE7 slow FIFO ambient value STAGE7 fast FIFO average value STAGE7 CDC FIFO WORD0 STAGE7 CDC FIFO WORD1 STAGE7 maximum value FIFO WORD0 STAGE7 maximum value FIFO WORD1 STAGE7 maximum value FIFO WORD2 STAGE7 maximum value FIFO WORD3 STAGE7 average maximum FIFO value STAGE7 high threshold value STAGE7 temporary maximum value STAGE7 minimum value FIFO WORD0 STAGE7 minimum value FIFO WORD1 STAGE7 minimum value FIFO WORD2 STAGE7 minimum value FIFO WORD3 STAGE7 average minimum FIFO value STAGE7 low threshold value STAGE7 temporary minimum value Rev. 0 | Page 61 of 68 AD7142 Table 57. STAGE8 Results Registers Address 0x200 0x201 0x202 0x203 0x204 0x205 0x206 0x207 0x208 0x209 0x20A 0x20B 0x20C 0x20D 0x20E 0x20F 0x210 0x211 0x212 0x213 0x214 0x215 0x216 0x217 0x218 0x219 0x21A 0x21B 0x21C 0x21D 0x21E 0x21F 0x220 0x221 0x222 0x223 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE8_CONV_DATA STAGE8_FF_WORD0 STAGE8_FF_WORD1 STAGE8_FF_WORD2 STAGE8_FF_WORD3 STAGE8_FF_WORD4 STAGE8_FF_WORD5 STAGE8_FF_WORD6 STAGE8_FF_WORD7 STAGE8_SF_WORD0 STAGE8_SF_WORD1 STAGE8_SF_WORD2 STAGE8_SF_WORD3 STAGE8_SF_WORD4 STAGE8_SF_WORD5 STAGE8_SF_WORD6 STAGE8_SF_WORD7 STAGE8_SF_AMBIENT STAGE8_FF_AVG STAGE8_CDC_WORD0 STAGE8_CDC_WORD1 STAGE8_MAX_WORD0 STAGE8_MAX_WORD1 STAGE8_MAX_WORD2 STAGE8_MAX_WORD3 STAGE8_MAX_AVG STAGE8_HIGH_THRESHOLD STAGE8_MAX_TEMP STAGE8_MIN_WORD0 STAGE8_MIN_WORD1 STAGE8_MIN_WORD2 STAGE8_MIN_WORD3 STAGE8_MIN_AVG STAGE8_LOW_THRESHOLD STAGE8_MIN_TEMP Unused Description STAGE8 CDC 16-bit conversion data (copy of data in STAGE8_CONV_DATA register) STAGE8 fast FIFO WORD0 STAGE8 fast FIFO WORD1 STAGE8 fast FIFO WORD2 STAGE8 fast FIFO WORD3 STAGE8 fast FIFO WORD4 STAGE8 fast FIFO WORD5 STAGE8 fast FIFO WORD6 STAGE8 fast FIFO WORD7 STAGE8 slow FIFO WORD0 STAGE8 slow FIFO WORD1 STAGE8 slow FIFO WORD2 STAGE8 slow FIFO WORD3 STAGE8 slow FIFO WORD4 STAGE8 slow FIFO WORD5 STAGE8 slow FIFO WORD6 STAGE8 slow FIFO WORD7 STAGE8 slow FIFO ambient value STAGE8 fast FIFO average value STAGE8 CDC FIFO WORD0 STAGE8 CDC FIFO WORD1 STAGE8 maximum value FIFO WORD0 STAGE8 maximum value FIFO WORD1 STAGE8 maximum value FIFO WORD2 STAGE8 maximum value FIFO WORD3 STAGE8 average maximum FIFO value STAGE8 high threshold value STAGE8 temporary maximum value STAGE8 minimum value FIFO WORD0 STAGE8 minimum value FIFO WORD1 STAGE8 minimum value FIFO WORD2 STAGE8 minimum value FIFO WORD3 STAGE8 average minimum FIFO value STAGE8 low threshold value STAGE7 temporary minimum value Rev. 0 | Page 62 of 68 AD7142 Table 58. STAGE9 Results Registers Address 0x224 0x225 0x226 0x227 0x228 0x229 0x22A 0x22B 0x22C 0x22D 0x22E 0x22F 0x230 0x231 0x232 0x233 0x234 0x235 0x236 0x237 0x238 0x239 0x23A 0x23B 0x23C 0x23D 0x23E 0x23F 0x240 0x241 0x242 0x243 0x244 0x245 0x246 0x247 Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE9_CONV_DATA STAGE9_FF_WORD0 STAGE9_FF_WORD1 STAGE9_FF_WORD2 STAGE9_FF_WORD3 STAGE9_FF_WORD4 STAGE9_FF_WORD5 STAGE9_FF_WORD6 STAGE9_FF_WORD7 STAGE9_SF_WORD0 STAGE9_SF_WORD1 STAGE9_SF_WORD2 STAGE9_SF_WORD3 STAGE9_SF_WORD4 STAGE9_SF_WORD5 STAGE9_SF_WORD6 STAGE9_SF_WORD7 STAGE9_SF_AMBIENT STAGE9_FF_AVG STAGE9_CDC_WORD0 STAGE9_CDC_WORD1 STAGE9_MAX_WORD0 STAGE9_MAX_WORD1 STAGE9_MAX_WORD2 STAGE9_MAX_WORD3 STAGE9_MAX_AVG STAGE9_HIGH_THRESHOLD STAGE9_MAX_TEMP STAGE9_MIN_WORD0 STAGE9_MIN_WORD1 STAGE9_MIN_WORD2 STAGE9_MIN_WORD3 STAGE9_MIN_AVG STAGE9_LOW_THRESHOLD STAGE9_MIN_TEMP Unused Description STAGE9 CDC 16-bit conversion data (copy of data in STAGE9_CONV_DATA register) STAGE9 fast FIFO WORD0 STAGE9 fast FIFO WORD1 STAGE9 fast FIFO WORD2 STAGE9 fast FIFO WORD3 STAGE9 fast FIFO WORD4 STAGE9 fast FIFO WORD5 STAGE9 fast FIFO WORD6 STAGE9 fast FIFO WORD7 STAGE9 slow FIFO WORD0 STAGE9 slow FIFO WORD1 STAGE9 slow FIFO WORD2 STAGE9 slow FIFO WORD3 STAGE9 slow FIFO WORD4 STAGE9 slow FIFO WORD5 STAGE9 slow FIFO WORD6 STAGE9 slow FIFO WORD7 STAGE9 slow FIFO ambient value STAGE9 fast FIFO average value STAGE9 CDC FIFO WORD0 STAGE9 CDC FIFO WORD1 STAGE9 maximum value FIFO WORD0 STAGE9 maximum value FIFO WORD1 STAGE9 maximum value FIFO WORD2 STAGE9 maximum value FIFO WORD3 STAGE9 average maximum FIFO value STAGE9 high threshold value STAGE9 temporary maximum value STAGE9 minimum value FIFO WORD0 STAGE9 minimum value FIFO WORD1 STAGE9 minimum value FIFO WORD2 STAGE9 minimum value FIFO WORD3 STAGE9 average minimum FIFO value STAGE9 low threshold value STAGE9 temporary minimum value Rev. 0 | Page 63 of 68 AD7142 Table 59. STAGE10 Results Registers Address 0x248 0x249 0x24A 0x24B 0x24C 0x24D 0x24E 0x24F 0x250 0x251 0x252 0x253 0x254 0x255 0x256 0x257 0x258 0x259 0x25A 0x25B 0x25C 0x25D 0x25E 0x25F 0x260 0x261 0x262 0x263 0x264 0x265 0x266 0x267 0x268 0x269 0x26A 0x26B Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE10_CONV_DATA STAGE10_FF_WORD0 STAGE10_FF_WORD1 STAGE10_FF_WORD2 STAGE10_FF_WORD3 STAGE10_FF_WORD4 STAGE10_FF_WORD5 STAGE10_FF_WORD6 STAGE10_FF_WORD7 STAGE10_SF_WORD0 STAGE10_SF_WORD1 STAGE10_SF_WORD2 STAGE10_SF_WORD3 STAGE10_SF_WORD4 STAGE10_SF_WORD5 STAGE10_SF_WORD6 STAGE10_SF_WORD7 STAGE10_SF_AMBIENT STAGE10_FF_AVG STAGE10_CDC_WORD0 STAGE10_CDC_WORD1 STAGE10_MAX_WORD0 STAGE10_MAX_WORD1 STAGE10_MAX_WORD2 STAGE10_MAX_WORD3 STAGE10_MAX_AVG STAGE10_HIGH_THRESHOLD STAGE10_MAX_TEMP STAGE10_MIN_WORD0 STAGE10_MIN_WORD1 STAGE10_MIN_WORD2 STAGE10_MIN_WORD3 STAGE10_MIN_AVG STAGE10_LOW_THRESHOLD STAGE10_MIN_TEMP Unused Description STAGE10 CDC 16-bit conversion data (copy of data in STAGE10_CONV_DATA register) STAGE10 fast FIFO WORD0 STAGE10 fast FIFO WORD1 STAGE10 fast FIFO WORD2 STAGE10 fast FIFO WORD3 STAGE10 fast FIFO WORD4 STAGE10 fast FIFO WORD5 STAGE10 fast FIFO WORD6 STAGE10 fast FIFO WORD7 STAGE10 slow FIFO WORD0 STAGE10 slow FIFO WORD1 STAGE10 slow FIFO WORD2 STAGE10 slow FIFO WORD3 STAGE10 slow FIFO WORD4 STAGE10 slow FIFO WORD5 STAGE10 slow FIFO WORD6 STAGE10 slow FIFO WORD7 STAGE10 slow FIFO ambient value STAGE10 fast FIFO average value STAGE10 CDC FIFO WORD0 STAGE10 CDC FIFO WORD1 STAGE10 maximum value FIFO WORD0 STAGE10 maximum value FIFO WORD1 STAGE10 maximum value FIFO WORD2 STAGE10 maximum value FIFO WORD3 STAGE10 average maximum FIFO value STAGE10 high threshold value STAGE10 temporary maximum value STAGE10 minimum value FIFO WORD0 STAGE10 minimum value FIFO WORD1 STAGE10 minimum value FIFO WORD2 STAGE10 minimum value FIFO WORD3 STAGE10 average minimum FIFO value STAGE10 low threshold value STAGE10 temporary minimum value Rev. 0 | Page 64 of 68 AD7142 Table 60. STAGE11 Results Registers Address 0x26C 0x26D 0x26E 0x26F 0x270 0x271 0x272 0x273 0x274 0x275 0x276 0x277 0x278 0x279 0x27A 0x27B 0x27C 0x27D 0x27E 0x27F 0x280 0x281 0x282 0x283 0x284 0x285 0x286 0x287 0x288 0x289 0x28A 0x28B 0x28C 0x28D 0x28E 0x28F Data Bit [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE11_CONV_DATA STAGE11_FF_WORD0 STAGE11_FF_WORD1 STAGE11_FF_WORD2 STAGE11_FF_WORD3 STAGE11_FF_WORD4 STAGE11_FF_WORD5 STAGE11_FF_WORD6 STAGE11_FF_WORD7 STAGE11_SF_WORD0 STAGE11_SF_WORD1 STAGE11_SF_WORD2 STAGE11_SF_WORD3 STAGE11_SF_WORD4 STAGE11_SF_WORD5 STAGE11_SF_WORD6 STAGE11_SF_WORD7 STAGE11_SF_AMBIENT STAGE11_FF_AVG STAGE11_CDC_WORD0 STAGE11_CDC_WORD1 STAGE11_MAX_WORD0 STAGE11_MAX_WORD1 STAGE11_MAX_WORD2 STAGE11_MAX_WORD3 STAGE11_MAX_AVG STAGE11_HIGH_THRESHOLD STAGE11_MAX_TEMP STAGE11_MIN_WORD0 STAGE11_MIN_WORD1 STAGE11_MIN_WORD2 STAGE11_MIN_WORD3 STAGE11_MIN_AVG STAGE11_LOW_THRESHOLD STAGE11_MIN_TEMP Unused Description STAGE11 CDC 16-bit conversion data (copy of data in STAGE11_CONV_DATA register) STAGE11 fast FIFO WORD0 STAGE11 fast FIFO WORD1 STAGE11 fast FIFO WORD2 STAGE11 fast FIFO WORD3 STAGE11 fast FIFO WORD4 STAGE11 fast FIFO WORD5 STAGE11 fast FIFO WORD6 STAGE11 fast FIFO WORD7 STAGE11 slow FIFO WORD0 STAGE11 slow FIFO WORD1 STAGE11 slow FIFO WORD2 STAGE11 slow FIFO WORD3 STAGE11 slow FIFO WORD4 STAGE11 slow FIFO WORD5 STAGE11 slow FIFO WORD6 STAGE11 slow FIFO WORD7 STAGE11 slow FIFO ambient value STAGE11 fast FIFO average value STAGE11 CDC FIFO WORD0 STAGE11 CDC FIFO WORD1 STAGE11 maximum value FIFO WORD0 STAGE11 maximum value FIFO WORD1 STAGE11 maximum value FIFO WORD2 STAGE11 maximum value FIFO WORD3 STAGE11 average maximum FIFO value STAGE11 high threshold value STAGE11 temporary maximum value STAGE11 minimum value FIFO WORD0 STAGE11 minimum value FIFO WORD1 STAGE11 minimum value FIFO WORD2 STAGE11 minimum value FIFO WORD3 STAGE11 average minimum FIFO value STAGE11 low threshold value STAGE11 temporary minimum value Rev. 0 | Page 65 of 68 AD7142 OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 24 32 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 17 16 8 3.25 3.10 SQ 2.95 0.50 0.40 0.30 12° MAX 9 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 58. 32-Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model AD7142ACPZ-REEL 1 AD7142ACPZ-500RL71 AD7142ACPZ-1REEL1 AD7142ACPZ-1500RL71 EVAL-AD7142EB EVAL-AD7142-1EB 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +85°C 0°C to +85°C Serial Interface Description SPI Interface SPI Interface I2C Interface I2C Interface SPI Interface I2C Interface Package Description 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ Evaluation Board Evaluation Board Package Option CP-32-2 CP-32-2 CP-32-2 CP-32-2 Z = Pb-free part. Rev. 0 | Page 66 of 68 AD7142 NOTES Rev. 0 | Page 67 of 68 AD7142 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05702-0-6/06(0) T T Rev. 0 | Page 68 of 68