CapTouch Programmable Controller for
Single-Electrode Capacitance Sensors
AD7147A
FEATURES
Cell phones
Personal music and multimedia players
Smart handheld devices
Television, A/V, and remote controls
Gaming consoles
Digital still cameras
GENERAL DESCRIPTION
The AD7147A CapTouch™ controller is designed for use with
capacitance sensors implementing functions such as buttons,
scroll bars, and wheels. The sensors need only one PCB layer,
enabling ultrathin applications.
The AD7147A is an integrated CDC with on-chip environmental calibration. The CDC has 13 inputs channeled through a
switch matrix to a 16-bit, 250 kHz sigma-delta (Σ-Δ) converter.
The CDC is capable of sensing changes in the capacitance of the
external sensors and uses this information to register a sensor
activation. By programming the registers, the user has full control
over the CDC setup.
High resolution sensors require minor software to run on the
host processor and may require two PCB layers.
ACSHIELD VCC
E4
GND
BIAS
E2
E3
D2
POWER-ON
RESET LOGIC
CIN0 D3
CIN1 A3
CIN2 B3
EXCITATION
SOURCE
CIN3 A4
CIN4 C3
CIN5 A5
CIN6 B4
CIN7 B5
CIN8 C4
CIN9
C5
AD7147A
CALIBRATION
RAM
16-BIT
Σ-Δ
CDC
CALIBRATION
ENGINE
CIN10 D4
CIN11 D5
CONTROL
AND DATA
REGISTERS
CIN12 E5
B2 TP
VDRIVE C2
SERIAL INTERFACE
AND CONTROL LOGIC
E1
D1
C1
INTERRUPT
AND GPIO
LOGIC
B1
A2 GPIO
A1
SDO
SDI SCLK CS
(SDA) (ADD0)
(ADD1)
INT
NOTES
1. PIN NAMES IN PARENTHESES ARE FOR THE AD7147A-1.
06663-001
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
SWITCH
MATRIX
Programmable capacitance-to-digital converter (CDC)
Femtofarad (fF) resolution
13 capacitance sensor inputs
9 ms update rate, all 13 sensor inputs
No external RC components required
Automatic conversion sequencer
On-chip automatic calibration logic
Automatic compensation for environmental changes
Automatic adaptive threshold and sensitivity levels
Register map is compatible with the AD714x
On-chip RAM to store calibration data
Serial peripheral interface (SPI) (AD7147A)
I2C-compatible serial interface (AD7147A-1)
Separate VDRIVE level for serial interface
Interrupt output and general-purpose input/output (GPIO)
25-ball, 2.3 mm × 2.1 mm WLCSP
2.6 V to 3.6 V supply voltage
Low operating current
Full power mode: 1 mA
Low power mode: 28.96 μA
Figure 1.
The AD7147A is designed for single electrode capacitance
sensors (grounded sensors). There is an active shield output to
minimize noise pickup in the sensor.
The AD7147A has on-chip calibration logic to compensate for
changes in the ambient environment. The calibration sequence
is performed automatically and at continuous intervals as long
as the sensors are not touched. This ensures that there are no
false or nonregistering touches on the external sensors due to a
changing environment.
The AD7147A has an SPI-compatible serial interface, and the
AD7147A-1 has an I2C®-compatible serial interface. Both parts
have an interrupt output, as well as a GPIO. There is a VDRIVE pin
to set the voltage level for the serial interface independent of VCC.
The AD7147A is available in a 25-ball, 2.3 mm × 2.1 mm
WLCSP and operates from a 2.6 V to 3.6 V supply. The operating
current consumption in low power mode is typically 28.96 μA
for 13 sensors.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
AD7147A
TABLE OF CONTENTS
Features .............................................................................................. 1
Capacitance Sensor Behavior Without Calibration ............... 23
Applications ....................................................................................... 1
Threshold Equations .................................................................. 23
General Description ......................................................................... 1
Capacitance Sensor Behavior with Calibration...................... 24
Functional Block Diagram .............................................................. 1
Slow FIFO .................................................................................... 24
Revision History ............................................................................... 2
SLOW_FILTER_UPDATE_LVL .............................................. 24
Specifications..................................................................................... 3
Adaptive Threshold and Sensitivity ............................................. 25
Average Current Specifications .................................................. 4
Interrupt Output ............................................................................. 27
SPI Timing Specifications (AD7147A) ...................................... 5
CDC Conversion-Complete Interrupt .................................... 27
2
I C Timing Specifications (AD7147A-1) .................................. 6
Sensor-Touch Interrupt ............................................................. 27
Absolute Maximum Ratings............................................................ 7
GPIO INT Output Control ....................................................... 29
ESD Caution .................................................................................. 7
Outputs ............................................................................................ 31
Pin Configurations and Function Descriptions ........................... 8
ACSHIELD Output .......................................................................... 31
Typical Performance Characteristics ............................................. 9
General-Purpose Input/Output (GPIO) ................................. 31
Theory of Operation ...................................................................... 11
Using the GPIO to Turn On/Off an LED ................................ 31
Capacitance Sensing Theory ..................................................... 11
Serial Interfaces............................................................................... 32
BIAS Pin ....................................................................................... 12
SPI Interface ................................................................................ 32
Operating Modes ........................................................................ 12
I2C-Compatible Interface .......................................................... 34
Capacitance-to-Digital Converter ................................................ 14
VDRIVE Input ................................................................................. 36
Oversampling the CDC Output ............................................... 14
PCB Design Guidelines ................................................................. 37
Capacitance Sensor Offset Control .......................................... 14
Capacitive Sensor Board Mechanical Specifications ............. 37
Conversion Sequencer ............................................................... 14
WLCSP Package ......................................................................... 37
CDC Conversion Sequence Time ............................................ 16
Power-Up Sequence ....................................................................... 38
CDC Conversion Results ........................................................... 16
Typical Application Circuits ......................................................... 39
Capacitance Sensor Input Configuration .................................... 17
Register Map ................................................................................... 40
CINx Input Multiplexer Setup .................................................. 17
Detailed Register Descriptions ..................................................... 41
Single-Ended Connections to the CDC .................................. 17
Bank 1 Registers ......................................................................... 41
Noncontact Proximity Detection ................................................. 18
Bank 2 Registers ......................................................................... 51
Recalibration ............................................................................... 18
Bank 3 Registers ......................................................................... 56
Proximity Sensitivity .................................................................. 18
Outline Dimensions ....................................................................... 68
FF_SKIP_CNT ............................................................................ 21
Ordering Guide .......................................................................... 68
Environmental Calibration ........................................................... 23
REVISION HISTORY
3/09—Rev. 0 to Rev. A
12/09—Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 68
Changes to Figure 1 .......................................................................... 1
Changes to Figure 5, Figure 6, and Pin Description for B2 ........ 8
Changes to Figure 59 and Figure 60 ............................................. 39
Changes to Ordering Guide .......................................................... 68
1/09—Revision 0: Initial Version
Rev. B | Page 2 of 68
AD7147A
SPECIFICATIONS
VCC = 2.6 V to 3.6 V, TA = −40oC to +85°C, unless otherwise noted.
Table 1.
Parameter
CAPACITANCE-TO-DIGITAL CONVERTER
Update Rate
Resolution
CINx Input Range
No Missing Codes
CINx Input Leakage
Maximum Output Load
Total Unadjusted Error
Output Noise (Peak-to-Peak)
Min
Typ
Max
Unit
Test Conditions/Comments
8.73
17.46
34.9
9
18
36
16
±8
9.27
18.54
37.1
ms
ms
ms
Bits
pF
Bits
nA
pF
%
Codes
Codes
Codes
Codes
Codes
Codes
pF
pF
%
12 conversion stages, decimation = 64
12 conversion stages, decimation = 128
12 conversion stages, decimation = 256
16
25
20
±20
12
7
3
1.1
0.8
0.5
20
0.32
Output Noise (RMS)
CSTRAY Offset Range
CSTRAY Offset Resolution
Low Power Mode Delay Accuracy
ACSHIELD
Frequency
Output Voltage
Short-Circuit Source Current
Short-Circuit Sink Current
Maximum Output Load
LOGIC INPUTS (SDI, SCLK, CS, SDA, GPIO)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
Hysteresis
OPEN-DRAIN OUTPUTS (SCLK, SDA, INT)
Output Low Voltage, VOL
Output High Leakage Current, IOH
LOGIC OUTPUTS (SDO, GPIO)
Output Low Voltage, VOL
Output High Voltage, VOH
GPO, SDO Floating State Leakage
Current
POWER
VCC
VDRIVE
ICC
4
250
0
VCC
10
10
150
0.7 × VDRIVE
0.4
−1
1
150
V
V
μA
μA
mV
Capacitance load on CINx to ground
Decimation rate = 64
Decimation rate = 128
Decimation rate = 256
Decimation rate = 64
Decimation rate = 128
Decimation rate = 256
Percentage of 200 ms, 400 ms, 600 ms, or 800 ms
Oscillating
Capacitance load on ACSHIELD to ground
VIN = VDRIVE
VIN = GND
0.4
±1
V
μA
ISINK = −1 mA
VOUT = VDRIVE
0.4
±1
V
V
μA
ISINK = 1 mA, VDRIVE = 1.65 V to 3.6 V
ISOURCE = 1 mA, VDRIVE = 1.65 V to 3.6 V
Pin three-state, leakage measured to GND and VCC
0.8
1.1
1.2
1.6
15.5
3.6
3.6
1
1.3
1.5
1.8
24
V
V
mA
mA
mA
mA
μA
2.3
10
μA
±0.1
VDRIVE − 0.6
2.6
1.65
kHz
V
mA
mA
pF
Guaranteed by design, but not production tested
3.3
Rev. B | Page 3 of 68
Serial interface operating voltage
In full power mode, VCC + VDRIVE, Register 0x00, Bits[15:14] = 00
In full power mode, VCC + VDRIVE, Register 0x00, Bits[15:14] = 01
In full power mode, VCC + VDRIVE, Register 0x00, Bits[15:14] = 10
In full power mode, VCC + VDRIVE, Register 0x00, Bits[15:14] = 11
Low power mode, converter idle, VCC + VDRIVE, decimation = 256;
Register 0x00, Bits[15:14] = 01
Full shutdown, VCC + VDRIVE, Register 0x00, Bits[15:14] = 01
AD7147A
AVERAGE CURRENT SPECIFICATIONS
Table 2. Typical Average Current in Low Power Mode 1
Low Power
Mode Delay
200 ms
400 ms
600 ms
800 ms
1
Decimation
Rate
64
128
256
64
128
256
64
128
256
64
128
256
1
22.27
27.95
39.15
18.89
21.76
27.45
17.76
19.68
23.49
17.20
18.63
21.50
2
26.53
36.37
55.53
21.04
26.03
35.88
19.20
22.54
29.16
18.28
20.79
25.78
3
30.77
44.66
71.44
23.19
30.27
44.18
20.63
25.39
34.78
19.35
22.93
30.02
Current Values of Conversion Stages (μA)
5
6
7
8
9
39.15 43.29
47.40
51.48
55.53
60.89 68.82
76.64
84.34
91.94
101.9 116.48 130.67 144.47 157.90
27.45 29.57
31.68
33.78.
35.88
38.66 42.80
46.92
51.00
55.05
60.41 68.35
76.18
83.89
91.49
23.49 24.91
26.33
27.75
29.16
31.04 33.85
36.64
39.42
42.18
45.84 51.29
56.69
62.03
67.32
21.50 22.57
23.64
24.71
25.78
27.20 29.32
31.43
33.53
35.63
38.41 42.56
46.67
50.76
54.82
10
59.55
99.42
170.98
37.96
59.08
98.98
30.57
44.93
72.56
26.84
37.72
58.84
11
63.54
106.80
183.71
40.04
63.07
106.37
31.98
47.67
77.75
27.90
39.80
62.84
12
67.51
114.08
196.11
42.11
67.04
113.65
33.38
50.39
82.89
28.96
41.87
66.80
Current Values of Conversion Stages (μA)
5
6
7
8
9
54.35
59.67
64.95
70.18
75.37
82.23
92.37
102.36 112.18 121.85
134.51 153.02 170.96 188.38 205.28
39.35
42.08
44.80
47.50
50.19
53.77
59.09
64.38
69.61
74.81
81.67
91.82
101.82 111.65 121.33
34.27
36.11
37.94
39.76
41.58
44.00
47.60
51.19
54.76
58.31
63.01
70.00
76.92
83.76
90.52
31.72
33.10
34.48
35.85
37.23
39.05
41.78
44.50
47.21
49.90
53.48
58.80
64.09
69.33
74.53
10
80.52
131.27
221.70
52.88
79.96
130.86
43.39
61.84
97.21
38.60
52.59
79.68
11
85.63
140.74
237.65
55.55
85.07
140.24
45.20
65.35
103.83
39.96
55.26
84.80
12
90.69
149.97
253.15
58.21
90.14
149.47
47.00
68.84
110.39
41.33
57.92
89.87
4
34.98
52.84
86.89
25.32
34.48
52.36
22.06
28.22
40.34
20.43
25.07
34.23
VCC = 3.3 V, TA = 25°C, load = 50 pF.
Table 3. Maximum Average Current in Low Power Mode 1
Low Power
Mode Delay
200 ms
400 ms
600 ms
800 ms
1
Decimation
Rate
64
128
256
64
128
256
64
128
256
64
128
256
1
32.62
39.95
54.35
28.32
32.02
39.35
26.88
29.36
34.27
26.16
28.02
31.72
2
38.12
50.78
75.37
31.10
37.53
50.19
28.74
33.05
41.58
27.56
30.80
37.23
3
43.58
61.44
95.72
33.86
42.99
60.86
30.59
36.72
48.80
28.95
33.56
42.69
4
48.99
71.92
115.42
36.61
48.40
71.35
32.43
40.37
55.95
30.33
36.31
48.11
VCC = 3.6 V, TA = −40°C to +85°C, load = 50 pF.
Rev. B | Page 4 of 68
AD7147A
SPI TIMING SPECIFICATIONS (AD7147A)
TA = −40°C to +85°C, sample tested at 25°C to ensure compliance. VDRIVE = 1.65 V to 3.6 V, and VCC = 2.6 V to 3.6 V, unless otherwise
noted. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.
Table 4. SPI Timing Specifications
Parameter
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
Limit
5
5
20
20
15
15
20
16
15
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
Description
SCLK frequency
CS falling edge to first SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SDI setup time
SDI hold time
SDO access time after SCLK falling edge
CS rising edge to SDO high impedance
SCLK rising edge to CS high
SPI Timing Diagram
CS
t1
t2
1
SCLK
t8
t3
2
3
15
16
1
2
15
16
t4
t5
LSB
t6
SDO
MSB
Figure 2. SPI Detailed Timing Diagram
Rev. B | Page 5 of 68
t7
LSB
07727-002
SDI
MSB
AD7147A
I2C TIMING SPECIFICATIONS (AD7147A-1)
TA = −40°C to +85°C, sample tested at 25°C to ensure compliance. VDRIVE = 1.65 V to 3.6 V, and VCC = 2.6 V to 3.6 V, unless otherwise
noted. All input signals timed from a voltage level of 1.6 V.
Table 5. I2C Timing Specifications 1
Parameter
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
tR
tF
1
Limit
400
0.6
1.3
0.6
100
300
0.6
0.6
1.3
300
300
Unit
kHz max
μs min
μs min
μs min
ns min
ns min
μs min
μs min
μs min
ns max
ns max
Description
Start condition hold time, tHD; STA
Clock low period, tLOW
Clock high period, tHIGH
Data setup time, tSU; DAT
Data hold time, tHD; DAT
Stop condition setup time, tSU; STO
Start condition setup time, tSU; STA
Bus-free time between stop and start conditions, tBUF
Clock/data rise time
Clock/data fall time
Guaranteed by design, not production tested.
I2C Timing Diagram
tR
t2
tF
t1
SCLK
t3
t1
t5
t7
t6
t4
t8
STOP START
START
STOP
Figure 3. I2C Detailed Timing Diagram
200µA
1.6V
CL
50pF
200µA
IOH
07727-004
TO OUTPUT
PIN
IOL
Figure 4. Load Circuit for Digital Output Timing Specifications
Rev. B | Page 6 of 68
07727-003
SDA
AD7147A
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
VCC to GND
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Input Current to Any Pin Except Supplies1
ESD Rating
BIAS and ACSHIELD Pins (HBM Contact
and Air Discharge)
All Other Pins (HBM Contact)
Operating Temperature Range
Storage Temperature Range
Junction Temperature
WLCSP
Power Dissipation
θJA Thermal Impedance
IR Reflow Peak Temperature
Lead Temperature (Soldering, 10 sec)
1
Rating
−0.3 V to +3.6 V
−0.3 V to VCC + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
10 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
8 kV
ESD CAUTION
2 kV
−40°C to +105°C
−65°C to +150°C
150°C
1W
65°C/W
260°C (± 0.5°C)
300°C
Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. B | Page 7 of 68
AD7147A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
BALL A1
INDICATOR
BALL A1
INDICATOR
1
2
3
4
5
INT
GPIO
CIN1
CIN3
CIN5
A
1
2
3
4
5
INT
GPIO
CIN1
CIN3
CIN5
ADD1
TP
CIN2
CIN6
CIN7
SCLK VDRIVE CIN4
CIN8
CIN9
A
CS
TP
CIN2
CIN6
CIN7
B
B
SCLK VDRIVE CIN4
CIN8
CIN9
C
C
SDI
VCC
CIN0
CIN10 CIN11
D
ADD0
VCC
CIN0
SDA
GND
BIAS ACSHIELD CIN12
CIN10 CIN11
D
SDO
GND
BIAS ACSHIELD CIN12
E
NOTES
1. TP DENOTES FACTORY TEST POINT.
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
07727-005
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
NOTES
1. TP DENOTES FACTORY TEST POINT.
07727-006
E
Figure 6. AD7147A-1 Pin Configuration
Figure 5. AD7147A Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
AD7147A AD7147A-1
B4
B4
B5
B5
C4
C4
C5
C5
D4
D4
D5
D5
E5
E5
E4
E4
E3
E3
E2
E2
D2
D2
C2
C2
E1
N/A
N/A
E1
D1
N/A
N/A
D1
C1
C1
B1
N/A
N/A
B1
A1
A1
A2
A2
D3
D3
A3
A3
B3
B3
A4
A4
C3
C3
A5
A5
B2
B2
Mnemonic
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
CIN12
ACSHIELD
BIAS
GND
VCC
VDRIVE
SDO
SDA
SDI
ADD0
SCLK
CS
ADD1
INT
GPIO
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
Description
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
CDC Active Shield Output. Connect to external shield or plane.
Bias Node for Internal Circuitry. Requires 100 nF capacitor to ground.
Ground Reference Point for All Circuitry.
Supply Voltage.
Serial Interface Operating Voltage Supply.
SPI Serial Data Output.
I2C Serial Data Input/Output. SDA requires pull-up resistor.
SPI Serial Data Input.
I2C Address Bit 0.
Clock Input for Serial Interface.
SPI Chip Select Signal.
I2C Address Bit 1.
General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor.
Programmable General-Purpose Input/Output.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Factory Test Point Only. Tie to ground.
Rev. B | Page 8 of 68
AD7147A
TYPICAL PERFORMANCE CHARACTERISTICS
935
70
915
60
895
200ms
50
875
ICC (μA)
ICC (µA)
DECIMATION = 64
DECIMATION = 128
DECIMATION = 256
855
40
400ms
600ms
30
20
815
10
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
VCC (V)
0
2.5
07727-007
795
2.6
2.7
2.9
3.1
3.3
3.5
3.7
VCC (V)
Figure 7. Supply Current vs. Supply Voltage
07727-010
800ms
835
Figure 10. Low Power Supply Current vs. Supply Voltage,
Decimation Rate = 64
2.5
180
200ms
160
2.0
140
100
ICC (µA)
ICC (μA)
120
400ms
80
600ms
1.5
1.0
60
800ms
40
0.5
2.7
2.9
3.1
3.3
3.5
3.7
VCC (V)
0
2.7
07727-008
0
2.5
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC (V)
07727-011
20
Figure 11. Shutdown Supply Current vs. Supply Voltage
Figure 8. Low Power Supply Current vs. Supply Voltage,
Decimation Rate = 256
0.12
1150
0.10
200ms
1100
ICC (µA)
0.06
400ms
600ms
1050
1000
0.04
800ms
950
0
2.5
2.7
2.9
3.1
3.3
3.5
VCC (V)
3.7
Figure 9. Low Power Supply Current vs. Supply Voltage,
Decimation Rate = 128
900
0
100
200
300
400
500
ACSHIELD CAPACITIVE LOAD (pF)
Figure 12. Supply Current vs. Capacitive Load on ACSHIELD
Rev. B | Page 9 of 68
07727-012
0.02
07727-009
ICC (mA)
0.08
AD7147A
58,000
160
56,000
140
54,000
75mV
100mV
125mV
150mV
175mV
200mV
CDC NOISE p-p (LSB)
120
52,000
50,000
48,000
46,000
100
80
60
40
44,000
20
42,000
40,000
07727-016
819,200
SINE WAVE FREQUENCY (Hz)
1,640,000
409,600
204,800
51,200
102,400
25,600
6400
12,800
800
3200
ACSHIELD CAPACITIVE LOAD (pF)
1600
500
400
400
200
300
50
200
25
100
07727-013
0
0
100
CDC CODE (d)
25mV
50mV
Figure 16. Power Supply Sine Wave Rejection, VCC = 3.6 V
Figure 13. CDC Code vs. Capacitive Load on ACSHIELD
120
25mV
50mV
960
75mV
100mV
125mV
150mV
175mV
200mV
100
940
CDC NOISE p-p (LSB)
3.6V
920
900
ICC (µA)
3.3V
880
860
80
60
40
840
20
820
2.6V
800
6400
3200
1600
800
400
200
100
Figure 17. Power Supply Square Wave Rejection, VCC = 3.6 V
Figure 14. Supply Current vs. Temperature
35
12
30
INPUT CAPACITANCE (pF)
10
8
6
3.6V
4
3.3V
2.6V
2
25
20
15
10
0
–45
–25
–5
15
35
55
75
95
115
TEMPERATURE (°C)
135
0
0
10,000
20,000
30,000
40,000
50,000
CDC OUTPUT CODE
Figure 18. CDC Linearity, VCC = 3.3 V
Figure 15. Shutdown Supply Current vs. Temperature
Rev. B | Page 10 of 68
60,000
07727-018
5
07727-015
ICC (µA)
50
SQUARE WAVE FREQUENCY (Hz)
07727-017
120
1,640,000
100
819,200
80
409,600
60
204,800
40
102,400
20
TEMPERATURE (°C)
51,200
0
25,600
–20
12,800
–40
07727-014
25
0
780
–60
AD7147A
THEORY OF OPERATION
The AD7147A interfaces with up to 13 external capacitance
sensors. These sensors can be arranged as buttons, scroll bars,
or wheels, or as a combination of sensor types. The external
sensors consist of an electrode on a single- or multiple-layer
PCB that interfaces directly to the AD7147A.
The AD7147A can be set up to implement any set of input
sensors by programming the on-chip registers. The registers
can also be programmed to control features such as averaging,
offsets, and gains for each of the external sensors. There is an
on-chip sequencer that controls how each of the capacitance
inputs is polled.
The AD7147A can be programmed to operate in either full
power mode or low power automatic wake-up mode. The
automatic wake-up mode is particularly suited for portable
devices that require low power operation to provide the user
with significant power savings and full functionality.
The AD7147A has an interrupt output, INT, to indicate when new
data has been placed into the registers. INT is used to interrupt the
host on sensor activation. The AD7147A operates from a 2.6 V to
3.6 V supply and is available in a 2.3 mm × 2.1 mm WLCSP.
CAPACITANCE SENSING THEORY
The AD7147A measures capacitance changes from single electrode
sensors. The sensor electrode on the PCB comprises one plate
of a virtual capacitor. The other plate of the capacitor is the user’s
finger, which is grounded with respect to the sensor input.
The AD7147A first outputs an excitation signal to charge the
plate of the capacitor. When the user comes close to the sensor,
the virtual capacitor is formed, with the user acting as the second
capacitor plate.
PLASTIC COVER
The AD7147A has on-chip digital logic and 528 words of RAM
that are used for environmental compensation. The effects of
humidity, temperature, and other environmental factors can
affect the operation of capacitance sensors. Transparent to the
user, the AD7147A performs continuous calibration to compensate for these effects, allowing the AD7147A to consistently
provide error-free results.
The AD7147A requires a companion algorithm that runs on the
host or another microcontroller to implement high resolution
sensor functions, such as scroll bars or wheels. However, no
companion algorithm is required to implement buttons. Button
sensors are implemented on chip, entirely in digital logic.
MUX
SENSOR PCB
AD7147A
Σ-Δ
ADC
16-BIT
DATA
EXCITATION
SIGNAL
250kHz
07727-019
The AD7147A and AD7147A-1 are CDCs with on-chip environmental compensation. They are intended for use in portable
systems requiring high resolution user input. The internal
circuitry consists of a 16-bit, Σ-Δ converter that can change a
capacitive input signal into a digital value. There are 13 input
pins, CIN0 to CIN12. A switch matrix routes the input signals
to the CDC. The result of each capacitance-to-digital conversion
is stored in on-chip registers. The host subsequently reads the
results over the serial interface. The AD7147A has an SPI interface,
and the AD7147A-1 has an I2C interface, ensuring that the parts
are compatible with a wide range of host processors. AD7147A
refers to both the AD7147A and AD7147A-1, unless otherwise
noted, from this point forward in this data sheet.
Figure 19. Capacitance-Sensing Method
A square wave excitation signal is applied to CINx during
the conversion, and the modulator continuously samples the
charge going through CINx. The output of the modulator is
processed via a digital filter, and the resulting digital data is
stored in the CDC_RESULT_Sx registers for each conversion
stage, at Address 0x00B to Address 0x016.
Rev. B | Page 11 of 68
AD7147A
Registering a Sensor Activation
Complete Solution for Capacitance Sensing
When a user approaches a sensor, the total capacitance associated
with that sensor changes and is measured by the AD7147A. If
the change causes a set threshold to be exceeded, the AD7147A
interprets this as a sensor activation.
Analog Devices, Inc., provides a complete solution for capacitance
sensing. The two main elements to the solution are the sensor
PCB and the AD7147A.
If the application requires high resolution sensors such as scroll
bars or wheels, software that runs on the host processor is required.
The memory requirements for the host depend on the sensor
and are typically 10 kB of code and 600 bytes of data memory,
depending on the sensor type.
SENSOR PCB
SENSOR ACTIVE A
SPI OR I2C
STAGEx_HIGH_THRESHOLD
HOST PROCESSOR
1 MIPS
10kB ROM
600 BYTES RAM
CDC_RESULT_Sx
AMBIENT OR
NO-TOUCH VALUE
Figure 21. Three-Part Capacitance Sensing Solution
STAGEx_LOW_THRESHOLD
07727-020
CDC OUTPUT CODES
AD7147A
07727-021
On-chip threshold limits are used to determine when a sensor
activation occurs. Figure 20 shows the change in CDC_RESULT_Sx
when a user activates a sensor. The sensor is deemed to be active
only when the value of CDC_RESULT_Sx is either greater than the
value of STAGEx_HIGH_THRESHOLD or less than the value
of STAGEx_LOW_THRESHOLD.
SENSOR ACTIVE B
Analog Devices supplies the sensor PCB footprint design
libraries to the customer and supplies any necessary software on
an open-source basis.
BIAS PIN
Figure 20. Sensor Activation Thresholds
In Figure 20, two sensor activations are shown. Sensor Active A
occurs when a sensor is connected to the positive input of the
converter. In this case, when a user activates the sensor, there is an
increase in CDC code, and the value of CDC_RESULT_Sx exceeds
that of STAGEx_HIGH_THRESHOLD. Sensor Active B occurs
when the sensor is connected to the negative input of the converter.
In this case, when a user activates the sensor, there is a decrease
in CDC code, and the value of CDC_RESULT_Sx becomes less
than the value of STAGEx_LOW_THRESHOLD.
For each conversion stage, the STAGEx_HIGH_THRESHOLD
and STAGEx_LOW_THRESHOLD registers are in Bank 3.
The values in these registers are updated automatically by the
AD7147A due to its environmental calibration and adaptive
threshold logic.
At power-up, the values in the STAGEx_HIGH_THRESHOLD
and STAGEx_LOW_THRESHOLD registers are the same as those
in the STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW
registers in Bank 2. The user must program the STAGEx_OFFSET
_HIGH and STAGEx_OFFSET_LOW registers on device powerup. See the Environmental Calibration section of the data sheet
for more information.
This pin is connected internally to a bias node of the AD7147A.
To ensure correct operation of the AD7147A, connect a 100 nF
capacitor between the BIAS pin and ground. The voltage seen at
the BIAS pin is VCC/2.
OPERATING MODES
The AD7147A has three operating modes. Full power mode, where
the device is always fully powered, is suited for applications where
power is not a concern (for example, game consoles that have an
ac power supply). Low power mode, where the part automatically
powers down when no sensor is active, is tailored to provide
significant power savings compared with full power mode and
is suited for mobile applications, where power must be conserved.
In shutdown mode, the part shuts down completely.
The POWER_MODE Bits[1:0] of the power control register
(PWR_CONTROL, Address 0x000) set the operating mode on
the AD7147A. Table 8 shows the POWER_MODE settings for
each operating mode. To put the AD7147A into shutdown
mode, set the POWER_MODE bits to either 01 or 11.
Table 8. POWER_MODE Settings
POWER_MODE Bits
00
01
10
11
Operating Mode
Full power mode
Shutdown mode
Low power mode
Shutdown mode
The power-on default setting of the POWER_MODE bits is 00,
full power mode.
Rev. B | Page 12 of 68
AD7147A
Full Power Mode
is 400 ms, the AD7147A typically uses 0.85 mA of current for
36 ms and 14 μA of current for 400 ms during the conversion
interval. (Note that these conversion timings can be altered
through the register settings. See the CDC Conversion Sequence
Time section for more information.)
In full power mode, all sections of the AD7147A remain fully
powered and converting at all times. While a sensor is being
touched, the AD7147A processes the sensor data. If no sensor is
touched, the AD7147A measures the ambient capacitance level
and uses this data for the on-chip compensation routines. In full
power mode, the AD7147A converts at a constant rate. See the
CDC Conversion Sequence Time section for more information.
The time for the AD7147A to transition from a full power state
to a reduced power state after the user stops touching the external
sensors is configurable. The PWR_DOWN_TIMEOUT bits in
the Ambient Compensation Control 0 register (AMB_COMP_
CTRL0, Address 0x002) control the time delay before the
AD7147A transitions to the reduced power state after the user
stops touching the sensors.
Low Power Mode
When AD7147A is in low power mode, the POWER_MODE
bits are set to 10 upon device initialization. If the external
sensors are not touched, the AD7147A reduces its conversion
frequency, thereby greatly reducing its power consumption.
The part remains in a reduced power state while the sensors are
not touched. The AD7147A performs a conversion after a delay
defined by the LP_CONV_DELAY bits, and it uses this data to
update the compensation logic and check if the sensors are active.
The LP_CONV_DELAY bits set the delay between conversions
to 200 ms, 400 ms, 600 ms, or 800 ms.
Low Latency from Touch to Response
In low power mode, the AD7147A remains in a low power state
until proximity is detected on any one of the external sensors.
When proximity is detected, the AD7147A begins a conversion
sequence every 36 ms, or 18 ms, or 9 ms to read back data from
the sensors. The latency between first touch and AD7147A
response is greatly reduced compared to the AD7147 because
the part is already in a full power state by the time the user
touches the sensor.
In low power mode, the total current consumption of the
AD7147A is an average of the current used during a conversion
and the current used while the AD7147A is waiting for the next
conversion to begin. For example, when LP_CONV_DELAY
AD7147A SETUP
AND INITIALIZATION
POWER_MODE = 10
NO
USER IN
PROXIMITY
TO SENSOR?
CONVERSION SEQUENCE
EVERY LP_CONV_DELAY
UPDATE COMPENSATION
LOGIC DATA PATH
YES
CONVERSION SEQUENCE
EVERY 9ms, 18ms, OR
36ms FOR SENSOR
READBACK
YES
USER IN
PROXIMITY
TO SENSOR?
PROXIMITY TIMER TIMEOUT
COUNTDOWN
Figure 22. Low Power Mode Operation, AD7147A
Rev. B | Page 13 of 68
07727-022
NO
AD7147A
CAPACITANCE-TO-DIGITAL CONVERTER
from midscale, decrease the POS_AFE_OFFSET or
NEG_AFE_OFFSET value by 1.
The capacitance-to-digital converter on the AD7147A has a
Σ-Δ architecture with 16-bit resolution. There are 13 possible
inputs to the CDC that are connected to the input of the converter
through a switch matrix. The sampling frequency of the CDC is
250 kHz.
The goal is to ensure that the CDC_RESULT_Sx is as close
to midscale as possible. This process is required only once
during the initial capacitance sensor characterization.
OVERSAMPLING THE CDC OUTPUT
+DAC
(20pF RANGE)
The decimation rate, or oversampling ratio, is determined by
Bits[9:8] of the power control register (PWR_CONTROL,
Address 0x000), as listed in Table 9.
CDC Output Rate
Per Stage (ms)
3.072
1.536
0.768
0.768
The decimation process on the AD7147A is an averaging
process, where a number of samples are taken and the averaged
result is output. Due to the architecture of the digital filter
employed, the number of samples taken (per stage) is equal to 3×
the decimation rate. So 3 × 256 or 3 × 128 samples are averaged
to obtain each stage result.
The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage; therefore, there is a trade-off
possible between the amount of noise in the signal and the
speed of sampling.
CAPACITANCE SENSOR OFFSET CONTROL
There are two programmable DACs on board the AD7147A to null
the effect of any stray capacitances on the CDC measurement.
These offsets are due to stray capacitance to ground.
A simplified block diagram in Figure 23 shows how to apply
the STAGEx_AFE_OFFSET registers to null the offsets. The
POS_AFE_OFFSET and NEG_AFE_OFFSET bits (Bits[13:8] and
Bits[5:0], respectively) program the offset DACs to provide 0.32
pF resolution offset adjustment over a range of 20 pF.
The best practice is to ensure that the CDC output for any stage
is approximately equal to midscale (~32,700) when all sensors
are inactive. To correctly offset the stray capacitance to ground for
each stage, use the following procedure:
1.
2.
3.
Read back the CDC value from the CDC_RESULT_Sx
register.
If this value is not close to midscale, increase the value of
POS_AFE_OFFSET or NEG_AFE_OFFSET (depending
on if the CINx input is connected to the positive or negative
input of the converter) by 1. The CINx connections are
determined by the STAGEx_CONNECTION registers.
If the CDC value in CDC_RESULT_Sx is now closer
to midscale, repeat Step 2. If the CDC value is further
CINx
+
16-BIT
_ CDC
16
NEG_AFE_OFFSET_SWAP BIT
–DAC
(20pF RANGE)
6
NEG_AFE_OFFSET
CINx_CONNECTION_SETUP
07727-023
Decimation Rate
256
128
64
64
POS_AFE_OFFSET
POS_AFE_OFFSET_SWAP BIT
Table 9. CDC Decimation Rate
Decimation Bits
00
01
10
11
6
Figure 23. Analog Front-End Offset Control
CONVERSION SEQUENCER
The AD7147A has an on-chip sequencer to implement conversion
control for the input channels. Up to 12 conversion stages can be
performed in one sequence. Each of the 12 conversions stages can
measure the input from a different sensor. By using the Bank 2
registers, each stage can be uniquely configured to support multiple
capacitance sensor interface requirements. For example, a slider
sensor can be assigned to STAGE1 through STAGE8, with a
button sensor assigned to STAGE0. For each conversion stage,
the input mux that connects the CINx inputs to the converter
can have a unique setting.
The AD7147A on-chip sequence controller provides conversion
control, beginning with STAGE0. Figure 24 shows a block diagram
of the CDC conversion stages and CINx inputs. A conversion
sequence is defined as a sequence of CDC conversions starting
at STAGE0 and ending at the stage determined by the value
programmed in the SEQUENCE_STAGE_NUM bits (Bits[7:4],
Address 0x00). Depending on the number and type of capacitance
sensors that are used, not all conversion stages are required. Use
the SEQUENCE_STAGE_NUM bits to set the number of conversions in one sequence. This number depends on the sensor
interface requirements. For example, the register should be set
to 5 if the CINx inputs are mapped to only six conversion stages.
In addition, the STAGE_CAL_EN register (Address 0x001)
should be set according to the number of stages that are used.
The number of required conversion stages depends solely on
the number of sensors attached to the AD7147A. Figure 25
shows how many conversion stages are required for each sensor
and how many inputs to the AD7147A each sensor requires.
Rev. B | Page 14 of 68
AD7147A
A wheel sensor requires eight stages, whereas a slider requires
two stages. The result from each stage is used by the host software to determine the user’s position on the slider or wheel. The
algorithms that perform this process are available from Analog
Devices and are free of charge but require signing a software
license.
A button sensor generally requires one sequencer stage; this is
shown in Figure 25 as B1. However, it is possible to configure
two button sensors to operate differentially for one conversion
stage. Only one button can be activated at a time; pressing both
buttons simultaneously results in neither button being activated.
The configuration with two button sensors operating differentially requires one conversion stage and is shown in Figure 25,
with B2 and B3 representing the differentially configured button
sensors.
STAGE11
STAGE10
STAGE9
STAGE8
STAGE7
STAGE6
STAGE5
STAGE4
STAGE3
STAGE2
STAGE1
STAGE0
CIN0
CIN1
CIN6
CIN7
CIN8
CIN9
UEN
CE
CIN5
Σ-Δ
16-BIT
ADC
SEQ
CIN4
CO
NVE
RSI
ON
CIN3
SWITCH MATRIX
CIN2
CIN10
07727-024
CIN11
CIN12
Figure 24. CDC Conversion Stages
AD7147A
BUTTONS
SEQUENCER
STAGE0
+
CDC
–
B1
STAGE8
+ CDC
–
STAGE1
+
CDC
–
B2
STAGE9
+ CDC
–
STAGE2
+ CDC
–
B3
STAGE3
+ CDC
–
STAGE4
+ CDC
–
SEQUENCER
STAGE5
+ CDC
–
STAGE10
+ CDC
–
AD7147A
SLIDER
STAGE6
+ CDC
–
STAGE7
+ CDC
–
Figure 25. Sequencer Setup for Sensors
Rev. B | Page 15 of 68
STAGE11
+ CDC
–
07727-025
SCROLL
WHEEL
AD7147A
SEQUENCER
AD7147A
CDC CONVERSION SEQUENCE TIME
Table 10. CDC Conversion Times for Full Power Mode
Conversion Time (ms)
Decimation = 128
1.536
3.072
4.608
6.144
7.68
9.216
10.752
12.288
13.824
15.36
16.896
18.432
Decimation = 64
0.768
1.536
2.304
3.072
3.84
4.608
5.376
6.144
6.912
7.68
8.448
9.216
The time required for the CDC to complete the measurement of
all 12 stages is defined as the CDC conversion sequence time. The
SEQUENCE_STAGE_NUM and DECIMATION bits determine
the conversion time, as listed in Table 10.
For example, if the device is operated with a decimation rate
of 128 and the SEQUENCE_STAGE_NUM bit is set to 5 for the
conversion of six stages in a sequence, the conversion sequence
time is 9.216 ms.
Full Power Mode CDC Conversion Sequence Time
The full power mode CDC conversion sequence time for all
12 stages is set by configuring the SEQUENCE_STAGE_NUM
and DECIMATION bits as outlined in Table 10.
Figure 26 shows a simplified timing diagram of the full power
mode CDC conversion time. The full power mode CDC conversion time (tCONV_FP) is set using the values shown in Table 10.
CDC
CONVERSION
CONVERSION
SEQUENCE N
CONVERSION
CONVERSION
SEQUENCE N + 1 SEQUENCE N + 2
07727-026
tCONV_FP
Figure 26. Full Power Mode CDC Conversion Sequence Time
Decimation = 256
3.072
6.144
9.216
12.288
15.36
18.432
21.504
24.576
27.648
30.72
33.792
36.864
For example, maximum power savings is achieved when the
LP_CONV_DELAY bits are set to 11. With a setting of 11,
the AD7147A automatically wakes up, performing a conversion
every 800 ms.
Table 11. LP_CONV_DELAY Settings
LP_CONV_DELAY Bits
00
01
10
11
Delay Between Conversions (ms)
200
400
600
800
Figure 27 shows a simplified timing example of the low power
mode CDC conversion time. As shown, the low power mode CDC
conversion time is set by tCONV_FP and the LP_CONV_DELAY bits.
tCONV_LP
tCONV_FP
CDC
CONVERSION
CONVERSION
SEQUENCE N
LP_CONV_DELAY
CONVERSION
SEQUENCE N + 1
07727-027
SEQUENCE_STAGE_NUM
0
1
2
3
4
5
6
7
8
9
10
11
Figure 27. Low Power Mode CDC Conversion Sequence Time
CDC CONVERSION RESULTS
Low Power Mode CDC Conversion Sequence Time
with Delay
The frequency of each CDC conversion while operating in the
low power automatic wake-up mode is controlled by using the
LP_CONV_DELAY Bits[3:2] located at Address 0x000 in addition to the registers listed in Table 10. This feature provides some
flexibility for optimizing the trade-off between the conversion time
needed to meet system requirements and the power consumption
of the AD7147A.
Certain high resolution sensors require the host to read back the
CDC conversion results for processing. The registers required
for host processing are located in Bank 3. The host processes the
data read back from these registers using a software algorithm to
determine position information.
In addition to the results registers in Bank 3, the AD7147A
provides the 16-bit CDC output data directly, starting at
Address 0x00B of Bank 1. Reading back the CDC 16-bit
conversion data register allows for customer-specific application
data processing.
Rev. B | Page 16 of 68
AD7147A
CAPACITANCE SENSOR INPUT CONFIGURATION
Each input connection from the external capacitance sensors to
the converter of the AD7147A can be uniquely configured by
using the stage configuration registers in Bank 2 (see Table 39).
These registers are used to configure the input pin connection
setups, sensor offsets, sensor sensitivities, and sensor limits
for each stage. Each sensor can be individually optimized. For
example, a button sensor connected to STAGE0 can have different sensitivity and offset values than a button with another
function that is connected to a different stage.
CINx INPUT MULTIPLEXER SETUP
Table 35 and Table 36 list the available options for the CINx_
CONNECTION_SETUP bits when the sensor input pins are
connected to the CDC.
The AD7147A has an on-chip multiplexer that routes the input
signals from each CINx pin to the input of the converter. Each
input pin can be tied to either the negative or positive input of
the CDC, or it can be left floating. Each input can also be
internally connected to the BIAS signal to help prevent crosscoupling. If an input is not used, always connect it to BIAS.
Connecting a CINx input pin to the positive CDC input results
in an increase in CDC output code when the corresponding
sensor is activated. Connecting a CINx input pin to the negative
CDC input results in a decrease in CDC output code when the
corresponding sensor is activated.
The AD7147A performs a sequence of 12 conversions. The multiplexer can have different settings for each of the 12 conversions.
For example, CIN0 is connected to the negative CDC input for
conversion STAGE1, left floating for conversion STAGE1, and
so on, for all 12 conversion stages.
For each CINx input for each conversion stage, two bits control
how the input is connected to the converter, as shown in Figure 28.
Examples
To connect CIN3 to the positive CDC input on Stage 0, use the
following setting:
STAGE0_CONNECTION[6:0] = 0xFFBF
STAGE0_CONNECTION[12:7] = 0x2FFF
STAGE5_CONNECTION[6:0] = 0xFFFE
STAGE5_CONNECTION[12:7] = 0x37FF
SINGLE-ENDED CONNECTIONS TO THE CDC
A single-ended connection to the CDC is defined as one CINx
input connected to either the positive or negative CDC input
for one conversion stage. A differential connection to the CDC is
defined as one CINx input connected to the positive CDC input
and a second CINx input connected to the negative input of the
CDC for one conversion stage.
For any stage, if a single-ended connection to the CDC is made
in that stage, the SE_CONNECTION_SETUP Bits[13:12] in the
STAGEx_CONNECTION[12:7] register should be applied as
described in Table 12.
Table 12. SE_CONNECTION_SETUP Bits
SE_CONNECTION_SETUP
00
01
10
11
Description
Do not use.
Single-ended connection. For this
stage, there is one CINx connected
to the positive CDC input.
Single-ended connection. For this
stage, there is one CINx connected
to the negative CDC input.
Differential connection. For this
stage, there is one CINx connected
to the negative CDC input and one
CINx connected to the positive
CDC input.
The SE_CONNECTION_SETUP Bits[13:12] ensure that during a
single-ended connection to the CDC, the input paths to both
CDC terminals are matched, which, in turn, improves the
power-supply rejection of the converter measurement.
These bits should be applied in addition to setting the other bits
in the STAGEx_CONNECTION registers, as outlined in the
CINX Input Multiplexer Setup section.
If more than one CINx input is connected to either the positive
or negative input of the converter for the same conversion, set
SE_CONNECTION_SETUP to 11. For example, if CIN0 and
CIN3 are connected to the positive input of the CDC, set
SE_CONNECTION_SETUP to 11.
CIN CONNECTION SETUP BITS
CIN SETTING
00
CINx FLOATING
01
CINx CONNECTED TO
NEGATIVE CDC INPUT
+
10
CINx CONNECTED TO
POSITIVE CDC INPUT
–
11
CINx CONNECTED TO
BIAS
CDC
Figure 28. Input Mux Configuration Options
Rev. B | Page 17 of 68
07727-028
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
CIN12
To connect CIN0 to the positive CDC input and CIN12 to the
negative CIN input on STAGE5, use the following settings:
AD7147A
NONCONTACT PROXIMITY DETECTION
The AD7147A internal signal processing continuously monitors
all capacitance sensors for noncontact proximity detection. This
feature provides the ability to detect when a user is approaching
a sensor, at which time all internal calibration is immediately
disabled while the AD7147 is automatically configured to detect
a valid contact.
The AD7147A recalibrates automatically when the measured CDC
value exceeds the stored ambient value by an amount determined
by the PROXIMITY_RECAL_LVL bits for a set period of time
known as the recalibration timeout. In full power mode, the recalibration timeout is controlled by FP_PROXIMITY_RECAL; in
low power mode, by LP_PROXMTY_RECAL.
The proximity control register bits are described in Table 13. The
FP_PROXIMITY_CNT and LP_PROXIMITY_CNT register
bits control the length of the calibration disable period after the
user stops touching the sensor and is not in close proximity to
the sensor during full or low power mode. The calibration is
disabled during this period and then enabled again. Figure 29
and Figure 30 show examples of how these register bits are
used to set the calibration disable periods for the full and low
power modes.
The recalibration timeout in full power mode is the value of
FP_PROXIMITY_RECAL multiplied by the time for one
conversion sequence in full power mode. The recalibration timeout in low power mode is the value of LP_PROXIMITY_RECAL
multiplied by the time for one conversion sequence in low
power mode.
The calibration disable period in full power mode is the value
of the FP_PROXIMITY_CNT multiplied by 16 multiplied by
the time for one conversion sequence in full power mode. The
calibration disable period in low power mode is the value of the
LP_PROXIMITY_CNT multiplied by 4 multiplied by the time
for one conversion sequence in low power mode.
Figure 31 and Figure 32 show examples of how the FP_
PROXIMITY_RECAL and LP_PROXIMITY_RECAL register
bits control the timeout period before a recalibration while
operating in the full and low power modes. In these examples,
a user approaches a sensor and then leaves, but the proximity
detection remains active. The measured CDC value exceeds the
stored ambient value by the amount set in the PROXIMITY_
RECAL_LVL bits for the entire timeout period. The sensor is
automatically recalibrated at the end of the timeout period.
RECALIBRATION
PROXIMITY SENSITIVITY
In certain situations, for example, when a user hovers over a
sensor for a long time, the proximity flag can be set for a long
period. The environmental calibration on the AD7147A is suspended while proximity is detected, but changes may occur
to the ambient capacitance level during the proximity event.
This means that the ambient value stored on the AD7147A no
longer represents the actual ambient value. In this case, even
when the user is not in close proximity to the sensor, the proximity flag may still be set. This situation can occur if the user
interaction creates some moisture on the sensor, causing the
new sensor ambient value to be different from the expected
value. In this situation, the AD7147A automatically forces a
recalibration internally. This ensures that the ambient values
are recalibrated, regardless of how long the user hovers over
the sensor. A recalibration ensures maximum AD7147A sensor
performance.
The fast filter in Figure 33 is used to detect when someone is
close to the sensor (proximity). Two conditions, detected by
Comparator 1 and Comparator 2, set the internal proximity
detection signal: Comparator 1 detects when a user is approaching or leaving a sensor, and Comparator 2 detects when a user
hovers over a sensor or approaches a sensor very slowly.
The sensitivity of Comparator 1 is controlled by the PROXIMITY_
DETECTION_RATE bits (Address 0x003). For example, if
PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1
signal is set when the absolute difference between WORD1 and
WORD3 exceeds (4 × 16) LSB codes.
The PROXIMITY_RECAL_LVL bits (Address 0x003) control
the sensitivity of Comparator 2. For example, if PROXIMITY_
RECAL_LVL is set to 75, the Proximity 2 signal is set when the
absolute difference between the fast filter average value and the
ambient value exceeds (75 × 16) LSB codes.
Rev. B | Page 18 of 68
AD7147A
Table 13. Proximity Control Registers (See Figure 33)
Bit Name
FP_PROXIMITY_CNT
LP_PROXIMITY_CNT
FP_PROXIMITY_RECAL
LP_PROXIMITY_RECAL
PROXIMITY_RECAL_LVL
Length
(Bits)
4
4
10
6
8
Register Address
0x002[7:4]
0x002[11:8]
0x004[9:0]
0x004[15:10]
0x003[7:0]
PROXIMITY_DETECTION_RATE
6
0x003[13:8]
USER APPROACHES
SENSOR
Description
Calibration disable time in full power mode.
Calibration disable time in low power mode.
Full power mode proximity recalibration time control.
Low power mode proximity recalibration time control.
Proximity recalibration level. This value, multiplied by 16, controls the
sensitivity of Comparator 2 (see Figure 33).
Proximity detection rate. This value, multiplied by 16, controls the
sensitivity of Comparator 1 (see Figure 33).
USER LEAVES
SENSOR AREA
tCONV_FP
CDC CONVERSION
SEQUENCE
(INTERNAL)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tCALDIS
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
07727-029
PROXIMITY
DETECTION
(INTERNAL)
Figure 29. Example of Full Power Mode Proximity Detection (FP_PROXIMITY_CNT = 1)
USER APPROACHES
SENSOR
USER LEAVES
SENSOR AREA
tCONV_LP
CDC CONVERSION
SEQUENCE
(INTERNAL)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tCALDIS
PROXIMITY
DETECTION
(INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
NOTES
1. SEQUENCE CONVERSION TIME tCONV_LP = tCONV_FP + LP_CONV_DELAY.
2. PROXIMITY IS SET WHEN THE USER APPROACHES THE SENSOR, AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED.
3. tCALDIS = (tCONV_LP × LP_PROXIMITY_CNT × 4).
Figure 30. Example of Low Power Mode Proximity Detection (LP_PROXIMITY_CNT = 4)
Rev. B | Page 19 of 68
07727-030
CALIBRATION
(INTERNAL)
AD7147A
USER APPROACHES
SENSOR
tRECAL
MEASURED CDC VALUE > STORED AMBIENT
BY PROXIMITY_RECAL _LVL
USER LEAVES
SENSOR AREA
tCONV_FP
16
CDC CONVERSION
SEQUENCE
(INTERNAL)
30
70
tCALDIS
PROXIMITY
DETECTION
(INTERNAL)
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
RECALIBRATION TIMEOUT
CALIBRATION ENABLED
tRECAL_TIMEOUT
RECALIBRATION
COUNTER
(INTERNAL)
07727-031
NOTES
1. SEQUENCE CONVERSION TIME tCONV_FP (SEE TABLE 10).
2. tCALDIS = tCONV_FP × FP_PROXIMITY_CNT × 16.
3. tRECAL_TIMEOUT = tCONV_FP × FP_PROXIMITY_RECAL.
4. tRECAL = 2 × tCONV_FP .
Figure 31. Example of Full Power Mode Proximity Detection with Forced Recalibration (FP_PROXIMITY_CNT = 1 and FP_PROXIMITY_RECAL = 40)
USER APPROACHES
SENSOR
tRECAL
MEASURED CDC VALUE > STORED AMBIENT
BY PROXIMITY_RECAL _LVL
USER LEAVES
SENSOR AREA
tCONV_LP
30
PROXIMITY
DETECTION
(INTERNAL)
tCALDIS
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
70
RECALIBRATION TIMEOUT
CALIBRATION ENABLED
tRECAL_TIMEOUT
RECALIBRATION
(INTERNAL)
NOTES
1. SEQUENCE CONVERSION TIME tCONV_LP = tCONV_FP + LP_CONV_DELAY.
2. tCALDIS = tCONV_LP × LP_PROXIMITY_CNT × 4.
3. tRECAL_TIMEOUT = tCONV_LP × LP_PROXIMITY_RECAL.
4. tRECAL = 2 × tCONV_LP .
Figure 32. Example of Low Power Mode Proximity Detection with Forced Recalibration (LP_PROXIMITY_CNT = 4 and LP_PROXIMITY_RECAL = 40)
Rev. B | Page 20 of 68
07727-032
CDC CONVERSION
SEQUENCE
(INTERNAL)
16
AD7147A
FF_SKIP_CNT
The proximity detection fast FIFO is used by the on-chip logic
to determine if proximity is detected. The fast FIFO expects to
receive samples from the converter at a set rate. The fast filter
skip control, FF_SKIP_CNT (Bits[3:0], Address 0x002), is used
to normalize the frequency of the samples going into the FIFO,
regardless of how many conversion stages are in a sequence.
This value determines which CDC samples are not used
(skipped) by the proximity detection fast FIFO.
Determining the FF_SKIP_CNT value is required only once
during the initial setup of the capacitance sensor interface.
Table 13 shows how FF_SKIP_CNT controls the update rate of
the fast FIFO. The recommended value for the setting when
using all 12 conversion stages on the AD7147A is 0000, or no
samples skipped.
Table 14. FF_SKIP_CNT Settings
FF_SKIP
_CNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Decimation = 64
0.768 × (SEQUENCE_STAGE_NUM + 1) ms
1.536 × (SEQUENCE_STAGE_NUM + 1) ms
2.304 × (SEQUENCE_STAGE_NUM + 1) ms
3.072 × (SEQUENCE_STAGE_NUM + 1) ms
3.84 × (SEQUENCE_STAGE_NUM + 1) ms
4.608 × (SEQUENCE_STAGE_NUM + 1) ms
5.376 × (SEQUENCE_STAGE_NUM + 1) ms
6.144 × (SEQUENCE_STAGE_NUM + 1) ms
6.912 × (SEQUENCE_STAGE_NUM + 1) ms
7.68 × (SEQUENCE_STAGE_NUM + 1) ms
8.448 × (SEQUENCE_STAGE_NUM + 1) ms
9.216 × (SEQUENCE_STAGE_NUM + 1) ms
9.984 × (SEQUENCE_STAGE_NUM + 1) ms
10.752 × (SEQUENCE_STAGE_NUM + 1) ms
11.52 × (SEQUENCE_STAGE_NUM + 1) ms
12.288 × (SEQUENCE_STAGE_NUM + 1) ms
FAST FIFO Update Rate
Decimation = 128
1.536 × (SEQUENCE_STAGE_NUM + 1) ms
3.072 × (SEQUENCE_STAGE_NUM + 1) ms
4.608 × (SEQUENCE_STAGE_NUM + 1) ms
6.144 × (SEQUENCE_STAGE_NUM + 1) ms
7.68 × (SEQUENCE_STAGE_NUM + 1) ms
9.216 × (SEQUENCE_STAGE_NUM + 1) ms
10.752 × (SEQUENCE_STAGE_NUM + 1) ms
12.288 × (SEQUENCE_STAGE_NUM + 1) ms
13.824 × (SEQUENCE_STAGE_NUM + 1) ms
15.36 × (SEQUENCE_STAGE_NUM + 1) ms
16.896 × (SEQUENCE_STAGE_NUM + 1) ms
18.432 × (SEQUENCE_STAGE_NUM + 1) ms
19.968 × (SEQUENCE_STAGE_NUM + 1) ms
21.504 × (SEQUENCE_STAGE_NUM + 1) ms
23.04 × (SEQUENCE_STAGE_NUM + 1) ms
24.576 × (SEQUENCE_STAGE_NUM + 1) ms
Rev. B | Page 21 of 68
Decimation = 256
3.072 × (SEQUENCE_STAGE_NUM + 1) ms
6.144 × (SEQUENCE_STAGE_NUM + 1) ms
9.216 × (SEQUENCE_STAGE_NUM + 1) ms
12.288 × (SEQUENCE_STAGE_NUM + 1) ms
15.36 × (SEQUENCE_STAGE_NUM + 1) ms
18.432 × (SEQUENCE_STAGE_NUM + 1) ms
21.504 × (SEQUENCE_STAGE_NUM + 1) ms
24.576 × (SEQUENCE_STAGE_NUM + 1) ms
27.648 × (SEQUENCE_STAGE_NUM + 1) ms
30.72 × (SEQUENCE_STAGE_NUM + 1) ms
33.792 × (SEQUENCE_STAGE_NUM + 1) ms
36.864 × (SEQUENCE_STAGE_NUM + 1) ms
39.936 × (SEQUENCE_STAGE_NUM + 1) ms
43.008 × (SEQUENCE_STAGE_NUM + 1) ms
46.08 × (SEQUENCE_STAGE_NUM + 1) ms
49.152 × (SEQUENCE_STAGE_NUM + 1) ms
AD7147A
FP_PROXIMITY_CNT
REGISTER 0x002
16
CDC
STAGEx_FF_WORD0
STAGEx_FF_WORD1
COMPARATOR 1
|WORD0 – WORD3|
STAGEx_FF_WORD2
STAGEx_FF_WORD3
STAGEx_FF_WORD4
PROXIMITY TIMING
CONTROL LOGIC
PROXIMITY_DETECTION_RATE
REGISTER 0x003
BANK 3 REGISTERS
7
WORD(N)
Σ
N=0
PROXIMITY
FP_PROXIMITY_RECAL
REGISTER 0x004
LP_PROXIMITY_RECAL
REGISTER 0x004
PROXIMITY 2
STAGEx_FF_WORD5
STAGEx_FF_WORD6
STAGEx_FF_WORD7
PROXIMITY 1
LP_PROXIMITY_CNT
REGISTER 0x002
STAGEx_FF_AVG
BANK 3 REGISTERS
8
COMPARATOR 2
|AVERAGE – AMBIENT|
STAGEx_FF_WORDx
PROXIMITY
SLOW_FILTER_UPDATE_LVL
REGISTER 0x003
STAGEx_SF_WORD0
STAGEx_SF_WORD1
STAGEx_SF_WORD2
STAGEx_SF_WORD3
STAGEx_SF_WORD4
STAGEx_SF_WORD5
STAGEx_SF_WORD6
STAGEx_SF_WORD7
PROXIMITY_RECAL_LVL
REGISTER 0x003
STAGEx_SF_AMBIENT
BANK 3 REGISTERS
AMBIENT
VALUE
STAGEx_SF_WORDx
SENSOR
CONTACT
t
BANK 3 REGISTERS
NOTES
1. SLOW_FILTER_EN, WHICH IS THE NAME OF THE OUTPUT OF COMPARATOR 3, IS SET AND SW1 IS CLOSED WHEN |STAGEx_SF_WORD0 – CDC VALUE|
EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE_LVL REGISTER PROVIDING PROXIMITY IS NOT SET.
2. PROXIMITY 1 IS SET WHEN |STAGEx_FF_WORD0 – STAGEx_FF_WORD3| EXCEEDS THE VALUE PROGRAMMED IN THE
PROXIMITY_DETECTION_RATE REGISTER.
3. PROXIMITY 2 IS SET WHEN |AVERAGE – AMBIENT| EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER.
4. DESCRIPTION OF COMPARATOR FUNCTIONS:
COMPARATOR 1: USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR.
COMPARATOR 2: USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR OR APPROACHING A SENSOR VERY SLOWLY.
ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF THE USER INTERACTION.
FOR EXAMPLE, HUMIDITY OR DIRT LEFT BEHIND ON SENSOR.
COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW_FILTER_EN IS SET AND
PROXIMITY IS NOT SET.
Figure 33. Proximity-Detection Logic
Rev. B | Page 22 of 68
07727-033
COMPARATOR 3
|WORD0 – CDC VALUE|
CDC OUTPUT CODE
SLOW_FILTER_EN
SW1
AD7147A
ENVIRONMENTAL CALIBRATION
The ambient compensation control registers provide the host
with access to general setup and controls for the compensation
algorithm. On-chip RAM stores the compensation data for each
conversion stage, as well as setup information specific for each stage.
Figure 34 shows an example of the ideal behavior of a capacitance sensor, where the CDC ambient level remains constant
regardless of the environmental conditions. The CDC output
shown is for a pair of differential button sensors, where one
sensor caused an increase and the other caused a decrease in
measured capacitance when activated. The positive and negative
sensor threshold levels are calculated as a percentage of the
STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW values,
and are based on the threshold sensitivity settings and the
ambient value. These values are sufficient to detect a sensor
contact and result in the AD7147A asserting the INT output
when the threshold levels are exceeded.
CDC AMBIENT VALUE
STAGEx_LOW_THRESHOLD
07727-034
SENSOR 2 INT
ASSERTED
t
CHANGING ENVIRONMENTAL CONDITIONS
Figure 34. Ideal Sensor Behavior with a Constant Ambient Level
CAPACITANCE SENSOR BEHAVIOR WITHOUT
CALIBRATION
Figure 35 shows the typical behavior of a capacitance sensor when
calibration is not applied and the ambient levels drifting over time
as environmental conditions change. As a result of the initial
threshold levels remaining constant while the ambient levels
drift upward, Sensor 2 fails to detect a user contact in this example.
The Capacitance Sensor Behavior with Calibration section
describes how the AD7147A adaptive calibration algorithm
prevents such errors from occurring.
SENSOR 1 INT
ASSERTED
STAGEx_HIGH_THRESHOLD
CDC AMBIENT
VALUE DRIFTING
STAGEx_LOW_THRESHOLD
SENSOR 2 INT
NOT ASSERTED
07727-035
After the AD7147A is configured, the compensation logic runs
automatically with each conversion when the AD7147A is not
being touched. This allows the AD7147A to compensate for
rapidly changing environmental conditions.
STAGEx_HIGH_THRESHOLD
CDC OUTPUT CODES
The AD7147A achieves optimal and reliable sensor performance
by continuously monitoring the CDC ambient levels and compensating for any environmental changes by adjusting the values of
the STAGEx_HIGH_THRESHOLD registers and the STAGEx_
LOW_THRESHOLD registers as described in the Threshold
Equations section. The CDC ambient level is defined as the
output level of the capacitance sensor during periods when the
user is not approaching or in contact with the sensor.
SENSOR 1 INT
ASSERTED
CDC OUTPUT CODES
The AD7147A provides on-chip capacitance sensor calibration
to automatically adjust for environmental conditions that have
an effect on the ambient levels of the capacitance sensor. The
output levels of the capacitance sensor are sensitive to temperature, humidity, and, in some cases, dirt.
t
CHANGING ENVIRONMENTAL CONDITIONS
Figure 35. Typical Sensor Behavior Without Calibration
THRESHOLD EQUATIONS
On-Chip Logic Stage High Threshold
⎛ STAGEx _ OFFSET _ HIGH ⎞ +
⎟
⎠
⎝
4
STAGEx
_
OFFSET
_
HIGH
⎛⎛
⎞⎞
⎜ ⎜ STAGEx _ OFFSET _ HIGH −
⎟⎟
⎠ ⎟ × POS _ THRESHOLD _ SENSITIVITY
4
⎜⎝
16
⎟
⎜
⎟
⎜
⎠
⎝
STAGEx _ HIGH _ THRESHOLD = STAGEx _ SF _ AMBIENT + ⎜
(1)
On-Chip Logic Stage Low Threshold
⎛ STAGEx _ OFFSET _ LOW ⎞ +
⎟
⎝
⎠
4
STAGEx _ OFFSET _ LOW ⎞ ⎞
⎛⎛
⎜ ⎜ STAGEx _ OFFSET _ LOW −
⎟⎟
⎠ ⎟ × NEG _ THRESHOLD _ SENSITIVITY
4
⎜⎝
⎜
⎟
16
⎜
⎟
⎝
⎠
STAGEx _ LOW _ THRESHOLD = STAGEx _ SF _ AMBIENT + ⎜
Rev. B | Page 23 of 68
(2)
AD7147A
AVG_FP_SKIP and AVG_LP_SKIP
CAPACITANCE SENSOR BEHAVIOR WITH
CALIBRATION
The AD7147A on-chip adaptive calibration algorithm prevents
sensor detection errors such as the one shown in Figure 35.
This is achieved by monitoring the CDC ambient levels and
readjusting the initial STAGEx_OFFSET_HIGH and STAGEx_
OFFSET_LOW values according to the amount of ambient drift
measured on each sensor. Based on the new stage offset values,
the internal STAGEx_HIGH_THRESHOLD and STAGEx_
LOW_THRESHOLD values described in Equation 1 and
Equation 2 are automatically updated.
This closed-loop routine ensures the reliability and repeatable
operation of every sensor connected to the AD7147A when they
are subjected to dynamic environmental conditions. Figure 36
shows a simplified example of how the AD7147A applies the
adaptive calibration process, resulting in no interrupt errors
even with changing CDC ambient levels due to dynamic
environmental conditions.
SENSOR 1 INT
ASSERTED
3
CDC OUTPUT CODES
1
Determining the AVG_FP_SKIP and AVG_LP_SKIP values is
required only once during the initial setup of the capacitance
sensor interface. The recommended values for these settings
when using all 12 conversion stages on the AD7147A are as follows:
6
STAGEx_LOW_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
4
•
•
SENSOR 2 INT
ASSERTED
AVG_FP_SKIP = 00 = skip three samples
AVG_LP_SKIP = 00 = skip zero samples
t
1INITIAL STAGEx_OFFSET_HIGH REGISTER VALUE.
2POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD.
3POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD.
4INITIAL STAGEx_LOW_THRESHOLD.
5POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
6POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
SLOW_FILTER_UPDATE_LVL
07727-036
CHANGING ENVIRONMENTAL CONDITIONS
Slow FIFO update rate in full power mode = AVG_FP_SKIP ×
[(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM + 1) ×
(FF_SKIP_CNT + 1) × 4 × 10−6].
Slow FIFO update rate in low power mode =
((AVG_LP_SKIP + 1) × (3 × Decimation Rate) ×
(SEQUENCE_STAGE_NUM + 1) × (4 × 10−6))+
LP_CONV_DELAY.
The slow FIFO is used by the on-chip logic to track the ambient
capacitance value. The slow FIFO expects to receive samples from
the converter at a rate between 33 ms and 40 ms. AVG_FP_SKIP
and AVG_LP_SKIP are used to normalize the frequency of the
samples going into the FIFO, regardless of how many conversion
stages are in a sequence.
CDC AMBIENT
VALUE DRIFTING
5
•
•
STAGEx_HIGH_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
2
In Register 0x001, Bits[13:12] are the slow FIFO skip control for
full power mode, AVG_FP_SKIP. Bits[15:14] in the same register
are the slow FIFO skip control for low power mode, AVG_LP_
SKIP, and determine which CDC samples are not used (skipped)
in the slow FIFO. Changing the values of the AVG_FP_SKIP
and AVG_LP_SKIP bits slows down or speeds up the rate at
which the ambient capacitance value tracks the measured
capacitance value read by the converter.
Figure 36. Typical Sensor Behavior with Calibration Applied on the Data Path
SLOW FIFO
As shown in Figure 33, there are a number of FIFOs implemented on the AD7147A. These FIFOs are located in Bank 3 of
the on-chip memory. The slow FIFOs are used by the on-chip
logic to monitor the ambient capacitance level from each sensor.
SLOW_FILTER_UPDATE_LVL controls whether the most
recent CDC measurement goes into the slow FIFO (slow filter).
The slow filter is updated when the difference between the
current CDC value and the last value of the slow FIFO is
greater than the value of SLOW_FILTER_UPDATE_LVL,
which is in the Ambient Control 1 register (AMB_COMP_
CTRL1), Address 0x003.
Rev. B | Page 24 of 68
AD7147A
ADAPTIVE THRESHOLD AND SENSITIVITY
The AD7147A provides an on-chip, self-adjusting adaptive
threshold and sensitivity algorithm. This algorithm continuously monitors the output levels of each sensor and automatically
rescales the threshold levels in proportion to the sensor area
covered by the user. As a result, the AD7147A maintains
optimal threshold and sensitivity levels for all users regardless
of their finger sizes.
finger results in a large average maximum or minimum value,
whereas a small finger results in smaller values. When the
average maximum or minimum value changes, the threshold
levels are rescaled to ensure that the threshold levels are
appropriate for the current user. Figure 38 shows how the
minimum and maximum sensor responses are tracked by the
on-chip logic.
The threshold level is always referenced from the ambient level
and is defined as the CDC converter output level that must be
exceeded before a valid sensor contact can occur. The sensitivity
level is defined as how sensitive the sensor must be before a
valid contact can be registered.
Reference A in Figure 37 shows a less sensitive threshold level
for a user with small fingers and demonstrates the disadvantages
of a fixed threshold level.
Figure 37 provides an example of how the adaptive threshold
and sensitivity algorithm works. The positive and negative
sensor threshold levels are calculated as a percentage of the
STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW
values and are based on the threshold sensitivity settings and
the ambient value. After the AD7147A is configured, initial
estimates are supplied for both STAGEx_OFFSET_HIGH
and STAGEx_OFFSET_LOW, and then the calibration engine
automatically adjusts the STAGEx_HIGH_THRESHOLD and
STAGEx_LOW_THRESHOLD values for sensor response.
The AD7147A tracks the average maximum and minimum
values measured from each sensor. These values provide an
indication of how the user is interacting with the sensor. A large
By enabling the adaptive threshold and sensitivity algorithm, the
positive and negative threshold levels are determined by the
POS_THRESHOLD_SENSITIVITY and NEG_THRESHOLD_
SENSITIVITY bit values and by the most recent average maximum sensor output value. These bits can be used to select 16
different positive and negative sensitivity levels ranging between
25% and 95.32% of the most recent average maximum output
level referenced from the ambient value. The smaller the sensitivity percentage setting, the easier it is to trigger a sensor
activation. Reference B shows that the positive adaptive threshold
level is set at almost midsensitivity with a 62.51% threshold
level by setting POS_THRESHOLD_ SENSITIVITY = 1000.
Figure 37 also provides a similar example for the negative threshold level, with NEG_THRESHOLD_SENSITIVITY = 0011.
AVERAGE MAXIMUM VALUE
STAGEx_OFFSET_HIGH
IS UPDATED
AVERAGE MAXIMUM VALUE
62.51% =
POS_THRESHOLD
_SENSITIVITY
A
STAGEx_OFFSET_HIGH
95.32%
STAGEx_OFFSET_HIGH
IS UPDATED
62.51% =
POS_THRESHOLD
_SENSITIVITY
25%
25%
B
AMBIENT LEVEL
25%
NEG_THRESHOLD_SENSITIVITY = 39.08%
STAGEx_OFFSET_LOW
IS UPDATED
STAGEx_OFFSET_LOW
25%
NEG_THRESHOLD_SENSITIVITY = 39.08%
95.32%
STAGEx_OFFSET_LOW
IS UPDATED
95.32%
SENSOR CONTACTED
BY LARGE FINGER
SENSOR CONTACTED
BY SMALL FINGER
Figure 37. Example of Threshold Sensitivity (POS_THRESHOLD_SENSITIVITY = 1000, NEG_THRESHOLD_SENSITIVITY = 0011)
Rev. B | Page 25 of 68
07727-037
CDC OUTPUT CODES
95.32%
AD7147A
STAGEx_MAX_WORD0
STAGEx_MAX_WORD1
STAGEx_MAX_WORD2
BANK 3 REGISTERS
STAGEx_MAX_WORD3
Σ-Δ
16-BIT
CDC
16
MAXIMUM
LEVEL
DETECTION
LOGIC
STAGEx_MAX_AVG
BANK 3 REGISTERS
STAGEx_MAX_TEMP
BANK 3 REGISTERS
STAGEx_HIGH_THRESHOLD
BANK 3 REGISTERS
STAGEx_MIN_WORD0
STAGEx_MIN_WORD1
STAGEx_MIN_WORD2
BANK 3 REGISTERS
STAGEx_MIN_WORD3
MINIMUM
LEVEL
DETECTION
LOGIC
STAGEx_MIN_AVG
BANK 3 REGISTERS
STAGEx_LOW_THRESHOLD
BANK 3 REGISTERS
07727-038
STAGEx_MIN_TEMP
BANK 3 REGISTERS
Figure 38. Tracking the Minimum and Maximum Average Sensor Values
Table 15. Additional Information About Environmental Calibration and Adaptive Threshold Registers
Register/Bit
NEG_THRESHOLD_SENSITIVITY
NEG_PEAK_DETECT
Register
Location
Bank 2
Bank 2
POS_THRESHOLD_SENSITIVITY
POS_PEAK_DETECT
Bank 2
Bank 2
STAGEx_OFFSET_LOW
Bank 2
STAGEx_OFFSET_HIGH
Bank 2
STAGEx_OFFSET_HIGH_CLAMP
Bank 2
STAGEx_OFFSET_LOW_CLAMP
Bank 2
STAGEx_SF_AMBIENT
Bank 3
STAGEx_HIGH_THRESHOLD
STAGEx_LOW_THRESHOLD
Bank 3
Bank 3
Description
Used in Equation 2. This value is programmed once at startup.
Used by internal adaptive threshold logic only.
The NEG_PEAK_DETECT is set to a percentage of the difference between the ambient
CDC value and the minimum average CDC value. If the output of the CDC approaches the
NEG_PEAK_DETECT percentage of the minimum average, the minimum average value is updated.
Used in Equation 1. This value is programmed once at startup.
Used by internal adaptive threshold logic only.
The POS_PEAK_DETECT is set to a percentage of the difference between the ambient
CDC value and the maximum average CDC value. If the output of the CDC approaches the
POS_PEAK_DETECT percentage of the maximum average, the maximum average value is updated.
Used in Equation 2. An initial value (based on sensor characterization) is programmed into
this register at startup. The AD7147A on-chip calibration algorithm automatically updates
this register based on the amount of sensor drift due to changing ambient conditions. Set
this register to 80% of the STAGEx_OFFSET_LOW_CLAMP value.
Used in Equation 1. An initial value (based on sensor characterization) is programmed into
this register at startup. The AD7147A on-chip calibration algorithm automatically updates
this register based on the amount of sensor drift due to changing ambient conditions. Set
this register to 80% of the STAGEx_OFFSET_HIGH_CLAMP value.
Used by internal environmental calibration and adaptive threshold algorithms only.
An initial value (based on sensor characterization) is programmed into this register at startup.
The value in this register prevents a user from causing the output value of a sensor to exceed
the expected nominal value.
Set this register to the maximum expected sensor response or the maximum change in CDC
output code.
Used by internal environmental calibration and adaptive threshold algorithms only.
An initial value (based on sensor characterization) is programmed into this register at startup.
The value in this register prevents a user from causing the output value of a sensor to exceed
the expected nominal value.
Set this register to the minimum expected sensor response or the minimum change in CDC
output code.
Used in Equation 1 and Equation 2. This is the ambient sensor output when the sensor is not
touched, as calculated using the slow FIFO.
Equation 1 value.
Equation 2 value.
Rev. B | Page 26 of 68
AD7147A
INTERRUPT OUTPUT
The AD7147A has an interrupt output that triggers an interrupt
service routine on the host processor. The INT signal is on Pin A1
and is an open-drain output. There are three types of interrupt
events on the AD7147A: a CDC conversion-complete interrupt,
a sensor-touch interrupt, and a GPIO interrupt. Each interrupt
has enable and status registers. The conversion-complete and
sensor-touch (sensor-activation) interrupts can be enabled on
a per-conversion-stage basis. The status registers indicate what
type of interrupt triggered the INT pin. Status registers are cleared,
and the INT signal is reset high during a read operation. The
signal returns high as soon as the read address has been set up.
CDC CONVERSION-COMPLETE INTERRUPT
The AD7147A interrupt signal asserts low to indicate the completion of a conversion stage and that new conversion result data is
available in the registers.
The interrupt can be independently enabled for each conversion
stage. Each conversion-stage-complete interrupt can be enabled via
the STAGE_COMPLETE_INT_ENABLE register (Address 0x007).
This register has a bit that corresponds to each conversion stage.
Setting this bit to 1 enables the interrupt for that stage. Clearing this
bit to 0 disables the conversion-complete interrupt for that stage.
The AD7147A interrupt should be enabled only for the last
stage in a conversion sequence. For example, if there are five
conversion stages, only the conversion-complete interrupt for
STAGE4 is enabled. Therefore, INT asserts only when all five
conversion stages are complete and the host can read new data
from all five result registers. The interrupt is cleared by reading
the STAGE_COMPLETE_INT_STATUS register located at
Address 0x00A.
SENSOR-TOUCH INTERRUPT
The sensor-touch interrupt mode is implemented when the host
processor requires an interrupt only when a sensor is contacted.
Configuring the AD7147A into this mode results in the interrupt
being asserted when the user makes contact with the sensor and
again when the user stops touching the sensor. The second
interrupt is required to alert the host processor that the user is
no longer contacting the sensor.
The registers located at Address 0x005 and Address 0x006 are
used to enable the interrupt output for each stage. The registers
located at Address 0x008 and Address 0x009 are used to read
back the interrupt status for each stage.
Figure 39 shows the interrupt output timing during contact with
one of the sensors connected to STAGE0 while operating in the
sensor-touch interrupt mode. For a low limit configuration, the
interrupt output is asserted as soon as the sensor is contacted and
again after the user has stopped touching the sensor. (Note that
the interrupt output remains low until the host processor reads
back the interrupt status registers located at Address 0x008 and
Address 0x009.)
The interrupt output is asserted when there is a change in the
interrupt status bits. This can indicate that a user is touching the
sensor(s) for the first time, the number of sensors being touched
has changed, or the user is no longer touching the sensor(s).
Reading the status bits in the interrupt status register shows the
current sensor activations.
FINGER ON SENSOR
FINGER OFF SENSOR
Register 0x00A is the conversion-complete interrupt status
register. Each bit in this register corresponds to a conversion
stage. If a bit is set, it means that the conversion-complete
interrupt for the corresponding stage was triggered. This
register is cleared upon a read if the underlying condition
that triggered the interrupt is not present.
1
3
CONVERSION
STAGE
STAGE0
2
STAGE1
4
SERIAL
READBACK
1USER TOUCHING SENSOR.
2ADDRESS 0x008 IS READ BACK TO CLEAR INTERRUPT.
3USER STOPS TOUCHING SENSOR.
4ADDRESS 0x008 IS READ BACK TO CLEAR INTERRUPT.
Figure 39. Example of Sensor-Touch Interrupt
Rev. B | Page 27 of 68
07727-039
INT OUTPUT
AD7147A
STAGE0
CONVERSIONS
STAGE1
STAGE2
STAGE3
STAGE4
STAGE5
STAGE6
STAGE7
STAGE8
STAGE9
STAGE10
STAGE11
INT
1
2
3
SERIAL
READS
NOTES
THIS IS AN EXAMPLE OF A CDC CONVERSION-COMPLETE INTERRUPT.
THIS TIMING EXAMPLE SHOWS THAT THE INTERRUPT OUTPUT HAS BEEN ENABLED TO BE ASSERTED AT THE END OF A CONVERSION CYCLE FOR
STAGE0, STAGE5, AND STAGE9. THE INTERRUPTS FOR ALL OTHER STAGES HAVE BEEN DISABLED.
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE5, AND STAGE9 (x = 0, 5, 9):
STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0
STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 1
SERIAL READBACK REQUIREMENTS FOR STAGE0, STAGE5, AND STAGE9 (THIS READBACK OPERATION IS REQUIRED TO CLEAR THE INTERRUPT OUTPUT.):
THE STAGE0_COMPLETE_INT_STATUS (ADDRESS 0x00A) BIT
THE STAGE5_COMPLETE_INT_STATUS (ADDRESS 0x00A) BIT
THE STAGE9_COMPLETE_INT_STATUS (ADDRESS 0x00A) BIT
1READ
2READ
3READ
07727-040
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE1 THROUGH STAGE8, STAGE10, AND STAGE11 (x = 1, 2, 3, 4, 6, 7, 8, 10, 11):
STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0
STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 0
Figure 40. Example of Configuring the Registers for Conversion-Complete Interrupt Setup
CONVERSIONS
STAGE0
STAGE1
STAGE2
STAGE3
STAGE4
STAGE5
STAGE6
STAGE7
STAGE8
STAGE9
STAGE10
STAGE11
INT
1
4
2
SERIAL
READS
NOTES
THIS IS AN EXAMPLE OF A SENSOR-TOUCH INTERRUPT FOR A CASE WHERE THE LOW THRESHOLD LEVELS WERE EXCEEDED.
FOR EXAMPLE, THE SENSOR CONNECTED TO STAGE0 AND STAGE9 WERE CONTACTED, AND THE LOW THRESHOLD LEVELS WERE EXCEEDED, RESULTING
IN THE INTERRUPT BEING ASSERTED. THE STAGE6 INTERRUPT WAS NOT ASSERTED BECAUSE THE USER DID NOT CONTACT THE SENSOR CONNECTED TO
STAGE6.
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE6, AND STAGE9 (x = 0, 6, 9):
STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 1
STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0
STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 0
SERIAL READBACK REQUIREMENTS FOR STAGE0 AND STAGE9 (THIS READBACK OPERATION IS REQUIRED TO CLEAR THE INTERRUPT OUTPUT.):
1READ THE STAGE0_LOW_INT_STATUS (ADDRESS 0x008) BIT
2READ THE STAGE5_LOW_INT_STATUS (ADDRESS 0x008) BIT
Figure 41. Example of Configuring the Registers for Sensor-Touch Interrupt Setup
Rev. B | Page 28 of 68
07727-041
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE1 THROUGH STAGE7, STAGE8, STAGE10, AND STAGE11 (x = 1, 2, 3, 4, 5, 7, 8, 10, 11):
STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0
STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 0
AD7147A
GPIO INT OUTPUT CONTROL
The INT output signal can be controlled by the GPIO pin when
the GPIO is configured as an input. The GPIO is configured as
an input by setting the GPIO_SETUP bits in the interrupt enable
register to 01. See the General-Purpose Input/Output (GPIO)
section for more information on how to configure the GPIO.
Enable the GPIO interrupt by setting the GPIO_INT_ENABLE
bit in Register 0x007 to 1, or disable the GPIO interrupt by
clearing this bit to 0. The GPIO status bit in the conversioncomplete interrupt status register reflects the status of the GPIO
interrupt. This bit is set to 1 when the GPIO has triggered INT.
The bit is cleared upon reading the GPIO_INT_STATUS bit if the
condition that caused the interrupt is no longer present.
The GPIO interrupt can be set to trigger on a rising edge, falling
edge, high level, or low level at the GPIO input pin. Table 16 shows
how the settings of the GPIO_INPUT_CONFIG bits in the interrupt enable (STAGE_LOW_INT_ENABLE) register affect the
behavior of INT.
Figure 42 to Figure 45 show how the interrupt output is cleared
upon a read from the GPIO_INT_STATUS bit.
Table 16. GPIO Interrupt Behavior
GPIO_INPUT_CONFIG
00 = Negative Level Triggered
00 = Negative Level Triggered
01 = Positive Edge Triggered
01 = Positive Edge Triggered
10 = Negative Edge Triggered
10 = Negative Edge Triggered
11 = Positive Level Triggered
11 = Positive Level Triggered
GPIO Pin
1
0
1
0
1
0
1
0
GPIO_INT_STATUS
0
1
1
0
0
1
1
0
INT
INT Behavior
1
0
0
1
1
0
0
1
Not triggered
Asserted while signal on GPIO pin is low
Pulses low at low-to-high GPIO transition
Not triggered
Pulses low at high-to-low GPIO transition
Not triggered
Asserted while signal on GPIO pin is high
Not triggered
Rev. B | Page 29 of 68
AD7147A
1
1
SERIAL
READBACK
SERIAL
READBACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO
INPUT
GPIO
INPUT
INT
OUTPUT
INT
OUTPUT
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO
INPUT
GPIO
INPUT
INT
OUTPUT
1READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT.
1READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT.
Figure 42. Example of INT Output Controlled by the GPIO Input
(GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 00)
Figure 44. Example of INT Output Controlled by the GPIO Input
(GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 10)
1
1
SERIAL
READBACK
SERIAL
READBACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO
INPUT
GPIO
INPUT
INT
OUTPUT
INT
OUTPUT
GPIO
INPUT
INT
OUTPUT
INT
OUTPUT
07727-043
GPIO
INPUT
Figure 43. Example of INT Output Controlled by the GPIO Input
(GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 01)
NOTES
1READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT.
Figure 45. Example of INT Output Controlled by the GPIO Input
(GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 11)
Rev. B | Page 30 of 68
07727-045
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
1READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT.
07727-044
07727-042
INT
OUTPUT
AD7147A
OUTPUTS
ACSHIELD OUTPUT
The AD7147A measures the capacitance between CINx and
ground. Any capacitance to ground on the signal path between
the CINx pins and the sensor is included in the AD7147A
conversion result.
To eliminate stray capacitance to ground, the ACSHIELD signal should
be used to shield the connection between the sensor and CINx,
as shown in Figure 46. The plane around the sensors should also
be connected to ACSHIELD.
When the GPIO is configured as an output, the voltage level on
the pin is set to either a low level or a high level, as defined by
the GPIO_SETUP bits (see Table 17).
The GPIO_INPUT_CONFIG bits in the STAGE_LOW_INT_
ENABLE register determine the response of the AD7147A to a
signal on the GPIO pin when the GPIO is configured as an
input. The GPIO can be configured as either active high or
active low, as well as either edge triggered or level triggered (see
Table 18).
Table 18. GPIO_INPUT_CONFIG Bits
GPIO_INPUT_CONFIG
00
01
10
11
07727-046
Figure 46. ACSHIELD
The ACSHIELD output is the same signal waveform as the excitation
signal on CINx. Therefore, there is no ac current between CINx
and ACSHIELD, and any capacitance between these pins does not
affect the CINx charge transfer.
Using ACSHIELD eliminates capacitance-to-ground pickup, which
means that the AD7147A can be placed up to 10 cm away from
the sensors. This allows the AD7147A to be placed on a separate
PCB from that of the sensors if the connections between the
sensors and the CINx inputs are correctly shielded using
ACSHIELD.
When GPIO is configured as an input, it triggers the interrupt
output on the AD7147A.
Table 16 lists the interrupt output behavior for each of the GPIO
configuration setups.
USING THE GPIO TO TURN ON/OFF AN LED
The GPIO on the AD7147A can be used to turn an LED on and
off by setting the GPIO as either output high or low. Setting the
GPIO output high turns on the LED; setting the GPIO output
low turns off the LED. The GPIO pin connects to a transistor
that provides the drive current for the LED. Suitable transistors
include the KTC3875 from Korea Electronics Co., Ltd. (KEC).
V
KTC3875 CC
OR SIMILAR
AD7147A
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
The AD7147A has one GPIO pin. It can be configured as an input
or an output. The GPIO_SETUP Bits[13:12] in the STAGE_LOW_
INT_ENABLE register determine how the GPIO pin is configured.
GPIO
Figure 47. Controlling an LED Using the GPIO
Table 17. GPIO_SETUP Bits
GPIO_SETUP
00
01
10
11
GPIO Configuration
Triggered on negative level (active low)
Triggered on positive edge (active high)
Triggered on negative edge (active low)
Triggered on positive level (active high)
07727-047
SENSOR PCB
CIN0 AD7147A
CIN1
CIN2
CIN3
ACSHIELD GND
GPIO Configuration
GPIO disabled
Input
Output low
Output high
Rev. B | Page 31 of 68
AD7147A
SERIAL INTERFACES
Bits[15:11] of the command word must be set to 11100 to
successfully begin a bus transaction.
The AD7147A is available with an SPI interface. The AD7147A-1
is available with an I2C-compatible interface. Both parts are the
same, with the exception of the serial interface.
Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates
a write.
SPI INTERFACE
Bits[9:0] contain the target register address. When reading or
writing to more than one register, this address indicates the
address of the first register to be written to or read from.
The AD7147A has a 4-wire serial peripheral interface (SPI).
The SPI has a data input pin (SDI) for inputting data to the
device, a data output pin (SDO) for reading data back from the
device, and a data clock pin (SCLK) for clocking data into and
out of the device. A chip select pin (CS) enables or disables the
serial interface. CS is required for correct operation of the SPI.
Data is clocked out of the AD7147A on the negative edge of
SCLK and data is clocked into the device on the positive edge
of SCLK.
Writing Data
Data is written to the AD7147A in 16-bit words. The first word
written to the device is the command word, with the read/write
bit set to 0. The master then supplies the 16-bit input data-word
on the SDI line. The AD7147A clocks the data into the register
addressed in the command word. If there is more than one word of
data to be clocked in, the AD7147A automatically increments
the address pointer and clocks the subsequent data-word into
the next register.
SPI Command Word
All data transactions on the SPI bus begin with the master
taking CS from high to low and sending out the command
word. This indicates to the AD7147A whether the transaction is
a read or a write and provides the address of the register from
which to begin the data transfer. The following bit map shows
the SPI command word.
MSB
15
1
14
1
13
1
12
0
11
0
The AD7147A continues to clock in data on the SDI line until
either the master finishes the write transition by pulling CS high
or the address pointer reaches its maximum value. The AD7147A
address pointer does not wrap around. When it reaches its
maximum value, any data provided by the master on the SDI
line is ignored by the AD7147A.
LSB
9:0
Register address
10
R/W
16-BIT COMMAND WORD
ENABLE WORD
SDI
CW
15
CW
14
CW
13
R/W
CW
12
CW
11
t2
SCLK
CW
10
REGISTER ADDRESS
CW
9
CW
8
t4
1
t1
2
3
4
5
CW
7
CW
6
CW
5
CW
4
16-BIT DATA
CW
3
CW
2
CW
1
CW
0
D15
D14
D13
D2
D1
D0
t5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
30
31
32
t8
t3
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR THE CONTROL WORD AND 16 BITS FOR THE DATA.
3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS)
Figure 48. Single Register Write SPI Timing
Rev. B | Page 32 of 68
07727-048
CS
AD7147A
16-BIT COMMAND WORD
ENABLE WORD
SDI
SCLK
CW
15
CW
14
CW
13
CW
12
CW
11
2
3
4
5
1
DATA FOR STARTING
REGISTER ADDRESS
STARTING REGISTER ADDRESS
R/W
CW
10
CW
9
6
CW
8
7
CW
7
8
9
CW
6
10
CW
5
11
CW
4
CW
3
12
CW
2
13
CW
1
14
CW
0
15
D15 D14
16
17
DATA FOR NEXT
REGISTER ADDRESS
D1
18
D15 D14
D0
31
32
33
D1
34
D15
D0
47
48
49
CS
07727-049
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB-JUSTIFIED REGISTER ADDRESS)
Figure 49. Sequential Register Write SPI Timing
16-BIT COMMAND WORD
ENABLE WORD
SDI
CW
15
CW
13
CW
14
R/W
CW
12
CW
11
t2
SCLK
CW
10
REGISTER ADDRESS
CW
9
CW
8
CW
7
t4
1
2
t1
3
4
5
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
X
X
X
X
X
X
t5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
30
t3
31
32
t8
CS
t6
SDO
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
D15
D14
t7
D13
D2
D1
D0
XXX
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE REGISTER DATA IS READ BACK ON THE SDO PIN.
4. X DENOTES DON’T CARE.
5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS)
07727-050
16-BIT READBACK DATA
Figure 50. Single Register Readback SPI Timing
Reading Data
A read transaction begins when the master writes the command
word to the AD7147A with the read/write bit set to 1. The
master then supplies 16 clock pulses per data-word to be read,
and the AD7147A clocks out data from the addressed register
on the SDO line. The first data-word is clocked out on the first
falling edge of SCLK following the command word, as shown in
Figure 50.
The AD7147A continues to clock out data on the SDO line if
the master continues to supply the clock signal on SCLK. The
read transaction finishes when the master takes CS high. If the
AD7147A address pointer reaches its maximum value, the
AD7147A repeatedly clocks out data from the addressed register.
The address pointer does not wrap around.
Rev. B | Page 33 of 68
AD7147A
16-BIT COMMAND WORD
ENABLE WORD
R/W
REGISTER ADDRESS
SDI
CW
15
CW
14
CW
13
CW
12
CW
11
CW
10
CW
9
CW
8
CW
7
SCLK
1
2
3
4
5
6
7
8
9
CW
6
10
CW
5
11
CW
4
12
CW
3
13
CW
2
14
CW
1
15
CW
0
X
X
16
17
18
XXX XXX XXX
D15
D14
X
31
X
32
X
X
33
34
X
X
47
48
X
49
CS
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX
XXX XXX XXX
D1
D0
READBACK DATA FOR
STARTING REGISTER ADDRESS
D15
D14
D1
D0
D15
READBACK DATA FOR
NEXT REGISTER ADDRESS
NOTES
1. MULTIPLE REGISTERS CAN BE READ BACK CONTINUOUSLY.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDO PIN.
4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
5. X DENOTES DON’T CARE.
6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB-JUSTIFIED REGISTER ADDRESS)
07727-051
SDO
Figure 51. Sequential Register Readback SPI Timing
I2C-COMPATIBLE INTERFACE
The AD7147A-1 supports the industry standard, 2-wire I2C
serial interface protocol. The two wires associated with the
I2C timing are the SCLK and SDA inputs. The SDA is an I/O pin
that allows both register write and register readback operations. The
AD7147A-1 is always a slave device on the I2C serial interface bus.
The AD7147A-1 has a 7-bit device address, Address 0101 1XX.
The lower two bits are set by tying the ADD0 and ADD1 pins
high or low. The AD7147A-1 responds when the master device
sends its device address over the bus. The AD7147A-1 cannot
initiate data transfers on the bus.
Table 19. AD7147A-1 I2C Device Address
ADD1
0
0
1
1
I2C Address
0101 100
0101 101
0101 110
0101 111
ADD0
0
1
0
1
Data Transfer
2
Data is transferred over the I C serial interface in 8-bit bytes.
The master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data
line, SDA, while the serial clock line, SCLK, remains high. This
indicates that an address/data stream follows.
All slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus an R/W bit that determines the
direction of the data transfer. The peripheral whose address
corresponds to the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as the
acknowledge bit. All other devices on the bus then remain idle
while the selected device waits for data to be read from or written
to it. If the R/W bit is 0, the master writes to the slave device. If
the R/W bit is 1, the master reads from the slave device.
Data is sent over the serial bus in a sequence of nine clock
pulses—eight bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur during
the low period of the clock signal and remain stable during the
high period, because a low-to-high transition when the clock is
high can be interpreted as a stop signal. The number of data
bytes transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave devices
can handle.
When all data bytes are read or written, a stop condition is
established. A stop condition is defined by a low-to-high
transition on SDA while SCLK remains high. If the AD7147A
encounters a stop condition, it returns to its idle condition, and
the address pointer register resets to Address 0x00.
Rev. B | Page 34 of 68
AD7147A
START
AD7147A-1 DEVICE ADDRESS
REGISTER ADDRESS [A15:A8]
REGISTER ADDRESS [A7:A0]
SDA
DEV
A6
DEV
A5
DEV
A4
DEV DEV DEV
A3
A2
A1
t1
DEV
A0
R/W
ACK
7
8
9
A15
A9
A14
A8
ACK
A7
A6
A1
A0
t3
SCLK
1
2
3
4
5
6
10
11
16
17
18
19
20
25
26
t2
ACK
D15
D14
D9
REGISTER DATA [D7:D0]
ACK
D8
D7
D6
t4
27
28
29
34
D1
D0
36
37
t6
38
43
AD7147A-1 DEVICE ADDRESS
ACK
t5
35
START
t8
44
45
DEV
A6
DEV
A5
1
2
DEV
A4
t7
46
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE X IS A DON’T CARE BIT.
4. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X IS A DON’T CARE BIT.
5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
3
07727-052
STOP
REGISTER DATA [D15:D8]
Figure 52. Example of I2C Timing for Single Register Write Operation
Writing Data over the I2C Bus
The process for writing to the AD7147A-1 over the I2C bus is
shown in Figure 52 and Figure 54. The device address is sent
over the bus, followed by the R/W bit being set to 0 and then
two bytes of data that contain the 10-bit address of the internal
data register to be written. The following bit map shows the
upper register address bytes. Note that Bit 7 to Bit 2 in the upper
address byte are don’t care bits. The address is contained in the
10 LSBs of the register address bytes.
MSB
7
X
LSB
6
X
5
X
4
X
3
X
2
X
1
Register
Address
Bit 9
0
Register
Address
Bit 8
The following bit map shows the lower register address bytes:
MSB
7
Reg
Add
Bit 7
6
Reg
Add
Bit 6
5
Reg
Add
Bit 5
4
Reg
Add
Bit 4
3
Reg
Add
Bit 3
2
Reg
Add
Bit 2
1
Reg
Add
Bit 1
LSB
0
Reg
Add
Bit 0
The third data byte contains the eight MSBs of the data to be
written to the internal register. The fourth data byte contains
the eight LSBs of data to be written to the internal register.
The AD7147A-1 address pointer register automatically increments after each write. This allows the master to sequentially
write to all registers on the AD7147A-1 in the same write
transaction. However, the address pointer register does not
wrap around after the last address. Therefore, any data written
to the AD7147A-1 after the address pointer has reached its
maximum value is discarded.
All registers on the AD7147A-1 are 16 bits. Two consecutive
8-bit data bytes are combined and written to the 16-bit registers.
To avoid errors, all writes to the device must contain an even
number of data bytes.
To finish the transaction, the master generates a stop condition
on SDO, or generates a repeat start condition if the master is to
maintain control of the bus.
Reading Data over the I2C Bus
To read from the AD7147A-1, the address pointer register must
first be set to the address of the required internal register. The
master performs a write transaction and then writes to the
AD7147A-1 to set the address pointer. Next, the master outputs
a repeat start condition to keep control of the bus, or if this is
not possible, ends the write transaction with a stop condition.
A read transaction is initiated, with the R/W bit set to 1.
The AD7147A-1 supplies the upper eight bits of data from the
addressed register in the first readback byte, followed by the
lower eight bits in the next byte. This is shown in Figure 53 and
Figure 54.
Because the address pointer automatically increments after each
read, the AD7147A-1 continues to output readback data until
the master sends a no acknowledge and stop condition to the
bus. If the address pointer reaches its maximum value and the
master continues to read from the part, the AD7147A-1 repeatedly
sends data from the last register that was addressed.
Rev. B | Page 35 of 68
AD7147A
START
AD7147A-1 DEVICE ADDRESS
REGISTER ADDRESS [A15:A8]
REGISTER ADDRESS [A7:A0]
SDA
DEV
A6
DEV
A5
DEV
A4
DEV DEV DEV
A2
A1
A3
t1
DEV
A0
R/W
ACK
7
8
9
A15
A9
A14
A8
A7
ACK
A6
A1
A0
ACK
t3
SCLK
1
2
3
5
4
6
10
11
16
17
18
19
20
25
26
27
t2
P
AD7147A-1 DEVICE ADDRESS
SR
DEV
A6
DEV
A5
DEV
A1
USING
REPEATED START
REGISTER DATA [D7:D0]
DEV
A0
D7
ACK
R/W
D6
t4
28
P
34
30
29
D1
DEV
A6
DEV
A5
35
36
DEV
A1
37
38
t6
44
39
R/W ACK
D7
34
30
45
D6
DEV
A6
DEV
A5
1
2
DEV
A4
t7
46
3
P
D1
D0
ACK
t5
t4
29
AD7147A-1 DEVICE ADDRESS
ACK
REGISTER DATA [D7:D0]
DEV
A0
SEPARATE READ AND
WRITE TRANSACTIONS
28
D0
t5
AD7147A-1 DEVICE ADDRESS
S
t8
35
36
37
38
44
39
45
46
07727-053
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA.
4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB Xs ARE DON'T CARE BITS.
5. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB Xs ARE DON’T CARE BITS.
6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY LOW ACK BITS.
7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.
Figure 53. Example of I2C Timing for Single Register Readback Operation
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
ACK
WRITE DATA
LOW BYTE [7:0]
ACK
ACK
REGISTER ADDR
LOW BYTE
WRITE DATA
HIGH BYTE [15:8]
ACK
REGISTER ADDR
[7:0]
ACK
SR
REGISTER ADDR
[15:8]
ACK
6-BIT DEVICE
ADDRESS W
ACK
S
ACK
WRITE
P
6-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
ACK
REGISTER ADDR
HIGH BYTE
ACK
6-BIT DEVICE
ADDRESS W
R
ACK
S
ACK
READ (USING REPEATED START)
READ DATA
LOW BYTE [7:0]
ACK P
S = START BIT
P = STOP BIT
SR = REPEATED START BIT
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
ACK = ACKNOWLEDGE BIT
ACK = NO ACKNOWLEDGE BIT
READ DATA
HIGH BYTE [15:8]
ACK
S 6-BIT DEVICE
ADDRESS
ACK
P
READ DATA
LOW BYTE [7:0]
ACK P
07727-054
OUTPUT FROM MASTER
OUTPUT FROM AD7147-1
REGISTER ADDR
LOW BYTE
R
ACK
REGISTER ADDR
HIGH BYTE
ACK
6-BIT DEVICE
ADDRESS W
ACK
S
ACK
READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS)
Figure 54. Example of Sequential I2C Write and Readback Operations
VDRIVE INPUT
The supply voltage for the pins (SDO, SDI, SCLK, SDA, CS,
INT, and GPIO) associated with both the I2C and SPI serial
interfaces is supplied from the VDRIVE pin and is separate from the
main VCC supply.
This allows the AD7147A to be connected directly to processors
whose supply voltage is less than the minimum operating voltage
of the AD7147A without the need for external level-shifters.
The VDRIVE pin can be connected to voltage supplies as low as
1.65 V and as high as VCC.
Rev. B | Page 36 of 68
AD7147A
PCB DESIGN GUIDELINES
CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS
Table 20.
Parameter
Distance from Edge of Any Sensor to Edge of Grounded Metal Object
Distance Between Sensor Edges 1
Distance Between Bottom of Sensor Board and Controller Board or Grounded
Metal Casing 2
Symbol
D1
D2 = D3 = D4
D5
Min
0.1
0
Typ
Max
1.0
Unit
mm
mm
mm
1
The distance is dependent on the application and the position of the switches relative to each other and with respect to the user’s finger position and handling.
Adjacent sensors with no space between them are implemented differentially.
2
The 1.0 mm specification is intended to prevent direct sensor board contact with any conductive material. This specification, however, does not guarantee an absence
of EMI coupling from the controller board to the sensors. To avoid potential EMI-coupling issues, place a grounded metal shield between the capacitive sensor board
and the main controller board, as shown in Figure 57.
CAPACITIVE SENSOR BOARD
METAL OBJECT
CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
CAPACITIVE SENSOR
PRINTED CIRCUIT
8-WAY
SWITCH
07727-056
D5
Figure 56. Capacitive Sensor Board, Side View
D4
CAPACITIVE SENSOR BOARD
SLIDER
D5
BUTTONS
CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
D3
07727-057
GROUNDED METAL SHIELD
Figure 57. Capacitive Sensor Board with Grounded Shield
D2
WLCSP PACKAGE
07727-055
D1
Figure 55. Capacitive Sensor Board, Top View
Nonsolder mask definer PCB fabrication is recommended to
increase the reliability of the solder joint.
The copper pad on the user’s PCB should be 80% of the diameter
of the WLCSP ball. The solder mask opening should be 50 μm
on either side of the copper pad.
See the AN-617 Application Note, MicroCSP™ Wafer Level Chip
Scale Package, for more information and layout guidelines for
the WLCSP package.
Rev. B | Page 37 of 68
AD7147A
POWER-UP SEQUENCE
To power up the AD7147A, use the following sequence when
initially developing the AD7147A and microprocessor serial
interface:
1.
2.
3.
Turn on the power supplies to the AD7147A.
Write to the Bank 2 registers at Address 0x080 through
Address 0x0DF. These registers are contiguous; therefore, a
sequential register write sequence can be applied.
Note that the Bank 2 register values are unique for each
application. Register values come from characterization of
the sensor in the application. The characterization process
is outlined in the AN-929 Application Note, available from
Analog Devices.
Write to the Bank 1 registers at Address 0x000 through
Address 0x007, outlined as follows. These registers are
contiguous; therefore, a sequential register write sequence
can be applied (see Figure 49 and Figure 54).
Caution: At this time, Address 0x001 must remain set
to a default value of 0x0000 during this contiguous write
operation.
Register values:
Address 0x000 = 0x82B2
Address 0x001 = 0x000
Address 0x002 = 0x3230 (depends on number of
conversion stages used)
Address 0x003 = 0x419
4.
5.
6.
Address 0x004 = 832
Address 0x005 = interrupt enable register (depends on
required interrupt behavior)
Address 0x006 = interrupt enable register (depends on
required interrupt behavior)
Address 0x007 = interrupt enable register (depends on
required interrupt behavior)
Write to the Bank 1 register, Address 0x001 = 0x0FFF
(depends on number of conversion stages used).
Read back the corresponding interrupt status register at
Address 0x008, Address 0x009, or Address 0x00A. This is
determined by the interrupt output configuration, as
explained in the Interrupt Output section.
Note that the specific registers required to be read back
depend on each application. For buttons, the interrupt
status registers are read back while other sensors read data
back from the AD7147A according to the slider or wheel
algorithm requirements. Analog Devices can provide this
information after the user develops the sensor board.
Repeat Step 5 every time INT is asserted.
POWER
HOST
SERIAL
INTERFACE
CONVERSION STAGES DISABLED
0
1
2
3
4
5
6
7
8
9
10 11
0
1
2
9
10
11
0
1
2
9
10
AD7147A INT
FIRST CONVERSION SEQUENCE
SECOND CONVERSION
SEQUENCE
Figure 58. Recommended Start-Up Sequence
Rev. B | Page 38 of 68
THIRD CONVERSION
SEQUENCE
11
0
1
07727-058
CONVERSION
STAGE
AD7147A
TYPICAL APPLICATION CIRCUITS
VDRIVE
2.2kΩ
HOST WITH SPI
INTERFACE
INT
GPIO
CIN1
CIN3
CIN5
INT
A1
A2
A3
A4
A5
SS
CS
TP
CIN2
CIN6
CIN7
B1
B2
B3
B4
B5
CIN8
CIN9
C4
C5
SCK
SCLK VDRIVE CIN4
MOSI
MISO
VHOST
1.8V
C1
C2
C3
SDI
VCC
CIN0
D1
D2
D3
SDO
GND
E1
E2
BUTTON
BUTTON
SCROLL
WHEEL
CIN10 CIN11
D4
BUTTON
D5
BIAS ACSHIELD CIN12
E3
E4
BUTTON
E5
AD7147A
SENSOR PCB
VCC 2.7V TO 3.6V
PLANE AROUND SENSORS
CONNECTED TO ACSHIELD
100nF
07727-059
1μF TO 10μF
(OPTIONAL)
Figure 59. Typical Application Circuit with SPI Interface
VDRIVE
VDRIVE
VDRIVE
2.2kΩ
2.2kΩ
HOST WITH I2C
INTERFACE
2.2kΩ
INT
GPIO
CIN1
CIN3
CIN5
A1
A2
A3
A4
A5
ADD1
TP
CIN2
CIN6
CIN7
B1
B2
B3
B4
B5
CIN8
CIN9
C4
C5
BUTTON
SCK
SCLK VDRIVE CIN4
C1
SDO
ADD0
C2
C3
VCC
CIN0
D1
D2
SDA
GND
E1
E2
D3
BUTTON
BUTTON
CIN10 CIN11
D4
D5
SLIDER
INT
2-WAY
SWITCH
BIAS ACSHIELD CIN12
E3
E4
E5
AD7147A-1
1μF TO 10μF
(OPTIONAL)
100nF
PLANE AROUND SENSORS
CONNECTED TO ACSHIELD
Figure 60. Typical Application Circuit with I2C Interface
Rev. B | Page 39 of 68
07727-060
VCC 2.7V TO 3.6V
AD7147A
REGISTER MAP
The AD7147A address space is divided into three register
banks, referred to as Bank 1, Bank 2, and Bank 3. Figure 61
illustrates the division of these banks.
Bank 3 registers contain the results of each conversion stage.
These registers automatically update at the end of each conversion
sequence. Although these registers are primarily used by the
AD7147A internal data processing, they are accessible by the
host processor for additional external data processing, if
desired.
Bank 1 registers contain control registers, CDC conversion
control registers, interrupt enable registers, interrupt status
registers, CDC 16-bit conversion data registers, device ID
registers, and proximity status registers.
Bank 2 registers contain the configuration registers used to
configure the individual CINx inputs for each conversion stage.
Initialize the Bank 2 configuration registers immediately after
power-up to obtain valid CDC conversion result data.
BANK 2 REGISTERS
ADDR 0x080
SETUP CONTROL
(1 REGISTER)
ADDR 0x088
ADDR 0x001
INTERRUPT ENABLE
(3 REGISTERS)
ADDR 0x0A0
ADDR 0x008
CDC 16-BIT CONVERSION DATA
(12 REGISTERS)
ADDR 0x017
96 REGISTERS
26 REGISTERS
ADDR 0x098
STAGE2 CONFIGURATION
(8 REGISTERS)
STAGE4 CONFIGURATION
(8 REGISTERS)
STAGE5 CONFIGURATION
(8 REGISTERS)
ADDR 0x0B0
STAGE6 CONFIGURATION
(8 REGISTERS)
DEVICE ID REGISTER
(1 REGISTER)
ADDR 0x14C
STAGE3 CONFIGURATION
(8 REGISTERS)
ADDR 0x0A8
ADDR 0x0B8
ADDR 0x128
STAGE7 CONFIGURATION
(8 REGISTERS)
STAGE8 CONFIGURATION
(8 REGISTERS)
INVALID DO NOT ACCESS
ADDR 0x042
PROXIMITY STATUS REGISTER
(1 REGISTER)
ADDR 0x0C8
STAGE4 RESULTS
(36 REGISTERS)
STAGE5 RESULTS
(36 REGISTERS)
ADDR 0x1B8
ADDR 0x1DC
STAGE6 RESULTS
(36 REGISTERS)
STAGE7 RESULTS
(36 REGISTERS)
STAGE8 RESULTS
(36 REGISTERS)
ADDR 0x224
STAGE9 RESULTS
(36 REGISTERS)
ADDR 0x248
STAGE10 RESULTS
(36 REGISTERS)
STAGE10 CONFIGURATION
(8 REGISTERS)
ADDR 0x26C
ADDR 0x0D8
INVALID DO NOT ACCESS
STAGE2 RESULTS
(36 REGISTERS)
ADDR 0x194
STAGE9 CONFIGURATION
(8 REGISTERS)
ADDR 0x0D0
ADDR 0x043
STAGE1 RESULTS
(36 REGISTERS)
ADDR 0x200
ADDR 0x0C0
ADDR 0x018
STAGE0 RESULTS
(36 REGISTERS)
STAGE3 RESULTS
(36 REGISTERS)
ADDR 0x170
432 REGISTERS
ADDR 0x090
ADDR 0x005
ADDR 0x00B
ADDR 0x104
STAGE1 CONFIGURATION
(8 REGISTERS)
CALIBRATION AND SETUP
(4 REGISTERS)
INTERRUPT STATUS
(3 REGISTERS)
BANK 3 REGISTERS
ADDR 0x0E0
STAGE0 CONFIGURATION
(8 REGISTERS)
STAGE11 CONFIGURATION
(8 REGISTERS)
ADDR 0x7F0
Figure 61. Layout of Bank 1, Bank 2, and Bank 3 Registers
Rev. B | Page 40 of 68
STAGE11 RESULTS
(36 REGISTERS)
07727-061
BANK 1 REGISTERS
ADDR 0x000
Default values are undefined for Bank 2 registers and Bank 3
registers until after power-up and configuration of the Bank 2
registers.
AD7147A
DETAILED REGISTER DESCRIPTIONS
BANK 1 REGISTERS
All addresses and default values are expressed in hexadecimal.
Table 21. PWR_CONTROL Register
Address
0x000
Data Bit
[1:0]
Default
Value
0
Type
R/W
Name
POWER_MODE
[3:2]
0
R/W
LP_CONV_DELAY
[7:4]
0
R/W
SEQUENCE_STAGE_NUM
[9:8]
0
R/W
DECIMATION
[10]
0
R/W
SW_RESET
[11]
0
R/W
INT_POL
[12]
0
R/W
EXT_SOURCE
[13]
[15:14]
0
0
R/W
Unused
CDC_BIAS
Rev. B | Page 41 of 68
Description
Operating modes
00 = full power mode (normal operation, CDC
conversions approximately every 36 ms)
01 = full shutdown mode (no CDC conversions)
10 = low power mode (automatic wake-up operation)
11 = full shutdown mode (no CDC conversions)
Low power mode conversion delay
00 = 200 ms
01 = 400 ms
10 = 600 ms
11 = 800 ms
Number of stages in sequence (N + 1)
0000 = 1 conversion stage in sequence
0001 = 2 conversion stages in sequence
…
Maximum value = 1011 = 12 conversion stages per
sequence
ADC decimation factor
00 = decimate by 256
01 = decimate by 128
10 = decimate by 64
11 = decimate by 64
Software reset control (self-clearing)
1 = resets all registers to default values
Interrupt polarity control
0 = active low
1 = active high
Excitation source control
0 = enable excitation source to CINx pins
1 = disable excitation source to CINx pins
Set to 0
CDC bias current control
00 = normal operation
01 = normal operation + 20%
10 = normal operation + 35%
11 = normal operation + 50%
AD7147A
Table 22. STAGE_CAL_EN Register
Address
0x001
Data Bit
[0]
Default
Value
0
Type
R/W
Name
STAGE0_CAL_EN
[1]
0
R/W
STAGE1_CAL_EN
[2]
0
R/W
STAGE2_CAL_EN
[3]
0
R/W
STAGE3_CAL_EN
[4]
0
R/W
STAGE4_CAL_EN
[5]
0
R/W
STAGE5_CAL_EN
[6]
0
R/W
STAGE6_CAL_EN
[7]
0
R/W
STAGE7_CAL_EN
[8]
0
R/W
STAGE8_CAL_EN
[9]
0
R/W
STAGE9_CAL_EN
[10]
0
R/W
STAGE10_CAL_EN
[11]
0
R/W
STAGE11_CAL_EN
[13:12]
0
R/W
AVG_FP_SKIP
[15:14]
0
R/W
AVG_LP_SKIP
Rev. B | Page 42 of 68
Description
STAGE0 calibration enable
0 = disable
1 = enable
STAGE1 calibration enable
0 = disable
1 = enable
STAGE2 calibration enable
0 = disable
1 = enable
STAGE3 calibration enable
0 = disable
1 = enable
STAGE4 calibration enable
0 = disable
1 = enable
STAGE5 calibration enable
0 = disable
1 = enable
STAGE6 calibration enable
0 = disable
1 = enable
STAGE7 calibration enable
0 = disable
1 = enable
STAGE8 calibration enable
0 = disable
1 = enable
STAGE9 calibration enable
0 = disable
1 = enable
STAGE10 calibration enable
0 = disable
1 = enable
STAGE11 calibration enable
0 = disable
1 = enable
Full power mode skip control
00 = skip three samples
01 = skip seven samples
10 = skip 15 samples
11 = skip 31 samples
Low power mode skip control
00 = use all samples
01 = skip one sample
10 = skip two samples
11 = skip three samples
AD7147A
Table 23. AMB_COMP_CTRL0 Register
Address
0x002
Data Bit
[3:0]
Default
Value
0
Type
R/W
Name
FF_SKIP_CNT
[7:4]
F
R/W
FP_PROXIMITY_CNT
[11:8]
F
R/W
LP_PROXIMITY_CNT
[13:12]
0
R/W
PWR_DOWN_TIMEOUT
[14]
0
R/W
FORCED_CAL
[15]
0
R/W
CONV_RESET
Description
Fast filter skip control (N + 1)
0000 = no sequence of results is skipped
0001 = one sequence of results is skipped for every one
allowed into fast FIFO
0010 = two sequences of results are skipped for every
one allowed into fast FIFO
1011 = maximum value = 12 sequences of results are
skipped for every one allowed into fast FIFO
Calibration disable period in full power mode =
FP_PROXIMITY_CNT × 16 × time for one conversion
sequence in full power mode
Calibration disable period in low power mode =
LP_PROXIMITY_CNT × 4 × time for one conversion
sequence in low power mode
Full power to low power mode timeout control
00 = 1.25 × (FP_PROXIMITY_CNT)
01 = 1.50 × (FP_PROXIMITY_CNT)
10 = 1.75 × (FP_PROXIMITY_CNT)
11 = 2.00 × (FP_PROXIMITY_CNT)
Forced calibration control
0 = normal operation
1 = forces all conversion stages to recalibrate
Conversion reset control (self-clearing)
0 = normal operation
1 = resets the conversion sequence to STAGE0
Table 24. AMB_COMP_CTRL1 Register
Address
0x003
Data Bit
[7:0]
Default
Value
64
Type
R/W
Name
PROXIMITY_RECAL_LVL
[13:8]
1
R/W
PROXIMITY_DETECTION_RATE
[15:14]
0
R/W
SLOW_FILTER_UPDATE_LVL
Description
Proximity recalibration level. Value is multiplied by 16 to
determine actual recalibration level.
Proximity detection rate. Value is multiplied by 16 to
determine actual detection rate.
Slow filter update level.
Name
FP_PROXIMITY_RECAL
LP_PROXIMITY_RECAL
Description
Full power mode proximity recalibration time control
Low power mode proximity recalibration time control
Table 25. AMB_COMP_CTRL2 Register
Address
0x004
Data Bit
[9:0]
[15:10]
Default
Value
3FF
3F
Type
R/W
R/W
Rev. B | Page 43 of 68
AD7147A
Table 26. STAGE_LOW_INT_ENABLE Register
Address
0x005
Data Bit
[0]
Default
Value
0
Type
R/W
Name
STAGE0_LOW_INT_ENABLE
[1]
0
R/W
STAGE1_LOW_INT_ENABLE
[2]
0
R/W
STAGE2_LOW_INT_ENABLE
[3]
0
R/W
STAGE3_LOW_INT_ENABLE
[4]
0
R/W
STAGE4_LOW_INT_ENABLE
[5]
0
R/W
STAGE5_LOW_INT_ENABLE
[6]
0
R/W
STAGE6_LOW_INT_ENABLE
[7]
0
R/W
STAGE7_LOW_INT_ENABLE
[8]
0
R/W
STAGE8_LOW_INT_ENABLE
[9]
0
R/W
STAGE9_LOW_INT_ENABLE
[10]
0
R/W
STAGE10_LOW_INT_ENABLE
[11]
0
R/W
STAGE11_LOW_INT_ENABLE
[13:12]
0
R/W
GPIO_SETUP
[15:14]
0
R/W
GPIO_INPUT_CONFIG
Rev. B | Page 44 of 68
Description
STAGE0 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 low threshold is exceeded
STAGE1 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE1 low threshold is exceeded
STAGE2 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE2 low threshold is exceeded
STAGE3 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE3 low threshold is exceeded
STAGE4 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE4 low threshold is exceeded
STAGE5 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE5 low threshold is exceeded
STAGE6 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE6 low threshold is exceeded
STAGE7 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE7 low threshold is exceeded
STAGE8 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE8 low threshold is exceeded
STAGE9 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE9 low threshold is exceeded
STAGE10 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE10 low threshold is exceeded
STAGE11 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE11 low threshold is exceeded
GPIO setup
00 = disable GPIO pin
01 = configure GPIO as an input
10 = configure GPIO as an active low output
11 = configure GPIO as an active high output
GPIO input configuration
00 = triggered on negative level
01 = triggered on positive edge
10 = triggered on negative edge
11 = triggered on positive level
AD7147A
Table 27. STAGE_HIGH_INT_ENABLE Register
Address
0x006
Data Bit
[0]
Default
Value
0
Type
R/W
Name
STAGE0_HIGH_INT_ENABLE
[1]
0
R/W
STAGE1_HIGH_INT_ENABLE
[2]
0
R/W
STAGE2_HIGH_INT_ENABLE
[3]
0
R/W
STAGE3_HIGH_INT_ENABLE
[4]
0
R/W
STAGE4_HIGH_INT_ENABLE
[5]
0
R/W
STAGE5_HIGH_INT_ENABLE
[6]
0
R/W
STAGE6_HIGH_INT_ENABLE
[7]
0
R/W
STAGE7_HIGH_INT_ENABLE
[8]
0
R/W
STAGE8_HIGH_INT_ENABLE
[9]
0
R/W
STAGE9_HIGH_INT_ENABLE
[10]
0
R/W
STAGE10_HIGH_INT_ENABLE
[11]
0
R/W
STAGE11_HIGH_INT_ENABLE
[15:12]
Unused
Rev. B | Page 45 of 68
Description
STAGE0 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
STAGE1 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE1 high threshold is exceeded
STAGE2 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE2 high threshold is exceeded
STAGE3 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE3 high threshold is exceeded
STAGE4 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE4 high threshold is exceeded
STAGE5 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE5 high threshold is exceeded
STAGE6 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE6 high threshold is exceeded
STAGE7 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE7 high threshold is exceeded
STAGE8 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE8 high threshold is exceeded
STAGE9 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE9 high threshold is exceeded
STAGE10 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE10 high threshold is exceeded
STAGE11 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE11 high threshold is exceeded
Set to 0
AD7147A
Table 28. STAGE_COMPLETE_INT_ENABLE Register
Address
0x007
Data Bit
[0]
Default
Value
0
Type
R/W
Name
STAGE0_COMPLETE_INT_ENABLE
[1]
0
R/W
STAGE1_COMPLETE_INT_ENABLE
[2]
0
R/W
STAGE2_COMPLETE_INT_ENABLE
[3]
0
R/W
STAGE3_COMPLETE_INT_ENABLE
[4]
0
R/W
STAGE4_COMPLETE_INT_ENABLE
[5]
0
R/W
STAGE5_COMPLETE_INT_ENABLE
[6]
0
R/W
STAGE6_COMPLETE_INT_ENABLE
[7]
0
R/W
STAGE7_COMPLETE_INT_ENABLE
[8]
0
R/W
STAGE8_COMPLETE_INT_ENABLE
[9]
0
R/W
STAGE9_COMPLETE_INT_ENABLE
[10]
0
R/W
STAGE10_COMPLETE_INT_ENABLE
[11]
0
R/W
STAGE11_COMPLETE_INT_ENABLE
[12]
0
R/W
GPIO_INT_ENABLE
[15:13]
Unused
Rev. B | Page 46 of 68
Description
STAGE0 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE0 conversion
STAGE1 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE1 conversion
STAGE2 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE2 conversion
STAGE3 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE3 conversion
STAGE4 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE4 conversion
STAGE5 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE5 conversion
STAGE6 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE6 conversion
STAGE7 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE7 conversion
STAGE8 conversion complete interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE8 conversion
STAGE9 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE9 conversion
STAGE10 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE10 conversion
STAGE11 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE11 conversion
Interrupt control when GPIO input pin changes level
0 = disabled
1 = enabled
Set to 0
AD7147A
Table 29. STAGE_LOW_INT_STATUS Register 1
Address
0x008
Data Bit
[0]
Default
Value
0
Type
R
Name
STAGE0_LOW_INT_STATUS
[1]
0
R
STAGE1_LOW_INT_STATUS
[2]
0
R
STAGE2_LOW_INT_STATUS
[3]
0
R
STAGE3_LOW_INT_STATUS
[4]
0
R
STAGE4_LOW_INT_STATUS
[5]
0
R
STAGE5_LOW_INT_STATUS
[6]
0
R
STAGE6_LOW_INT_STATUS
[7]
0
R
STAGE7_LOW_INT_STATUS
[8]
0
R
STAGE8_LOW_INT_STATUS
[9]
0
R
STAGE9_LOW_INT_STATUS
[10]
0
R
STAGE10_LOW_INT_STATUS
[11]
0
R
STAGE11_LOW_INT_STATUS
[15:12]
1
Unused
Registers self-clear to 0 after readback if the limits are not exceeded.
Rev. B | Page 47 of 68
Description
STAGE0 CDC conversion low limit interrupt result
1 = indicates STAGE0_LOW_THRESHOLD value was
exceeded
STAGE1 CDC conversion low limit interrupt result
1 = indicates STAGE1_LOW_THRESHOLD value was
exceeded
STAGE2 CDC conversion low limit interrupt result
1 = indicates STAGE2_LOW_THRESHOLD value was
exceeded
STAGE3 CDC conversion low limit interrupt result
1 = indicates STAGE3_LOW_THRESHOLD value was
exceeded
STAGE4 CDC conversion low limit interrupt result
1 = indicates STAGE4_LOW_THRESHOLD value was
exceeded
STAGE5 CDC conversion low limit interrupt result
1 = indicates STAGE5_LOW_THRESHOLD value was
exceeded
STAGE6 CDC conversion low limit interrupt result
1 = indicates STAGE6_LOW_THRESHOLD value was
exceeded
STAGE7 CDC conversion low limit interrupt result
1 = indicates STAGE7_LOW_THRESHOLD value was
exceeded
STAGE8 CDC conversion low limit interrupt result
1 = indicates STAGE8_LOW_THRESHOLD value was
exceeded
STAGE9 CDC conversion low limit interrupt result
1 = indicates STAGE9_LOW_THRESHOLD value was
exceeded
STAGE10 CDC conversion low limit interrupt result
1 = indicates STAGE10_LOW_THRESHOLD value was
exceeded
STAGE11 CDC conversion low limit interrupt result
1 = indicates STAGE11_LOW_THRESHOLD value was
exceeded
Set to 0
AD7147A
Table 30. STAGE_HIGH_INT_STATUS Register 1
Address
0x009
Data Bit
[0]
Default
Value
0
Type
R
Name
STAGE0_HIGH_INT_STATUS
[1]
0
R
STAGE1_HIGH_INT_STATUS
[2]
0
R
STAGE2_HIGH_INT_STATUS
[3]
0
R
STAGE3_HIGH_INT_STATUS
[4]
0
R
STAGE4_HIGH_INT_STATUS
[5]
0
R
STAGE5_HIGH_INT_STATUS
[6]
0
R
STAGE6_HIGH_INT_STATUS
[7]
0
R
STAGE7_HIGH_INT_STATUS
[8]
0
R
STAGE8_HIGH_INT_STATUS
[9]
0
R
STAGE9_HIGH_INT_STATUS
[10]
0
R
STAGE10_HIGH_INT_STATUS
[11]
0
R
STAGE11_HIGH_INT_STATUS
[15:12]
1
Unused
Registers self-clear to 0 after readback if the limits are not exceeded.
Rev. B | Page 48 of 68
Description
STAGE0 CDC conversion high limit interrupt result
1 = indicates STAGE0_HIGH_THRESHOLD value was
exceeded
STAGE1 CDC conversion high limit interrupt result
1 = indicates STAGE1_HIGH_THRESHOLD value was
exceeded
STAGE2 CDC conversion high limit interrupt result
1 = indicates STAGE2_HIGH_THRESHOLD value was
exceeded
STAGE3 CDC conversion high limit interrupt result
1 = indicates STAGE3_HIGH_THRESHOLD value was
exceeded
STAGE4 CDC conversion high limit interrupt result
1 = indicates STAGE4_HIGH_THRESHOLD value was
exceeded
STAGE5 CDC conversion high limit interrupt result
1 = indicates STAGE5_HIGH_THRESHOLD value was
exceeded
STAGE6 CDC conversion high limit interrupt result
1 = indicates STAGE6_HIGH_THRESHOLD value was
exceeded
STAGE7 CDC conversion high limit interrupt result
1 = indicates STAGE7_HIGH_THRESHOLD value was
exceeded
STAGE8 CDC conversion high limit interrupt result
1 = indicates STAGE8_HIGH_THRESHOLD value was
exceeded
STAGE9 CDC conversion high limit interrupt result
1 = indicates STAGE9_HIGH_THRESHOLD value was
exceeded
STAGE10 CDC conversion high limit interrupt result
1 = indicates STAGE10_HIGH_THRESHOLD value was
exceeded
STAGE11 CDC conversion high limit interrupt result
1 = indicates STAGE11_HIGH_THRESHOLD value was
exceeded
Set to 0
AD7147A
Table 31. STAGE_COMPLETE_INT_STATUS Register 1
Address
0x00A
Data Bit
[0]
Default
Value
0
Type
R
Name
STAGE0_COMPLETE_INT_STATUS
[1]
0
R
STAGE1_COMPLETE_INT_STATUS
[2]
0
R
STAGE2_COMPLETE_INT_STATUS
[3]
0
R
STAGE3_COMPLETE_INT_STATUS
[4]
0
R
STAGE4_COMPLETE_INT_STATUS
[5]
0
R
STAGE5_COMPLETE_INT_STATUS
[6]
0
R
STAGE6_COMPLETE_INT_STATUS
[7]
0
R
STAGE7_COMPLETE_INT_STATUS
[8]
0
R
STAGE8_COMPLETE_INT_STATUS
[9]
0
R
STAGE9_COMPLETE_INT_STATUS
[10]
0
R
STAGE10_COMPLETE_INT_STATUS
[11]
0
R
STAGE11_COMPLETE_INT_STATUS
[12]
0
R
GPIO_INT_STATUS
[15:13]
1
Unused
Description
STAGE0 conversion-complete register interrupt status
1 = indicates STAGE0 conversion completed
STAGE1 conversion-complete register interrupt status
1 = indicates STAGE1 conversion completed
STAGE2 conversion-complete register interrupt status
1 = indicates STAGE2 conversion completed
STAGE3 conversion-complete register interrupt status
1 = indicates STAGE3 conversion completed
STAGE4 conversion-complete register interrupt status
1 = indicates STAGE4 conversion completed
STAGE5 conversion-complete register interrupt status
1 = indicates STAGE5 conversion completed
STAGE6 conversion-complete register interrupt status
1 = indicates STAGE6 conversion completed
STAGE7 conversion-complete register interrupt status
1 = indicates STAGE7 conversion completed
STAGE8 conversion-complete register interrupt status
1 = indicates STAGE8 conversion completed
STAGE9 conversion-complete register interrupt status
1 = indicates STAGE9 conversion completed
STAGE10 conversion-complete register interrupt status
1 = indicates STAGE10 conversion completed
STAGE11 conversion-complete register interrupt status
1 = indicates STAGE11 conversion completed
GPIO input pin status
1 = indicates level on GPIO pin has changed
Set to 0
Registers self-clear to 0 after readback if the limits are not exceeded.
Table 32. CDC 16-Bit Conversion Data Registers
Address
0x00B
0x00C
0x00D
0x00E
0x00F
0x010
0x011
0x012
0x013
0x014
0x015
0x016
Data Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Default
Value
0
0
0
0
0
0
0
0
0
0
0
0
Type
R
R
R
R
R
R
R
R
R
R
R
R
Name
CDC_RESULT_S0
CDC_RESULT_S1
CDC_RESULT_S2
CDC_RESULT_S3
CDC_RESULT_S4
CDC_RESULT_S5
CDC_RESULT_S6
CDC_RESULT_S7
CDC_RESULT_S8
CDC_RESULT_S9
CDC_RESULT_S10
CDC_RESULT_S11
Rev. B | Page 49 of 68
Description
STAGE0 CDC 16-bit conversion data
STAGE1 CDC 16-bit conversion data
STAGE2 CDC 16-bit conversion data
STAGE3 CDC 16-bit conversion data
STAGE4 CDC 16-bit conversion data
STAGE5 CDC 16-bit conversion data
STAGE6 CDC 16-bit conversion data
STAGE7 CDC 16-bit conversion data
STAGE8 CDC 16-bit conversion data
STAGE9 CDC 16-bit conversion data
STAGE10 CDC 16-bit conversion data
STAGE11 CDC 16-bit conversion data
AD7147A
Table 33. Device ID Register
Address
0x017
Data Bit
[3:0]
[15:4]
Default
Value
0
147
Type
R
R
Name
REVISION_CODE
DEVID
Description
Revision code
Device ID = 0001 0100 0111
Description
STAGE0 proximity status register
1 = indicates proximity has been detected on STAGE0
STAGE1 proximity status register
1 = indicates proximity has been detected on STAGE1
STAGE2 proximity status register
1 = indicates proximity has been detected on STAGE2
STAGE3 proximity status register
1 = indicates proximity has been detected on STAGE3
STAGE4 proximity status register
1 = indicates proximity has been detected on STAGE4
STAGE5 proximity status register
1 = indicates proximity has been detected on STAGE5
STAGE6 proximity status register
1 = indicates proximity has been detected on STAGE6
STAGE7 proximity status register
1 = indicates proximity has been detected on STAGE7
STAGE8 proximity status register
1 = indicates proximity has been detected on STAGE8
STAGE9 proximity status register
1 = indicates proximity has been detected on STAGE9
STAGE10 proximity status register
1 = indicates proximity has been detected on STAGE10
STAGE11 proximity status register
1 = indicates proximity has been detected on STAGE11
Set to 0
Table 34. Proximity Status Register
Address
0x042
Data Bit
[0]
Default
Value
0
Type
R
Name
STAGE0_PROXIMITY_STATUS
[1]
0
R
STAGE1_PROXIMITY_STATUS
[2]
0
R
STAGE2_PROXIMITY_STATUS
[3]
0
R
STAGE3_PROXIMITY_STATUS
[4]
0
R
STAGE4_PROXIMITY_STATUS
[5]
0
R
STAGE5_PROXIMITY_STATUS
[6]
0
R
STAGE6_PROXIMITY_STATUS
[7]
0
R
STAGE7_PROXIMITY_STATUS
[8]
0
R
STAGE8_PROXIMITY_STATUS
[9]
0
R
STAGE9_PROXIMITY_STATUS
[10]
0
R
STAGE10_PROXIMITY_STATUS
[11]
0
R
STAGE11_PROXIMITY_STATUS
[15:12]
Unused
Rev. B | Page 50 of 68
AD7147A
BANK 2 REGISTERS
All address values are expressed in hexadecimal.
Table 35. STAGEx_CONNECTION[6:0] Register Description (x = 0 to 11)
Data Bit
[1:0]
Default
Value 1
X
Type
R/W
Name
CIN0_CONNECTION_SETUP
[3:2]
X
R/W
CIN1_CONNECTION_SETUP
[5:4]
X
R/W
CIN2_CONNECTION_SETUP
[7:6]
X
R/W
CIN3_CONNECTION_SETUP
[9:8]
X
R/W
CIN4_CONNECTION_SETUP
[11:10]
X
R/W
CIN5_CONNECTION_SETUP
[13:12]
X
R/W
CIN6_CONNECTION_SETUP
[15:14]
X
1
Unused
Description
CIN0 connection setup
00 = CIN0 not connected to CDC inputs
01 = CIN0 connected to CDC negative input
10 = CIN0 connected to CDC positive input
11 = CIN0 connected to BIAS (connect unused CINx inputs)
CIN1 connection setup
00 = CIN1 not connected to CDC inputs
01 = CIN1 connected to CDC negative input
10 = CIN1 connected to CDC positive input
11 = CIN1 connected to BIAS (connect unused CINx inputs)
CIN2 connection setup
00 = CIN2 not connected to CDC inputs
01 = CIN2 connected to CDC negative input
10 = CIN2 connected to CDC positive input
11 = CIN2 connected to BIAS (connect unused CINx inputs)
CIN3 connection setup
00 = CIN3 not connected to CDC inputs
01 = CIN3 connected to CDC negative input
10 = CIN3 connected to CDC positive input
11 = CIN3 connected to BIAS (connect unused CINx inputs)
CIN4 connection setup
00 = CIN4 not connected to CDC inputs
01 = CIN4 connected to CDC negative input
10 = CIN4 connected to CDC positive input
11 = CIN4 connected to BIAS (connect unused CINx inputs)
CIN5 connection setup
00 = CIN5 not connected to CDC inputs
01 = CIN5 connected to CDC negative input
10 = CIN5 connected to CDC positive input
11 = CIN5 connected to BIAS (connect unused CINx inputs)
CIN6 connection setup
00 = CIN6 not connected to CDC inputs
01 = CIN6 connected to CDC negative input
10 = CIN6 connected to CDC positive input
11 = CIN6 connected to BIAS (connect unused CINx inputs)
Set to 0
X = don’t care.
Rev. B | Page 51 of 68
AD7147A
Table 36. STAGEx_CONNECTION[12:7] Register Description (x = 0 to 11)
Data Bit
[1:0]
Default
Value 1
X
Type
R/W
Name
CIN7_CONNECTION_SETUP
[3:2]
X
R/W
CIN8_CONNECTION_SETUP
[5:4]
X
R/W
CIN9_CONNECTION_SETUP
[7:6]
X
R/W
CIN10_CONNECTION_SETUP
[9:8]
X
R/W
CIN11_CONNECTION_SETUP
[11:10]
X
R/W
CIN12_CONNECTION_SETUP
[13:12]
X
R/W
SE_CONNECTION_SETUP
[14]
X
R/W
NEG_AFE_OFFSET_DISABLE
[15]
X
R/W
POS_AFE_OFFSET_DISABLE
1
Description
CIN7 connection setup
00 = CIN7 not connected to CDC inputs
01 = CIN7 connected to CDC negative input
10 = CIN7 connected to CDC positive input
11 = CIN7 connected to BIAS (connect unused CINx inputs)
CIN8 connection setup
00 = CIN8 not connected to CDC inputs
01 = CIN8 connected to CDC negative input
10 = CIN8 connected to CDC positive input
11 = CIN8 connected to BIAS (connect unused CINx inputs)
CIN9 connection setup
00 = CIN9 not connected to CDC inputs
01 = CIN9 connected to CDC negative input
10 = CIN9 connected to CDC positive input
11 = CIN9 connected to BIAS (connect unused CINx inputs)
CIN10 connection setup
00 = CIN10 not connected to CDC inputs
01 = CIN10 connected to CDC negative input
10 = CIN10 connected to CDC positive input
11 = CIN10 connected to BIAS (connect unused CINx inputs)
CIN11 connection setup
00 = CIN11 not connected to CDC inputs
01 = CIN11 connected to CDC negative input
10 = CIN11 connected to CDC positive input
11 = CIN11 connected to BIAS (connect unused CINx inputs)
CIN12 connection setup
00 = CIN12 not connected to CDC inputs
01 = CIN12 connected to CDC negative input
10 = CIN12 connected to CDC positive input
11 = CIN12 connected to BIAS (connect unused CINx inputs)
Single-ended measurement connection setup
00 = Do not use
01 = Use when one CINx is connected to CDC positive
input, single-ended measurements only
10 = Use when one CINx is connected to CDC negative
input, single-ended measurements only
11 = Differential connection to CDC
Negative AFE offset enable control
0 = enable
1 = disable
Positive AFE offset enable control
0 = enable
1 = disable
X = don’t care.
Rev. B | Page 52 of 68
AD7147A
Table 37. STAGEx_AFE_OFFSET Register Description (x = 0 to 11)
Data Bit
[5:0]
Default
Value 1
X
Type
R/W
Name
NEG_AFE_OFFSET
[6]
[7]
X
X
R/W
Unused
NEG_AFE_OFFSET_SWAP
[13:8]
X
R/W
POS_AFE_OFFSET
[14]
[15]
X
X
R/W
Unused
POS_AFE_OFFSET_SWAP
1
Description
Negative AFE offset setting (20 pF range)
1 LSB value = 0.32 pF of offset
Set to 0
Negative AFE offset swap control
0 = NEG_AFE_OFFSET applied to CDC negative input
1 = NEG_AFE_OFFSET applied to CDC positive input
Positive AFE offset setting (20 pF range)
1 LSB value = 0.32 pF of offset
Set to 0
Positive AFE offset swap control
0 = POS_AFE_OFFSET applied to CDC positive input
1 = POS_AFE_OFFSET applied to CDC negative input
X = don’t care.
Table 38. STAGEx_SENSITIVITY Register Description (x = 0 to 11)
Data Bit
[3:0]
Default
Value 1
X
Type
R/W
Name
NEG_THRESHOLD_SENSITIVITY
[6:4]
X
R/W
NEG_PEAK_DETECT
[7]
[11:8]
X
X
R/W
R/W
Unused
POS_THRESHOLD_SENSITIVITY
[14:12]
X
R/W
POS_PEAK_DETECT
[15]
X
R/W
Unused
1
Description
Negative threshold sensitivity control
0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08%
0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15%
0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22%
1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28%
1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32%
Negative peak detect setting
000 = 40% level, 001 = 50% level, 010 = 60% level
011 = 70% level, 100 = 80% level, 101 = 90% level
Set to 0
Positive threshold sensitivity control
0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08%
0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15%
0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22%
1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28%
1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32%
Positive peak detect setting
000 = 40% level, 001 = 50% level, 010 = 60% level
011 = 70% level, 100 = 80% level, 101 = 90% level
Set to 0
X = don’t care.
Rev. B | Page 53 of 68
AD7147A
Table 39. STAGE0 to STAGE12 Configuration Registers
Address
0x080
0x081
0x082
0x083
0x084
0x085
0x086
0x087
0x088
0x089
0x08A
0x08B
0x08C
0x08D
0x08E
0x08F
0x090
0x091
0x092
0x093
0x094
0x095
0x096
0x097
0x098
0x099
0x09A
0x09B
0x09C
0x09D
0x09E
0x09F
0x0A0
0x0A1
0x0A2
0x0A3
0x0A4
0x0A5
0x0A6
0x0A7
0x0A8
0x0A9
0x0AA
0x0AB
0x0AC
0x0AD
0x0AE
0x0AF
Data Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Default 1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
STAGE0_CONNECTION[6:0]
STAGE0_CONNECTION[12:7]
STAGE0_AFE_OFFSET
STAGE0_SENSITIVITY
STAGE0_OFFSET_LOW
STAGE0_OFFSET_HIGH
STAGE0_OFFSET_HIGH_CLAMP
STAGE0_ OFFSET_LOW_CLAMP
STAGE1_CONNECTION[6:0]
STAGE1_CONNECTION[12:7]
STAGE1_AFE_OFFSET
STAGE1_SENSITIVITY
STAGE1_OFFSET_LOW
STAGE1_OFFSET_HIGH
STAGE1_OFFSET_HIGH_CLAMP
STAGE1_OFFSET_LOW_CLAMP
STAGE2_CONNECTION[6:0]
STAGE2_CONNECTION[12:7]
STAGE2_AFE_OFFSET
STAGE2_SENSITIVITY
STAGE2_OFFSET_LOW
STAGE2_OFFSET_HIGH
STAGE2_OFFSET_HIGH_CLAMP
STAGE2_OFFSET_LOW_CLAMP
STAGE3_CONNECTION[6:0]
STAGE3_CONNECTION[12:7]
STAGE3_AFE_OFFSET
STAGE3_SENSITIVITY
STAGE3_OFFSET_LOW
STAGE3_OFFSET_HIGH
STAGE3_OFFSET_HIGH_CLAMP
STAGE3_OFFSET_LOW_CLAMP
STAGE4_CONNECTION[6:0]
STAGE4_CONNECTION[12:7]
STAGE4_AFE_OFFSET
STAGE4_SENSITIVITY
STAGE4_OFFSET_LOW
STAGE4_OFFSET_HIGH
STAGE4_OFFSET_HIGH_CLAMP
STAGE4_OFFSET_LOW_CLAMP
STAGE5_CONNECTION[6:0]
STAGE5_CONNECTION[12:7]
STAGE5_AFE_OFFSET
STAGE5_SENSITIVITY
STAGE5_OFFSET_LOW
STAGE5_OFFSET_HIGH
STAGE5_OFFSET_HIGH_CLAMP
STAGE5_OFFSET_LOW_CLAMP
Rev. B | Page 54 of 68
Description
STAGE0 CIN[6:0] connection setup (see Table 35)
STAGE0 CIN[12:7] connection setup (see Table 36)
STAGE0 AFE offset control (see Table 37)
STAGE0 sensitivity control (see Table 38)
STAGE0 initial offset low value
STAGE0 initial offset high value
STAGE0 offset high clamp value
STAGE0 offset low clamp value
STAGE1 CIN[6:0] connection setup (see Table 35)
STAGE1 CIN[12:7] connection setup (see Table 36)
STAGE1 AFE offset control (see Table 37)
STAGE1 sensitivity control (see Table 38)
STAGE1 initial offset low value
STAGE1 initial offset high value
STAGE1 offset high clamp value
STAGE1 offset low clamp value
STAGE2 CIN[6:0] connection setup (see Table 35)
STAGE2 CIN[12:7] connection setup (see Table 36)
STAGE2 AFE offset control (see Table 37)
STAGE2 sensitivity control (see Table 38)
STAGE2 initial offset low value
STAGE2 initial offset high value
STAGE2 offset high clamp value
STAGE2 offset low clamp value
STAGE3 CIN[6:0] connection setup (see Table 35)
STAGE3 CIN[12:7] connection setup (see Table 36)
STAGE3 AFE offset control (see Table 37)
STAGE3 sensitivity control (see Table 38)
STAGE3 initial offset low value
STAGE3 initial offset high value
STAGE3 offset high clamp value
STAGE3 offset low clamp value
STAGE4 CIN[6:0] connection setup (see Table 35)
STAGE4 CIN[12:7] connection setup (see Table 36)
STAGE4 AFE offset control (see Table 37)
STAGE4 sensitivity control (see Table 38)
STAGE4 initial offset low value
STAGE4 initial offset high value
STAGE4 offset high clamp value
STAGE4 offset low clamp value
STAGE5 CIN[6:0] connection setup (see Table 35)
STAGE5 CIN[12:7] connection setup (see Table 36)
STAGE5 AFE offset control (see Table 37)
STAGE5 sensitivity control (see Table 38)
STAGE5 initial offset low value
STAGE5 initial offset high value
STAGE5 offset high clamp value
STAGE5 offset low clamp value
AD7147A
Address
0x0B0
0x0B1
0x0B2
0x0B3
0x0B4
0x0B5
0x0B6
0x0B7
0x0B8
0x0B9
0x0BA
0x0BB
0x0BC
0x0BD
0x0BE
0x0BF
0x0C0
0x0C1
0x0C2
0x0C3
0x0C4
0x0C5
0x0C6
0x0C7
0x0C8
0x0C9
0x0CA
0x0CB
0x0CC
0x0CD
0x0CE
0x0CF
0x0D0
0x0D1
0x0D2
0x0D3
0x0D4
0x0D5
0x0D6
0x0D7
0x0D8
0x0D9
0x0DA
0x0DB
0x0DC
0x0DD
0x0DE
0x0DF
1
Data Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Default 1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
STAGE6_CONNECTION[6:0]
STAGE6_CONNECTION[12:7]
STAGE6_AFE_OFFSET
STAGE6_SENSITIVITY
STAGE6_OFFSET_LOW
STAGE6_OFFSET_HIGH
STAGE6_OFFSET_HIGH_CLAMP
STAGE6_OFFSET_LOW_CLAMP
STAGE7_CONNECTION[6:0]
STAGE7_CONNECTION[12:7]
STAGE7_AFE_OFFSET
STAGE7_SENSITIVITY
STAGE7_OFFSET_LOW
STAGE7_OFFSET_HIGH
STAGE7_OFFSET_HIGH_CLAMP
STAGE7_OFFSET_LOW_CLAMP
STAGE8_CONNECTION[6:0]
STAGE8_CONNECTION[12:7]
STAGE8_AFE_OFFSET
STAGE8_SENSITIVITY
STAGE8_OFFSET_LOW
STAGE8_OFFSET_HIGH
STAGE8_OFFSET_HIGH_CLAMP
STAGE8_OFFSET_LOW_CLAMP
STAGE9_CONNECTION[6:0]
STAGE9_CONNECTION[12:7]
STAGE9_AFE_OFFSET
STAGE9_SENSITIVITY
STAGE9_OFFSET_LOW
STAGE9_OFFSET_HIGH
STAGE9_OFFSET_HIGH_CLAMP
STAGE9_OFFSET_LOW_CLAMP
STAGE10_CONNECTION[6:0]
STAGE10_CONNECTION[12:7]
STAGE10_AFE_OFFSET
STAGE10_SENSITIVITY
STAGE10_OFFSET_LOW
STAGE10_OFFSET_HIGH
STAGE10_OFFSET_HIGH_CLAMP
STAGE10_OFFSET_LOW_CLAMP
STAGE11_CONNECTION[6:0]
STAGE11_CONNECTION[12:7]
STAGE11_AFE_OFFSET
STAGE11_SENSITIVITY
STAGE11_OFFSET_LOW
STAGE11_OFFSET_HIGH
STAGE11_OFFSET_HIGH_CLAMP
STAGE11_OFFSET_LOW_CLAMP
X = don’t care.
Rev. B | Page 55 of 68
Description
STAGE6 CIN[6:0] connection setup (see Table 35)
STAGE6 CIN[12:7] connection setup (see Table 36)
STAGE6 AFE offset control (see Table 37)
STAGE6 sensitivity control (see Table 38)
STAGE6 initial offset low value
STAGE6 initial offset high value
STAGE6 offset high clamp value
STAGE6 offset low clamp value
STAGE7 CIN[6:0] connection setup (see Table 35)
STAGE7 CIN[12:7] connection setup (see Table 36)
STAGE7 AFE offset control (see Table 37)
STAGE7 sensitivity control (see Table 38)
STAGE7 initial offset low value
STAGE7 initial offset high value
STAGE7 offset high clamp value
STAGE7 offset low clamp value
STAGE8 CIN[6:0] connection setup (see Table 35)
STAGE8 CIN[12:7] connection setup (see Table 36)
STAGE8 AFE offset control (see Table 37)
STAGE8 sensitivity control (see Table 38)
STAGE8 initial offset low value
STAGE8 initial offset high value
STAGE8 offset high clamp value
STAGE8 offset low clamp value
STAGE9 CIN[6:0] connection setup (see Table 35)
STAGE9 CIN[12:7] connection setup (see Table 36)
STAGE9 AFE offset control (see Table 37)
STAGE9 sensitivity control (see Table 38)
STAGE9 initial offset low value
STAGE9 initial offset high value
STAGE9 offset high clamp value
STAGE9 offset low clamp value
STAGE10 CIN[6:0] connection setup (see Table 35)
STAGE10 CIN[12:7] connection setup (see Table 36)
STAGE10 AFE offset control (see Table 37)
STAGE10 sensitivity control (see Table 38)
STAGE10 initial offset low value
STAGE10 initial offset high value
STAGE10 offset high clamp value
STAGE10 offset low clamp value
STAGE11 CIN[6:0] connection setup (see Table 35)
STAGE11 CIN[12:7] connection setup (see Table 36)
STAGE11 AFE offset control (see Table 37)
STAGE11 sensitivity control (see Table 38)
STAGE11 initial offset low value
STAGE11 initial offset high value
STAGE11 offset high clamp value
STAGE11 offset low clamp value
AD7147A
BANK 3 REGISTERS
All address values are expressed in hexadecimal.
Table 40. STAGE0 Results Registers
Address
0x0E0
Data Bit
[15:0]
Default
Value 1
X
Type
R/W
Name
STAGE0_CONV_DATA
0x0E1
0x0E2
0x0E3
0x0E4
0x0E5
0x0E6
0x0E7
0x0E8
0x0E9
0x0EA
0x0EB
0x0EC
0x0ED
0x0EE
0x0EF
0x0F0
0x0F1
0x0F2
0x0F3
0x0F4
0x0F5
0x0F6
0x0F7
0x0F8
0x0F9
0x0FA
0x0FB
0x0FC
0x0FD
0x0FE
0x0FF
0x100
0x101
0x102
0x103
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE0_FF_WORD0
STAGE0_FF_WORD1
STAGE0_FF_WORD2
STAGE0_FF_WORD3
STAGE0_FF_WORD4
STAGE0_FF_WORD5
STAGE0_FF_WORD6
STAGE0_FF_WORD7
STAGE0_SF_WORD0
STAGE0_SF_WORD1
STAGE0_SF_WORD2
STAGE0_SF_WORD3
STAGE0_SF_WORD4
STAGE0_SF_WORD5
STAGE0_SF_WORD6
STAGE0_SF_WORD7
STAGE0_SF_AMBIENT
STAGE0_FF_AVG
STAGE0_PEAK_DETECT_WORD0
STAGE0_PEAK_DETECT_WORD1
STAGE0_MAX_WORD0
STAGE0_MAX_WORD1
STAGE0_MAX_WORD2
STAGE0_MAX_WORD3
STAGE0_MAX_AVG
STAGE0_HIGH_THRESHOLD
STAGE0_MAX_TEMP
STAGE0_MIN_WORD0
STAGE0_MIN_WORD1
STAGE0_MIN_WORD2
STAGE0_MIN_WORD3
STAGE0_MIN_AVG
STAGE0_LOW_THRESHOLD
STAGE0_MIN_TEMP
Unused
1
X = don’t care.
Rev. B | Page 56 of 68
Description
STAGE0 CDC 16-bit conversion data
(copy of CDC_RESULT_S0 register)
STAGE0 fast FIFO WORD0
STAGE0 fast FIFO WORD1
STAGE0 fast FIFO WORD2
STAGE0 fast FIFO WORD3
STAGE0 fast FIFO WORD4
STAGE0 fast FIFO WORD5
STAGE0 fast FIFO WORD6
STAGE0 fast FIFO WORD7
STAGE0 slow FIFO WORD0
STAGE0 slow FIFO WORD1
STAGE0 slow FIFO WORD2
STAGE0 slow FIFO WORD3
STAGE0 slow FIFO WORD4
STAGE0 slow FIFO WORD5
STAGE0 slow FIFO WORD6
STAGE0 slow FIFO WORD7
STAGE0 slow FIFO ambient value
STAGE0 fast FIFO average value
STAGE0 peak FIFO WORD0 value
STAGE0 peak FIFO WORD1 value
STAGE0 maximum value FIFO WORD0
STAGE0 maximum value FIFO WORD1
STAGE0 maximum value FIFO WORD2
STAGE0 maximum value FIFO WORD3
STAGE0 average maximum FIFO value
STAGE0 high threshold value
STAGE0 temporary maximum value
STAGE0 minimum value FIFO WORD0
STAGE0 minimum value FIFO WORD1
STAGE0 minimum value FIFO WORD2
STAGE0 minimum value FIFO WORD3
STAGE0 average minimum FIFO value
STAGE0 low threshold value
STAGE0 temporary minimum value
Set to 0
AD7147A
Table 41. STAGE1 Results Registers
Address
0x104
Data Bit
[15:0]
Default
Value 1
X
Type
R/W
Name
STAGE1_CONV_DATA
0x105
0x106
0x107
0x108
0x109
0x10A
0x10B
0x10C
0x10D
0x10E
0x10F
0x110
0x111
0x112
0x113
0x114
0x115
0x116
0x117
0x118
0x119
0x11A
0x11B
0x11C
0x11D
0x11E
0x11F
0x120
0x121
0x122
0x123
0x124
0x125
0x126
0x127
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE1_FF_WORD0
STAGE1_FF_WORD1
STAGE1_FF_WORD2
STAGE1_FF_WORD3
STAGE1_FF_WORD4
STAGE1_FF_WORD5
STAGE1_FF_WORD6
STAGE1_FF_WORD7
STAGE1_SF_WORD0
STAGE1_SF_WORD1
STAGE1_SF_WORD2
STAGE1_SF_WORD3
STAGE1_SF_WORD4
STAGE1_SF_WORD5
STAGE1_SF_WORD6
STAGE1_SF_WORD7
STAGE1_SF_AMBIENT
STAGE1_FF_AVG
STAGE1_PEAK_DETECT_WORD0
STAGE1_PEAK_DETECT_WORD1
STAGE1_MAX_WORD0
STAGE1_MAX_WORD1
STAGE1_MAX_WORD2
STAGE1_MAX_WORD3
STAGE1_MAX_AVG
STAGE1_HIGH_THRESHOLD
STAGE1_MAX_TEMP
STAGE1_MIN_WORD0
STAGE1_MIN_WORD1
STAGE1_MIN_WORD2
STAGE1_MIN_WORD3
STAGE1_MIN_AVG
STAGE1_LOW_THRESHOLD
STAGE1_MIN_TEMP
Unused
1
X = don’t care.
Rev. B | Page 57 of 68
Description
STAGE1 CDC 16-bit conversion data
(copy of CDC_RESULT_S1 register
STAGE1 fast FIFO WORD0
STAGE1 fast FIFO WORD1
STAGE1 fast FIFO WORD2
STAGE1 fast FIFO WORD3
STAGE1 fast FIFO WORD4
STAGE1 fast FIFO WORD5
STAGE1 fast FIFO WORD6
STAGE1 fast FIFO WORD7
STAGE1 slow FIFO WORD0
STAGE1 slow FIFO WORD1
STAGE1 slow FIFO WORD2
STAGE1 slow FIFO WORD3
STAGE1 slow FIFO WORD4
STAGE1 slow FIFO WORD5
STAGE1 slow FIFO WORD6
STAGE1 slow FIFO WORD7
STAGE1 slow FIFO ambient value
STAGE1 fast FIFO average value
STAGE1 peak FIFO WORD0 value
STAGE1 peak FIFO WORD1 value
STAGE1 maximum value FIFO WORD0
STAGE1 maximum value FIFO WORD1
STAGE1 maximum value FIFO WORD2
STAGE1 maximum value FIFO WORD3
STAGE1 average maximum FIFO value
STAGE1 high threshold value
STAGE1 temporary maximum value
STAGE1 minimum value FIFO WORD0
STAGE1 minimum value FIFO WORD1
STAGE1 minimum value FIFO WORD2
STAGE1 minimum value FIFO WORD3
STAGE1 average minimum FIFO value
STAGE1 low threshold value
STAGE1 temporary minimum value
Set to 0
AD7147A
Table 42. STAGE2 Results Registers
Address
0x128
Data Bit
[15:0]
Default
Value 1
X
Type
R/W
Name
STAGE2_CONV_DATA
0x129
0x12A
0x12B
0x12C
0x12D
0x12E
0x12F
0x130
0x131
0x132
0x133
0x134
0x135
0x136
0x137
0x138
0x139
0x13A
0x13B
0x13C
0x13D
0x13E
0x13F
0x140
0x141
0x142
0x143
0x144
0x145
0x146
0x147
0x148
0x149
0x14A
0x14B
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE2_FF_WORD0
STAGE2_FF_WORD1
STAGE2_FF_WORD2
STAGE2_FF_WORD3
STAGE2_FF_WORD4
STAGE2_FF_WORD5
STAGE2_FF_WORD6
STAGE2_FF_WORD7
STAGE2_SF_WORD0
STAGE2_SF_WORD1
STAGE2_SF_WORD2
STAGE2_SF_WORD3
STAGE2_SF_WORD4
STAGE2_SF_WORD5
STAGE2_SF_WORD6
STAGE2_SF_WORD7
STAGE2_SF_AMBIENT
STAGE2_FF_AVG
STAGE2_PEAK_DETECT_WORD0
STAGE2_PEAK_DETECT_WORD1
STAGE2_MAX_WORD0
STAGE2_MAX_WORD1
STAGE2_MAX_WORD2
STAGE2_MAX_WORD3
STAGE2_MAX_AVG
STAGE2_HIGH_THRESHOLD
STAGE2_MAX_TEMP
STAGE2_MIN_WORD0
STAGE2_MIN_WORD1
STAGE2_MIN_WORD2
STAGE2_MIN_WORD3
STAGE2_MIN_AVG
STAGE2_LOW_THRESHOLD
STAGE2_MIN_TEMP
Unused
1
X = don’t care.
Rev. B | Page 58 of 68
Description
STAGE2 CDC 16-bit conversion data
(copy of CDC_RESULT_S2 register)
STAGE2 fast FIFO WORD0
STAGE2 fast FIFO WORD1
STAGE2 fast FIFO WORD2
STAGE2 fast FIFO WORD3
STAGE2 fast FIFO WORD4
STAGE2 fast FIFO WORD5
STAGE2 fast FIFO WORD6
STAGE2 fast FIFO WORD7
STAGE2 slow FIFO WORD0
STAGE2 slow FIFO WORD1
STAGE2 slow FIFO WORD2
STAGE2 slow FIFO WORD3
STAGE2 slow FIFO WORD4
STAGE2 slow FIFO WORD5
STAGE2 slow FIFO WORD6
STAGE2 slow FIFO WORD7
STAGE2 slow FIFO ambient value
STAGE2 fast FIFO average value
STAGE2 peak FIFO WORD0 value
STAGE2 peak FIFO WORD1 value
STAGE2 maximum value FIFO WORD0
STAGE2 maximum value FIFO WORD1
STAGE2 maximum value FIFO WORD2
STAGE2 maximum value FIFO WORD3
STAGE2 average maximum FIFO value
STAGE2 high threshold value
STAGE2 temporary maximum value
STAGE2 minimum value FIFO WORD0
STAGE2 minimum value FIFO WORD1
STAGE2 minimum value FIFO WORD2
STAGE2 minimum value FIFO WORD3
STAGE2 average minimum FIFO value
STAGE2 low threshold value
STAGE2 temporary minimum value
Set to 0
AD7147A
Table 43. STAGE3 Results Registers
Address
0x14C
Data Bit
[15:0]
Default
Value 1
X
Type
R/W
Name
STAGE3_CONV_DATA
0x14D
0x14E
0x14F
0x150
0x151
0x152
0x153
0x154
0x155
0x156
0x157
0x158
0x159
0x15A
0x15B
0x15C
0x15D
0x15E
0x15F
0x160
0x161
0x162
0x163
0x164
0x165
0x166
0x167
0x168
0x169
0x16A
0x16B
0x16C
0x16D
0x16E
0x16F
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE3_FF_WORD0
STAGE3_FF_WORD1
STAGE3_FF_WORD2
STAGE3_FF_WORD3
STAGE3_FF_WORD4
STAGE3_FF_WORD5
STAGE3_FF_WORD6
STAGE3_FF_WORD7
STAGE3_SF_WORD0
STAGE3_SF_WORD1
STAGE3_SF_WORD2
STAGE3_SF_WORD3
STAGE3_SF_WORD4
STAGE3_SF_WORD5
STAGE3_SF_WORD6
STAGE3_SF_WORD7
STAGE3_SF_AMBIENT
STAGE3_FF_AVG
STAGE3_PEAK_DETECT_WORD0
STAGE3_PEAK_DETECT_WORD1
STAGE3_MAX_WORD0
STAGE3_MAX_WORD1
STAGE3_MAX_WORD2
STAGE3_MAX_WORD3
STAGE3_MAX_AVG
STAGE3_HIGH_THRESHOLD
STAGE3_MAX_TEMP
STAGE3_MIN_WORD0
STAGE3_MIN_WORD1
STAGE3_MIN_WORD2
STAGE3_MIN_WORD3
STAGE3_MIN_AVG
STAGE3_LOW_THRESHOLD
STAGE3_MIN_TEMP
Unused
1
X = don’t care.
Rev. B | Page 59 of 68
Description
STAGE3 CDC 16-bit conversion data
(copy of CDC_RESULT_S3 register)
STAGE3 fast FIFO WORD0
STAGE3 fast FIFO WORD1
STAGE3 fast FIFO WORD2
STAGE3 fast FIFO WORD3
STAGE3 fast FIFO WORD4
STAGE3 fast FIFO WORD5
STAGE3 fast FIFO WORD6
STAGE3 fast FIFO WORD7
STAGE3 slow FIFO WORD0
STAGE3 slow FIFO WORD1
STAGE3 slow FIFO WORD2
STAGE3 slow FIFO WORD3
STAGE3 slow FIFO WORD4
STAGE3 slow FIFO WORD5
STAGE3 slow FIFO WORD6
STAGE3 slow FIFO WORD7
STAGE3 slow FIFO ambient value
STAGE3 fast FIFO average value
STAGE3 peak FIFO WORD0 value
STAGE3 peak FIFO WORD1 value
STAGE3 maximum value FIFO WORD0
STAGE3 maximum value FIFO WORD1
STAGE3 maximum value FIFO WORD2
STAGE3 maximum value FIFO WORD3
STAGE3 average maximum FIFO value
STAGE3 high threshold value
STAGE3 temporary maximum value
STAGE3 minimum value FIFO WORD0
STAGE3 minimum value FIFO WORD1
STAGE3 minimum value FIFO WORD2
STAGE3 minimum value FIFO WORD3
STAGE3 average minimum FIFO value
STAGE3 low threshold value
STAGE3 temporary minimum value
Set to 0
AD7147A
Table 44. STAGE4 Results Registers
Address
0x170
Data Bit
[15:0]
Default
Value 1
X
Type
R/W
Name
STAGE4_CONV_DATA
0x171
0x172
0x173
0x174
0x175
0x176
0x177
0x178
0x179
0x17A
0x17B
0x17C
0x17D
0x17E
0x17F
0x180
0x181
0x182
0x183
0x184
0x185
0x186
0x187
0x188
0x189
0x18A
0x18B
0x18C
0x18D
0x18E
0x18F
0x190
0x191
0x192
0x193
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE4_FF_WORD0
STAGE4_FF_WORD1
STAGE4_FF_WORD2
STAGE4_FF_WORD3
STAGE4_FF_WORD4
STAGE4_FF_WORD5
STAGE4_FF_WORD6
STAGE4_FF_WORD7
STAGE4_SF_WORD0
STAGE4_SF_WORD1
STAGE4_SF_WORD2
STAGE4_SF_WORD3
STAGE4_SF_WORD4
STAGE4_SF_WORD5
STAGE4_SF_WORD6
STAGE4_SF_WORD7
STAGE4_SF_AMBIENT
STAGE4_FF_AVG
STAGE4_PEAK_DETECT_WORD0
STAGE4_PEAK_DETECT_WORD1
STAGE4_MAX_WORD0
STAGE4_MAX_WORD1
STAGE4_MAX_WORD2
STAGE4_MAX_WORD3
STAGE4_MAX_AVG
STAGE4_HIGH_THRESHOLD
STAGE4_MAX_TEMP
STAGE4_MIN_WORD0
STAGE4_MIN_WORD1
STAGE4_MIN_WORD2
STAGE4_MIN_WORD3
STAGE4_MIN_AVG
STAGE4_LOW_THRESHOLD
STAGE4_MIN_TEMP
Unused
1
X = don’t care.
Rev. B | Page 60 of 68
Description
STAGE4 CDC 16-bit conversion data
(copy of CDC_RESULT_S4 register)
STAGE4 fast FIFO WORD0
STAGE4 fast FIFO WORD1
STAGE4 fast FIFO WORD2
STAGE4 fast FIFO WORD3
STAGE4 fast FIFO WORD4
STAGE4 fast FIFO WORD5
STAGE4 fast FIFO WORD6
STAGE4 fast FIFO WORD7
STAGE4 slow FIFO WORD0
STAGE4 slow FIFO WORD1
STAGE4 slow FIFO WORD2
STAGE4 slow FIFO WORD3
STAGE4 slow FIFO WORD4
STAGE4 slow FIFO WORD5
STAGE4 slow FIFO WORD6
STAGE4 slow FIFO WORD7
STAGE4 slow FIFO ambient value
STAGE4 fast FIFO average value
STAGE4 peak FIFO WORD0 value
STAGE4 peak FIFO WORD1 value
STAGE4 maximum value FIFO WORD0
STAGE4 maximum value FIFO WORD1
STAGE4 maximum value FIFO WORD2
STAGE4 maximum value FIFO WORD3
STAGE4 average maximum FIFO value
STAGE4 high threshold value
STAGE4 temporary maximum value
STAGE4 minimum value FIFO WORD0
STAGE4 minimum value FIFO WORD1
STAGE4 minimum value FIFO WORD2
STAGE4 minimum value FIFO WORD3
STAGE4 average minimum FIFO value
STAGE4 low threshold value
STAGE4 temporary minimum value
Set to 0
AD7147A
Table 45. STAGE5 Results Registers
Address
0x194
Data Bit
[15:0]
Default
Value 1
X
Type
R/W
Name
STAGE5_CONV_DATA
0x195
0x196
0x197
0x198
0x199
0x19A
0x19B
0x19C
0x19D
0x19E
0x19F
0x1A0
0x1A1
0x1A2
0x1A3
0x1A4
0x1A5
0x1A6
0x1A7
0x1A8
0x1A9
0x1AA
0x1AB
0x1AC
0x1AD
0x1AE
0x1AF
0x1B0
0x1B1
0x1B2
0x1B3
0x1B4
0x1B5
0x1B6
0x1B7
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE5_FF_WORD0
STAGE5_FF_WORD1
STAGE5_FF_WORD2
STAGE5_FF_WORD3
STAGE5_FF_WORD4
STAGE5_FF_WORD5
STAGE5_FF_WORD6
STAGE5_FF_WORD7
STAGE5_SF_WORD0
STAGE5_SF_WORD1
STAGE5_SF_WORD2
STAGE5_SF_WORD3
STAGE5_SF_WORD4
STAGE5_SF_WORD5
STAGE5_SF_WORD6
STAGE5_SF_WORD7
STAGE5_SF_AMBIENT
STAGE5_FF_AVG
STAGE5_PEAK_DETECT_WORD0
STAGE5_PEAK_DETECT_WORD1
STAGE5_MAX_WORD0
STAGE5_MAX_WORD1
STAGE5_MAX_WORD2
STAGE5_MAX_WORD3
STAGE5_MAX_AVG
STAGE5_HIGH_THRESHOLD
STAGE5_MAX_TEMP
STAGE5_MIN_WORD0
STAGE5_MIN_WORD1
STAGE5_MIN_WORD2
STAGE5_MIN_WORD3
STAGE5_MIN_AVG
STAGE5_LOW_THRESHOLD
STAGE5_MIN_TEMP
Unused
1
X = don’t care.
Rev. B | Page 61 of 68
Description
STAGE5 CDC 16-bit conversion data
(copy of CDC_RESULT_S5 register)
STAGE5 fast FIFO WORD0
STAGE5 fast FIFO WORD1
STAGE5 fast FIFO WORD2
STAGE5 fast FIFO WORD3
STAGE5 fast FIFO WORD4
STAGE5 fast FIFO WORD5
STAGE5 fast FIFO WORD6
STAGE5 fast FIFO WORD7
STAGE5 slow FIFO WORD0
STAGE5 slow FIFO WORD1
STAGE5 slow FIFO WORD2
STAGE5 slow FIFO WORD3
STAGE5 slow FIFO WORD4
STAGE5 slow FIFO WORD5
STAGE5 slow FIFO WORD6
STAGE5 slow FIFO WORD7
STAGE5 slow FIFO ambient value
STAGE5 fast FIFO average value
STAGE5 peak FIFO WORD0 value
STAGE5 peak FIFO WORD1 value
STAGE5 maximum value FIFO WORD0
STAGE5 maximum value FIFO WORD1
STAGE5 maximum value FIFO WORD2
STAGE5 maximum value FIFO WORD3
STAGE5 average maximum FIFO value
STAGE5 high threshold value
STAGE5 temporary maximum value
STAGE5 minimum value FIFO WORD0
STAGE5 minimum value FIFO WORD1
STAGE5 minimum value FIFO WORD2
STAGE5 minimum value FIFO WORD3
STAGE5 average minimum FIFO value
STAGE5 low threshold value
STAGE5 temporary minimum value
Set to 0
AD7147A
Table 46. STAGE6 Results Registers
Address
0x1B8
Data Bit
[15:0]
Default
Value 1
X
Type
R/W
Name
STAGE6_CONV_DATA
0x1B9
0x1BA
0x1BB
0x1BC
0x1BD
0x1BE
0x1BF
0x1C0
0x1C1
0x1C2
0x1C3
0x1C4
0x1C5
0x1C6
0x1C7
0x1C8
0x1C9
0x1CA
0x1CB
0x1CC
0x1CD
0x1CE
0x1CF
0x1D0
0x1D1
0x1D2
0x1D3
0x1D4
0x1D5
0x1D6
0x1D7
0x1D8
0x1D9
0x1DA
0x1DB
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE6_FF_WORD0
STAGE6_FF_WORD1
STAGE6_FF_WORD2
STAGE6_FF_WORD3
STAGE6_FF_WORD4
STAGE6_FF_WORD5
STAGE6_FF_WORD6
STAGE6_FF_WORD7
STAGE6_SF_WORD0
STAGE6_SF_WORD1
STAGE6_SF_WORD2
STAGE6_SF_WORD3
STAGE6_SF_WORD4
STAGE6_SF_WORD5
STAGE6_SF_WORD6
STAGE6_SF_WORD7
STAGE6_SF_AMBIENT
STAGE6_FF_AVG
STAGE6_PEAK_DETECT_WORD0
STAGE6_PEAK_DETECT_WORD1
STAGE6_MAX_WORD0
STAGE6_MAX_WORD1
STAGE6_MAX_WORD2
STAGE6_MAX_WORD3
STAGE6_MAX_AVG
STAGE6_HIGH_THRESHOLD
STAGE6_MAX_TEMP
STAGE6_MIN_WORD0
STAGE6_MIN_WORD1
STAGE6_MIN_WORD2
STAGE6_MIN_WORD3
STAGE6_MIN_AVG
STAGE6_LOW_THRESHOLD
STAGE6_MIN_TEMP
Unused
1
X = don’t care.
Rev. B | Page 62 of 68
Description
STAGE6 CDC 16-bit conversion data
(copy of CDC_RESULT_S6 register)
STAGE6 fast FIFO WORD0
STAGE6 fast FIFO WORD1
STAGE6 fast FIFO WORD2
STAGE6 fast FIFO WORD3
STAGE6 fast FIFO WORD4
STAGE6 fast FIFO WORD5
STAGE6 fast FIFO WORD6
STAGE6 fast FIFO WORD7
STAGE6 slow FIFO WORD0
STAGE6 slow FIFO WORD1
STAGE6 slow FIFO WORD2
STAGE6 slow FIFO WORD3
STAGE6 slow FIFO WORD4
STAGE6 slow FIFO WORD5
STAGE6 slow FIFO WORD6
STAGE6 slow FIFO WORD7
STAGE6 slow FIFO ambient value
STAGE6 fast FIFO average value
STAGE6 peak FIFO WORD0 value
STAGE6 peak FIFO WORD1 value
STAGE6 maximum value FIFO WORD0
STAGE6 maximum value FIFO WORD1
STAGE6 maximum value FIFO WORD2
STAGE6 maximum value FIFO WORD3
STAGE6 average maximum FIFO value
STAGE6 high threshold value
STAGE6 temporary maximum value
STAGE6 minimum value FIFO WORD0
STAGE6 minimum value FIFO WORD1
STAGE6 minimum value FIFO WORD2
STAGE6 minimum value FIFO WORD3
STAGE6 average minimum FIFO value
STAGE6 low threshold value
STAGE6 temporary minimum value
Set to 0
AD7147A
Table 47. STAGE7 Results Registers
Address
0x1DC
Data Bit
[15:0]
Default
Value 1
X
Type
R/W
Name
STAGE7_CONV_DATA
0x1DD
0x1DE
0x1DF
0x1E0
0x1E1
0x1E2
0x1E3
0x1E4
0x1E5
0x1E6
0x1E7
0x1E8
0x1E9
0x1EA
0x1EB
0x1EC
0x1ED
0x1EE
0x1EF
0x1F0
0x1F1
0x1F2
0x1F3
0x1F4
0x1F5
0x1F6
0x1F7
0x1F8
0x1F9
0x1FA
0x1FB
0x1FC
0x1FD
0x1FE
0x1FF
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE7_FF_WORD0
STAGE7_FF_WORD1
STAGE7_FF_WORD2
STAGE7_FF_WORD3
STAGE7_FF_WORD4
STAGE7_FF_WORD5
STAGE7_FF_WORD6
STAGE7_FF_WORD7
STAGE7_SF_WORD0
STAGE7_SF_WORD1
STAGE7_SF_WORD2
STAGE7_SF_WORD3
STAGE7_SF_WORD4
STAGE7_SF_WORD5
STAGE7_SF_WORD6
STAGE7_SF_WORD7
STAGE7_SF_AMBIENT
STAGE7_FF_AVG
STAGE7_PEAK_DETECT_WORD0
STAGE7_PEAK_DETECT_WORD1
STAGE7_MAX_WORD0
STAGE7_MAX_WORD1
STAGE7_MAX_WORD2
STAGE7_MAX_WORD3
STAGE7_MAX_AVG
STAGE7_HIGH_THRESHOLD
STAGE7_MAX_TEMP
STAGE7_MIN_WORD0
STAGE7_MIN_WORD1
STAGE7_MIN_WORD2
STAGE7_MIN_WORD3
STAGE7_MIN_AVG
STAGE7_LOW_THRESHOLD
STAGE7_MIN_TEMP
Unused
1
X = don’t care.
Rev. B | Page 63 of 68
Description
STAGE7 CDC 16-bit conversion data
(copy of CDC_RESULT_S7 register)
STAGE7 fast FIFO WORD0
STAGE7 fast FIFO WORD1
STAGE7 fast FIFO WORD2
STAGE7 fast FIFO WORD3
STAGE7 fast FIFO WORD4
STAGE7 fast FIFO WORD5
STAGE7 fast FIFO WORD6
STAGE7 fast FIFO WORD7
STAGE7 slow FIFO WORD0
STAGE7 slow FIFO WORD1
STAGE7 slow FIFO WORD2
STAGE7 slow FIFO WORD3
STAGE7 slow FIFO WORD4
STAGE7 slow FIFO WORD5
STAGE7 slow FIFO WORD6
STAGE7 slow FIFO WORD7
STAGE7 slow FIFO ambient value
STAGE7 fast FIFO average value
STAGE7 peak FIFO WORD0 value
STAGE7 peak FIFO WORD1 value
STAGE7 maximum value FIFO WORD0
STAGE7 maximum value FIFO WORD1
STAGE7 maximum value FIFO WORD2
STAGE7 maximum value FIFO WORD3
STAGE7 average maximum FIFO value
STAGE7 high threshold value
STAGE7 temporary maximum value
STAGE7 minimum value FIFO WORD0
STAGE7 minimum value FIFO WORD1
STAGE7 minimum value FIFO WORD2
STAGE7 minimum value FIFO WORD3
STAGE7 average minimum FIFO value
STAGE7 low threshold value
STAGE7 temporary minimum value
Set to 0
AD7147A
Table 48. STAGE8 Results Registers
Address
0x200
Data Bit
[15:0]
Default
Value 1
X
Type
R/W
Name
STAGE8_CONV_DATA
0x201
0x202
0x203
0x204
0x205
0x206
0x207
0x208
0x209
0x20A
0x20B
0x20C
0x20D
0x20E
0x20F
0x210
0x211
0x212
0x213
0x214
0x215
0x216
0x217
0x218
0x219
0x21A
0x21B
0x21C
0x21D
0x21E
0x21F
0x220
0x221
0x222
0x223
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE8_FF_WORD0
STAGE8_FF_WORD1
STAGE8_FF_WORD2
STAGE8_FF_WORD3
STAGE8_FF_WORD4
STAGE8_FF_WORD5
STAGE8_FF_WORD6
STAGE8_FF_WORD7
STAGE8_SF_WORD0
STAGE8_SF_WORD1
STAGE8_SF_WORD2
STAGE8_SF_WORD3
STAGE8_SF_WORD4
STAGE8_SF_WORD5
STAGE8_SF_WORD6
STAGE8_SF_WORD7
STAGE8_SF_AMBIENT
STAGE8_FF_AVG
STAGE8_PEAK_DETECT_WORD0
STAGE8_PEAK_DETECT_WORD1
STAGE8_MAX_WORD0
STAGE8_MAX_WORD1
STAGE8_MAX_WORD2
STAGE8_MAX_WORD3
STAGE8_MAX_AVG
STAGE8_HIGH_THRESHOLD
STAGE8_MAX_TEMP
STAGE8_MIN_WORD0
STAGE8_MIN_WORD1
STAGE8_MIN_WORD2
STAGE8_MIN_WORD3
STAGE8_MIN_AVG
STAGE8_LOW_THRESHOLD
STAGE8_MIN_TEMP
Unused
1
X = don’t care.
Rev. B | Page 64 of 68
Description
STAGE8 CDC 16-bit conversion data
(copy of CDC_RESULT_S8 register)
STAGE8 fast FIFO WORD0
STAGE8 fast FIFO WORD1
STAGE8 fast FIFO WORD2
STAGE8 fast FIFO WORD3
STAGE8 fast FIFO WORD4
STAGE8 fast FIFO WORD5
STAGE8 fast FIFO WORD6
STAGE8 fast FIFO WORD7
STAGE8 slow FIFO WORD0
STAGE8 slow FIFO WORD1
STAGE8 slow FIFO WORD2
STAGE8 slow FIFO WORD3
STAGE8 slow FIFO WORD4
STAGE8 slow FIFO WORD5
STAGE8 slow FIFO WORD6
STAGE8 slow FIFO WORD7
STAGE8 slow FIFO ambient value
STAGE8 fast FIFO average value
STAGE8 peak FIFO WORD0 value
STAGE8 peak FIFO WORD1 value
STAGE8 maximum value FIFO WORD0
STAGE8 maximum value FIFO WORD1
STAGE8 maximum value FIFO WORD2
STAGE8 maximum value FIFO WORD3
STAGE8 average maximum FIFO value
STAGE8 high threshold value
STAGE8 temporary maximum value
STAGE8 minimum value FIFO WORD0
STAGE8 minimum value FIFO WORD1
STAGE8 minimum value FIFO WORD2
STAGE8 minimum value FIFO WORD3
STAGE8 average minimum FIFO value
STAGE8 low threshold value
STAGE7 temporary minimum value
Set to 0
AD7147A
Table 49. STAGE9 Results Registers
Address
0x224
Data Bit
[15:0]
Default
Value 1
X
Type
R/W
Name
STAGE9_CONV_DATA
0x225
0x226
0x227
0x228
0x229
0x22A
0x22B
0x22C
0x22D
0x22E
0x22F
0x230
0x231
0x232
0x233
0x234
0x235
0x236
0x237
0x238
0x239
0x23A
0x23B
0x23C
0x23D
0x23E
0x23F
0x240
0x241
0x242
0x243
0x244
0x245
0x246
0x247
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE9_FF_WORD0
STAGE9_FF_WORD1
STAGE9_FF_WORD2
STAGE9_FF_WORD3
STAGE9_FF_WORD4
STAGE9_FF_WORD5
STAGE9_FF_WORD6
STAGE9_FF_WORD7
STAGE9_SF_WORD0
STAGE9_SF_WORD1
STAGE9_SF_WORD2
STAGE9_SF_WORD3
STAGE9_SF_WORD4
STAGE9_SF_WORD5
STAGE9_SF_WORD6
STAGE9_SF_WORD7
STAGE9_SF_AMBIENT
STAGE9_FF_AVG
STAGE9_PEAK_DETECT_WORD0
STAGE9_PEAK_DETECT_WORD1
STAGE9_MAX_WORD0
STAGE9_MAX_WORD1
STAGE9_MAX_WORD2
STAGE9_MAX_WORD3
STAGE9_MAX_AVG
STAGE9_HIGH_THRESHOLD
STAGE9_MAX_TEMP
STAGE9_MIN_WORD0
STAGE9_MIN_WORD1
STAGE9_MIN_WORD2
STAGE9_MIN_WORD3
STAGE9_MIN_AVG
STAGE9_LOW_THRESHOLD
STAGE9_MIN_TEMP
Unused
1
X = don’t care.
Rev. B | Page 65 of 68
Description
STAGE9 CDC 16-bit conversion data
(copy of CDC_RESULT_S9 register)
STAGE9 fast FIFO WORD0
STAGE9 fast FIFO WORD1
STAGE9 fast FIFO WORD2
STAGE9 fast FIFO WORD3
STAGE9 fast FIFO WORD4
STAGE9 fast FIFO WORD5
STAGE9 fast FIFO WORD6
STAGE9 fast FIFO WORD7
STAGE9 slow FIFO WORD0
STAGE9 slow FIFO WORD1
STAGE9 slow FIFO WORD2
STAGE9 slow FIFO WORD3
STAGE9 slow FIFO WORD4
STAGE9 slow FIFO WORD5
STAGE9 slow FIFO WORD6
STAGE9 slow FIFO WORD7
STAGE9 slow FIFO ambient value
STAGE9 fast FIFO average value
STAGE9 peak FIFO WORD0 value
STAGE9 peak FIFO WORD1 value
STAGE9 maximum value FIFO WORD0
STAGE9 maximum value FIFO WORD1
STAGE9 maximum value FIFO WORD2
STAGE9 maximum value FIFO WORD3
STAGE9 average maximum FIFO value
STAGE9 high threshold value
STAGE9 temporary maximum value
STAGE9 minimum value FIFO WORD0
STAGE9 minimum value FIFO WORD1
STAGE9 minimum value FIFO WORD2
STAGE9 minimum value FIFO WORD3
STAGE9 average minimum FIFO value
STAGE9 low threshold value
STAGE9 temporary minimum value
Set to 0
AD7147A
Table 50. STAGE10 Results Registers
Address
0x248
Data Bit
[15:0]
Default
Value 1
X
Type
R/W
Name
STAGE10_CONV_DATA
0x249
0x24A
0x24B
0x24C
0x24D
0x24E
0x24F
0x250
0x251
0x252
0x253
0x254
0x255
0x256
0x257
0x258
0x259
0x25A
0x25B
0x25C
0x25D
0x25E
0x25F
0x260
0x261
0x262
0x263
0x264
0x265
0x266
0x267
0x268
0x269
0x26A
0x26B
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE10_FF_WORD0
STAGE10_FF_WORD1
STAGE10_FF_WORD2
STAGE10_FF_WORD3
STAGE10_FF_WORD4
STAGE10_FF_WORD5
STAGE10_FF_WORD6
STAGE10_FF_WORD7
STAGE10_SF_WORD0
STAGE10_SF_WORD1
STAGE10_SF_WORD2
STAGE10_SF_WORD3
STAGE10_SF_WORD4
STAGE10_SF_WORD5
STAGE10_SF_WORD6
STAGE10_SF_WORD7
STAGE10_SF_AMBIENT
STAGE10_FF_AVG
STAGE10_PEAK_DETECT_WORD0
STAGE10_PEAK_DETECT_WORD1
STAGE10_MAX_WORD0
STAGE10_MAX_WORD1
STAGE10_MAX_WORD2
STAGE10_MAX_WORD3
STAGE10_MAX_AVG
STAGE10_HIGH_THRESHOLD
STAGE10_MAX_TEMP
STAGE10_MIN_WORD0
STAGE10_MIN_WORD1
STAGE10_MIN_WORD2
STAGE10_MIN_WORD3
STAGE10_MIN_AVG
STAGE10_LOW_THRESHOLD
STAGE10_MIN_TEMP
Unused
1
X = don’t care.
Rev. B | Page 66 of 68
Description
STAGE10 CDC 16-bit conversion data
(copy of CDC_RESULT_S10 register)
STAGE10 fast FIFO WORD0
STAGE10 fast FIFO WORD1
STAGE10 fast FIFO WORD2
STAGE10 fast FIFO WORD3
STAGE10 fast FIFO WORD4
STAGE10 fast FIFO WORD5
STAGE10 fast FIFO WORD6
STAGE10 fast FIFO WORD7
STAGE10 slow FIFO WORD0
STAGE10 slow FIFO WORD1
STAGE10 slow FIFO WORD2
STAGE10 slow FIFO WORD3
STAGE10 slow FIFO WORD4
STAGE10 slow FIFO WORD5
STAGE10 slow FIFO WORD6
STAGE10 slow FIFO WORD7
STAGE10 slow FIFO ambient value
STAGE10 fast FIFO average value
STAGE10 peak FIFO WORD0 value
STAGE10 peak FIFO WORD1 value
STAGE10 maximum value FIFO WORD0
STAGE10 maximum value FIFO WORD1
STAGE10 maximum value FIFO WORD2
STAGE10 maximum value FIFO WORD3
STAGE10 average maximum FIFO value
STAGE10 high threshold value
STAGE10 temporary maximum value
STAGE10 minimum value FIFO WORD0
STAGE10 minimum value FIFO WORD1
STAGE10 minimum value FIFO WORD2
STAGE10 minimum value FIFO WORD3
STAGE10 average minimum FIFO value
STAGE10 low threshold value
STAGE10 temporary minimum value
Set to 0
AD7147A
Table 51. STAGE11 Results Registers
Address
0x26C
Data Bit
[15:0]
Default
Value 1
X
Type
R/W
Name
STAGE11_CONV_DATA
0x26D
0x26E
0x26F
0x270
0x271
0x272
0x273
0x274
0x275
0x276
0x277
0x278
0x279
0x27A
0x27B
0x27C
0x27D
0x27E
0x27F
0x280
0x281
0x282
0x283
0x284
0x285
0x286
0x287
0x288
0x289
0x28A
0x28B
0x28C
0x28D
0x28E
0x28F
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE11_FF_WORD0
STAGE11_FF_WORD1
STAGE11_FF_WORD2
STAGE11_FF_WORD3
STAGE11_FF_WORD4
STAGE11_FF_WORD5
STAGE11_FF_WORD6
STAGE11_FF_WORD7
STAGE11_SF_WORD0
STAGE11_SF_WORD1
STAGE11_SF_WORD2
STAGE11_SF_WORD3
STAGE11_SF_WORD4
STAGE11_SF_WORD5
STAGE11_SF_WORD6
STAGE11_SF_WORD7
STAGE11_SF_AMBIENT
STAGE11_FF_AVG
STAGE11_PEAK_DETECT_WORD0
STAGE11_PEAK_DETECT_WORD1
STAGE11_MAX_WORD0
STAGE11_MAX_WORD1
STAGE11_MAX_WORD2
STAGE11_MAX_WORD3
STAGE11_MAX_AVG
STAGE11_HIGH_THRESHOLD
STAGE11_MAX_TEMP
STAGE11_MIN_WORD0
STAGE11_MIN_WORD1
STAGE11_MIN_WORD2
STAGE11_MIN_WORD3
STAGE11_MIN_AVG
STAGE11_LOW_THRESHOLD
STAGE11_MIN_TEMP
Unused
1
X = don’t care.
Rev. B | Page 67 of 68
Description
STAGE11 CDC 16-bit conversion data
(copy of CDC_RESULT_S11 register)
STAGE11 fast FIFO WORD0
STAGE11 fast FIFO WORD1
STAGE11 fast FIFO WORD2
STAGE11 fast FIFO WORD3
STAGE11 fast FIFO WORD4
STAGE11 fast FIFO WORD5
STAGE11 fast FIFO WORD6
STAGE11 fast FIFO WORD7
STAGE11 slow FIFO WORD0
STAGE11 slow FIFO WORD1
STAGE11 slow FIFO WORD2
STAGE11 slow FIFO WORD3
STAGE11 slow FIFO WORD4
STAGE11 slow FIFO WORD5
STAGE11 slow FIFO WORD6
STAGE11 slow FIFO WORD7
STAGE11 slow FIFO ambient value
STAGE11 fast FIFO average value
STAGE11 peak FIFO WORD0 value
STAGE11 peak FIFO WORD1 value
STAGE11 maximum value FIFO WORD0
STAGE11 maximum value FIFO WORD1
STAGE11 maximum value FIFO WORD2
STAGE11 maximum value FIFO WORD3
STAGE11 average maximum FIFO value
STAGE11 high threshold value
STAGE11 temporary maximum value
STAGE11 minimum value FIFO WORD0
STAGE11 minimum value FIFO WORD1
STAGE11 minimum value FIFO WORD2
STAGE11 minimum value FIFO WORD3
STAGE11 average minimum FIFO value
STAGE11 low threshold value
STAGE11 temporary minimum value
Set to 0
AD7147A
OUTLINE DIMENSIONS
0.600
0.555
0.510
2.295
2.245
2.195
SEATING
PLANE
5
4
3
2
1
A
BALL 1
IDENTIFIER
B
2.100
2.050
2.000
0.287
0.267
0.247
1.60
REF
C
D
E
0.40
REF
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
0.23
0.20
0.17
081908-A
1.60 REF
Figure 62. 25-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-25-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7147AACBZ-RL1, 2
AD7147AACBZ500RL71, 2
AD7147A-1ACBZ-RL1, 2
AD7147A-1ACBZ500RL71, 2
EVAL-AD7147EBZ1
EVAL-AD7147-1EBZ1
1
2
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Description
Wake-up on proximity
Wake-up on proximity
Wake-up on proximity
Wake-up on proximity
Serial Interface
Description
SPI Interface
SPI Interface
I2C Interface
I2C Interface
SPI Interface
I2C Interface
Z = RoHS Compliant Part.
This package is halide free.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07727-0-12/09(B)
Rev. B | Page 68 of 68
Package
Description
25-Ball WLCSP
25-Ball WLCSP
25-Ball WLCSP
25-Ball WLCSP
Evaluation Board
Evaluation Board
Package
Option
CB-25-3
CB-25-3
CB-25-3
CB-25-3
Branding
T3K
T3K
T3J
T3J
工商网监
湘ICP备2023018690号
