AD7153

12-Bit Capacitance-to-Digital Converter AD7152/AD7153 FEATURES Capacitance-to-digital converters Interfaces to floating sensors Resolution down to 0.25 fF (that is, up to 12 ENOB) Linearity: 0.05% Common-mode (not changing) capacitance up to 5 pF Four capacitance ranges selectable per operation mode ±0.25 pF to ±2 pF in differential mode 0.5 pF to 4 pF in single-ended mode Tolerant of parasitic capacitance to ground up to 50 pF Conversion time per channel: 5 ms, 20 ms, 50 ms, and 60 ms Internal clock oscillator 2-wire serial interface (I2C-compatible) Power 2.7 V to 3.6 V single-supply operation 100 μA current consumption Operating temperature: −40°C to +85°C 10-lead MSOP package GENERAL DESCRIPTION The AD7152/AD7153 are 12-bit sigma-delta (Σ-Δ) capacitance-todigital converters (CDCs). The capacitance to be measured is connected directly to the device inputs. The architecture features inherent high resolution (12-bit no missing codes, up to 12-bit effective resolution) and high linearity (±0.05%). The AD7152/AD7153 have four capacitance input ranges per operation mode, ±0.25 pF to ±2 pF in differential mode and 0.5 pF to 4 pF in single-ended mode. The AD7152/AD7153 can accept up to 5 pF common-mode capacitance (not changing), which can be balanced by a programmable on-chip, digital-to-capacitance converter (CAPDAC). The AD7153 has one capacitance input channel, while the AD7152 has two channels. Each channel can be configured as single-ended or differential. The AD7152/AD7153 are designed for floating capacitive sensors. The AD7152/AD7153 have a 2-wire, I2C®-compatible serial interface. Both parts can operate with a single power supply from 2.7 V to 3.6 V. They are specified over the temperature range of −40°C to +85°C and are available in a 10-lead MSOP package. APPLICATIONS Automotive, industrial, and medical systems for Pressure measurement Position sensing Level sensing Flowmeters Humidity sensing FUNCTIONAL BLOCK DIAGRAMS VDD CAP+ CAP– CIN1(+) CIN1(–) EXC1 CIN2(+) CIN2(–) EXC2 07450-001 07450-002 VDD AD7152 CLOCK GENERATOR VOLTAGE REFERENCE CIN1(+) CIN1(–) SCL EXC1 MUX CAP+ CAP– CLOCK GENERATOR VOLTAGE REFERENCE AD7153 MUX 12-BIT Σ-Δ MODULATOR I2C SERIAL INTERFACE SDA 12-BIT Σ-Δ MODULATOR I2C SERIAL INTERFACE SDA SCL EXCITATION DIGITAL FILTER GND CONTROL LOGIC CALIBRATION EXCITATION DIGITAL FILTER GND CONTROL LOGIC CALIBRATION Figure 1. Figure 2. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. AD7152/AD7153 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 Serial Interface ................................................................................ 11 Write Operation .......................................................................... 11 Read Operation ........................................................................... 11 AD7152/AD7153 Reset ............................................................. 12 General Call................................................................................. 12 Register Map.................................................................................... 13 Status Register ............................................................................. 14 Data Registers ............................................................................. 15 Offset Calibration Registers ...................................................... 15 Gain Calibration Registers ........................................................ 15 CAP Setup Registers .................................................................. 16 Configuration Register .............................................................. 16 CAPDAC POS Register ............................................................. 17 CAPDAC NEG Register ............................................................ 17 Configuration2 Register ............................................................ 17 Circuit Description......................................................................... 18 Capacitance-to-Digital Converter (CDC) .............................. 18 Excitation Source ........................................................................ 18 CAPDAC ..................................................................................... 19 Single-Ended Capacitive Input ................................................. 19 Differential Capacitive Input .................................................... 20 Parasitic Capacitance to Ground .............................................. 20 Parasitic Resistance to Ground ................................................. 20 Parasitic Parallel Resistance ...................................................... 21 Parasitic Serial Resistance ......................................................... 21 Input EMC Protection ............................................................... 21 Power Supply Decoupling and Filtering.................................. 21 Capacitive Gain Calibration ..................................................... 21 Capacitive System Offset Calibration ...................................... 21 Typical Application Diagram .................................................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23 REVISION HISTORY 5/08—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD7152/AD7153 SPECIFICATIONS VDD = 2.7 V to 3.6 V; GND = 0 V; −40°C to +85°C, unless otherwise noted. Table 1. Parameter CAPACITIVE INPUT Capacitive Input Ranges Min Typ ±2 ±1 ±0.5 ±0.25 4 2 1 0.5 ±3 ±0.05 12 10 12 ±20 40 5 1 0.5 0.4 50 10 20 Max Unit 1 pF pF pF pF pF pF pF pF % of FS % of FS Bits Bits Bits fF % of FSR fF fF % of FSR % of FSR pF MΩ kΩ fF/V dB dB dB pF fF LSB % of CAPDAC FSR kHz V pF V V μA V μA V ISINK = −6.0 mA VOUT = VDD Test Conditions/Comments Differential mode Single-ended mode Gain Matching Between Ranges Integral Nonlinearity (INL) 2 No Missing Codes2 Resolution, p-p2, 3 Resolution Effective2, 3 Absolute Error 4 System Offset Calibration Range 5, 6 Offset Deviation over Temperature2 25°C, VDD = 3.3 V, 4 pF range 25°C, VDD = 3.3 V, 4 pF range 25°C, VDD = 3.3 V, after system offset calibration, ±2 pF range Single-ended mode, CIN and EXC pins disconnected, see Figure 8 Differential mode, CIN and EXC pins disconnected 25°C, VDD = 3.3 V See Figure 7 See Figure 9 and Figure 10 See Figure 13 See Figure 16 See Figure 17 50 Hz ± 1 Hz, conversion time = 60 ms 60 Hz ± 1 Hz, conversion time = 50 ms AD7152 only 1 0.3 Gain Error 7 Gain Deviation over Temperature2 Allowed Capacitance, CIN to GND2 Allowed Resistance, CIN to GND2 Allowed Serial Resistance2 Power Supply Rejection DC Normal-Mode Rejection2 Channel-to-Channel Isolation2 CAPDAC Full Range Resolution 8 Differential Nonlinearity (DNL)2 Offset Deviation over Temperature2 EXCITATION Frequency Voltage Allowed Capacitance, EXC to GND2 SERIAL INTERFACE LOGIC INPUTS (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current (SCL) OPEN-DRAIN OUTPUT (SDA) Output Low Voltage, VOL Output High Leakage Current, IOH POWER SUPPLY MONITOR Threshold Voltage, VDD 0.3 2 −70 −70 −70 5 6.25 200 0.25 0.3 30.9 32 ±VDD/2 32.8 300 1.5 ±0.1 0.8 ±5 0.4 0.1 2.45 5 2.65 5-bit CAPDAC See Figure 18 and Figure 19 Single-ended mode See Figure 11 and Figure 12 Rev. 0 | Page 3 of 24 AD7152/AD7153 Parameter POWER REQUIREMENTS VDD-to-GND Voltage Current, IDD 9 Current Power-Down Mode, IDD9 Min 2.7 100 1 3 Typ Max 3.6 120 5 10 Unit 1 V μA μA μA Test Conditions/Comments VDD = 3.3 V, nominal Temperature ≤ 25°C Temperature = 85°C 1 2 Capacitance units: 1 pF = 10−12 F; 1 fF = 10−15 F; 1 aF = 10−18 F. Specification is not production tested but is supported by characterization data at initial product release. 3 Except Channel 2 in differential mode. To achieve the specified performance in differential mode, the I2C interface must be idle during the capacitance conversion to prevent signal coupling from the SCL pin to the adjacent CIN2(−) pin. 4 Factory calibrated. The absolute error includes factory gain calibration error and integral nonlinearity error all at 25°C. At different temperatures, compensation for gain drift over temperature is required. 5 Specification is not production tested but guaranteed by design. 6 A system offset calibration is effectively a conversion; therefore, the offset error is of the order of the conversion noise. This applies after calibration at the temperature, capacitive input range, and applied VDD of interest. The capacitive input offset can be reduced using a system offset calibration. Large offsets should be removed using CAPDACs. 7 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required. 8 The CAPDAC resolution is five bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can further reduce the CIN offset or the unchanging CIN component. 9 Digital inputs equal to VDD or GND. Rev. 0 | Page 4 of 24 AD7152/AD7153 TIMING SPECIFICATIONS VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; −40°C to +85°C, unless otherwise noted. Table 2. Parameter SERIAL INTERFACE 1, 2 SCL Frequency SCL High Pulse Width, tHIGH SCL Low Pulse Width, tLOW SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Hold Time (Start Condition), tHD;STA Set-Up Time (Start Condition), tSU;STA Data Set-Up Time, tSU;DAT Setup Time (Stop Condition), tSU;STO Data Hold Time, tHD;DAT (Master) Bus-Free Time (Between Stop and Start Conditions, tBUF) 1 2 Min 0 0.6 1.3 Typ Max 400 Unit kHz μs μs μs μs μs μs μs μs μs μs Test Conditions/Comments See Figure 3. 0.3 0.3 0.6 0.6 0.1 0.6 0.01 1.3 After this period, the first clock is generated. Relevant for repeated start condition. Sample tested during initial release to ensure compliance. All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs; output load = 10 pF. tR tF tLOW SCL tHD;STA tHD;STA SDA tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO tBUF P S S P Figure 3. Serial Interface Timing Diagram Rev. 0 | Page 5 of 24 07450-003 AD7152/AD7153 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Positive Supply Voltage, VDD to GND Voltage on Any Input or Output Pin to GND ESD Rating (ESD Association Human Body Model, S5.1) ESD Rating (Field-Induced Charged Device Model) Operating Temperature Range Storage Temperature Range Junction Temperature MSOP θJA Thermal Impedance-to-Air θJC Thermal Impedance-to-Case Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Rating −0.3 V to +3.9 V −0.3 V to VDD + 0.3 V 4 kV 750 V −40°C to +85°C −65°C to +150°C 150°C 206°C/W 44°C/W 260 (+0/−5)°C 10 sec to 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 6 of 24 AD7152/AD7153 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS GND 1 GND 1 VDD 2 CIN1(–) 3 CIN1(+) 4 EXC2 5 10 SDA 10 SDA SCL NC NC EXC1 07450-005 VDD 2 CIN1(–) 3 CIN1(+) 4 07450-004 AD7152 TOP VIEW (Not to Scale) 9 8 7 6 SCL CIN2(–) CIN2(+) EXC1 AD7153 TOP VIEW (Not to Scale) 9 8 7 6 NC 5 NC = NO CONNECT Figure 4. AD7152 Pin Configuration Figure 5. AD7153 Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic GND VDD CIN1(–) CIN1(+) EXC2/NC Description Ground Pin. Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example, in combination with a 10 μF tantalum and a 0.1 μF multilayer ceramic capacitor. CDC Negative Capacitive Input of Channel 1. If not used, this pin can be left as an open circuit or connected to GND. This pin is internally disconnected in single-ended CDC configuration. CDC Positive Capacitive Input of Channel 1. If not used, this pin can be left as an open circuit or connected to GND. AD7152: CDC Excitation Output for Channel 2. The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, these pins should be left as an open circuit. AD7153: No Connect. This pin must be left as an open circuit. CDC Excitation Output for Channel 1. The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, these pins should be left as an open circuit. AD7152: CDC Positive Capacitive Input of Channel 2. If not used, this pin can be left as an open circuit or connected to GND. AD7153: No Connect. This pin must be left as an open circuit. AD7152: CDC Negative Capacitive Input of Channel 2. If not used, this pin can be left as an open circuit or connected to GND. This pin is internally disconnected in single-ended CDC configuration. AD7153: No Connect. This pin must be left as an open circuit. Serial Interface Clock Input. Connects to the master clock line. Requires a pull-up resistor if one is not already provided in the system. Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if one is not provided elsewhere in the system. 6 7 EXC1 CIN2(+)/NC 8 CIN2(–)/NC 9 10 SCL SDA Rev. 0 | Page 7 of 24 AD7152/AD7153 TYPICAL PERFORMANCE CHARACTERISTICS 0.05 0.04 0.03 GAIN ERROR (%FSR) 0.02 2 0 –2 9pF –4 –6 –8 –10 07450-106 07450-109 INL (% of FSR) 3pF 0.01 0 0.01 0.02 0.03 0.04 0.05 –2 –1 0 CAPACITANCE (pF) 1 2 –12 0 50 100 150 200 250 300 350 CAP LOAD TO GND (pF) Figure 6. Capacitance Input Integral Nonlinearity, VDD = 3.3 V, See Figure 34 0.20 TC ≈ 28ppm/°C 0.15 0.10 GAIN ERROR (%FSR) Figure 9. Capacitance Input Error vs. Capacitance Between CIN and GND; Single-Ended Mode, CIN(+) to EXC = 3 pF and 9 pF, VDD = 3.3 V 2 2pF 0 –2 –4 –6 –8 –10 07450-110 07450-111 0.05 0.00 –0.05 –0.10 –0.15 –0.20 07450-107 GAIN ERROR (%FSR) 8pF –0.25 50 25 0 25 50 TEMPERATURE (°C) 75 100 –12 0 50 100 150 200 250 300 350 CAP LOAD TO GND (pF) Figure 7. Capacitance Input Gain Drift vs. Temperature, VDD = 3.3 V, Range = ±2 pF Figure 10. Capacitance Input Error vs. Capacitance Between CIN and GND, Differential Mode, CIN(+) to EXC = 2 pF and 8 pF, CIN(−) to EXC = 0 pF and 6 pF, VDD = 3.3 V 0.3 0.4 0.2 OFFSET CAPACITANCE (fF) 0.2 GAIN ERROR (%FSR) 0.1 0 0 –0.1 –0.2 –0.2 –25 0 25 50 75 100 07450-108 –0.4 –50 –0.3 0 50 100 150 200 250 300 350 TEMPERATURE (°C) CAP LOAD TO GND (pF) Figure 8. Capacitance Input Offset Drift vs. Temperature, VDD = 3.3 V, CIN and EXC Pins Open Circuit Figure 11. Capacitance Input Error vs. Capacitance Between EXC and GND, Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V Rev. 0 | Page 8 of 24 AD7152/AD7153 0.3 10 0.2 0 GAIN ERROR (%FSR) 07450-112 GAIN ERROR (%FSR) 0.1 –10 0 –20 –0.1 –30 –0.2 –40 0 50 100 150 200 250 300 350 1 10 100 1000 CAP LOAD TO GND (pF) PARALLEL RESISTANCE (MΩ) Figure 12. Capacitance Input Error vs. Capacitance Between EXC and GND, Differential Mode, CIN(+) to EXC = 8 pF, CIN(−) to EXC = 6 pF, VDD = 3.3 V 2 Figure 15. Capacitance Input Error vs. Parasitic Parallel Resistance Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V 0 3pF 0 GAIN ERROR (%FSR) GAIN ERROR (%FSR) –5 –2 –10 9pF –15 –4 –6 –20 –8 –25 07450-113 1 10 100 1000 0 20 40 60 80 100 RESISTANCE CIN TO GROUND (MΩ) SERIAL RESISTANCE (kΩ) Figure 13. Capacitance Input Error vs. Parasitic Resistance CIN to GND, Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V 0.6 Figure 16. Capacitance Input Error vs. Serial Resistance, Single-Ended Mode, CIN(+) to EXC = 3 pF and 9 pF, VDD = 3.3 V 0.2 0.4 GAIN ERROR (%FSR) 0.0 GAIN ERROR (fF) 0.2 –0.2 0 –0.4 –0.2 –0.6 –0.4 –0.8 1 10 100 1000 07450-114 2.8 3.0 3.2 VDD (V) 3.4 3.6 3.8 RESISTANCE EXC TO GROUND (MΩ) Figure 14. Capacitance Input Error vs. Parasitic Resistance EXC to GND, Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V Figure 17. Capacitance Input Power Supply Rejection (PSR), Differential Mode; CIN(+) to EXC = 1.9 pF Rev. 0 | Page 9 of 24 07450-117 –0.6 –1.0 2.6 07450-116 –10 –30 07450-115 –0.3 –50 AD7152/AD7153 30 0 20 –20 FILTER GAIN (dB) 07450-118 10 DNL (fF) 0 –40 –10 –60 –20 0 5 10 15 CAPDAC CODE 20 25 30 0 50 100 150 INPUT SIGNAL FREQUENCY (Hz) Figure 18. CAPDAC(+) Differential Nonlinearity (DNL) 30 0 Figure 20. Capacitance Channel Frequency Response, Conversion Time = 60 ms 20 –20 FILTER GAIN (dB) 10 DNL (fF) 0 –40 –10 –60 –20 07450-119 0 5 10 15 CAPDAC CODE 20 25 30 0 50 100 150 INPUT SIGNAL FREQUENCY (Hz) Figure 19. CAPDAC(−) Differential Nonlinearity (DNL) Figure 21. Capacitance Channel Frequency Response, Conversion Time = 50 ms Rev. 0 | Page 10 of 24 07450-221 –30 –80 07450-120 –30 –80 AD7152/AD7153 SERIAL INTERFACE The AD7152/AD7153 support an I2C-compatible, 2-wire serial interface. The two wires on the I2C bus are called SCL (clock) and SDA (data). These two wires carry all addressing, control, and data information one bit at a time over the bus to all connected peripheral devices. The SDA wire carries the data, while the SCL wire synchronizes the sender and receiver during the data transfer. I2C devices are classified as either master or slave devices. A device that initiates a data transfer message is called a master; a device that responds to this message is called a slave. To control the AD7152/AD7153 via the bus, the following protocol must be followed. The master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that the start byte follows. This 8-bit start byte is made up of a 7-bit address plus an R/W bit indicator. All peripherals connected to the bus respond to the start condition and shift in the next 8 bits (7-bit address and an R/W bit). The bits arrive MSB first. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. An exception to this is the general call address, which is described in the General Call section. The idle condition is where the device monitors the SDA and SCL lines waiting for the start condition and the correct address byte. The R/W bit determines the direction of the data transfer. A Logic 0 LSB in the start byte means that the master writes information to the addressed peripheral. In this case, the device becomes a slave receiver. A Logic 1 LSB in the start byte means that the master reads information from the addressed peripheral. In this case, the device becomes a slave transmitter. In all instances, the AD7152/AD7153 act as a standard slave device on the I2C bus. The start byte address is Address 0x90 for a write and Address 0x91 for a read. A stop condition is defined by a low-to-high transition on SDA while SCL remains high. If a stop condition is ever encountered by the AD7152/AD7153, it returns to its idle condition and the address pointer is reset to Address 0x00. If a data byte is transmitted after the register address pointer byte, the AD7152/AD7153 load this byte into the register that is currently addressed by the address pointer register. The parts send an acknowledge and the address pointer autoincrementer automatically increments the address pointer register to the next internal register address. Thus, subsequent transmitted data bytes are loaded into sequentially incremented addresses. If a repeated start condition is encountered after the address pointer byte, all peripherals connected to the bus respond exactly as previously outlined for a start condition, that is, a repeated start condition is treated the same as a start condition. When a master device issues a stop condition, it relinquishes control of the bus, allowing another master device to take control. Hence, a master wanting to retain control of the bus issues successive start conditions known as repeated start conditions. READ OPERATION When a read is selected in the start byte, the register that is currently addressed by the address pointer is transmitted onto the SDA line by the AD7152/AD7153. The regulator is then clocked out by the master device, and the AD7152/AD7153 await an acknowledge from the master. If an acknowledge is received from the master, the address autoincrementer automatically increments the address pointer register and outputs the next addressed register content onto the SDA line for transmission to the master. If no acknowledge is received, the AD7152/AD7153 return to the idle state and the address pointer is not incremented. The autoincrementer of the address pointers allows block data to be written or read from the starting address and subsequent incremental addresses. In continuous conversion mode, autoincrementer of the address pointers should be used for reading a conversion result; that is, the three data bytes should be read using one multibyte read transaction rather than three separate single-byte transactions. The single-byte data read transaction may result in the data bytes from two different results being mixed. WRITE OPERATION When a write is selected, the byte following the start byte is always the register address pointer (subaddress) byte, which points to one of the internal registers on the AD7152/AD7153. The address pointer byte is automatically loaded into the address pointer register and acknowledged by the AD7152/ AD7153. After the address pointer byte acknowledge, a stop condition, a repeated start condition, or another data byte can follow from the master. Rev. 0 | Page 11 of 24 AD7152/AD7153 The user can also access any unique register (address) on a one-to-one basis without having to update all the registers. However, the address pointer register contents cannot be read. If an incorrect address pointer location is accessed, or if the user allows the autoincrementer to exceed the required register address, apply the following requirements: • In read mode, the AD7152/AD7153 continue to output various internal register contents until the master device issues a no acknowledge, start, or stop condition. The contents of the address pointers autoincrementer are reset to point to the status register at Address 0x00 when a stop condition is received at the end of a read operation. This allows the status register to be read (polled) continually without having to constantly write to the address pointer. In write mode, the data for the invalid address is not loaded into the registers of the AD7152/AD7153, but an acknowledge is issued by the AD7152/AD7153. AD7152/AD7153 RESET To reset the AD7152/AD7153 without having to reset the entire I2C bus, an explicit reset command is provided. This command uses a particular address pointer word as a command word to reset the part and upload all default settings. The AD7152/ AD7153 do not respond to the I2C bus commands (no acknowledge) during the default values upload for approximately 150 μs (maximum 200 μs). The reset command address word is 0xBF. GENERAL CALL When a master issues a slave address consisting of seven 0s with the eighth bit (R/W bit) set to 0, this is called the general call address. The general call address is for addressing every device connected to the I2C bus. The AD7152/AD7153 acknowledge this address and read the following data byte. If the second byte is 0x06, the AD7152/AD7153 are reset, completely uploading all default values. The AD7152/AD7153 do not respond to the I2C bus commands (no acknowledge) during the default values upload for approximately 150 μs (maximum 200 μs). The AD7152/AD7153 do not acknowledge any other general call commands. • SDA START ADDR R/W ACK SUBADDRESS ACK DATA ACK STOP Figure 22. Bus Data Transfer WRITE SEQUENCE S SLAVE ADDR A(S) LSB = 0 SUB ADDR A(S) DATA A(S) LSB = 1 DATA A(S) P Figure 23. Write and Read Sequences Table 5. I2C Abbreviation Abbreviation S P A(S) A(M) A(S) A(M) ACK R/W Definition Start bit Stop bit Acknowledge by slave Acknowledge by master No acknowledge by slave No acknowledge by master Acknowledge Read/write Rev. 0 | Page 12 of 24 07450-007 READ SEQUENCE 07450-006 SCL S 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 P S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA A(M) DATA A(M) P AD7152/AD7153 REGISTER MAP The master can write to or read from all of the registers except the address pointer register, which is a write-only register. The address pointer register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the address pointer register. After the part has been accessed over the bus and a Table 6. Register Summary Register Name Status Channel 1 Data MSB Channel 1 Data LSB Channel 2 Data MSB1 Channel 2 Data LSB Channel 1 Offset MSB Channel 1 Offset LSB Channel 2 Offset MSB1 Channel 2 Offset LSB1 Channel 1 Gain MSB Channel 1 Gain LSB Channel 1 Setup Channel 2 Gain MSB1 Channel 2 Gain LSB1 Channel 2 Setup1 Configuration Reserved CAPDAC POS CAPDAC NEG Configuration2 1 read/write operation is selected, the address pointer register is set up. The address pointer register determines from or to which register the operation takes place. A read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. Subaddress Dec Hex 0 0x00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 26 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x1A Access R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 PWDN Bit 6 Unused Bit 5 Unused Bit 4 Unused Bit 3 Unused Bit 2 C1C2 Bit 1 RDY2 Bit 0 RDY1 Default Value 0x03 0x00 0x00 0x00 0x00 0x80 0x00 0x80 0x00 0xXX 0xXX 0x00 0xXX 0xXX 0x00 0x00 0x00 0x00 0x00 0x00 Channel 1 data, high byte Channel 1 data, low byte Channel 2 data, high byte Channel 2 data, low byte Channel 1 offset calibration coefficient, high byte Channel 1 offset calibration coefficient, low byte Channel 2 offset calibration coefficient, high byte Channel 2 offset calibration coefficient, low byte Channel 1 gain coefficient, high byte, factory calibrated Channel 1 gain coefficient, low byte, factory calibrated Range 1 Range 0 CAPDIFF Unused Unused Channel 2 gain coefficient, high byte, factory calibrated Channel 2 gain coefficient, low byte, factory calibrated Range 0 CAPDIFF Unused Unused Unused Unused Ch1en Ch2en MD2 MD1 Unused Unused Unused Unused Unused OSR1 DACP Bits[4:0] value DACN Bits[4:0] value OSR0 Unused Unused Range 1 Unused Unused DACPen DACNen Unused MD0 Unused Unused AD7152 only. Rev. 0 | Page 13 of 24 AD7152/AD7153 STATUS REGISTER Address 0x00 Read Only Default Value 0x03 This register indicates the status of the converter. The status register can be read via the 2-wire serial interface to query a finished conversion. Table 7. Status Register Bit Map Bit Mnemonic Default Bit 7 PWDN 0 Bit 6 Unused 0 Bit 5 Unused 0 Bit 4 Unused 0 Bit 3 Unused 0 Bit 2 C1C2 0 Bit 1 RDY2 1 Bit 0 RDY1 1 Table 8. Status Register Bit Descriptions Bit 7 6 to 3 2 1 0 Mnemonic PWDN N/A C1C2 RDY2 RDY1 Description PWDN = 1 indicates that the VDD voltage level is below 2.45 V typically or part is in power-down mode Not used, always read 0 C1C2 = 0 indicates that the last conversion performed was from Channel 1, C1C2 = 1 indicates that the last conversion performed was from Channel 2 RDY2 = 0 indicates that a conversion on the Channel 2 has been finished and new unread data is available (AD7152 only) RDY1 = 0 indicates that a conversion on the Channel 1 has been finished and new unread data is available Rev. 0 | Page 14 of 24 AD7152/AD7153 DATA REGISTERS Address 0x01, Address 0x02 for Channel 1 Address 0x03, Address 0x04 (AD7152 Only) Channel 2 16 Bits, Read-Only, Default Value 0x0000 Data from the last complete capacitance-to-digital conversion reflects the capacitance on the input. Only the 12 MSBs of the data registers are used for the CDC result. The 4 LSBs are always 0, as shown in Figure 24. MSB DATA HIGH DATA LOW LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 07450-044 Therefore, to prevent incorrect data reading through the serial interface, the two bytes of a data register should be read sequentially using the register address pointer autoincrement feature of the serial interface. OFFSET CALIBRATION REGISTERS Address 0x05, Address 0x06 for Channel 1, Address 0x07, Address 0x08 for Channel 2 (AD7152 Only) 16 Bits Read/Write, Default Value 0x8000 The offset calibration registers hold the zero-scale calibration coefficients. The zero-scale calibration coefficient digitally maps the zero capacitance on the CDC input to the zero-scale data code. The coefficient can be used for compensation of the AD7152/ AD7153 internal offset as well as the system level offset within specified offset calibration limits. Users can set the coefficient by executing the offset calibration after connecting the zero-scale capacitance to the system input. Alternatively, the coefficient value can be written to the offset calibration register(s) by the host software, for example, values stored in a host nonvolatile memory. Note that there is a difference between code mapping in differential and single-ended input mode. In differential mode, the nominal zero-scale calibration coefficient value is a power-on default, 0x8000. In single–ended mode, the nominal zero-scale calibration coefficient value is 0x3000. The difference means that before using the single-ended mode (or any time when changing between modes afterwards), the user should either perform offset calibration with capacitance close to 0 pF connected to the input or write the offset calibration register(s) value(s) close to 0x8000 for differential mode or value close to 0x3000 for single-ended mode. On the AD7152, the two capacitive channels have individual offset registers and each channel can be calibrated individually. 12-BIT CDC RESULT 0 Figure 24. CDC Data Register The AD7152/AD7153 are factory gain calibrated and map the CDC full-scale raw data range of 0x3000 to 0xCFF0F to a CDC full-scale data register range of 0x0000 to 0xFFF0 (see Table 9). Table 9. AD7152/AD7153 Capacitance-to-Data Mapping Data Reg 0x0000 0x8000 0xFFF0 Input Capacitance (4 pF range) Differential Mode Single-Ended Mode Negative full scale (–2 pF) Zero scale (0 pF) Zero scale (0 pF) Midscale (2 pF) Positive full scale (+2 pF) Full scale (4 pF) The data register output in differential mode is internally calculated using the following equation: Data Reg = (Code – (Offset Reg – 0x8000)) × Gain + 0x8000 (1) The input capacitance can be calculated from the output data using the following equation: C(pF) = Data Reg − 0 x 8000 0 xFFF 0 × Input Range (2) The data register output in single-ended mode is internally calculated using the following equation: Data Reg = (Code − (Offset Reg − 0x3000)) × Gain The input capacitance can be calculated from the output data using the following equation: C(pF) = Data Reg 0 xFFF 0 × Input Range (3) GAIN CALIBRATION REGISTERS (4) Address 0x09, Address 0x0A for Channel1 Address 0x0C, Address 0x0D for Channel 2 (AD7152 only) 16 Bits Read/Write, Default Value 0xXXXX The capacitive gain calibration registers hold the capacitive channel full-scale factory calibration coefficient. The gain calibration factor can be calculated using the following equation: where Input Range = 4 pF, 2 pF, 1 pF, or 0.5 pF. A data register is updated after a finished conversion on the capacitive channel, with one exception: when the serial interface read operation from the data register is in progress, the data register is not updated and the new capacitance conversion result is lost. The stop condition on the serial interface is considered to be the end of the read operation. Gain = 216 + Gain Reg 216 (5) On the AD7152, the two capacitive channels each have a gain register, which allows the part to gain calibrate each channel individually. Rev. 0 | Page 15 of 24 AD7152/AD7153 CAP SETUP REGISTERS Address 0x0B for Channel 1 Address 0x0E Channel 2 (AD7152 Only) Default Value 0x00 Table 10. CAP Setup Register Bit Map Bit Mnemonic Default Bit 7 Range 1 0 Bit 6 Range 0 0 Bit 5 CAPDIFF 0 Bit 4 Unused 0 Bit 3 Unused 0 Bit 2 Unused 0 Bit 1 Unused 0 Bit 0 Unused 0 Table 11. CAP Setup Register Bit Descriptions Bit 7 6 5 Mnemonic Range 1 Range 0 CAPDIFF Description Capacitive input range and mode setup Capacitive Input Range Range 1 Range 0 CAPDIFF = 1 (Differential Mode) CAPDIFF = 0 (Single-Ended Mode) 0 0 ±1 pF 2 pF 0 1 ±0.25 pF 0.5 pF 1 0 ±0.5 pF 0.25 pF 1 1 ±2 pF 4 pF These bits must be 0 for proper operation 4 to 0 N/A CONFIGURATION REGISTER Address Pointer 0x0F Default Value 0x00 Table 12. Configuration Register Bit Map Bit Mnemonic Default Bit 7 Unused 0 Bit 6 Unused 0 Bit 5 Unused 0 Bit 4 Ch1en 0 Bit 3 Ch2en 0 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 0 Table 13. Configuration Register Bit Descriptions Bit 7 to 5 4 3 2 1 0 Mnemonic N/A Ch1en Ch2en MD2 MD1 MD0 Description These bits must be 0 for proper operation Ch2en = 1 enables Channel 1 for single conversion, continuous conversion, or calibration Ch2en = 1 enables Channel 2 for single conversion, continuous conversion, or calibration Converter mode of operation setup MD2 MD1 MD0 Mode 0 0 0 Idle 0 0 1 Continuous conversion 0 1 0 Single conversion 0 1 1 Power-down 1 0 0 N/A 1 0 1 Capacitance system offset calibration 1 1 0 Capacitance system gain calibration 1 1 1 N/A Rev. 0 | Page 16 of 24 AD7152/AD7153 CAPDAC POS REGISTER Address 0x11 Default Value 0x00 Table 14. Status Register Bit Map Bit Mnemonic Default Bit 7 DACPen 0 Bit 6 Unused 0 Bit 5 Unused 0 Bit 4 Bit 3 Bit 2 Bit 1 DACP – Bits[4:0] Value 0x00 Bit 0 Table 15. Status Register Bit Descriptions Bit 7 6 to 5 4 to 0 Mnemonic DACPen N/A DACP Description DACPen = 1 connects the capacitive DAC POS to the positive capacitive input These bits must be 0 for proper operation DACP value, Code 0x00 = 0 pF, Code 0x1F = full range CAPDAC NEG REGISTER Address 0x12 Default Value 0x00 Table 16. Status Register Bit Map Bit Mnemonic Default Bit 7 DACNen 0 Bit 6 Unused 0 Bit 5 Unused 0 Bit 4 Bit 3 Bit 2 Bit 1 DACN – Bit[4:0] Value 0x00 Bit 0 Table 17. Status Register Bit Descriptions Bit 7 6 to 5 4 to 0 Mnemonic DACNen N/A DACN Description DACNen = 1 connects the capacitive DAC NEG to the positive capacitive input These bits must be 0 for proper operation DACN value, Code 0x00 = 0 pF, Code 0x1F = full range CONFIGURATION2 REGISTER Address 0x1A, Default Value 0x00 Table 18. Configuration2 Register Bit Map Bit Mnemonic Default Bit 7 Unused 0 Bit 6 Unused 0 Bit 5 OSR1 0 Bit 4 OSR0 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Table 19. Configuration2 Register Bit Descriptions Bit 7 to 6 5 4 Mnemonic N/A OSR1 OSR0 Description These bits must be 0 for proper operation Capacitive channel digital filter setup; conversion time/update rate setup per channel OSR1 OSR0 Conversion Time (ms) Update Rate (Hz) 0 0 5 200 0 1 20 50 1 0 50 20 1 1 60 16.7 These bits must be 0 for proper operation 3 to 0 N/A Rev. 0 | Page 17 of 24 AD7152/AD7153 CIRCUIT DESCRIPTION VDD CAP+ CAP– CIN1(+) CIN1(–) EXC1 CIN2(+) CIN2(–) EXC2 07450-025 CAPACITANCE-TO-DIGITAL CONVERTER (CDC) AD7152 CLOCK GENERATOR VOLTAGE REFERENCE MUX 12-BIT Σ-Δ MODULATOR I2C SERIAL INTERFACE SDA SCL EXCITATION DIGITAL FILTER GND CONTROL LOGIC CALIBRATION Figure 25. AD7152 Block Diagram VDD CAP+ CAP– CLOCK GENERATOR VOLTAGE REFERENCE Figure 27 shows the CDC simplified functional diagram. The measured capacitance CX is connected between the excitation source and the Σ-Δ modulator input. A square-wave excitation signal is applied on the CX during the conversion and the modulator continuously samples the charge going through the CX. The digital filter processes the modulator output, which is a stream of 0s and 1s containing the information in 0 and 1 density. The data from the digital filter is scaled, applying the calibration coefficients, and the final result can be read through the serial interface. The AD7152/AD7153 are designed for floating capacitive sensors. Therefore, both CX plates have to be isolated from ground. CAPACITANCE-TO-DIGITAL CONVERTER (CDC) CLOCK GENERATOR DATA 12-BIT Σ-Δ MODULATOR DIGITAL FILTER AD7153 CIN1(+) CIN1(–) EXC1 EXCITATION DIGITAL FILTER GND CONTROL LOGIC CALIBRATION MUX 12-BIT Σ-Δ MODULATOR I2C SERIAL INTERFACE SDA SCL CX CIN 07450-026 Figure 27. CDC Simplified Block Diagram Figure 26. AD7153 Block Diagram EXCITATION SOURCE The AD7152/AD7153 have one excitation source. For the AD7152, the excitation source is switched between the excitation pins, EXC1 and EXC2, depending on which channel performs a conversion. The core of the AD7152/AD7153 is a precision converter consisting of a second-order modulator (Σ-Δ or chargebalancing) and a third-order digital filter. In addition to the converter, the AD7152/AD7153 integrate a multiplexer, an excitation source, and CAPDACs for the capacitive inputs, a voltage reference, a complete clock generator, a control and calibration logic, and an I2C-compatible serial interface. The AD7153 has one capacitive input, while the AD7152 has two capacitive inputs. For the AD7152, the modulator input and the excitation source are multiplexed between the converting channel. All other features and specifications are identical for both parts. Rev. 0 | Page 18 of 24 07450-027 EXC EXCITATION AD7152/AD7153 CAPDAC The CDC full-scale input range of the AD7152/AD7153 can be set to ±0.25 pF, ±0.5 pF, ± 1 pF, and ±2 pF in differential mode or 0.5 pF, 1 pF, 2 pF, and 4 pF in single-ended mode. For simplicity, the following text and figures use the maximum full scale of ±2 pF and +4 pF. The parts can accept a higher capacitance on the input and the common-mode or offset capacitance (unchanging component) can be balanced by programmable on-chip CAPDACs. CAPDAC(+) CIN(+) CIN(–) CDC DATA CX 0pF TO 4pF EXC CAPDAC(–) OFF SINGLE-ENDED CAPACITIVE INPUT When configured for a single-ended mode (the CAPDIFF bit in the Channel 1 Setup or Channel 2 Setup registers is set to 0), the AD7152/AD7153 CIN(−) pin is disconnected internally. The CDC (without using the CAPDACs) can measure positive input capacitance in the range of 0 pF to 4 pF (see Figure 29). CAPDAC(+) OFF CIN(+) CIN(–) CAPDIFF = 0 0pF TO 4pF CDC 0x0000 ... 0xFFF0 DATA CX CY CAPDAC(–) Figure 29. CDC Single-Ended Input Mode 07450-010 EXC Figure 28. Using a CAPDAC The CAPDAC can be used for programmable shifting of the input range. Figure 30 shows how to shift the input range up to 9 pF absolute value of capacitance connected to the CIN(+) using the CAPDAC(+) only. CAPDAC(+) 5pF CIN(+) CIN(–) CAPDIFF = 0 0pF TO 4pF CDC 0x0000 ... 0xFFF0 DATA The CAPDAC can be understood as a negative capacitance connected internally to the CIN pin. There are two independent CAPDACs, one connected to the CIN(+) and the second connected to the CIN(–). In differential mode, the relationship between the capacitance input and output data can be expressed as DATA ≈ (CX − CAPDAC(+)) − (CY − CAPDAC(−)) In single-ended mode, the relationship between the capacitance input and output data can be expressed as DATA ≈ CX −(CAPDAC(+) + CAPDAC(−)) The CAPDACs have a 5-bit resolution each, monotonic transfer function, are well matched to each other, and have a defined temperature coefficient. The CAPDAC full range (absolute value) is not factory calibrated and can vary up to ±20% with the manufacturing process (see the Specifications section, Figure 18, and Figure 19). The CAPDACs are shared by the two capacitive channels on the AD7152. If the CAPDACs need to be set individually, the host controller software should reload the CAPDAC values to the AD7152 before executing a conversion on a different channel. CX 5pF TO 9pF EXC CAPDAC(–) OFF Figure 30. Using CAPDAC in Single-Ended Mode Figure 31 shows how to shift the input range up to 14 pF absolute value of capacitance connected to the CIN(+) using both CAPDAC(+) and CAPDAC(−). CAPDAC(+) 5pF CIN(+) CIN(–) CAPDIFF = 0 0pF TO 4pF CDC 0x0000 ... 0xFFF0 DATA CX 10pF TO 14pF EXC CAPDAC(–) 5pF Figure 31. Using CAPDAC in Single-Ended Mode Rev. 0 | Page 19 of 24 07450-224 07450-124 07450-024 AD7152/AD7153 DIFFERENTIAL CAPACITIVE INPUT When configured for differential mode (the CAPDIFF bit in the Channel 1 Setup or Channel 2 Setup registers is set to 1), the CDC measures the difference between positive and negative capacitance input. Each of the two input capacitances, CX and CY, between the EXC and CIN pins must be less than 2 pF (without using the CAPDACs) or must be less than 9 pF and balanced by the CAPDACs. Balancing by the CAPDACs means that both CX − CAPDAC(+) and CY − CAPDAC(−) are less than 2 pF. If the unbalanced capacitance between the EXC and CIN pins is higher than 2 pF, the CDC introduces a gain error, an offset error, and nonlinearity error (see Figure 32, Figure 33, and Figure 34). CAPDAC(+) OFF CIN(+) CIN(–) CAPDIFF = 1 ± 2pF CDC 0x0000 ... 0xFFF0 DATA PARASITIC CAPACITANCE TO GROUND CGND1 CIN CDC DATA CX EXC Figure 35. Parasitic Capacitance to Ground The CDC architecture used in the AD7152/AD7153 measures CX connected between the EXC pin and the CIN pin. In theory, any capacitance, CGND, to ground should not affect the CDC result (see Figure 35). The practical implementation of the circuitry in the chip implies certain limits and the result is gradually affected by capacitance to ground. See the allowed capacitance to GND in the Specifications table and, Figure 9 through Figure 12. CX 0pF TO 4pF CY 0pF TO 4pF EXC CAPDAC(–) OFF PARASITIC RESISTANCE TO GROUND 07450-020 Figure 32. CDC Differential Input Mode RGND1 CIN CDC DATA CAPDAC(+) 5pF CIN(+) CIN(–) CAPDIFF = 1 ± 2pF CDC 0x0000 ... 0xFFF0 DATA RGND2 CX EXC Figure 33. Using CAPDAC in Differential Mode 07450-021 CX 4pF TO 6pF (5 ± 1pF) CY 4pF TO 6pF (5 ± 1pF) EXC CAPDAC(–) 5pF Figure 36. Parasitic Resistance to Ground The CDC result can be affected by a leakage current from the CX to ground; therefore, the CX should be isolated from the ground. The influence of the leakage current varies with the power supply voltage (see Figure 36). A higher leakage current to ground results in a gain error, an offset error, and a nonlinearity error (see Figure 13 and Figure 14). CAPDAC(+) 5pF CIN(+) CIN(–) CAPDIFF = 1 ± 2pF CDC 0x0000 ... 0xFFF0 DATA CX 3pF TO 7pF (5 ± 2pF) CY 5pF EXC CAPDAC(–) 5pF Figure 34. Using CAPDAC in Differential Mode Rev. 0 | Page 20 of 24 07450-121 07450-013 07450-012 CGND2 AD7152/AD7153 PARASITIC PARALLEL RESISTANCE Some applications may require an additional input filter for improving electromagnetic compatibility (EMC). Any input filter must be carefully designed, considering the balance between the system capacitance performance and system electromagnetic immunity. Figure 39 shows one of the possible input circuit configurations significantly improving the system immunity against high frequency noise and slightly affecting the AD7152 performance in terms of additional gain and offset error. 07450-022 CIN CDC DATA CX RP EXC POWER SUPPLY DECOUPLING AND FILTERING 1kΩ 0.1µF 10µF 1kΩ SDA CDC SCL 1kΩ VDD Figure 37. Parasitic Parallel Resistance GND PARASITIC SERIAL RESISTANCE Figure 40. AD7152/AD7153 VDD Decoupling and Filtering RS1 CIN CDC DATA The AD7152 has good dc and low frequency power supply rejection but may be sensitive to higher frequency ripple and noise, specifically around the excitation frequency and its harmonics. Figure 40 shows a possible circuit configuration for improving the system immunity against ripple and noise coupled to the AD7152 via the power supply. Because the serial interface is connected to the other circuits in the system, it is better to connect the pull-up resistors on the other side of the VDD filter than to connect to the AD7152. CX EXC 07450-023 RS2 Figure 38. Parasitic Serial Resistance CAPACITIVE GAIN CALIBRATION The gain of the AD7152/AD7153 is factory calibrated for the full scale of 4 pF in the production for each part individually. The factory gain coefficient is stored in a one-time programmable (OTP) memory and is copied to the capacitive gain registers at power-up or after reset. The gain can be changed by executing a capacitance gain calibration mode, for which an external full-scale capacitance needs to be connected to the capacitance input, or by writing a user value to the capacitive gain register. This change is temporary and the factory gain coefficient can be reloaded after power-up or reset. The part is tested and specified only for use with the default factory calibration coefficient. The CDC result is affected by a resistance in series with the measured capacitance. The total serial resistance, which refers to RS1 and RS2 in Figure 38, should be less than 20 kΩ for the specified performance (see Figure 16). INPUT EMC PROTECTION R1 C1 CX R3 C3 EXC GND 07450-039 R2 C2 CIN CDC CAPACITIVE SYSTEM OFFSET CALIBRATION The capacitive offset is dominated by the parasitic offset in the application, such as the initial capacitance of the sensor, any parasitic capacitance of tracks on the board, and the capacitance of any other connections between the sensor and the CDC. Therefore, the AD7152/AD7153 are not factory calibrated for capacitive offset. The user should calibrate the system capacitance offset in the application. Figure 39. AD7152/AD7153 EMC Protection Rev. 0 | Page 21 of 24 07450-058 The CDC measures the charge transfer between the EXC pin and CIN pin. Any resistance connected in parallel to the measured capacitance CX (see Figure 37), such as the parasitic resistance of the sensor, also transfers charge. Therefore, the parallel resistor is seen as an additional capacitance in the output data causing a capacitive input error (see Figure 15). AD7152/AD7153 The offset register of the AD7152/AD7153 allows for offset calibration over the full capacitive input range. However, the user must ensure that the offset to be removed is within 40% of the full scale range; this can be achieved by using the CAPCAC to perform a coarse offset calibration and use the system offset calibration then to compensate for an offset within the 40% of full-scale range pF of the CAPDAC. The offset calibration register is reloaded by the default value 0x8000 at power-on or after reset. Therefore, if the offset calibration is not repeated after each system power-up, the calibration coefficient value should be stored by the host controller and reloaded as part of the AD7152/AD7153 setup. Note that the AD7152/AD7153 zero scale for differential mode is around 0x8000; therefore, the offset register also needs a value of around 0x8000, where the zero scale in single-ended mode is 0x0000, with a required offset register value of 0x3000. For more detailed information, see the Data Registers section. TYPICAL APPLICATION DIAGRAM 1kΩ 0.1µF VDD R1 R2 C1 CIN1(+) C2 10µF 1µF 3.3V ADP1720-3.3 VSUPPLY 1µF AD7153 SDA SCL 1kΩ 1kΩ HOST SYSTEM R3 R4 C3 CIN1(–) C4 GND CSENS1 CSENS2 10kΩ EXC1 GND 07450-061 47pF Figure 41. Basic Application Diagram for a Differential Capacitive Sensor Rev. 0 | Page 22 of 24 AD7152/AD7153 OUTLINE DIMENSIONS 3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 0.33 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8° 0° 0.80 0.60 0.40 10 6 1 5 5.15 4.90 4.65 SEATING PLANE 0.23 0.08 Figure 42. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model AD7152BRMZ 1 AD7152BRMZ-REEL1 AD7153BRMZ1 AD7153BRMZ-REEL1 EVAL-AD7152EBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 Branding C5P C5P C5Q C5Q Z = RoHS Compliant Part. Rev. 0 | Page 23 of 24 AD7152/AD7153 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07450-0-5/08(0) Rev. 0 | Page 24 of 24