Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta
ADC with True Rail-to-Rail Buffers
AD7172-4
Data Sheet
FEATURES
GENERAL DESCRIPTION
Fast and flexible output rate: 1.25 SPS to 31.25 kSPS
Channel scan data rate of 6.21 kSPS/channel (161 μs settling)
Performance specifications
17.2 noise free bits at 31.25 kSPS
24 noise free bits at 5 SPS
INL: ±2 ppm of FSR
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
User configurable input channels
4 fully differential channels or 8 single-ended channels
Crosspoint multiplexer
True rail-to-rail analog and reference input buffers
Internal or external clock
Power supply
AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V
Split supply with AVDD1 and AVSS at ±2.5 V or ±1.65 V
ADC current: 1.5 mA
Temperature range: −40°C to +105°C
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
Serial port interface (SPI), QSPI-, MICROWIRE-, and DSPcompatible
The AD7172-4 is a low noise, low power, multiplexed, Σ-Δ analogto-digital converter (ADC) with 4- or 8-channel (fully differential/
single-ended) inputs for low bandwidth signals. The AD7172-4
has a maximum channel scan rate of 6.21 kSPS (161 μs) for fully
settled data. The output data rates range from 1.25 SPS to 31.25 kSPS.
APPLICATIONS
Note that, throughout this data sheet, the dual function pin
names are referenced by the relevant function only.
The AD7172-4 integrates key analog and digital signal conditioning blocks to allow users to configure an individual setup for
each analog input channel in use via the SPI. Integrated true rail-torail buffers on the analog inputs and reference inputs provide easy
to drive high impedance inputs.
The digital filter allows simultaneous 50 Hz and 60 Hz rejection
at a 27.27 SPS output data rate. The user can switch between
different filter options according to the demands of each channel
in the application, with further digital processing functions such
as offset and gain calibration registers, which are configurable
on a per channel basis. General-purpose input/outputs (GPIOs)
control external multiplexers synchronous to the ADC conversion
timing. The specified temperature range is −40°C to +105°C.
The AD7172-4 is in a 5 mm × 5 mm, 32-lead LFCSP.
Process control: PLC/DCS modules
Temperature and pressure measurement
Medical and scientific multichannel instrumentation
Chromatography
FUNCTIONAL BLOCK DIAGRAM
AVDD1
CROSSPOINT
MULTIPLEXER
AIN0/REF2–
AVDD2 REGCAPA REF– REF+
1.8V
LDO
AVDD
AIN1/REF2+
IOVDD REGCAPD
RAIL-TO-RAIL
REFERENCE
INPUT
BUFFERS
RAIL-TO-RAIL
ANALOG
INPUT
BUFFERS
1.8V
LDO
CS
SCLK
Σ-∆ ADC
DIGITAL
FILTER
SERIAL
INTERFACE
AND CONTROL
DIN
DOUT/RDY
SYNC
AIN7
AVSS
AIN8
I/O AND EXTERNAL
MUX CONTROL
ERROR
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
AVSS
PDSW
GPIO0 GPIO1 GPO2
GPO3
XTAL1 XTAL2/CLKIO
DGND
12676-001
AD7172-4
Figure 1.
Rev. B
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AD7172-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
CRC Calculation......................................................................... 40
Applications ....................................................................................... 1
Integrated Functions ...................................................................... 42
General Description ......................................................................... 1
General-Purpose Input/Output................................................ 42
Functional Block Diagram .............................................................. 1
External Multiplexer Control ................................................... 42
Revision History ............................................................................... 3
Delay ............................................................................................ 42
Specifications..................................................................................... 4
16-Bit/24-Bit Conversions......................................................... 42
Timing Characteristics ................................................................ 7
DOUT_RESET ........................................................................... 42
Timing Diagrams.......................................................................... 7
Synchronization .......................................................................... 42
Absolute Maximum Ratings............................................................ 8
Error Flags ................................................................................... 43
Thermal Resistance ...................................................................... 8
DATA_STAT ............................................................................... 43
ESD Caution .................................................................................. 8
IOSTRENGTH ........................................................................... 43
Pin Configuration and Function Descriptions ............................. 9
Grounding and Layout .................................................................. 44
Typical Performance Characteristics ........................................... 11
Register Summary .......................................................................... 45
Noise Performance and Resolution .............................................. 17
Register Details ............................................................................... 47
Getting Started ................................................................................ 18
Communications Register ......................................................... 47
Power Supplies ............................................................................ 19
Status Register ............................................................................. 48
Digital Communication............................................................. 19
ADC Mode Register ................................................................... 49
AD7172-4 Reset .......................................................................... 20
Interface Mode Register ............................................................ 50
Configuration Overview ........................................................... 20
Register Check ............................................................................ 51
Circuit Description ......................................................................... 26
Data Register ............................................................................... 51
Buffered Analog Input ............................................................... 26
GPIO Configuration Register ................................................... 52
Crosspoint Multiplexer .............................................................. 26
ID Register................................................................................... 53
AD7172-4 Reference .................................................................. 27
Channel Register 0 ..................................................................... 54
Buffered Reference Input........................................................... 28
Channel Register 1 to Channel Register 7 .............................. 55
Clock Source ............................................................................... 28
Setup Configuration Register 0 ................................................ 56
Digital Filters ................................................................................... 29
Sinc5 + Sinc1 Filter..................................................................... 29
Setup Configuration Register 1 to Setup Configuration
Register 7 ..................................................................................... 57
Sinc3 Filter ................................................................................... 29
Filter Configuration Register 0 ................................................. 58
Single Cycle Settling ................................................................... 30
Filter Configuration Register 1 to Filter Configuration
Register 7 ..................................................................................... 59
Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 33
Operating Modes ............................................................................ 35
Continuous Conversion Mode ................................................. 35
Continuous Read Mode ............................................................. 36
Single Conversion Mode ........................................................... 37
Standby and Power-Down Modes ............................................ 38
Calibration ................................................................................... 38
Offset Register 0 ......................................................................... 59
Offset Register 1 to Offset Register 7 ....................................... 59
Gain Register 0............................................................................ 60
Gain Register 1 to Gain Register 7 ........................................... 60
Outline Dimensions ....................................................................... 61
Ordering Guide .......................................................................... 61
Digital Interface .............................................................................. 39
Checksum Protection................................................................. 39
Rev. B | Page 2 of 61
Data Sheet
AD7172-4
REVISION HISTORY
4/2017—Rev. A to Rev. B
Changes to Outline Dimensions ...................................................68
Changes to Ordering Guide ...........................................................68
5/2015—Revision 0: Initial Version
5/2016—Rev. 0 to Rev. A
Moved Revision History ................................................................... 3
Changes to Table 5 ............................................................................ 9
Changes to Figure 18 and Figure 19 .............................................13
Changes to Power Supplies Section ..............................................19
Rev. B | Page 3 of 61
AD7172-4
Data Sheet
SPECIFICATIONS
AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, MCLK = internal master
clock = 2 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.
Table 1.
Parameter
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR)
No Missing Codes1
Resolution
Noise
ACCURACY
Integral Nonlinearity (INL)
Offset Error2
Offset Drift
Gain Error2
Gain Drift
REJECTION
Power Supply Rejection
Common-Mode Rejection
At DC
At 50 Hz, 60 Hz1
Normal Mode Rejection1
ANALOG INPUTS
Differential Input Range
Absolute Voltage Limits1
Input Buffers Disabled
Input Buffers Enabled
Analog Input Current
Input Buffers Disabled
Input Current
Input Current Drift
Input Buffers Enabled
Input Current
Input Current Drift
Crosstalk
REFERENCE INPUTS
Differential Input Range
Absolute Voltage Limits1
Input Buffers Disabled
Input Buffers Enabled
REFIN Input Current
Input Buffers Disabled
Input Current
Input Current Drift
Input Buffers Enabled
Input Current
Input Current Drift
Normal Mode Rejection1
Common-Mode Rejection
BURNOUT CURRENTS
Source/Sink Current
Test Conditions/Comments
Excluding sinc3 filter ≥ 15 kSPS
See Table 6 and Table 7
See Table 6 and Table 7
Min
Typ
1.25
24
±2
±75
±230
±5
±0.2
Internal short
Internal short
AVDD1 = 5 V
AVDD1, AVDD2, VIN = 1 V
VIN = 0.1 V
Max
Unit
31,250
SPS
Bits
±5.2
ppm of FSR
μV
nV/°C
ppm of FSR
ppm/°C
±45
±0.5
98
20 Hz output data rate (postfilter), 50 Hz
± 1 Hz and 60 Hz ± 1 Hz
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
Internal clock, 20 SPS ODR (postfilter)
External clock, 20 SPS ODR (postfilter)
95
120
71
85
VREF = (REF+) − (REF−)
dB
dB
90
90
dB
dB
±VREF
V
AVSS − 0.05
AVSS
1 kHz input
VREF = (REF+) − (REF−)
dB
1
AVDD1 + 0.05
AVDD1
±6
±0.45
μA/V
nA/V/°C
±5.5
±0.1
−120
nA
nA/°C
dB
2.5
AVSS − 0.05
AVSS
External clock
Internal clock
V
V
AVDD1
V
AVDD1 + 0.05
AVDD1
V
V
±9
±0.75
±1
μA/V
nA/V/°C
nA/V/°C
±100
±2.5
nA
nA/°C
95
dB
±10
μA
See the Rejection parameter
Analog input buffers must be enabled
Rev. B | Page 4 of 61
Data Sheet
Parameter
GPIO (GPIO0, GPIO1)
Input Mode Leakage Current1
Floating State Output
Capacitance
Output Voltage1
High, VOH
Low, VOL
Input Voltage1
High, VIH
Low, VIL
CLOCK
Internal Clock
Frequency
Accuracy
Duty Cycle
Output Voltage
Low, VOL
High, VOH
Crystal
Frequency
Startup Time
External Clock (CLKIO)
Duty Cycle1
LOGIC INPUTS
Input Voltage1
High, VINH
Low, VINL
Hysteresis1
Leakage Currents
LOGIC OUTPUT (DOUT/RDY)
Output Voltage1
High, VOH
Low, VOL
Leakage Current
Output Capacitance
SYSTEM CALIBRATION1
Full-Scale (FS) Calibration Limit
Zero-Scale Calibration Limit
Input Span
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 to AVSS
AVDD2 to AVSS
AVSS to DGND
IOVDD to DGND
IOVDD to AVSS
AD7172-4
Test Conditions/Comments
With respect to AVSS
Min
Typ
−10
Max
Unit
+10
μA
pF
5
ISOURCE = 200 μA
ISINK = 800 μA
AVSS + 4
AVSS + 0.4
V
V
AVSS + 0.7
V
V
AVSS + 3
2
−2.6%
+2.5%
50
0.4
V
V
16.384
2.048
70
MHz
μs
MHz
%
0.35 × IOVDD
0.7
0.25
0.2
+10
V
V
V
V
V
V
μA
0.8 × IOVDD
14
30
2 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
2 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
IOVDD ≥ 2.7 V
IOVDD < 2.7 V
16
10
2
50
0.65 × IOVDD
0.7 × IOVDD
0.08
0.04
−10
IOVDD ≥ 4.5 V, ISOURCE = 1 mA
2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 μA
IOVDD < 2.7 V, ISOURCE = 200 μA
IOVDD ≥ 4.5 V, ISINK = 2 mA
2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA
IOVDD < 2.7 V, ISINK = 400 μA
Floating state
Floating state
0.8 × IOVDD
0.8 × IOVDD
0.8 × IOVDD
0.4
0.4
0.4
+10
−10
10
1.05 × FS
−1.05 × FS
0.8 × FS
3.0
2
−2.75
2
For AVSS < DGND
Rev. B | Page 5 of 61
MHz
%
%
V
V
V
V
V
V
μA
pF
2.1 × FS
V
V
V
5.5
5.5
0
5.5
6.35
V
V
V
V
V
AD7172-4
Parameter
POWER SUPPLY CURRENTS
Full Operating Mode
AVDD1 Current
AVDD1 = 5 V Typical,
5.5 V Maximum
AVDD1 = 3.3 V Typical,
3.6 V Maximum1
AVDD2 Current
IOVDD Current
Standby Mode
Power-Down Mode
POWER DISSIPATION
Full Operating Mode
Standby Mode
Power-Down Mode
1
2
Data Sheet
Test Conditions/Comments
All outputs unloaded, digital inputs
connected to IOVDD or DGND
Min
Typ
Max
Unit
AIN± and REF± buffers disabled
0.23
0.29
mA
AIN± and REF± buffers enabled
Each buffer: AIN± and REF±
AIN± and REF± buffers disabled
1.7
0.38
0.15
2.15
mA
mA
mA
AIN± and REF± buffers enabled
Each buffer: AIN± and REF±
1.45
0.33
1
0.33
0.61
0.98
32
1
External clock
Internal clock
External crystal
LDO on
Full power-down including LDO
Unbuffered, external clock; AVDD1 =
3.3 V, AVDD2 = 2 V, IOVDD = 2 V
Unbuffered, external clock;
all supplies = 5 V
Unbuffered, external clock;
all supplies = 5.5 V
Fully buffered, internal clock; AVDD1 =
3.3 V, AVDD2 = 2 V, IOVDD = 2 V
Fully buffered, internal clock;
all supplies = 5 V
Fully buffered, internal clock;
all supplies = 5.5 V
All supplies = 5 V
Full power-down, all supplies = 5 V
Full power-down, all supplies = 5.5 V
0.2
1.9
1.1
0.5
0.82
10
mA
mA
mA
mA
mA
mA
μA
μA
3.16
mW
7.8
mW
10.4
mW
8
mW
16.6
mW
22.4
mW
55
μW
μW
μW
160
5
Specification is not production tested but is supported by characterization data at initial product release.
Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale
calibration reduces the gain error to the order of the noise for the programmed output data rate.
Rev. B | Page 6 of 61
Data Sheet
AD7172-4
TIMING CHARACTERISTICS
IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted.
Table 2.
Parameter
SCLK
t3
t4
READ OPERATION
t1
t23
t5
t6
t75
WRITE OPERATION
t8
t9
t10
t11
Limit at TMIN, TMAX
Unit
Test Conditions/Comments1, 2
25
25
ns min
ns min
SCLK high pulse width
SCLK low pulse width
0
15
40
0
12.5
25
2.5
20
0
10
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
CS falling edge to DOUT/RDY active time
IOVDD = 4.75 V to 5.5 V
IOVDD = 2 V to 3.6 V
SCLK active edge to data valid delay4
IOVDD = 4.75 V to 5.5 V
IOVDD = 2 V to 3.6 V
Bus relinquish time after CS inactive edge
0
8
8
5
ns min
ns min
ns min
ns min
CS falling edge to SCLK active edge setup time4
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high/low
1
Sample tested during initial release to ensure compliance.
See Figure 2 and Figure 3.
3
This parameter is defined as the time required for the output to cross the VOL or VOH limits.
4
The SCLK active edge is the falling edge of SCLK.
5
DOUT/RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required,
while DOUT/RDY is high, although care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is
enabled, the digital word can be read only once.
2
TIMING DIAGRAMS
CS (I)
t6
t1
t5
MSB
DOUT/RDY (O)
LSB
t7
t2
t3
12676-003
SCLK (I)
t4
I = INPUT, O = OUTPUT
Figure 2. Read Cycle Timing Diagram
CS (I)
t11
t8
SCLK (I)
t9
t10
MSB
LSB
I = INPUT, O = OUTPUT
Figure 3. Write Cycle Timing Diagram
Rev. B | Page 7 of 61
12676-004
DIN (I)
AD7172-4
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 3.
θJA is specified for a device soldered on a JEDEC test board for
surface-mount packages.
Parameter
AVDD1, AVDD2 to AVSS
AVDD1 to DGND
IOVDD to DGND
IOVDD to AVSS
AVSS to DGND
Analog Input Voltage to AVSS
Reference Input Voltage to AVSS
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Analog Input/Digital Input Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Lead Soldering, Reflow Temperature
ESD Rating (HBM)
Rating
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +7.5 V
−3.25 V to +0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
10 mA
−40°C to +105°C
−65°C to +150°C
150°C
260°C
4 kV
Table 4. Thermal Resistance
Package Type
32-Lead, 5 mm × 5 mm LFCSP
1-Layer JEDEC Board
4-Layer JEDEC Board
4-Layer JEDEC Board with 9 Thermal Vias
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 8 of 61
θJA
Unit
138
63
41
°C/W
°C/W
°C/W
Data Sheet
AD7172-4
32
31
30
29
28
27
26
25
REF+
REF–
GPO3
AIN8
AIN7
AIN6
AIN5
AIN4
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
AD7172-4
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
AIN3
AIN2
GPO2
GPIO1
GPIO0
REGCAPD
DGND
IOVDD
NOTES
1. DNC = DO NOT CONNECT.
2. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON THE PCB UNDER THE
EXPOSED PAD TO CONFER MECHANICAL STRENGTH TO THE PACKAGE
AND FOR HEAT DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO
AVSS THROUGH THIS PAD ON THE PCB.
12676-002
XTAL1
XTAL2/CLKIO
DOUT/RDY
DIN
SCLK
CS
ERROR
SYNC
9
10
11
12
13
14
15
16
AIN0/REF2–
AIN1/REF2+
DNC
REGCAPA
AVSS
AVDD1
AVDD2
PDSW
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin
No.
1
Mnemonic
AIN0/REF2−
Type1
AI
2
AIN1/REF2+
AI
3
4
5
6
7
8
9
10
DNC
REGCAPA
AVSS
AVDD1
AVDD2
PDSW
XTAL1
XTAL2/CLKIO
AO
P
P
P
AO
AI
AI/DI
11
DOUT/RDY
DO
12
DIN
DI
13
SCLK
DI
Description
Analog Input 0/Reference 2 Negative Input Terminal. A reference can be applied between the REF2+ and
REF2− pins. REF2− can span from AVSS to AVDD1 − 1 V. Analog Input 0 is selectable through the crosspoint
multiplexer. Reference 2 can be selected through the REF_SELx bits in the setup configuration
(SETUPCONx) registers.
Analog Input 1/Reference 2 Positive Input Terminal. A reference can be applied between the REF2+ and
REF2− pins. REF2+ can span from AVDD1 to AVSS + 1 V. Analog Input 1 is selectable through the crosspoint
multiplexer. Reference 2 can be selected through the REF_SELx bits in the setup configuration
(SETUPCONx) registers.
Do Not Connect. Do not connect to this pin.
Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 μF capacitor.
Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V.
Analog Supply Voltage 1. This voltage ranges from 3.0 V minimum to 5.5 V maximum with respect to AVSS.
Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS.
Power-Down Switch Connected to AVSS. This pin is controlled by the PDSW bit in the GPIOCON register.
Input 1 for Crystal.
Input 2 for Crystal/Clock Input or Output. See the CLOCKSEL bit settings in the ADCMODE register in Table 28 for
more information.
Serial Data Output/Data Ready Output. DOUT/RDY is a dual purpose pin. This pin is a serial data output pin
to access the output shift register of the ADC. The output shift register can contain data from any of the
on-chip data or control registers. The data-word/control word information is placed on the DOUT/RDY pin
on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is
tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a data ready pin, going
low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes
high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor,
indicating that valid data is available.
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the
control registers in the ADC, with the register address (RA) bits of the communications register identifying
the appropriate register. Data is clocked in on the rising edge of SCLK.
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK pin has a
Schmitt triggered input, making the interface suitable for opto-isolated applications.
Rev. B | Page 9 of 61
AD7172-4
Data Sheet
Pin
No.
14
Mnemonic
CS
Type1
DI
15
ERROR
DI/O
16
SYNC
DI
17
IOVDD
P
18
19
DGND
REGCAPD
P
AO
20
GPIO0
I/O
21
GPIO1
I/O
22
23
24
25
26
27
28
29
30
31
GPO2
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GPO3
REF−
O
AI
AI
AI
AI
AI
AI
AI
O
AI
32
REF+
AI
EP
P
1
Description
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC
in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to operate
in 3-wire mode with the SCLK, DIN, and DOUT pins interfacing with the device. When CS is high, the
DOUT/RDY output is tristated.
This pin can be used in one of the following three modes:
Active low error input mode: this mode sets the ADC_ERROR bit in the status register.
Active low, open-drain error output mode: the status register error bits are mapped to the ERROR pin. The
ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any
device can be observed.
General-purpose output mode: the status of the pin is controlled by the ERR_DAT bit in the GPIOCON register.
The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the
GPIO0 and GPIO1 pins. The ERROR pin has an active pull-up in this case.
Synchronization Input. This pin allows synchronization of the digital filters and analog modulators when
using multiple AD7172-4 devices.
Digital Input/Output Supply Voltage. The IOVDD voltage ranges from 2 V to 5 V. IOVDD is independent of
AVDD1 and AVDD2. For example, IOVDD can be operated at 3.3 V when AVDD1 or AVDD2 equals 5 V, or
vice versa. If AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V.
Digital Ground.
Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using
a 1 μF capacitor.
General-Purpose Input/Output. 0 The logic input/output on this this pin is referred to the AVDD1 and AVSS
supplies.
General-Purpose Input/Output 1. The logic input/output on this this pin is referred to the AVDD1 and AVSS
supplies.
General-Purpose Output. The logic output on this this pin is referred to the AVDD1 and AVSS supplies.
Analog Input 2. Analog Input 2 is selectable through the crosspoint multiplexer.
Analog Input 3. Analog Input 3 is selectable through the crosspoint multiplexer.
Analog Input 4. Analog Input 4 is selectable through the crosspoint multiplexer.
Analog Input 5. Analog Input 5 is selectable through the crosspoint multiplexer.
Analog Input 6. Analog Input 6 is selectable through the crosspoint multiplexer.
Analog Input 7. Analog Input 7 is selectable through the crosspoint multiplexer.
Analog Input 8. Analog Input 8 is selectable through the crosspoint multiplexer.
General-Purpose Output. The logic output on this this pin is referred to the AVDD1 and AVSS supplies.
Reference 1 Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V. Reference 1 can be
selected through the REF_SELx bits in the setup configuration (SETUPCONx) registers.
Reference 1 Input Positive Terminal. A reference can be applied between REF+ and REF−. REF+ can span
from AVDD1 to AVSS + 1 V. Reference 1 can be selected through the REF_SELx bits in the setup
configuration (SETUPCONx) registers.
Exposed Pad. Solder the exposed pad to a similar pad on the printed circuit board (PCB) under the
exposed pad to confer mechanical strength to the package and for heat dissipation. The exposed pad must
be connected to AVSS through this pad on the PCB.
AI is analog input, AO is analog output, DI/O is bidirectional digital input/output, DO is digital output, DI is digital input, and P is power supply, I/O is input/output, and
O is output.
Rev. B | Page 10 of 61
Data Sheet
AD7172-4
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, TA = 25°C, unless otherwise noted.
1200
8388492
8388490
1000
8388488
OCCURENCE
8388486
8388484
600
400
8388482
200
8388480
0
200
400
600
800
1000
SAMPLE NUMBER
0
12676-205
8388478
12676-208
ADC CODE
800
8388480 8388482 8388484 8388486 8388488 8388490 8388492
ADC CODE
Figure 5. Noise (Analog Input Buffers Disabled, VREF = 5 V,
Output Data Rate = 1.25 SPS)
Figure 8. Histogram (Analog Input Buffers Disabled, VREF = 5 V,
Output Data Rate = 1.25 SPS)
140
8388510
8388505
120
8388500
100
OCCURENCE
ADC CODE
8388495
8388490
8388485
8388480
8388475
80
60
40
8388470
ADC CODE
Figure 6. Noise (Analog Input Buffers Disabled, VREF = 5 V,
Output Data Rate = 2.6 kSPS)
Figure 9. Histogram (Analog Input Buffers Disabled, VREF = 5 V,
Output Data Rate = 2.6 kSPS)
8388540
100
8388530
90
8388520
80
70
OCCURENCE
8388500
8388490
8388480
8388470
60
50
40
30
8388460
20
8388450
100
200
300
400
500
600
700
800
900
SAMPLE NUMBER
1000
0
ADC CODE
Figure 7. Noise (Analog Input Buffers Disabled, VREF = 5 V,
Output Data Rate = 31.25 kSPS)
Figure 10. Histogram (Analog Input Buffers Disabled, VREF = 5 V,
Output Data Rate = 31.25 kSPS)
Rev. B | Page 11 of 61
12676-210
0
8388446
8388449
8388452
8388455
8388458
8388461
8388464
8388467
8388470
8388473
8388476
8388479
8388482
8388485
8388488
8388491
8388494
8388497
8388500
8388503
8388506
8388509
8388512
8388515
8388518
8388521
8388524
8388527
8388530
8388533
10
12676-207
ADC CODE
8388510
8388440
12676-209
8388505
8388503
8388501
8388499
8388497
8388495
8388493
8388491
8388489
SAMPLE NUMBER
0
8388487
1000
8388485
900
8388483
800
8388481
700
8388479
600
8388477
500
8388475
400
8388473
300
8388471
200
8388469
100
8388467
0
12676-206
8388460
8388465
20
8388465
AD7172-4
Data Sheet
8388495
1200
8388493
1000
8388491
OCCURENCE
ADC CODE
800
8388489
8388487
600
400
8388485
400
600
800
1000
SAMPLE NUMBER
0
ADC CODE
Figure 14. Histogram (Analog Input Buffers Enabled, VREF = 5 V,
Output Data Rate = 1.25 SPS)
120
8388510
100
8388500
80
OCCURENCE
8388520
8388490
60
8388480
40
8388470
20
0
100
200
300
400
500
600
700
800
900
1000
SAMPLE NUMBER
0
12676-212
ADC CODE
Figure 11. Noise (Analog Input Buffers Enabled, VREF = 5 V,
Output Data Rate = 1.25 SPS)
8388460
8388482 8388484 8388486 8388488 8388490 8388492 8388494
ADC CODE
Figure 12. Noise (Analog Input Buffers Enabled, VREF = 5 V,
Output Data Rate = 2.6 kSPS)
12676-215
200
8388462
8388464
8388466
8388468
8388470
8388472
8388474
8388476
8388478
8388480
8388482
8388484
8388486
8388488
8388490
8388492
8388494
8388496
8388498
8388500
8388502
8388504
8388506
8388508
8388510
8388512
8388514
8388516
0
12676-211
8388481
12676-214
200
8388483
Figure 15. Histogram (Analog Input Buffers Enabled, VREF = 5 V,
Output Data Rate = 2.6 kSPS)
8388560
120
8388540
100
80
OCCURENCE
8388500
8388480
8388460
60
40
8388440
8388542
ADC CODE
Figure 13. Noise (Analog Input Buffers Enabled, VREF = 5 V,
Output Data Rate = 31.25 kSPS)
Figure 16. Histogram (Analog Input Buffers Enabled, VREF = 5 V,
Output Data Rate = 31.25 kSPS)
Rev. B | Page 12 of 61
12676-216
8388534
8388526
0
8388518
1000
8388510
900
8388502
800
8388494
700
8388486
600
8388478
500
8388470
400
SAMPLE NUMBER
8388462
300
8388454
200
8388446
100
8388438
0
8388430
8388400
8388422
20
8388420
12676-213
ADC CODE
8388520
Data Sheet
AD7172-4
0.000020
–60
ANALOG INPUT BUFFERS OFF
ANALOG INPUT BUFFERS ON
0.000018
–70
0.000016
–80
0.000012
PSRR (dB)
NOISE (µV rms)
0.000014
0.000010
0.000008
0.000006
–90
–100
–110
–120
0.000004
–130
–140
12676-218
0
1000 201000 401000 601000 80100010010001201000140100016010001801000
FREQUENCY (MHz)
10
–20
4
–40
2
INL (ppm/FS)
6
–60
–80
10k
100k
1M
10M
100M
CRYSTAL BUFFERS OFF
CRYSTAL BUFFERS ON
CLK BUFFERS OFF
CLK BUFFERS ON
2.5V REFERENCE,
ANALOG INPUT BUFFERS OFF
0
–2
–100
–4
–6
–5
10
100
1k
10k
100k
1M
VIN FREQUENCY (Hz)
Figure 18. Common-Mode Rejection Ratio (CMRR) vs. VIN Frequency
(VIN = 0.1 V, Output Data Rate = 31.25 kSPS)
–3
–2
–1
0
1
2
3
4
5
Figure 21. Integral Nonlinearity (INL) vs. VIN
(Differential Input)
0
35
–20
30
–40
25
–80
–100
20
15
–120
10
–140
5
–160
0
30
40
50
60
70
VIN FREQUENCY (Hz)
Figure 19. Common-Mode Rejection Ratio (CMRR) vs. VIN Frequency
(VIN = 0.1 V, 10 Hz to 70 Hz, Output Data Rate = 20 SPS, Enhanced Filter)
INL (ppm)
12676-225
20
0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25
12676-228
OCCURENCE
–60
–180
10
–4
VIN (V)
12676-224
1
2.5V REFERENCE, ANALOG INPUT BUFFERS ON
5V REFERENCE, ANALOG INPUT BUFFERS OFF
5V REFERENCE, ANALOG INPUT BUFFERS ON
12676-227
–120
CMRR (dB)
1k
Figure 20. Power Supply Rejection Ratio (PSRR) vs. VIN Frequency
0
–140
100
VIN FREQUENCY (Hz)
Figure 17. Noise vs. External Master Clock Frequency,
Analog Input Buffers On and Off
CMRR (dB)
1
12676-226
0.000002
Figure 22. INL Distribution Histogram (Differential Input, All Input Buffers
Enabled, VREF = 2.5 V External, 100 Units)
Rev. B | Page 13 of 61
AD7172-4
Data Sheet
40
5.0
AIN BUFFERS ON
AIN BUFFERS OFF
4.5
35
4.0
30
INL (ppm)
OCCURENCE
3.5
25
20
15
3.0
2.5
2.0
1.5
10
1.0
5
0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00
INL (ppm)
0
–40 –30 –20 –10 0
Figure 23. INL Distribution Histogram (Differential Input, All Input Buffers
Disabled, VREF = 2.5 V External, 100 Units)
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
12676-232
0.5
12676-229
0
Figure 26. INL vs. Temperature (Differential Input, VREF = 2.5 V External)
50
35
45
30
40
25
OCCURENCE
OCCURENCE
35
30
25
20
15
20
15
10
10
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
INL (ppm)
0
12676-230
0
Figure 24. INL Distribution Histogram (All Input Buffers Enabled, Differential
Input, VREF = 5 V External, 100 Units)
1.996
1.997
1.998
1.999
2.00
2.001
2.002
2.003
FREQUENCY (MHz)
12676-233
5
5
Figure 27. Internal Oscillator Frequency/Accuracy Distribution Histogram
(100 Units)
40
2.01
35
2.00
FREQUENCY (Hz)
OCCURENCE
30
25
20
15
1.99
1.98
1.97
10
0
0.2
0.4
0.6
0.8
INL (ppm)
1.0
1.2
1.4
12676-231
0
Figure 25. INL Distribution Histogram (All Input Buffers Disabled, Differential
Input, VREF = 5 V External, 100 Units)
Rev. B | Page 14 of 61
1.95
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
Figure 28. Internal Oscillator Frequency vs. Temperature
12676-234
1.96
5
Data Sheet
AD7172-4
30
25
25
20
OCCURENCE
OCCURENCE
20
15
15
10
10
0
10
20
30
40
50
60
70
OFFSET (µV)
0
–7
30
10
25
OCCURENCE
12
2
5
OFFSET DRIFT (nV/°C)
–2
–1
0
1
2
3
4
5
6
15
10
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110
–3
20
4
0
12676-237
OCCURENCE
35
0
–4
Figure 32. Gain Error Distribution Histogram
(All Input Buffers Disabled, 100 Units)
14
6
–5
GAIN ERROR (ppm of FSR)
Figure 29. Offset Error Distribution Histogram (Internal Short, 100 Units)
8
–6
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
GAIN DRIFT (ppm/°C)
Figure 30. Offset Error Drift Distribution Histogram (Internal Short, 100 Units)
12676-240
–50 –40 –30 –20 –10
12676-236
0
12676-239
5
5
Figure 33. Gain Drift Distribution Histogram
(All Input Buffers Enabled, 100 Units)
25
30
25
20
OCCURENCE
10
15
10
5
–8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
GAIN ERROR (ppm of FSR)
5
6
Figure 31. Gain Error Distribution Histogram
(All Input Buffers Enabled, 100 Units)
0
–0.05
0
0.05
0.10
0.15
0.20
GAIN DRIFT (ppm/°C)
Figure 34. Gain Drift Distribution Histogram
(All Input Buffers Disabled, 100 Units)
Rev. B | Page 15 of 61
0.25
12676-241
0
5
12676-238
OCCURENCE
20
15
AD7172-4
Data Sheet
700
10
–40°C, AIN–
–40°C, AIN+
+25°C, AIN–
+25°C, AIN+
+85°C, AIN–
+85°C, AIN+
+105°C, AIN–
600
5
INPUT CURRENT (nA)
CURRENT (µA)
500
400
300
200
0
–5
TEMPERATURE (°C)
–10
INPUT VOLTAGE (V)
Figure 37. Analog Input Current vs. Input Voltage
(VCM = 2.5 V)
Figure 35. Current Consumption vs. Temperature (Standby Mode)
45
15
AIN+ = AVDD1 – 0.2V
AIN– = AVSS + 0.2V
AIN+ = AVDD1
AIN– = AVSS
40
10
35
CURRENT (nA)
30
25
20
15
5
0
–5
10
–10
0
9.5
9.6
9.7
9.8
9.9
10.0 10.1 10.2 10.3 10.4 10.5
CURRENT (µA)
Figure 36. Burnout Current Distribution Histogram
(100 Units)
–15
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
Figure 38. Analog Input Current vs. Temperature
Rev. B | Page 16 of 61
12676-247
5
12676-245
OCCURENCE
12676-246
10 20 30 40 50 60 70 80 90 100
12676-243
0
–40 –30 –20 –10 0
–5.00
–4.62
–4.29
–3.96
–3.63
–3.30
–2.97
–2.64
–2.31
–1.98
–1.65
–1.32
–990.00m
–660.00m
–330.00m
0
330.00m
660.00m
990.00m
1.32
1.65
1.98
2.31
2.64
2.97
3.30
3.63
3.96
4.29
4.62
5.00
100
Data Sheet
AD7172-4
NOISE PERFORMANCE AND RESOLUTION
Table 6 and Table 7 show the rms noise, peak-to-peak noise,
effective resolution, and the noise free (peak-to-peak) resolution
of the AD7172-4 for various output data rates and filters. The
numbers given are for the bipolar input range with a 5 V
reference. These numbers are typical and are generated with a
differential input voltage of 0 V when the ADC is continuously
converting on a single channel. It is important to note that the
peak-to-peak resolution is calculated based on the peak-to-peak
noise. The peak-to-peak resolution represents the resolution for
which there is no code flicker.
Table 6. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate Using the Sinc5 + Sinc1 Filter (Default)1
Output Data Rate (SPS)
Input Buffers Disabled
31,250
15,625
10,417
1007
59.52
49.68
16.63
1.25
Input Buffers Enabled
31,250
15,625
10,417
1007
59.52
49.68
16.63
1.25
1
RMS Noise (μV rms)
Effective Resolution (Bits)
Peak-to-Peak Noise (μV p-p)
Peak-to-Peak Resolution (Bits)
8.2
7.0
6.0
2.2
0.48
0.47
0.25
0.088
20.2
20.4
20.7
22.2
24
24
24
24
66
52
45
15
3.2
3.1
1.6
0.32
17.2
17.5
17.8
19.3
21.6
21.6
22.6
24
9.5
8.2
7.1
2.6
0.62
0.53
0.32
0.089
20
20.2
20.4
21.9
24
24
24
24
74
63
53
16
3.6
3.3
1.7
0.35
17
17.3
17.5
19.3
21.4
21.5
22.2
24
Selected rates only, 1000 samples.
Table 7. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate Using the Sinc3 Filter1
Output Data Rate (SPS)
Input Buffers Disabled
31,250
15,625
10,417
1008
59.98
50
16.67
1.25
Input Buffers Enabled
31,250
15,625
10,417
1008
59.98
50
16.67
1.25
1
RMS Noise (μV rms)
Effective Resolution (Bits)
Peak-to-Peak Noise (μV p-p)
Peak-to-Peak Resolution (Bits)
211
27.2
7.9
1.6
0.38
0.35
0.21
0.054
15.5
18.5
20.3
22.6
24
24
24
24
1600
205
57
11
2.5
2.3
1.1
0.27
12.5
15.6
17.4
19.8
21.9
22
23.1
24
212
27.7
8.5
1.8
0.45
0.44
0.24
0.073
15.5
18.5
20.2
22.4
24
24
24
24
1600
210
63
13
2.8
2.5
1.2
0.29
12.5
15.5
17.3
19.6
21.8
22
23
24
Selected rates only, 1000 samples.
Rev. B | Page 17 of 61
AD7172-4
Data Sheet
GETTING STARTED
The AD7172-4 offers the user a fast settling, high resolution,
multiplexed ADC with high levels of configurability, including
the following features:
Four fully differential or eight single-ended analog inputs.
A crosspoint multiplexer that selects any analog input
combination as the input signals to be converted, routing
them to the modulator positive or negative input.
True rail-to-rail buffered analog and reference inputs.
Fully differential inputs or single-ended inputs relative to
any analog input.
Per channel configurability—up to eight different setups
can be defined. A separate setup can be mapped to each of
the channels. Each setup allows the user to configure
whether the buffers are enabled or disabled, gain and offset
correction, filter type, output data rate, and reference
source selection.
16MHz
CX2
CX1
SEE THE BUFFERED ANALOG INPUT SECTION
FOR FURTHER DETAILS.
OPTIONAL EXTERNAL
CRYSTAL CIRCUITRY
CAPACITORS
XTAL1 9
1
AIN0/REF2–
XTAL2/CLKIO 10
DOUT/RDY 11
2
DOUT/RDY
AIN1/REF2+
DIN
DIN 12
SCLK
SCLK 13
27 AIN6
CS
CS 14
ERROR
ERROR 15
28 AIN7
SYNC
SYNC 16
AD7172-4
29 AIN8
CLKIN
OPTIONAL
EXTERNAL
CLOCK
INPUT
IOVDD
IOVDD 17
0.1µF
DGND 18
VIN
1
2
4.7µF
0.1µF
VIN
3
REGCAPD 19
NC 7
0.1µF
ADR44xBRZ
4 GND
5
AVDD1
AVDD1 6
VOUT 6
8
1µF
0.1µF
32 REF+
0.1µF
4.7µF
0.1µF
AVDD2
AVDD2 7
31 REF–
0.1µF
REGCAPA 4
AVSS
5
Figure 39. Typical Connection Diagram
Rev. B | Page 18 of 61
0.1µF
1µF
12676-040
The AD7172-4 includes two separate linear regulator blocks for
both the analog and digital circuitry. The analog LDO regulator
regulates the AVDD2 supply to 1.8 V, supplying the ADC core.
Tie the AVDD1 and AVDD2 supplies together for the easiest
connection. If there is already a clean analog supply rail in the
system in the range of 2 V (minimum) to 5.5 V (maximum), the
user can choose to connect this supply to the AVDD2 input,
allowing lower power dissipation.
Data Sheet
AD7172-4
The ADM660 and ADP7182 generate a clean negative rail for
AVSS in the bipolar configuration to provide optimal converter
performance.
5V
INPUT
POWER SUPPLIES
The AD7172-4 has three independent power supply pins: AVDD1,
AVDD2, and IOVDD. AVDD1 powers the crosspoint multiplexer
and integrated analog and reference input buffers. AVDD1 is
referenced to AVSS, and AVDD1 − AVSS = 3.3 V or 5 V.
AVDD1 and AVSS can be a single 3.3 V or 5 V supply, or a
±1.65 V or ±2.5 V split supply. The split supply operation allows
true bipolar inputs. When using split supplies, consider the
absolute maximum ratings (see the Absolute Maximum Ratings
section).
AVDD2 powers the internal 1.8 V analog LDO regulator. This
regulator powers the ADC core. AVDD2 is referenced to AVSS,
and AVDD2 to AVSS can range from 5.5 V (maximum) to 2 V
(minimum).
ADP7118
+3.3V: IOVDD
ADM660
LDO
–5V
ADP7182
–2.5V: AVSS
LDO
Figure 41. Bipolar AD7172-4 Supply Rails
Table 8. Recommended Power Management Devices
Product
ADP7118
ADP7182
ADM660
Description
20 V, 200 mA, low noise, CMOS LDO regulator
−28 V, −200 mA, low noise, linear regulator
CMOS switched capacitor voltage converter
DIGITAL COMMUNICATION
The AD7172-4 has a 3- or 4-wire SPI interface that is compatible
with QSPI™, MICROWIRE, and DSPs. The interface operates in
SPI Mode 3 and can be operated with CS tied low. In SPI Mode 3,
the SCLK pin idles high, the falling edge of SCLK is the drive
edge, and the rising edge of SCLK is the sample edge. This
means that data is clocked out on the falling/drive edge and data
is clocked in on the rising/sample edge.
DRIVE EDGE
SAMPLE EDGE
12676-052
Fast scanning of analog input channels using the internal
multiplexer
Fast scanning of analog input channels using an external
multiplexer with automatic control from the GPIOs
High resolution at lower speeds in either channel scanning
or ADC per channel applications
Single ADC per channel: the fast low latency output allows
further application specific filtering in external microcontrollers, DSPs, or FPGAs
+2.5V: AVDD1/AVDD2
LDO
LDO
The AD7172-4 can be used across a wide variety of applications,
providing high resolution and accuracy. A sample of these
scenarios is as follows:
ADP7118
12676-101
The linear regulator for the digital IOVDD supply performs a
similar function, regulating the input voltage applied at the
IOVDD pin to 1.8 V for the internal digital filtering. The serial
interface signals always operate from the IOVDD supply at the
pin; meaning, if 3.3 V is applied to the IOVDD pin, the
interface logic inputs and outputs operate at this level.
Figure 42. SPI Mode 3 SCLK Edges
Accessing the ADC Register Map
IOVDD powers the internal 1.8 V digital LDO regulator. This
regulator powers the digital logic of the ADC. IOVDD sets the
voltage levels for the SPI interface of the ADC. IOVDD is referenced to DGND, and IOVDD to DGND can vary from 5.5 V
(maximum) to 2 V (minimum).
The communications register controls access to the full register
map of the ADC. This register is an 8-bit write only register. On
power-up or after a reset, the digital interface defaults to a state
where it is expecting a write to the communications register;
therefore, all communication begins by writing to the
communications register.
There are no specific requirements for a power supply sequence
on the AD7172-4. When all power supplies are stable, a device
reset is required; see the AD7172-4 Reset section for how to
reset the device.
The data written to the communications register determines
which register is being accessed and if the next operation is a read
or write. The RA bits (Bits[5:0] in Register 0x00) determine the
specific register to which the read or write operation applies.
Recommended Linear Regulators
When the read or write operation to the selected register is
complete, the interface returns to its default state, where it
expects a write operation to the communications register.
12V
INPUT
ADP7118
5V: AVDD1
ADP7118
3.3V: AVDD2/IOVDD
LDO
LDO
12676-100
The ADP7118 provides the positive supply rails, creating either
a single 5 V or 3.3 V, or dual AVDD1/IOVDD, depending on
the required supply configuration. The ADP7118 can operate
from input voltages up to 20 V.
Figure 40. Single Supply Linear Regulator
Rev. B | Page 19 of 61
AD7172-4
Data Sheet
Figure 43 and Figure 44 illustrate writing to and reading from a
register by first writing the 8-bit command to the communications
register, followed by the data for that register.
8-BIT COMMAND
8 BITS, 16 BITS,
OR 24 BITS OF DATA
COMMAND
DATA
CONFIGURATION OVERVIEW
After power-on or reset, the AD7172-4 default configuration is
as follows:
CS
DIN
12676-053
SCLK
Figure 43. Writing to a Register
(8-Bit Command with Register Address Followed by Data 8, 16, or 24 Bits; Data
Length on DIN Is Dependent on the Register Selected)
8-BIT COMMAND
Channel configuration. CH0 is enabled, AIN0 is selected
as the positive input, and AIN1 is selected as the negative
input. Setup 0 is selected.
Setup configuration. The analog input buffers are disabled
and the reference input buffers are also disabled. The REF±
pins are selected as the reference source.
Filter configuration. The sinc5 + sinc1 filter is selected and
the maximum output data rate of 31.25 kSPS is selected.
ADC mode. Continuous conversion mode and the internal
oscillator are enabled.
Interface mode. CRC and data + status output are disabled.
Note that only a few of the register setting options are shown;
this list is just an example. For full register information, see the
Register Details section.
8 BITS, 16 BITS,
OR 24 BITS OUTPUT
CS
Figure 45 shows an overview of the suggested flow for changing
the ADC configuration, divided into the following three blocks:
DIN
DOUT/RDY
COMMAND
DATA
Channel configuration (see Box A in Figure 45)
Setup configuration (see Box B in Figure 45)
ADC mode and interface mode configuration (see Box C
in Figure 45)
Channel Configuration
12676-054
SCLK
Figure 44. Reading from a Register
(8-Bit Command with Register Address Followed by Data of 8, 16, 24 Bits;
Data Length on DOUT/RDY Is Dependent on the Register Selected)
Reading the ID register is the recommended method for verifying
correct communication with the device. The ID register is a
read only register and contains the value 0x205X for the
AD7172-4. The communications register and the ID register
details are described in Table 9 and Table 10.
AD7172-4 RESET
After a power-up cycle and when the power supplies are stable,
a device reset is required. In situations where interface synchronization is lost, a device reset is also required. A write operation
of at least 64 serial clock cycles with DIN high returns the ADC to
its default state by resetting the entire device, including the register
contents. Alternatively, if CS is being used with the digital interface,
returning CS high sets the digital interface to its default state and
halts any serial interface operation.
The AD7172-4 has eight independent channels and eight
independent setups. The user can select any of the analog input
pairs on any channel, as well as any of the eight setups for any
channel, giving the user full flexibility in the channel configuration.
This also allows per channel configuration when using
differential inputs and single-ended inputs because each
channel can have its own dedicated setup.
Channel Registers
The channel registers select which of the nine analog input pins
(AIN0 to AIN8) are used as either the positive analog input
(AIN+) or the negative analog input (AIN−) for that channel.
This register also contains a channel enable/disable bit and the
setup selection bits, which are used to select which of the eight
available setups to use for this setup channel.
When the AD7172-4 is operating with more than one channel
enabled, the channel sequencer cycles through the enabled
channels in sequential order, from Channel 0 to Channel 7. If a
channel is disabled, it is skipped by the sequencer. Details of the
channel register for Channel 0 are shown in Table 11.
Rev. B | Page 20 of 61
AD7172-4
A
CHANNEL CONFIGURATION
SELECT POSITIVE AND NEGATIVE INPUT FOR EACH ADC CHANNEL
SELECT ONE OF 8 SETUPS FOR ADC CHANNEL
B
SETUP CONFIGURATION
8 POSSIBLE ADC SETUPS
SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE
C
ADC MODE AND INTERFACE MODE CONFIGURATION
SELECT ADC OPERATING MODE, CLOCK SOURCE,
ENABLE CRC, DATA + STATUS, AND MORE
12676-044
Data Sheet
Figure 45. Suggested ADC Configuration Flow
Table 9. Communications Register
Reg.
0x00
Name
COMMS
Bits
[7:0]
Bit 7
WEN
Bit 6
R/W
Bit 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0x00
RW
W
Bit 2
Bit 1
Bit 0
Reset
0x205X
RW
R
Bit 1
Bit 0
AINPOS0[4:3]
Reset
0x8001
RW
RW
RA
Table 10. ID Register
Reg.
0x07
Name
ID
Bits
[15:8]
[7:0]
Bit 4
Bit 3
ID[15:8]
ID[7:0]
Bit 5
Bit 4
SETUP_SEL0
AINPOS0[2:0]
Bit 3
Table 11. Channel Register 0
Reg.
0x10
Name
CH0
Bits
[15:8]
[7:0]
Bit 7
CH_EN0
Bit 6
Rev. B | Page 21 of 61
Bit 2
Reserved
AINNEG0
AD7172-4
Data Sheet
ADC Setups
Setup Configuration Registers
The AD7172-4 has eight independent setups. Each setup
consists of the following four registers:
The setup configuration registers allow the user to select the output
coding of the ADC by selecting between bipolar mode and
unipolar mode. In bipolar mode, the ADC accepts negative
differential input voltages, and the output coding is offset binary. In
unipolar mode, the ADC accepts only positive differential voltages,
and the coding is straight binary. In either case, the input voltage
must be within the AVDD1/AVSS supply voltages. The user can
select the reference source using these registers. Three options are
available: a reference connected between the REF+ and REF− pins,
between REF2+ and REF2− pins , or using AVDD1 − AVSS.
The analog input and reference input buffers can also be
enabled or disabled using these registers.
Setup configuration register
Filter configuration register
Gain register
Offset register
For example, Setup 0 consists of Setup Configuration Register 0,
Filter Configuration Register 0, Gain Register 0, and Offset
Register 0. Figure 46 shows the grouping of these registers The
setup is selectable from the channel registers (see the Channel
Configuration section), which allows each channel to be
assigned to one of eight separate setups. Table 12 through Table 15
show the four registers that are associated with Setup 0. This
structure is repeated for Setup 1 to Setup 7.
SETUP CONFIG
REGISTERS
Filter Configuration Registers
The filter configuration registers select which digital filter is
used at the output of the ADC modulator. The order of the filter
and the output data rate are selected by setting the bits in these
registers. For more information, see the Digital Filters section.
FILTER CONFIG
REGISTERS
GAIN REGISTERS*
OFFSET REGISTERS
SETUPCON0 0x20
FILTCON0 0x28
GAIN0
0x38
OFFSET0 0x30
SETUPCON1 0x21
FILTCON1 0x29
GAIN1
0x39
OFFSET1 0x31
SETUPCON2 0x22
FILTCON2 0x2A
GAIN2
0x3A
OFFSET2 0x32
SETUPCON3 0x23
FILTCON3 0x2B
GAIN3
0x3B
OFFSET3 0x33
SETUPCON4 0x24
FILTCON4 0x2C
GAIN4
0x3C
OFFSET4 0x34
SETUPCON5 0x25
FILTCON5 0x2D
GAIN5
0x3D
OFFSET5 0x35
SETUPCON6 0x26
FILTCON6 0x2E
GAIN6
0x3E
OFFSET6 0x36
SETUPCON7 0x27
FILTCON7 0x2F
GAIN7
0x3F
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
ANALOG INPUT BUFFERS
REFERENCE INPUT BUFFERS
BURNOUT
REFERENCE SOURCE
31.25kSPS TO 1.25SPS
SINC5 + SINC1
SINC3
SINC3 MAP
ENHANCED 50/60
GAIN CORRECTION
OPTIONALLY
PROGRAMMED
PER SETUP AS REQUIRED
(*FACTORY CALIBRATED)
OFFSET7 0x37
OFFSET CORRECTION
OPTIONALLY PROGRAMMED
PER SETUP AS REQUIRED
12676-045
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
Figure 46. ADC Setup Register Grouping
Table 12. Setup Configuration Register 0
Reg.
0x20
Name
Bits
Bit 7
Bit 6
SETUPCON0 [15:8]
Reserved
[7:0]
BURNOUT_EN0 Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
BI_UNIPOLAR0 REFBUF0+ REFBUF0− AINBUF0+ AINBUF0− 0x1000
REF_SEL0
Reserved
RW
RW
Table 13. Filter Configuration Register 0
Reg.
0x28
Name
FILTCON0
Bits
Bit 7
[15:8] SINC3_MAP0
[7:0] Reserved
Bit 6
Bit 5
Bit 4
Reserved
ORDER0
Bit 3
Bit 2
ENHFILTEN0
ODR0
Bit 1
Bit 0
ENHFILT0
Reset
0x0500
RW
RW
Table 14. Gain Register 0
Reg.
0x38
Name
GAIN0
Bits
[23:0]
Bits[23:0]
GAIN0[23:0]
Reset
RW
0x5XXXX0 RW
Bits[23:0]
OFFSET0[23:0]
Reset
RW
0x800000 RW
Table 15. Offset Register 0
Reg.
0x30
Name
OFFSET0
Bits
[23:0]
Rev. B | Page 22 of 61
Data Sheet
AD7172-4
Gain Registers
ADC Mode and Interface Mode Configuration
The gain registers are 24-bit registers that hold the gain
calibration coefficient for the ADC. The gain registers are
read/write registers. These registers are configured at power-on
with factory calibrated coefficients. Therefore, every device has
different default coefficients. The default value is automatically
overwritten if the user initiates a system full-scale calibration or
writes to a gain register. For more information on calibration,
see the Operating Modes section.
The ADC mode register and the interface mode register configure
the core peripherals for use by the AD7172-4 and the mode for
the digital interface.
ADC Mode Register
The ADC mode register primarily sets the conversion mode of
the ADC to either continuous or single conversion. The user
can also select the standby and power-down modes, as well as
any of the calibration modes. In addition, this register contains
the clock source select bits The reference select bits are
contained in the setup configuration registers (see the ADC
Setups section for more information). The details of this register
are shown in Table 16.
Offset Registers
The offset registers hold the offset calibration coefficient for the
ADC. The power-on reset value of the offset registers is 0x800000.
The offset registers are 24-bit read/write registers. The power-on
reset value is automatically overwritten if the user initiates an
internal or system zero-scale calibration or if the user writes to an
offset register.
Interface Mode Register
The interface mode register configures the digital interface
operation. This register allows the user to control data-word
length, CRC enable, data plus status read, and continuous read
mode. The details of this register are shown in Table 17. For more
information, see the Digital Interface section.
Table 16. ADC Mode Register
Reg.
0x01
Name
ADCMODE
Bits
[15:8]
[7:0]
Bit 7
Reserved
Reserved
Bit 6
HIDE_DELAY
Bit 5
SING_CYC
Mode
Bit 4
Bit 3
Reserved
Bit 2
CLOCKSEL
Bit 1
Bit 0
Delay
Reserved
Reset
0x2000
RW
RW
Reset
0x0000
RW
RW
Table 17. Interface Mode Register
Reg.
0x02
Name
IFMODE
Bits
[15:8]
[7:0]
Bit 7
CONTREAD
Bit 6
Reserved
DATA_STAT
Bit 5
REG_CHECK
Bit 4
ALT_SYNC
Reserved
Bit 3
Bit 2
Bit 1
IOSTRENGTH
Reserved
CRC_EN
Reserved
Rev. B | Page 23 of 61
Bit 0
DOUT_RESET
WL16
AD7172-4
Data Sheet
Understanding Configuration Flexibility
The most straightforward implementation of the AD7172-4 is
to use four differential inputs with adjacent analog inputs and
run all of them with the same setup, gain correction, and offset
correction registers. In this case, the user selects the following
differential inputs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, and
AIN6/AIN7. In Figure 47, the registers shown in black font
must be programmed for such a configuration. The registers
that are shown in gray font are redundant in this configuration.
An alternative way to implement these four fully differential
inputs is to take advantage of four of the eight available setups.
Motivation for doing this includes having a different speed/noise
requirement on each of the differential inputs, or a specific
offset or gain correction may be needed for each channel. Figure 48
shows how each of the differential inputs can use a separate
setup, allowing full flexibility in the configuration of each channel.
Programming the gain and offset registers is optional for any
use case, as indicated by the dashed lines between the register
blocks.
CHANNEL
REGISTERS
CH0
AIN1
CH1
AIN2
CH2
AIN3
CH3
AIN4
AIN5
AIN6
AIN7
CH4
CH5
CH6
CH7
FILTER CONFIG
REGISTERS
GAIN REGISTERS*
0x10
SETUPCON0 0x20
FILTCON0 0x28
GAIN0
0x11
SETUPCON1 0x21
FILTCON1 0x29
0x12
SETUPCON2 0x22
FILTCON2 0x2A
0x13
SETUPCON3 0x23
OFFSET REGISTERS
0x38
OFFSET0 0x30
GAIN1
0x39
OFFSET1 0x31
GAIN2
0x3A
OFFSET2 0x32
FILTCON3 0x2B
GAIN3
0x3B
OFFSET3 0x33
0x14
SETUPCON4 0x24
FILTCON4 0x2C
GAIN4
0x3C
OFFSET4 0x34
0x15
SETUPCON5 0x25
FILTCON5 0x2D
GAIN5
0x3D
OFFSET5 0x35
0x16
SETUPCON6 0x26
FILTCON6 0x2E
GAIN6
0x3E
OFFSET6 0x36
0x17
SETUPCON7 0x27
FILTCON7 0x2F
GAIN7
0x3F
OFFSET7 0x37
AIN8
SELECT ANALOG INPUT PARTS
ENABLE THE CHANNEL
SELECT SETUP 0
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
ANALOG INPUT BUFFERS
REFERENCE INPUT BUFFERS
BURNOUT
REFERENCE SOURCE
31.25kSPS TO 1.25SPS
SINC5 + SINC1
SINC3
GAIN CORRECTION
OFFSET CORRECTION
OPTIONALLY
OPTIONALLY PROGRAMMED
PROGRAMMED
PER SETUP AS REQUIRED
PER SETUP AS REQUIRED
(*FACTORY CALIBRATED)
12676-046
AIN0
SETUP CONFIG
REGISTERS
SINC3 MAP
ENHANCED 50/60
Figure 47. Four Fully Differential Inputs, Using a Single Setup (SETUPCON0, FILTCON0, GAIN0, OFFSET0)
AIN0
CH0
AIN1
CH1
AIN2
CH2
AIN3
CH3
AIN4
AIN5
AIN6
AIN7
CH4
CH5
CH6
CH7
SETUP CONFIG
REGISTERS
FILTER CONFIG
REGISTERS
GAIN REGISTERS*
0x10
SETUPCON0 0x20
FILTCON0 0x28
GAIN0
0x11
SETUPCON1 0x21
FILTCON1 0x29
0x12
SETUPCON2 0x22
FILTCON2 0x2A
0x13
SETUPCON3 0x23
OFFSET REGISTERS
0x38
OFFSET0 0x30
GAIN1
0x39
OFFSET1 0x31
GAIN2
0x3A
OFFSET2 0x32
FILTCON3 0x2B
GAIN3
0x3B
OFFSET3 0x33
0x14
SETUPCON4 0x24
FILTCON4 0x2C
GAIN4
0x3C
OFFSET4 0x34
0x15
SETUPCON5 0x25
FILTCON5 0x2D
GAIN5
0x3D
OFFSET5 0x35
0x16
SETUPCON6 0x26
FILTCON6 0x2E
GAIN6
0x3E
OFFSET6 0x36
0x17
SETUPCON7 0x27
FILTCON7 0x2F
GAIN7
0x3F
OFFSET7 0x37
AIN8
SELECT ANALOG INPUT PARTS
ENABLE THE CHANNEL
SELECT SETUP 0
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
ANALOG INPUT BUFFERS
REFERENCE INPUT BUFFERS
BURNOUT
REFERENCE SOURCE
31.25kSPS TO 1.25SPS
SINC5 + SINC1
SINC3
GAIN CORRECTION
OFFSET CORRECTION
OPTIONALLY
OPTIONALLY PROGRAMMED
PROGRAMMED
PER SETUP AS REQUIRED
PER SETUP AS REQUIRED
(*FACTORY CALIBRATED)
SINC3 MAP
ENHANCED 50/60
Figure 48. Four Fully Differential Inputs with One Setup per Channel
Rev. B | Page 24 of 61
12676-047
CHANNEL
REGISTERS
Data Sheet
AD7172-4
CHANNEL
REGISTERS
SETUP CONFIG
REGISTERS
are programmed as required. Optional gain and offset
correction can be employed on a per setup basis by
programming GAIN0 and GAIN1 and OFFSET0 and
OFFSET1.
In the example shown in Figure 49, the CH0 to CH4 registers
are used. Setting the MSB in each of these registers, the CH_EN0
to CH_EN4 bits enable the five combinations via the crosspoint
mux. When the AD7172-4 converts, the sequencer transitions
in ascending sequential order from CH0 through CH4 before
looping back to CH0 to repeat the sequence.
FILTER CONFIG
REGISTERS
GAIN REGISTERS*
AIN0
CH0
0x10
SETUPCON0 0x20
FILTCON0 0x28
GAIN0
AIN1
CH1
0x11
SETUPCON1 0x21
FILTCON1 0x29
AIN2
CH2
0x12
SETUPCON2 0x22
FILTCON2 0x2A
AIN3
CH3
0x13
SETUPCON3 0x23
AIN4
CH4
0x14
AIN5
CH5
AIN6
AIN7
OFFSET REGISTERS
0x38
OFFSET0 0x30
GAIN1
0x39
OFFSET1 0x31
GAIN2
0x3A
OFFSET2 0x32
FILTCON3 0x2B
GAIN3
0x3B
OFFSET3 0x33
SETUPCON4 0x24
FILTCON4 0x2C
GAIN4
0x3C
OFFSET4 0x34
0x15
SETUPCON5 0x25
FILTCON5 0x2D
GAIN5
0x3D
OFFSET5 0x35
CH6
0x16
SETUPCON6 0x26
FILTCON6 0x2E
GAIN6
0x3E
OFFSET6 0x36
CH7
0x17
SETUPCON7 0x27
FILTCON7 0x2F
GAIN7
0x3F
OFFSET7 0x37
AIN8
SELECT ANALOG INPUT PARTS
ENABLE THE CHANNEL
SELECT SETUP 0
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
ANALOG INPUT BUFFERS
REFERENCE INPUT BUFFERS
BURNOUT
REFERENCE SOURCE
31.25kSPS TO 1.25SPS
SINC5 + SINC1
SINC3
GAIN CORRECTION
OFFSET CORRECTION
OPTIONALLY
OPTIONALLY PROGRAMMED
PROGRAMMED
PER SETUP AS REQUIRED
PER SETUP AS REQUIRED
(*FACTORY CALIBRATED)
SINC3 MAP
ENHANCED 50/60
Figure 49. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups
Rev. B | Page 25 of 61
12676-048
Figure 49 shows an example of how the channel registers span
between the analog input pins and the setup configurations
downstream. In this example, three differential inputs and two
single-ended inputs are required. The single-ended inputs are the
AIN4/AIN8 and AIN7/AIN8 combinations. The differential input
pairs are AIN0/AIN1 and AIN2/AIN3, both using Setup 0, and
AIN5/AIN6 using Setup 2. The two single-ended input pairs are
set up as diagnostics, and in this example use separate setups,
namely Setup 1 and Setup 4. Given that five setups are selected
for use, the SETUPCON0 to SETUPCON4 registers are programmed as required, and the FILTCON0 to FILTCON4 registers
AD7172-4
Data Sheet
CIRCUIT DESCRIPTION
AVDD1
BUFFERED ANALOG INPUT
The AD7172-4 has true rail-to-rail, integrated, precision unitygain buffers on both ADC analog inputs. The buffers provide
high input impedance with only 5.5 nA typical input current,
allowing high impedance sources to be connected directly to
the analog inputs. The buffers fully drive the internal ADC
switch capacitor sampling network, simplifying the analog
front-end circuit requirements while consuming a very efficient
0.38 mA typical per buffer. Each analog input buffer amplifier is
fully chopped, meaning that it minimizes the offset error drift
and 1/f noise of the buffer. The 1/f noise profile of the ADC and
buffer combined is shown in Figure 50.
AIN0
AVSS
AVDD1
+IN
AIN1
Ø1
CS1
AVSS
Ø2
AVDD1
Ø2
AIN2
CS2
AVSS
–IN
AVDD1
Ø1
AIN3
0
AVSS
AVDD1
–50
–100
12676-056
AMPLITUDE (dB)
AIN4
AVSS
Figure 51. Simplified Analog Input Circuit
–150
The CS1 and CS2 capacitors have a magnitude in the order of a
number of picofarads each. This capacitance is the combination
of both the sampling capacitance and the parasitic capacitance.
–200
1
10
100
FREQUENCY (Hz)
1k
10k
12676-255
Fully Differential Inputs
–250
0.1
Figure 50. Shorted Input Fast Fourier Transform (FFT), Analog Input
Buffers Enabled
The analog input buffers do not suffer from linearity degradation
when operating at the rails, unlike many discrete amplifiers.
When operating at or close to the AVDD1 and AVSS supply
rails, there is an increase in input current. This increase is most
notable at higher temperatures. Figure 37 and Figure 38 show
the input current for various conditions. With the analog input
buffers disabled, the average input current to the AD7172-4
changes linearly with the differential input voltage at a rate of
6 μA/V.
CROSSPOINT MULTIPLEXER
There are nine analog input pins: AIN0 to AIN8. Each of these
pins connects to the internal crosspoint multiplexer. The
crosspoint multiplexer enables any of these inputs to be configured
as an input pair, either single-ended or fully differential. The
AD7172-4 can have up to eight active channels. When more than
one channel is enabled, the channels are automatically sequenced
in order from the lowest enabled channel number to the highest
enabled channel number. The output of the multiplexer is
connected to the input of the integrated true rail-to-rail buffers.
These buffers can be bypassed and the multiplexer output can
be directly connected to the switched capacitor input of the ADC.
The simplified analog input circuit is shown in Figure 51.
Because the AIN0 to AIN8 analog inputs are connected to a
crosspoint multiplexer, any combination of signals can create an
analog input pair. This allows the user to select four fully
differential inputs or eight single-ended inputs.
If four fully differential input paths are connected to the
AD7172-4, using adjacent analog inputs for the differential input
pair, such as AIN2/AIN3, is recommended. This is due to the
relative locations of these pins to each other. Decouple all analog
inputs to AVSS.
Single-Ended Inputs
The user can also choose to measure eight different singleended analog inputs. In this case, each of the analog inputs is
converted as the difference between the single-ended input to be
measured and a set analog input common pin. Because there is
a crosspoint multiplexer, the user can set any of the analog inputs
as the common pin. An example of such a scenario is to connect
the AIN4 pin to AVSS and then select this input when configuring
the crosspoint multiplexer. When using the AD7172-4 with
single-ended inputs, INL degrades.
Rev. B | Page 26 of 61
Data Sheet
AD7172-4
Standard low noise, low drift voltage references, such as the
ADR445, ADR444, and ADR441, are recommended for use.
Apply the reference to the AD7172-4 reference pins as shown in
Figure 52. Decouple the output of the reference to AVSS. As
shown in Figure 52, the ADR441 output is decoupled with a
0.1 μF capacitor at its output for stability purposes. The output
is then connected to a 4.7 μF capacitor, which acts as a reservoir
for any dynamic charge required by the ADC, and followed by a
0.1 μF decoupling capacitor at the REF+ input. This capacitor is
placed as close as possible to the REF+ and REF− pins. The
REF− pin is connected directly to the AVSS potential.
AD7172-4 REFERENCE
The AD7172-4 offers the user the option of either supplying a
reference to the REF± or REF2± pins of the device or using
AVDD1 – AVSS. Select the reference source to be used by the
analog input by setting the REF_SELx bits (Bits[5:4]) in the setup
configuration registers appropriately. The structure of the Setup
Configuration 0 register is shown in Table 18. The AD7172-4
defaults on power-up to use the REF+ and REF− reference
inputs, REF+ and REF−.
AD7172-4
3V TO 18V
ADR4412
2.5V VREF
0.1µF
1
0.1µF
4.7µF
1
1
32
REF+
31
REF–
0.1µF
1
1
1ALL DECOUPLING IS
2ANY OF THE ADR44x
12676-159
TO AVSS.
FAMILY OF REFERENCES CAN BE USED.
THE ADR441 ENABLES REUSE OF THE 3.3V ANALOG SUPPLY
NEEDED FOR AVDD1 TO POWER THE REFERENCE VIN.
Figure 52. ADR441 Connected to AD7172-4 REF± Pins
Table 18. Setup Configuration 0 Register
Reg.
0x20
Name
SETUPCON0
Bits
[15:8]
[7:0]
Bit 7
Bit 6
Reserved
BURNOUT_EN0 Reserved
Bit 5
Bit 4
BI_UNIPOLAR0
REF_SEL0
Bit 3
REFBUF0+
Bit 2
Bit 1
REFBUF0− AINBUF0+
Reserved
Bit 0
AINBUF0−
Reset
0x1000
RW
RW
Table 19. ADC Mode Register
Reg.
0x01
Name
ADCMODE
Bits
[15:8]
[7:0]
Bit 7
Reserved
Reserved
Bit 6
HIDE_DELAY
Bit 5
SING_CYC
Mode
Bit 4
Bit 3
Reserved
Rev. B | Page 27 of 61
Bit 2
CLOCKSEL
Bit 1
Bit 0
Delay
Reserved
Reset
0x2000
RW
RW
AD7172-4
Data Sheet
BUFFERED REFERENCE INPUT
The AD7172-4 has true rail-to-rail, integrated, precision unity
gain buffers on both ADC reference inputs. The buffers provide
the benefit of providing high input impedance and allowing
high impedance external sources to be directly connected to the
reference inputs. The integrated reference buffers can fully drive
the internal reference switch capacitor sampling network,
simplifying the reference circuit requirements while consuming
a very efficient 0.38 mA typical per buffer. Each reference input
buffer amplifier is fully chopped, meaning that it minimizes the
offset error drift and 1/f noise of the buffer. When using a
reference, such as the ADR445, ADR444, or ADR441, these
buffers are not required because these references, with proper
decoupling, can drive the reference inputs directly.
CLOCK SOURCE
The AD7172-4 uses a nominal master clock of 2 MHz. The
AD7172-4 can source its sampling clock from one of three
sources:
External Crystal
If higher precision, lower jitter clock sources are required, the
AD7172-4 can use an external crystal to generate the master clock.
The crystal is connected to the XTAL1 and XTAL2/CLKIO pins.
A recommended crystal for use is the FA-20H, a 16 MHz,
10 ppm, 9 pF crystal from Epson-Toyocom that is available in a
surface-mount package. As shown in Figure 53, insert two
capacitors (CX1 and CX2) from the traces connecting the
crystal to the XTAL1 and XTAL2/CLKIO pins. These capacitors
allow circuit tuning. Connect these capacitors to the DGND
pin. The value for these capacitors depends on the length and
capacitance of the trace connections between the crystal and the
XTAL1 and XTAL2/CLKIO pins. Therefore, the values of these
capacitors differ depending on the PCB layout and the crystal
employed.
AD7172-4
CX1
An internal oscillator
An external crystal (use a 16 MHz crystal automatically
divided internally to set the 2 MHz clock)
An external clock source
1
XTAL1 9
XTAL2/CLKIO 10
CX2
1
All output data rates listed in the data sheet relate to a master
clock rate of 2 MHz. Using a lower clock frequency from, for
instance, an external source scales any listed data rate proportionally. To achieve the specified data rates, particularly rates for
rejection of 50 Hz and 60 Hz, use a 2 MHz clock. The source of
the master clock is selected by setting the CLOCKSEL bits
(Bits[3:2]) in the ADC mode register as shown in Table 19. The
default operation on power-up and reset of the AD7172-4 is to
operate with the internal oscillator. It is possible to fine tune the
output data rate and filter notch at low output data rates using
the SINC3_MAPx bit. See the Sinc3 Filter section for more
information.
Internal Oscillator
The internal oscillator runs at 16 MHz and is internally divided
down to 2 MHz for the modulator and can be used as the ADC
master clock. The internal oscillator is the default clock source for
the AD7172-4 and is specified with an accuracy of −2.6% to
+2.5%.
There is an option to allow the internal clock oscillator to be output
on the XTAL2/CLKIO pin. The clock output is driven to the
IOVDD logic level. This option can affect the dc performance of
the AD7172-4 due to the disturbance introduced by the output
driver. The extent to which the performance is affected depends
on the IOVDD voltage supply. Higher IOVDD voltages create a
wider logic output swing from the driver and affect performance
to a greater extent. This effect is further exaggerated if the
1DECOUPLE
TO DGND.
12676-160
IOSTRENGTH bit is set at higher IOVDD levels (see Table 29
for more information).
Figure 53. External Crystal Connections
The external crystal circuitry can be sensitive to the SCLK
edges, depending on the SCLK frequency, IOVDD voltage,
crystal circuitry layout, and the crystal used. During crystal startup,
any disturbances caused by the SLCK edges may cause double
edges on the crystal input, resulting in invalid conversions until
the crystal voltage has reached a high enough level such that
any interference from the SCLK edges is insufficient to cause
double clocking. This double clocking can be avoided by
ensuring that the crystal circuitry has reached a sufficient
voltage level after startup before applying any SCLK.
Due to the nature of the crystal circuitry, it is therefore
recommended that empirical testing of the circuit be performed
under the required conditions, with the final PCB layout and
crystal, to ensure correct operation.
External Clock
The AD7172-4 can also use an externally supplied clock. In
systems where this is desirable, the external clock is routed to
the XTAL2/CLKIO pin. In this configuration, the XTAL2/
CLKIO pin accepts the externally sourced clock and routes it to
the modulator. The logic level of this clock input is defined by
the voltage applied to the IOVDD pin.
Rev. B | Page 28 of 61
Data Sheet
AD7172-4
DIGITAL FILTERS
The AD7172-4 has three flexible filter options to allow
optimization of noise, settling time, and rejection:
The sinc3 filter achieves the best single-channel noise performance
at lower rates and is, therefore, most suitable for single-channel
applications. The sinc3 filter always has a settling time equal to
The sinc5 + sinc1 filter
The sinc3 filter
Enhanced 50 Hz and 60 Hz rejection filters
Figure 56 shows the frequency domain filter response for the
sinc3 filter. The sinc3 filter has good roll-off over frequency and
has wide notches for good notch frequency rejection.
50Hz AND 60Hz
POSTFILTER
SINC1
SINC3
0
–10
–20
Figure 54. Digital Filter Block Diagram
The filter and output data rate are configured by setting the
appropriate bits in the filter configuration register for the
selected setup. Each channel can use a different setup and
therefore, a different filter and output data rate. See the Register
Details section for more information.
FILTER GAIN (dB)
–30
–80
–100
The sinc5 + sinc1 filter is targeted at multiplexed applications
and achieves single cycle settling at output data rates of 2.6 kSPS
and less. The sinc5 block output is fixed at the maximum rate of
31.25 kSPS, and the sinc1 block output data rate can be varied to
control the final ADC output data rate. Figure 55 shows the
frequency domain response of the sinc5 + sinc1 filter at a 50 SPS
output data rate. The sinc5 + sinc1 filter has a slow roll-off over
frequency and narrow notches.
0
–20
FILTER GAIN (dB)
–60
–70
–90
SINC5 + SINC1 FILTER
–40
–110
–120
0
50
100
150
FREQUENCY (Hz)
Figure 56. Sinc3 Filter Response
The output data rates with the accompanying settling time and
rms noise for the sinc3 filter are shown in Table 22 and Table 23. It
is possible to fine tune the output data rate for the sinc3 filter by
setting the SINC3_MAPx bit in the filter configuration registers.
If this bit is set, the mapping of the filter register changes to directly
program the decimation rate of the sinc3 filter. All other options
are eliminated. The data rate when on a single channel can be
calculated using the following equation:
Output Data Rate
–60
f MOD
32 FILTCONx[1 4:0]
where:
fMOD is the modulator rate (MCLK/2) and is equal to 1 MHz.
FILTCONx[14:0] are the contents on the filter configuration
registers, excluding the MSB.
–80
0
50
100
150
FREQUENCY (Hz)
12676-059
–100
–120
–40
–50
12676-060
SINC5
tSETTLE = 3/Output Data Rate
12676-058
SINC3 FILTER
Figure 55. Sinc5 + Sinc1 Filter Response at 50 SPS ODR
For example, an output data rate of 50 SPS can be achieved with
SINC3_MAPx enabled by setting the FILTCONx[14:0] bits to a
value of 625.
The output data rates with the accompanying settling time and
rms noise for the sinc5 + sinc1 filter are shown in Table 20 and
Table 21.
Rev. B | Page 29 of 61
AD7172-4
Data Sheet
The AD7172-4 can be configured by setting the SING_CYC bit
in the ADC mode register so that only fully settled data is output,
thus effectively putting the ADC into a single cycle settling mode.
This mode achieves single cycle settling by reducing the output
data rate to be equal to the settling time of the ADC for the selected
output data rate. This bit has no effect with the sinc5 + sinc1 filter
at output data rates of 2.6 kSPS and less.
Figure 58 shows the same step on the analog input but with
single cycle settling enabled. The analog input requires at least a
single cycle for the output to be fully settled. The output data
rate, as indicated by the RDY signal, is now reduced to equal the
settling time of the filter at the selected output data rate.
ANALOG
INPUT
FULLY
SETTLED
ADC
OUTPUT
Figure 57 shows a step on the analog input with single cycle
settling mode disabled and the sinc3 filter selected. The analog
input requires at least three cycles after the step change for the
output to reach the final settled value.
12676-062
SINGLE CYCLE SETTLING
tSETTLE
Figure 58. Step Input with Single Cycle Settling
ANALOG
INPUT
ADC
OUTPUT
12676-061
FULLY
SETTLED
1/ODR
Figure 57. Step Input Without Single Cycle Settling
Table 20. Output Data Rate, Settling Time, and Noise Using the Sinc5 + Sinc1 Filter with Input Buffers Disabled
Default Output
Data Rate (SPS);
SING_CYC = 0 and
Single Channel
Enabled1
31,250
15,625
10,417
5208
2597
1007
503.8
381
200.3
100.2
59.52
49.68
20.01
16.63
10
5
2.5
1.25
1
2
Output Data Rate
(SPS/Channel);
SING_CYC = 1 or with
Multiple Channels
Enabled1
6211
5181
4444
3115
2597
1007
503.8
381
200.3
100.2
59.52
49.68
20.01
16.63
10
5
2.5
1.25
Settling
Time1
161 μs
193 μs
225 μs
321 μs
385 μs
993 μs
1.99 ms
2.63 ms
4.99 ms
9.99 ms
16.8 ms
20.13 ms
49.98 ms
60.13 ms
100 ms
200 ms
400 ms
800 ms
Notch
Frequency
(Hz)
31,250
15,625
10,417
5208
3906
1157
539
401
206
102
59.98
50
20
16.67
10
5
2.5
1.25
Noise
(μV rms)
8.2
7.0
6.0
4.5
3.9
2.2
1.5
1.3
0.88
0.64
0.48
0.47
0.27
0.25
0.2
0.14
0.091
0.088
Effective
Resolution with
5 V Reference
(Bits)
20.2
20.4
20.7
21.1
21.3
22.2
22.6
22.9
23.3
23.8
24
24
24
24
24
24
24
24
Noise
(μV p-p)2
66
52
45
33
29
15
10
9.1
6.1
4.2
3.2
3.1
1.7
1.6
1.1
0.75
0.32
0.32
Peak-to-Peak
Resolution with
5 V Reference
(Bits)
17.2
17.5
17.8
18.2
18.4
19.3
19.9
20.1
20.6
21.2
21.6
21.6
22.4
22.6
23.1
24
24
24
The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
1000 samples.
Rev. B | Page 30 of 61
Data Sheet
AD7172-4
Table 21. Output Data Rate, Settling Time, and Noise Using the Sinc5 + Sinc1 Filter with Input Buffers Enabled
Default Output Data
Rate (SPS);
SING_CYC = 0 and
Single Channel
Enabled1
31,250
15,625
10,417
5208
2597
1007
503.8
381
200.3
100.2
59.52
49.68
20.01
16.63
10
5
2.5
1.25
1
2
Output Data Rate
(SPS/Channel);
SING_CYC = 1 or
with Multiple
Channels Enabled1
6211
5181
4444
3115
2597
1007
503.8
381
200.3
100.2
59.52
49.68
20.01
16.63
10
5
2.5
1.25
Settling
Time1
161 μs
193 μs
225 μs
321 μs
385 μs
993 μs
1.99 ms
2.63 ms
4.99 ms
9.99 ms
16.8 ms
20.13 ms
49.98 ms
60.13 ms
100 ms
200 ms
400 ms
800 ms
Notch
Frequency
(Hz)
31,250
15,625
10,417
5208
3906
1157
539
401
206
102
59.98
50
20
16.67
10
5
2.5
1.25
Noise
(μV rms)
9.5
8.2
7.1
5.3
4.7
2.6
1.8
1.6
1.1
0.75
0.62
0.53
0.32
0.32
0.25
0.18
0.11
0.089
Effective
Resolution with
5 V Reference
(Bits)
20
20.2
20.4
20.9
21
21.9
22.4
22.6
23.1
23.6
24
24
24
24
24
24
24
24
Noise
(μV p-p)2
74
63
53
39
29
16
12
11
7.5
5.1
3.6
3.3
1.8
1.7
1.2
0.83
0.35
0.35
Peak-to-Peak
Resolution with
5 V Reference
(Bits)
17
17.3
17.5
18
18.4
19.3
19.7
19.8
20.3
21
21.4
21.5
22.4
22.5
23
23.5
24
24
The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
1000 samples.
Rev. B | Page 31 of 61
AD7172-4
Data Sheet
Table 22. Output Data Rate, Settling Time, and Noise Using the Sinc3 Filter with Input Buffers Disabled
Default Output
Data Rate (SPS);
SING_CYC = 0 and
Single Channel
Enabled1
31,250
15,625
10,417
5,208
2,604
1,008
504
400.6
200.3
100.2
59.98
50
20.01
16.67
10
5
2.5
1.25
1
2
Output Data Rate
(SPS/Channel);
SING_CYC = 1 or with
Multiple Channels
Enabled1
10,309
5,181
3,460
1,733
867.3
335.9
167.98
133.5
66.67
33.39
19.99
16.67
6.67
5.56
3.33
1.67
0.83
0.42
Settling
Time1
97 μs
193 μs
289 μs
577 μs
1.15 ms
2.98 ms
5.95 ms
7.49 ms
14.98 ms
29.95 ms
50.02 ms
60 ms
149.95 ms
180 ms
300 ms
600 ms
1.2 sec
2.4 sec
Notch
Frequency
(Hz)
31,250
15,625
10,417
5,208
2,604
1,008
504
400.6
200.3
100.2
59.98
50
20.01
16.67
10
5
2.5
1.25
Noise
(μV rms)
211
27.2
7.9
3.7
2.5
1.6
1.1
0.99
0.68
0.47
0.38
0.35
0.21
0.21
0.18
0.18
0.16
0.054
Effective
Resolution with
5 V Reference
(Bits)
15.5
18.5
20.3
21.4
21.9
22.6
23.1
23.3
23.7
24
24
24
24
24
24
24
24
24
Noise
(μV p-p)2
1600
205
57
27
17
11
7.5
6.7
4.6
3.1
2.5
2.3
1.2
1.1
0.83
0.56
0.41
0.27
Peak-to-Peak
Resolution with
5 V Reference
(Bits)
12.5
15.6
17.4
18.5
19.2
19.8
20.3
20.5
21
21.6
21.9
22
23
23.1
23.5
24
24
24
The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
1000 samples.
Table 23. Output Data Rate, Settling Time, and Noise Using the Sinc3 Filter with Input Buffers Enabled
Default Output
Data Rate (SPS);
SING_CYC = 0 and
Single Channel
Enabled1
31,250
15,625
10,417
5,208
2,604
1,008
504
400.6
200.3
100.2
59.98
50
20.01
16.67
10
5
2.5
1.25
1
2
Output Data Rate
(SPS/Channel);
SING_CYC = 1 or with
Multiple Channels
Enabled1
10,309
5,181
3,460
1,733
867.3
335.9
167.98
133.5
66.67
33.39
19.99
16.67
6.67
5.56
3.33
1.67
0.83
0.42
Settling
Time1
97 μs
193 μs
289 μs
577 μs
1.15 ms
2.98 ms
5.95 ms
7.49 ms
14.98 ms
29.95 ms
50.02 ms
60 ms
149.95 ms
180 ms
300 ms
600 ms
1.2 sec
2.4 sec
Notch
Frequency
(Hz)
31,250
15,625
10,417
5,208
2,604
1,008
504
400.6
200.3
100.2
59.98
50
20.01
16.67
10
5
2.5
1.25
Noise
(μV rms)
212
27.7
8.5
4.3
3.0
1.8
1.3
1.2
0.82
0.57
0.45
0.44
0.26
0.24
0.19
0.12
0.098
0.073
Effective
Resolution with
5 V Reference
(Bits)
15.5
18.5
20.2
21.2
21.7
22.4
22.9
23
23.5
24
24
24
24
24
24
24
24
24
Noise
(μV p-p)2
1600
210
63
28
20
13
8.9
8.2
5.6
3.8
2.8
2.5
1.3
1.2
0.91
0.62
0.45
0.29
Peak-to-Peak
Resolution with
5 V Reference
(Bits)
12.5
15.5
17.3
18.4
19
19.6
20.1
20.2
20.8
21.3
21.8
22
22.9
23
23.4
24
24
24
The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
1000 samples.
Rev. B | Page 32 of 61
Data Sheet
AD7172-4
ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS
The enhanced filters provide rejection of 50 Hz and 60 Hz
simultaneously and allow the user to trade off settling time and
rejection. These filters can operate up to 27.27 SPS or can reject
up to 90 dB of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz interference.
These filters are operated by postfiltering the output of the sinc5 +
sinc1 filter. For this reason, the sinc5 + sinc1 filter must be
selected when using the enhanced filters to achieve the specified
settling time and noise performance. Table 24 shows the output
data rates with the accompanying settling time, rejection, and
rms noise. Figure 59 to Figure 66 show the frequency domain
plots of the responses from the enhanced filters.
Table 24. Enhanced Filters Output Data Rate, Noise, Settling Time, and Rejection Using the Enhanced Filters
Output Data Rate (SPS)
27.27
25
20
16.667
Simultaneous Rejection of
50 Hz ± 1 Hz and 60 Hz ± 1 Hz(dB)1
47
62
85
90
Noise
(μV rms)
0.45
0.44
0.41
0.417
Peak-to-Peak
Resolution (Bits)
21.4
21.4
21.7
21.7
Comments
See Figure 59 and Figure 62
See Figure 60 and Figure 63
See Figure 61 and Figure 64
See Figure 65 and Figure 66
0
0
–10
–10
–20
–20
–30
–30
FILTER GAIN (dB)
–40
–50
–60
–70
–80
–40
–50
–60
–70
–90
–100
0
100
200
300
400
500
600
FREQUENCY (Hz)
12676-063
–90
–100
0
0
–10
–20
–20
–30
–30
FILTER GAIN (dB)
0
–40
–50
–60
–70
–70
500
FREQUENCY (Hz)
600
12676-065
–90
400
600
–60
–80
300
500
–50
–90
200
400
–40
–80
100
300
Figure 61. 20 SPS ODR, 50 ms Settling Time
–10
0
200
FREQUENCY (Hz)
Figure 59. 27.27 SPS ODR, 36.67 ms Settling Time
–100
100
12676-067
–80
Figure 60. 25 SPS ODR, 40 ms Settling Time
–100
40
45
50
55
60
65
70
FREQUENCY (Hz)
Figure 62. 27.27 SPS ODR, 36.67 ms Settling Time (40 Hz to 70 Hz)
Rev. B | Page 33 of 61
12468-064
FILTER GAIN (dB)
Master clock = 2.00 MHz.
FILTER GAIN (dB)
1
Settling
Time (ms)
36.67
40.0
50.0
60.0
Data Sheet
0
–10
–20
–20
–30
–30
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–90
–90
45
50
55
60
65
70
FREQUENCY (Hz)
–100
0
200
300
400
500
600
FREQUENCY (Hz)
Figure 63. 25 SPS ODR, 40 ms Settling Time (40 Hz to 70 Hz)
Figure 65. 16.667 SPS ODR, 60 ms Settling Time
0
–10
–10
–20
–20
–30
–30
FILTER GAIN (dB)
0
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–100
40
–100
40
45
50
55
60
65
FREQUENCY (Hz)
70
12676-068
FILTER GAIN (dB)
100
Figure 64. 20 SPS ODR, 50 ms Settling Time (40 Hz to 70 Hz)
45
50
55
60
65
70
FREQUENCY (Hz)
Figure 66. 16.667 SPS ODR, 60 ms Settling Time (40 Hz to 70 Hz)
Rev. B | Page 34 of 61
12676-070
–100
40
12676-069
FILTER GAIN (dB)
0
–10
12676-066
FILTER GAIN (dB)
AD7172-4
Data Sheet
AD7172-4
OPERATING MODES
The AD7172-4 has a number of operating modes that can be set
from the ADC mode register and interface mode register (see
Table 28 and Table 29). These modes are as follows and are
described in the following sections:
Continuous conversion mode
Continuous read mode
Single conversion mode
Standby mode
Power-down mode
Calibration modes (three)
CONTINUOUS CONVERSION MODE
Continuous conversion mode is the default power-up mode.
The AD7172-4 converts continuously, and the RDY bit in the
status register goes low each time a conversion is complete. If CS
is low, the RDY output also goes low when a conversion is
complete. To read a conversion, write to the communications
register to indicate that the next operation is a read of the data
register. When the data-word has been read from the data register,
the DOUT/RDY pin goes high. The user can read this register
additional times, if required. However, ensure that the data
register is not being accessed at the completion of the next
conversion; otherwise, the new conversion word is lost.
When several channels are enabled, the ADC automatically
sequences through the enabled channels, performing one
conversion on each channel. When all the channels have been
converted, the sequence starts again with the first channel. The
channels are converted in order from the lowest enabled channel
to the highest enabled channel. The data register is updated as
soon as each conversion is available. The RDY output pulses
low each time a conversion is available. The user can then read
the conversion while the ADC converts the next enabled channel.
If the DATA_STAT bit in the interface mode register is set to 1,
the contents of the status register, along with the conversion data,
are output each time the data register is read. The status register
indicates the channel to which the conversion corresponds.
CS
0x44
0x44
DIN
DATA
DATA
12676-071
DOUT/RDY
SCLK
Figure 67. Continuous Conversion Mode
Rev. B | Page 35 of 61
AD7172-4
Data Sheet
To enable continuous read mode, set the CONTREAD bit in the
interface mode register. When this bit is set, the only serial interface
operations possible are reads from the data register. To exit continuous read mode, issue a dummy read of the ADC data register
command (0x44) while the RDY output is low. Alternatively, apply
a software reset, that is, 64 SCLKs with CS = 0 and DIN = 1.
This resets the ADC and all register contents. These are the only
commands that the interface recognizes after it is placed in
continuous read mode. Hold DIN low in continuous read mode
until an instruction is to be written to the device.
CONTINUOUS READ MODE
In continuous read mode, it is not required to write to the
communications register before reading ADC data; apply only
the required number of SCLKs after the RDY output goes low to
indicate the end of a conversion. When the conversion is read,
the RDY output returns high until the next conversion is
available. In this mode, the data can be read only once. Ensure
that the data-word is read before the next conversion is
complete. If the user has not read the conversion before the
completion of the next conversion or if insufficient serial clocks
are applied to the AD7172-4 to read the data-word, the serial
output register is reset shortly before the next conversion is
complete, and the new conversion is placed in the output serial
register. The ADC must be configured for continuous
conversion mode to use continuous read mode.
If multiple ADC channels are enabled, each channel is output
in turn, with the status bits being appended to the data if the
DATA_STAT bit is set in the interface mode register. The status
register indicates the channel to which the conversion corresponds.
CS
DOUT/RDY
0x02
0x0080
DATA
DATA
DATA
12676-072
DIN
SCLK
Figure 68. Continuous Read Mode
Rev. B | Page 36 of 61
Data Sheet
AD7172-4
SINGLE CONVERSION MODE
In single conversion mode, the AD7172-4 performs a single
conversion and is placed in standby mode after the conversion
is complete. The RDY output goes low to indicate the completion
of a conversion. When the data-word has been read from the
data register, the RDY output goes high. The data register can be
read several times, if required, even when the RDY output has gone
high.
If several channels are enabled, the ADC automatically
sequences through the enabled channels and performs a
conversion on each channel. When a conversion is started, the
RDY output goes high and remains high until a valid conversion is
available and CS is low. When the conversion is available, the RDY
output goes low. The ADC then selects the next channel and
begins a conversion. The user can read the present conversion
while the next conversion is being performed. When the next
conversion is complete, the data register is updated; therefore,
the user has a limited period in which to read the conversion.
When the ADC has performed a single conversion on each of
the selected channels, it returns to standby mode.
If the DATA_STAT bit in the interface mode register is set to 1,
the contents of the status register, along with the conversion, are
output each time the data register is read. The two LSBs of the
status register indicate the channel to which the conversion
corresponds.
CS
DIN
0x01
0x8010
0x44
DATA
12676-073
DOUT/RDY
SCLK
Figure 69. Single Conversion Mode
Rev. B | Page 37 of 61
AD7172-4
Data Sheet
STANDBY AND POWER-DOWN MODES
In standby mode, most blocks are powered down. The LDO
regulators remain active so that the registers maintain their
contents. The crystal oscillator remains active if selected. To
power down the clock in standby mode, set the CLOCKSEL bits
in the ADC mode register to 00 (internal oscillator mode).
In power-down mode, all blocks are powered down, including
the LDO regulators. All registers lose their contents, and the GPIO
outputs are placed in three-state. To prevent accidental entry to
power-down mode, the ADC must first be placed in standby
mode. Exiting power-down mode requires 64 SCLKs with CS = 0
and DIN = 1, that is, a serial interface reset. A delay of 500 μs is
recommended before issuing a subsequent serial interface
command to allow the LDO regulator to power up.
CALIBRATION
The AD7172-4 allows a two-point calibration to be performed
to eliminate any offset and gain errors. Three calibration modes
are used to eliminate these offset and gain errors on a per setup
basis:
Internal zero-scale calibration mode
System zero-scale calibration mode
System full-scale calibration mode
There is no internal full-scale calibration mode because this is
calibrated in the factory at the time of production.
Only one channel can be active during calibration. After each
conversion, the ADC conversion result is scaled using the ADC
calibration registers before being written to the data register.
The default value of the offset register is 0x800000, and the
nominal value of the gain register is 0x555555. The calibration
range of the ADC gain is from 0.4 × VREF to 1.05 × VREF. The
following equations show the calculations that are used. In
unipolar mode, the ideal relationship—that is, not taking into
account the ADC gain error and offset error—is as follows:
0.75 VIN
Data
2 23 (Offset 0 x 800000)
V
REF
Gain
2
0 x 400000
In bipolar mode, the ideal relationship—that is, not taking into
account the ADC gain error and offset error—is as follows:
To start a calibration, write the relevant value to the mode bits
in the ADC mode register. The DOUT/RDY pin and the RDY bit
in the status register go high when the calibration initiates. When
the calibration is complete, the contents of the corresponding offset
or gain register are updated, the RDY bit in the status register is
reset and the RDY output pin returns low (if CS is low), and the
AD7172-4 reverts to standby mode.
During an internal offset calibration, the selected positive
analog input pin is disconnected, and both modulator inputs
are connected internally to the selected negative analog input
pin. Therefore, it is necessary to ensure that the voltage on the
selected negative analog input pin does not exceed the allowed
limits and is free from excessive noise and interference.
However, for system calibrations the system zero-scale (offset)
and system full-scale (gain) voltages must be applied to the
ADC pins before initiating the calibration modes. As a result,
errors external to the ADC are removed.
From an operational point of view, treat a calibration like
another ADC conversion. An offset calibration, if required,
must always be performed before a full-scale calibration. Set the
system software to monitor the RDY bit in the status register or
the RDY output to determine the end of a calibration via a
polling sequence or an interrupt driven routine. All calibrations
require a time equal to the settling time of the selected filter and
output data rate to be completed.
An internal offset calibration, system zero-scale calibration, and
system full-scale calibration can be performed at any output data
rate. Using lower output data rates results in better calibration
accuracy and is accurate for all output data rates. A new offset
calibration is required for a given channel if the reference source
for that channel is changed.
The offset error is typically ±75 μV and an offset calibration
reduces the offset error to the order of the noise. The gain error
is factory calibrated at ambient temperature. Following this
calibration, the gain error is typically ±5 ppm of FSR.
The AD7172-4 provides the user with access to the on-chip
calibration registers, allowing the microprocessor to read the
calibration coefficients of the device and to write its own
calibration coefficients. A read or write of the offset and gain
registers can be performed at any time except during an internal
or self calibration.
0.75 VIN
Data
2 23 (Offset 0 x 800000 )
VREF
Gain
0 x 800000
0 x 400000
Rev. B | Page 38 of 61
Data Sheet
AD7172-4
DIGITAL INTERFACE
x8 + x 2 + x + 1
During read operations, the user can select between this
polynomial and a simpler exclusive OR (XOR) function. The
XOR function requires less time to process on the host
microcontroller than the polynomial-based checksum. The
CRC_EN bits in the interface mode register enable and disable
the checksum and allow the user to select between the
polynomial check and the simple XOR check.
The checksum is appended to the end of each read and write
transaction. The checksum calculation for the write transaction
is calculated using the 8-bit command word and the 8-bit to
24-bit data. For a read transaction, the checksum is calculated
using the command word and the 8-bit to 32-bit data output.
Figure 70 and Figure 71 show SPI write and read transactions,
respectively.
DIN
Figure 2 and Figure 3 show timing diagrams for interfacing to
the AD7172-4 using CS to decode the device. Figure 2 shows
the timing for a read operation from the AD7172-4, and Figure 3
shows the timing for a write operation to the AD7172-4. It is
possible to read from the data register several times even though
the RDY output returns high after the first read operation.
However, take care to ensure that the read operations are complete
before the next output update occurs. In continuous read mode,
the data register can be read only once.
SCLK
Operate the serial interface in 3-wire mode by tying CS low. In
this case, the SCLK, DIN, and DOUT/RDY pins are used to
communicate with the AD7172-4. The end of the conversion
can also be monitored using the RDY bit in the status register.
DOUT/
RDY
The AD7172-4 can be reset by writing 64 SCLKs with CS = 0
and DIN = 1. A reset returns the interface to the state in which it
expects a write to the communications register. This operation
resets the contents of all registers to their power-on values.
Following a reset, allow a period of 500 μs before addressing the
serial interface.
CHECKSUM PROTECTION
8-BIT COMMAND
UP TO 24-BIT INPUT
8-BIT CRC
CS
DATA
CRC
CS
12676-074
The DOUT/RDY pin also functions as a data ready signal, with
the output going low if CS is low when a new data-word is
available in the data register. The RDY output is reset high when
a read operation from the data register is complete. The RDY
output also goes high before updating the data register to
indicate when not to read from the device to ensure that a data
read is not attempted while the register is being updated. Take
care to avoid reading from the data register when the RDY
output is about to go low. The best method to ensure that no data
read occurs is to always monitor the RDY output. Start reading
the data register as soon as the RDY output goes low, and
ensure a sufficient SCLK rate, such that the read is completed
before the next conversion result. CS is used to select a device. CS
can decode the AD7172-4 in systems where several components
are connected to the serial bus.
For CRC checksum calculations during a write operation, the
following polynomial is always used:
Figure 70. SPI Write Transaction with CRC
8-BIT COMMAND
UP TO 32-BIT
OUTPUT
8-BIT CRC
CS
DIN
CMD
DATA
CRC
SCLK
12676-075
The programmable functions of the AD7172-4 are controlled via
the SPI. The serial interface of the AD7172-4 consists of four
signals: CS, DIN, SCLK, and DOUT/RDY. The DIN input
transfers data into the on-chip registers, and the DOUT output
accesses data from the on-chip registers. SCLK is the serial clock
input for the device, and all data transfers (either on the DIN input
or on the DOUT output) occur with respect to the SCLK signal.
Figure 71. SPI Read Transaction with CRC
If checksum protection is enabled when continuous read mode
is active, an implied read data command of 0x44 before every
data transmission must be accounted for when calculating the
checksum value. This implied read data command ensures a
nonzero checksum value even if the ADC data equals 0x000000.
The AD7172-4 has a checksum mode that can improve
interface robustness. Using the checksum ensures that only
valid data is written to a register and allows data read from a
register to be validated. If an error occurs during a register
write, the CRC_ERROR bit is set in the status register. However,
to ensure that the register write is successful, read back the
register and verify the checksum.
Rev. B | Page 39 of 61
AD7172-4
Data Sheet
CRC CALCULATION
Polynomial
The checksum, which is eight bits wide, is generated using the
polynomial
x8 + x2 + x + 1
aligned so that the MSB is adjacent to the leftmost Logic 1 of the
data. An XOR function is applied to the data to produce a new,
shorter number. The polynomial is again aligned so that its MSB is
adjacent to the leftmost Logic 1 of the new result, and the procedure
is repeated. This process repeats until the original data is reduced to
a value less than the polynomial. This is the 8-bit checksum.
To generate the checksum, the data is left shifted by eight bits to
create a number ending in eight Logic 0s. The polynomial is
Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data)
An example of generating the 8-bit checksum using the polynomial based checksum is as follows:
Initial value
8
011001010100001100100001
2
x +x +x+1
01100101010000110010000100000000
left shifted eight bits
=
polynomial
100000111
100100100000110010000100000000
100000111
XOR result
polynomial
100011000110010000100000000
100000111
XOR result
polynomial
11111110010000100000000
100000111
XOR result
polynomial value
1111101110000100000000
100000111
XOR result
polynomial value
111100000000100000000
100000111
XOR result
polynomial value
11100111000100000000
100000111
XOR result
polynomial value
1100100100100000000
100000111
XOR result
polynomial value
100101010100000000
100000111
XOR result
polynomial value
101101100000000
100000111
1101011000000
100000111
101010110000
100000111
1010001000
100000111
10000110
XOR result
polynomial value
XOR result
polynomial value
XOR result
polynomial value
XOR result
polynomial value
checksum = 0x86
Rev. B | Page 40 of 61
Data Sheet
AD7172-4
XOR Calculation
The checksum, which is 8 bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes.
Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data)
Using the previous example, divide into three bytes: 0x65, 0x43, and 0x21
01100101
0x65
01000011
0x43
00100110
XOR result
00100001
0x21
00000111
CRC
Rev. B | Page 41 of 61
AD7172-4
Data Sheet
INTEGRATED FUNCTIONS
The AD7172-4 has integrated functions that improve the
usefulness of a number of applications as well as serve
diagnostic purposes in safety conscious applications.
GENERAL-PURPOSE INPUT/OUTPUT
The AD7172-4 has two digital GPIO pins (GPIO0 and GPIO1)
and two general-purpose digital output pins (GPO2 and
GPO3). As the naming convention suggests, the GPIO0 and
GPIO1 pins can be configured as inputs or outputs, but GPO2
and GPO3 are outputs only. The GPIOx and GPOx pins are
enabled using the following bits in the GPIOCON register:
IP_EN0, IP_EN1 (or OP_EN0, OP_EN1) for GPIO0 and
GPIO1, and OP_EN2_3 for GPO2 and GPO3.
When the GPIO0 pin or the GPIO1 pin is enabled as an input,
the logic level at the pin is contained in the GP_DATA0 or
GP_DATA1 bit, respectively. When the GPIO0, GPIO1, GPO2,
or GPO3 pin is enabled as an output, the GP_DATA0, GP_DATA1,
GP_DATA2, or GP_DATA3 bit, respectively, determine the logic
level output at the pin. The logic levels for these pins are referenced
to AVDD1 and AVSS.
The ERROR pin can also be used as a general-purpose output.
When the ERR_EN bits in the GPIOCON register are set to 11,
the ERROR pin operates as a general-purpose output. In this
configuration, the ERR_DAT bit in the GPIOCON register
determines the logic level output at the pin. The logic level for
the pin is referenced to IOVDD and DGND.
All general-purpose outputs have an active pull-up.
EXTERNAL MULTIPLEXER CONTROL
If an external multiplexer is used to increase the channel count,
the multiplexer logic pins can be controlled via the AD7172-4
GPIOx pins. With the MUX_IO bit, the GPIOx timing is controlled
by the ADC; therefore, the channel change is synchronized with
the ADC, eliminating any need for external synchronization.
DELAY
It is possible to insert a programmable delay before the AD7172-4
begins to take samples. This delay allows an external amplifier
or multiplexer to settle and can also alleviate the specification
requirements for the external amplifier or multiplexer. Eight
programmable settings, ranging from 0 μs to 8 ms, can be set using
the delay bits in the ADC mode register (Register 0x01, Bits[10:8]).
If a delay greater than 0 μs is selected and the HIDE_DELAY bit
in the ADC mode register is set to 0, this delay is added to the
conversion time, regardless of the selected output data rate.
When using the sinc5 + sinc1 filter, it is possible to hide this
delay such that the output data rate remains the same as the output
data rate without the delay enabled. If the HIDE_DELAY bit is
set to 1 and the selected delay is less than half of the conversion
time, the delay can be absorbed by reducing the number of
averages the digital filter performs, which keeps the conversion
time the same but can affect the noise performance.
The effect on the noise performance depends on the delay time
compared to the conversion time. It is possible to absorb the
delay only for output data rates less than 2.6 kSPS with the
exception of the following four rates, which cannot absorb any
delay: 381 SPS, 59.52 SPS, 49.68 SPS, and 16.66 SPS.
16-BIT/24-BIT CONVERSIONS
By default, the AD7172-4 generates 24-bit conversions.
However, the width of the conversions can be reduced to 16 bits.
Setting the WL16 bit in the interface mode register to 1 rounds
all data conversions to 16 bits. Clearing this bit sets the width of
the data conversions to 24 bits.
DOUT_RESET
The serial interface uses a shared DOUT/RDY pin. By default,
this pin outputs the RDY signal. During a data read, this pin
outputs the data from the register being read. After the read is
complete, the pin reverts to outputting the RDY signal after a short
fixed period of time (t7). However, this time may be too short for
some microcontrollers and can be extended until the CS pin is
brought high by setting the DOUT_RESET bit in the interface
mode register to 1. This setting means that CS must frame each
read operation and compete the serial interface transaction.
SYNCHRONIZATION
Normal Synchronization
When the SYNC_EN bit in the GPIOCON register is set to 1,
the SYNC pin functions as a synchronization input. The SYNC
input allows the user to reset the modulator and the digital filter
without affecting any of the setup conditions on the device. This
feature allows the user to start to gather samples of the analog
input from a known point, the rising edge of the SYNC input.
The SYNC input must be low for at least one master clock cycle
to ensure that synchronization occurs.
If multiple AD7172-4 devices are operated from a common master
clock, they can be synchronized so that their analog inputs are
sampled simultaneously. This synchronization is typically
completed after each AD7172-4 device has performed its own
calibration or has calibration coefficients loaded into its
calibration registers. A falling edge on the SYNC input resets the
digital filter and the analog modulator and places the AD7172-4
into a consistent known state. While the SYNC input is low, the
AD7172-4 is maintained in this known state. On the SYNC
input rising edge, the modulator and filter are taken out of this
reset state, and on the next master clock edge, the device starts to
gather input samples again.
The device is taken out of reset on the master clock falling edge
following the SYNC input low to high transition. Therefore, when
multiple devices are being synchronized, take the SYNC input
high on the master clock rising edge to ensure that all devices
are released on the master clock falling edge. If the SYNC input
is not taken high in sufficient time, a difference of one master
Rev. B | Page 42 of 61
Data Sheet
AD7172-4
clock cycle between the devices is possible; that is, the instant at
which conversions are available differs from device to device by
a maximum of one master clock cycle.
The SYNC input can also be used as a start conversion
command for a single channel when in normal synchronization
mode. In this mode, the rising edge of the SYNC input starts a
conversion, and the falling edge of the RDY output indicates
when the conversion is complete. The settling time of the filter is
required for each data register update. After the conversion is
complete, bring the SYNC input low in preparation for the next
conversion start signal.
Alternate Synchronization
In alternate synchronization mode, the SYNC input operates as a
start conversion command when several channels of the AD7172-4
are enabled. Setting the ALT_SYNC bit in the interface mode
register to 1 enables an alternate synchronization scheme. When
the SYNC input is taken low, the ADC completes the conversion
on the current channel, selects the next channel in the sequence,
and then waits until the SYNC input is taken high to start the
conversion. The RDY output goes low when the conversion is
complete on the current channel, and the data register is updated
with the corresponding conversion. Therefore, the SYNC input
does not interfere with the sampling on the currently selected
channel but allows the user to control the instant at which the
conversion begins on the next channel in the sequence.
Alternate synchronization mode can be used only when several
channels are enabled. It is not recommended to use this mode
when a single channel is enabled.
ERROR FLAGS
The status register contains three error bits (ADC_ERROR,
CRC_ERROR, and REG_ERROR) that flag errors with the
ADC conversion, errors with the CRC check, and errors caused
by changes in the registers, respectively. In addition, the ERROR
output can indicate that an error has occurred.
the on-chip registers. If a bit changes, the REG_ERROR bit is
set to 1. Therefore, for writes to the on-chip registers, set the
REG_CHECK bit to 0. When the registers have been updated,
the REG_CHECK bit can be set to 1. The AD7172-4 calculates a
checksum of the on-chip registers. If one of the register values
has changed, the REG_ERROR bit is set to 1. If an error is
flagged, the REG_CHECK bit must be set to 0 to clear the
REG_ERROR bit in the status register. The register check
function does not monitor the data register, status register, or
interface mode register.
ERROR Input/Output
The ERROR pin functions as an error input/output pin or as a
general-purpose output pin. The ERR_EN bits in the GPIOCON
register determine the function of the pin.
When ERR_EN is set to 10, the ERROR pin functions as an
open-drain error output. The three error bits in the status
register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are
OR’ed, inverted, and mapped to the ERROR output. Therefore, the
ERROR output indicates that an error has occurred. The status
register must be read to identify the error source.
When ERR_EN is set to 01, the ERROR pin functions as an
error input. The error output of another component can be
connected to the AD7172-4 ERROR input so that the AD7172-4
indicates when an error occurs on either itself or the external
component. The value on the ERROR input is inverted and OR’ed
with the errors from the ADC conversion, and the result is
indicated via the ADC_ERROR bit in the status register. The value
of the ERROR input is reflected in the ERR_DAT bit in the
GPIO onfiguration register.
The ERROR input/output is disabled when ERR_EN is set to 00.
When the ERR_EN bits are set to 11, the ERROR pin operates
as a general-purpose output.
DATA_STAT
The ADC_ERROR bit in the status register flags any errors that
occur during the conversion process. The flag is set when an overrange or underrange result is output from the ADC. The ADC
also outputs all 0s or all 1s when an undervoltage or overvoltage
occurs. This flag is reset only when the overvoltage or undervoltage
is removed. This flag is not reset by a read of the data register.
The contents of the status register can be appended to each conversion on the AD7172-4 using the DATA_STAT bit in the
IFMODE register. This function is useful if several channels are
enabled. Each time a conversion is output, the contents of the
status register are appended. The two LSBs of the status register
indicate to which channel the conversion corresponds. In
addition, the user can determine if any errors are being flagged
by the error bits.
CRC_ERROR
IOSTRENGTH
If the CRC value that accompanies a write operation does not
correspond with the information sent, the CRC_ERROR flag is
set. The flag is reset when the status register is explicitly read.
The serial interface can operate with a power supply as low as
2 V. However, at this low voltage, the DOUT/RDY pin may not
have sufficient drive strength if there is moderate parasitic
capacitance on the board or if the SCLK frequency is high. The
IOSTRENGTH bit in the interface mode register increases the
drive strength of the DOUT/RDY pin.
ADC_ERROR
REG_ERROR
The REG_ERROR flag is used in conjunction with the
REG_CHECK bit in the interface mode register. When the
REG_CHECK bit is set, the AD7172-4 monitors the values in
Rev. B | Page 43 of 61
AD7172-4
Data Sheet
GROUNDING AND LAYOUT
The analog inputs and reference inputs are differential and,
therefore, most of the voltages in the analog modulator are
common-mode voltages. The high common-mode rejection of
the device removes common-mode noise on these inputs. The
analog and digital supplies to the AD7172-4 are independent
and connected to separate pins to minimize coupling between the
analog and digital sections of the device. The digital filter
provides rejection of broadband noise on the power supplies,
except at integer multiples of the master clock frequency.
The digital filter also removes noise from the analog and
reference inputs, provided that these noise sources do not
saturate the analog modulator. As a result, the AD7172-4 is
more immune to noise interference than a conventional high
resolution converter. However, because the resolution of the
AD7172-4 is high and the noise levels from the converter are so
low, take care with regard to grounding and layout.
The PCB that houses the ADC must be designed such that the
analog and digital sections are separated and confined to
certain areas of the board. A minimum etch technique is
generally best for ground planes because it results in the best
shielding.
In any layout, the user must consider the flow of currents in the
system, ensuring that the paths for all return currents are as close as
possible to the paths the currents took to reach their destinations.
Avoid running digital lines under the device because this
couples noise onto the die. Allow the analog ground plane to
run under the AD7172-4 to prevent noise coupling. The power
supply lines to the AD7172-4 must use as wide a trace as
possible to provide low impedance paths and reduce glitches on
the power supply line. Shield fast switching signals like clocks
with digital ground to prevent radiating noise to other sections
of the board and never run clock signals near the analog inputs.
Avoid crossover of digital and analog signals. Run traces on
opposite sides of the board at right angles to each other. This
technique reduces the effects of feedthrough on the board. A
microstrip technique is by far the best but is not always possible
with a double-sided board.
Good decoupling is important when using high resolution ADCs.
The AD7172-4 has three power supply pins: AVDD1, AVDD2,
and IOVDD. The AVDD1 and AVDD2 pins are referenced to
AVSS, and the IOVDD pin is referenced to DGND. Decouple
AVDD1 and AVDD2 with a 10 μF capacitor in parallel with a
0.1 μF capacitor to AVSS on each pin. Place the 0.1 μF capacitor
as close as possible to the device on each supply, ideally right up
against the device. Decouple IOVDD with a 10 μF capacitor in
parallel with a 0.1 μF capacitor to DGND. Decouple all analog
inputs to AVSS. Decouple the REF± and REF2± pins to AVSS.
The AD7172-4 also has two on-board LDO regulators, one that
regulates the AVDD2 supply and one that regulates the IOVDD
supply. For the REGCAPA pin, use 1 μF and 0.1 μF capacitors to
AVSS. Similarly, for the REGCAPD pin, use 1 μF and 0.1 μF
capacitors to DGND.
If using the AD7172-4 for split supply operation, a separate
plane must be used for AVSS.
Rev. B | Page 44 of 61
Data Sheet
AD7172-4
REGISTER SUMMARY
Table 25. Register Summary
Reg.
0x00
Name
COMMS
Bits
[7:0]
Bit 7
WEN
Bit 6
R/W
Bit 5
Bit 4
0x00
STATUS
[7:0]
RDY
ADC_ERROR
CRC_ERROR
REG_ERROR
0x01
ADCMODE
[15:8]
[7:0]
[15:8]
[7:0]
[23:0]
[23:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
RESERVED
RESERVED
HIDE_DELAY
SING_CYC
MODE
0x02
IFMODE
0x03
0x04
0x06
REGCHECK
DATA
GPIOCON
0x07
ID
0x10
CH0
0x11
0x12
0x13
0x14
CH1
CH2
CH3
CH4
0x15
CH5
0x16
CH6
0x17
CH7
0x20
SETUPCON0
0x21
0x22
0x23
0x24
0x25
0x26
0x27
SETUPCON1
SETUPCON2
SETUPCON3
SETUPCON4
SETUPCON5
SETUPCON6
SETUPCON7
0x28
FILTCON0
0x29
FILTCON1
0x2A
FILTCON2
0x2B
FILTCON3
0x2C
FILTCON4
0x2D FILTCON5
0x2E
FILTCON6
CONTREAD
RESERVED
GP_DATA3
RESERVED
DATA_STAT
PDSW
GPDATA2
CH_EN0
REG_CHECK
OP_EN2_3
IP_EN1
SETUP_SEL0
SETUP_SEL1
AINPOS1[2:0]
CH_EN2
SETUP_SEL2
AINPOS2[2:0]
CH_EN3
SETUP_SEL3
AINPOS3[2:0]
CH_EN4
CH_EN5
CH_EN6
CH_EN7
BURNOUT_EN0
BURNOUT_EN1
BURNOUT_EN2
BURNOUT_EN3
BURNOUT_EN4
BURNOUT_EN5
BURNOUT_EN6
BURNOUT_EN7
SINC3_MAP0
RESERVED
SINC3_MAP1
RESERVED
SINC3_MAP2
RESERVED
SINC3_MAP3
RESERVED
SINC3_MAP3
RESERVED
SINC3_MAP3
RESERVED
SINC3_MAP3
RESERVED
Bit 2
RA
Bit 1
RESERVED
RESERVED
AINPOS0[2:0]
CH_EN1
Bit 3
CHANNEL
Reset
0x00
RW
W
0x80
R
DELAY
0x2000
RESERVED
RESERVED
DOUT_RESET 0x0000
RESERVED
WL16
0x000000
0x000000
ERR_EN
ERR_DAT
0x0800
GP_DATA1
GP_DATA0
0x205X
CLOCKSEL
ALT_SYNC
IOSTRENGTH
RESERVED
CRC_EN
REGISTER_CHECK[23:0]
DATA[23:0]
MUX_IO
SYNC_EN
IP_EN0
OP_EN1
OP_EN0
ID[15:8]
ID[7:0]
RESERVED
AINNEG0
RESERVED
AINNEG1
RESERVED
AINNEG2
RESERVED
AINNEG3
RESERVED
SETUP_SEL4
AINPOS4[2:0]
SETUP_SEL5
AINPOS5[2:0]
SETUP_SEL6
AINPOS6[2:0]
SETUP_SEL7
AINPOS7[2:0]
RESERVED
BI_UNIPOLAR0
RESERVED
REF_SEL0
RESERVED
BI_UNIPOLAR1
RESERVED
REF_SEL1
RESERVED
BI_UNIPOLAR2
RESERVED
REF_SEL2
RESERVED
BI_UNIPOLAR3
RESERVED
REF_SEL3
RESERVED
BI_UNIPOLAR4
RESERVED
REF_SEL4
RESERVED
BI_UNIPOLAR5
RESERVED
REF_SEL5
RESERVED
BI_UNIPOLAR6
RESERVED
REF_SEL6
RESERVED
BI_UNIPOLAR7
RESERVED
REF_SEL7
RESERVED
ORDER0
RESERVED
ORDER1
RESERVED
ORDER2
RESERVED
ORDER3
RESERVED
ORDER4
RESERVED
ORDER5
RESERVED
ORDER6
Bit 0
RW
RW
R
R
RW
R
AINPOS0[4:3]
0x8001
RW
AINPOS1[4:3]
0x0001
RW
AINPOS2[4:3]
0x0001
RW
AINPOS3[4:3]
0x0001
RW
AINPOS4[4:3]
0x0001
RW
0x0001
RW
0x0001
RW
0x0001
RW
0x1000
RW
0x1000
RW
0x1000
RW
0x1000
RW
0x1000
RW
0x1000
RW
0x1000
RW
0x1000
RW
0x0500
RW
0x0500
RW
0x0500
RW
0x0500
RW
0x0500
RW
0x0500
RW
0x0500
RW
AINNEG4
RESERVED
AINPOS5[4:3]
AINNEG5
RESERVED
AINPOS6[4:3]
AINNEG6
RESERVED
AINPOS7[4:3]
AINNEG7
REFBUF0+
REFBUF0AINBUF0+
AINBUF0−
RESERVED
REFBUF1+
REFBUF1−
AINBUF1+
AINBUF1−
RESERVED
REFBUF2+
REFBUF2−
AINBUF2+
AINBUF2−
RESERVED
REFBUF3+
REFBUF3−
AINBUF3+
AINBUF3−
RESERVED
REFBUF4+
REFBUF4−
AINBUF4+
AINBUF4−
RESERVED
REFBUF5+
REFBUF5−
AINBUF5+
AINBUF5−
RESERVED
REFBUF6+
REFBUF6−
AINBUF6+
AINBUF6−
RESERVED
REFBUF7+
REFBUF7−
AINBUF7+
AINBUF7−
RESERVED
ENHFILTEN0
ENHFILT0
ODR0
ENHFILTEN1
ENHFILT1
ODR1
ENHFILTEN2
ENHFILT2
ODR2
ENHFILTEN3
ENHFILT3
ODR3
ENHFILTEN4
ENHFILT4
ODR4
ENHFILTEN5
ENHFILT5
ODR5
ENHFILTEN6
ODR6
Rev. B | Page 45 of 61
AD7172-4
Reg.
0x2F
Name
FILTCON7
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
OFFSET0
OFFSET1
OFFSET2
OFFSET3
OFFSET4
OFFSET5
OFFSET6
OFFSET7
GAIN0
GAIN1
GAIN2
GAIN3
GAIN4
GAIN5
GAIN6
GAIN7
Data Sheet
Bits
[15:8]
[7:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
Bit 7
SINC3_MAP3
RESERVED
Bit 6
Bit 5
Bit 4
RESERVED
ORDER7
Bit 3
Bit 2
ENHFILTEN7
ODR7
OFFSET0[23:0]
OFFSET1[23:0]
OFFSET2[23:0]
OFFSET3[23:0]
OFFSET5[23:0]
OFFSET6[23:0]
OFFSET6[23:0]
OFFSET7[23:0]
GAIN0[23:0]
GAIN1[23:0]
GAIN2[23:0]
GAIN3[23:0]
GAIN4[23:0]
GAIN5[23:0]
GAIN6[23:0]
GAIN7[23:0]
Rev. B | Page 46 of 61
Bit 1
ENHFILT7
Bit 0
Reset
0x0500
RW
RW
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Data Sheet
AD7172-4
REGISTER DETAILS
COMMUNICATIONS REGISTER
Address: 0x00, Reset: 0x00, Name: COMMS
All access to the on-chip registers must start with a write to the communications register. This write determines what register is accessed
next and whether the operation is a write or a read.
Table 26. Bit Descriptions for COMMS
Bits
7
Bit Name
WEN
6
R/W
Settings
0
1
[5:0]
RA
000000
000001
000010
000011
000100
000110
000111
010000
010001
010010
010011
010100
010101
010110
010111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Description
This bit must be low to begin communications with the ADC.
Reset
0x0
Access
W
This bit determines if the command is a read or write operation.
0x0
W
0x00
W
Write command
Read command
The register address bits determine which register is to be read from or written to as part of the current communication.
Status register
ADC mode register
Interface mode register
Register check register
Data register
GPIO configuration register
ID register
Channel Register 0
Channel Register 1
Channel Register 2
Channel Register 3
Channel Register 4
Channel Register 5
Channel Register 6
Channel Register 7
Setup Configuration Register 0
Setup Configuration Register 1
Setup Configuration Register 2
Setup Configuration Register 3
Setup Configuration Register 4
Setup Configuration Register 5
Setup Configuration Register 6
Setup Configuration Register 7
Filter Configuration Register 0
Filter Configuration Register 1
Filter Configuration Register 2
Filter Configuration Register 3
Filter Configuration Register 4
Filter Configuration Register 5
Filter Configuration Register 6
Filter Configuration Register 7
Offset Register 0
Offset Register 1
Offset Register 2
Offset Register 3
Offset Register 4
Offset Register 5
Offset Register 6
Offset Register 7
Gain Register 0
Gain Register 1
Gain Register 2
Gain Register 3
Gain Register 4
Gain Register 5
Gain Register 6
Gain Register 7
Rev. B | Page 47 of 61
AD7172-4
Data Sheet
STATUS REGISTER
Address: 0x00, Reset: 0x80, Name: STATUS
The status register is an 8-bit register that contains ADC and serial interface status information. It can optionally be appended to the data
register by setting the DATA_STAT bit in the interface mode register.
Table 27. Bit Descriptions for STATUS
Bits
7
Bit Name
RDY
Settings
0
1
6
ADC_ERROR
0
1
5
CRC_ERROR
0
1
4
REG_ERROR
0
1
3
[2:0]
RESERVED
CHANNEL
000
001
010
011
100
101
110
111
Description
The status of RDY is output to the DOUT/RDYpin whenever CS is low and a
register is not being read. This bit goes low when the ADC has written a
new result to the data register. In ADC calibration modes, this bit goes low
when the ADC has written the calibration result. RDY is brought high
automatically by a read of the data register.
New data result available
Awaiting new data result
This bit by default indicates if an ADC overrange or underrange has
occurred. The ADC result is clamped to 0xFFFFFF for overrange errors and
0x000000 for underrange errors. This bit is updated when the ADC result is
written and is cleared at the next update after removing the overrange or
underrange condition.
No error
Error
This bit indicates if a CRC error has taken place during a register write. For
register reads, the host microcontroller determines if a CRC error has
occurred. This bit is cleared by a read of this register.
No error
CRC error
This bit indicates if the content of one of the internal registers has
changed from the value calculated when the register integrity check was
activated. The check is activated by setting the REG_CHECK bit in the
interface mode register. This bit is cleared by clearing the REG_CHECK bit.
No error
Error
These bits are reserved.
These bits indicate which channel was active for the ADC conversion
whose result is currently in the data register. This may be different from
the channel currently being converted. The mapping is a direct map from
the channel register; therefore, Channel 0 results in 0x0 and Channel 7
results in 0x7.
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Rev. B | Page 48 of 61
Reset
0x1
Access
R
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R
Data Sheet
AD7172-4
ADC MODE REGISTER
Address: 0x01, Reset: 0x2000, Name: ADCMODE
The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets
the filter and the RDY bits and starts a new conversion or calibration.
Table 28. Bit Descriptions for ADCMODE
Bits
15
14
Bit Name
RESERVED
HIDE_DELAY
Settings
0
1
13
SING_CYC
0
1
[12:11]
[10:8]
RESERVED
DELAY
000
001
010
011
100
101
110
111
7
[6:4]
RESERVED
MODE
000
001
010
011
100
110
111
[3:2]
CLOCKSEL
00
01
10
11
[1:0]
RESERVED
Description
Reserved
If a programmable delay is set using the DELAY bits, this bit allows the
delay to be hidden by absorbing the delay into the conversion time for
selected data rates with the sinc5 + sinc1 filter. See the Delay section for
more information.
Enabled
Disabled
This bit can be used when only a single channel is active to set the ADC
to only output at the settled filter data rate.
Disabled
Enabled
These bits are reserved; set these bits to 0.
These bits allow a programmable delay to be added after a channel
switch to allow settling of external circuitry before the ADC starts
processing its input.
0 μs
32 μs
128 μs
320 μs
800 μs
1.6 ms
4 ms
8 ms
This bit is reserved; set this bit to 0.
These bits control the operating mode of the ADC. See the Operating
Modes section for more information.
Continuous conversion mode
Single conversion mode
Standby mode
Power-down mode
Internal offset calibration
System offset calibration
System gain calibration
This bit is used to select the ADC clock source. Selecting internal
oscillator also enables the internal oscillator.
Internal oscillator
Internal oscillator output on the XTAL2/CLKIO pin
External clock input on the XTAL2/CLKIO pin
External crystal on the XTAL1 and XTAL2/CLKIO pins
These bits are reserved; set these bits to 0.
Rev. B | Page 49 of 61
Reset
0x0
0x0
Access
RW
RW
0x1
RW
0x0
0x0
R
RW
0x0
0x0
R
RW
0x0
RW
0x0
R
AD7172-4
Data Sheet
INTERFACE MODE REGISTER
Address: 0x02, Reset: 0x0000, Name: IFMODE
The interface mode register configures various serial interface options.
Table 29. Bit Descriptions for IFMODE
Bits
[15:13]
12
Bit Name
RESERVED
ALT_SYNC
Settings
0
1
11
IOSTRENGTH
0
1
[10:9]
8
RESERVED
DOUT_RESET
0
1
7
CONTREAD
0
1
6
DATA_STAT
0
1
5
REG_CHECK
0
1
4
[3:2]
RESERVED
CRC_EN
00
01
10
1
RESERVED
Description
These bits are reserved; set these bits to 0.
This bit enables a different behavior of the SYNC pin to allow the use of
SYNC as a control for conversions when cycling channels (see the
description of the SYNC_EN bit in the GPIO Configuration Register section
for details).
Disabled
Enabled
This bit controls the drive strength of the DOUT/RDY pin. Set this bit when
reading from the serial interface at high speed with a low IOVDD supply
and moderate capacitance.
Disabled (default)
Enabled
These bits are reserved; set these bits to 0.
See the DOUT_RESET section for more information.
Disabled
Enabled
This enables a continuous read of the ADC data register. The ADC must be
configured in continuous conversion mode to use continuous read. For
more details, see the Operating Modes section.
Disabled
Enabled
This enables the status register to be appended to the data register when
read so that the channel and status information are transmitted with the
data. This is the only way to ensure that the channel bits read from the
status register correspond to the data in the data register.
Disabled
Enabled
This bit enables a register integrity checker, which can be used to monitor
any change in the value of the user registers. To use this feature, configure
all other registers as desired, with this bit cleared. Then write to this register to
set the REG_CHECK bit to 1. If the contents of any of the registers change,
the REG_ERROR bit is set in the status register. To clear the error, set the
REG_CHECK bit to 0. Neither the interface mode register nor the ADC data
or status registers are included in the registers that are checked. If a
register must have a new value written, this bit must first be cleared;
otherwise, an error is flagged when the new register contents are written.
Disabled
Enabled
This bit is reserved; set this bit to 0.
Enables CRC protection of register reads/writes. CRC increases the
number of bytes in a serial interface transfer by one. See the CRC
Calculation section for more details.
Disabled
XOR checksum enabled for register read transactions; register writes still
use CRC with these bits set
CRC checksum enabled for read and write transactions
This bit is reserved; set this bit to 0.
Rev. B | Page 50 of 61
Reset
0x0
0x0
Access
R
RW
0x0
RW
0x0
0x0
R
RW
0x0
RW
0x0
RW
0x0
RW
0x0
0x00
R
RW
0x0
R
Data Sheet
Bits
0
Bit Name
WL16
AD7172-4
Settings
0
1
Description
This bit changes the ADC data register to 16 bits. The ADC is not reset by a
write to the interface mode register; therefore, the ADC result is not
rounded to the correct word length immediately after writing to this bit.
The first new ADC result is correct.
24-bit data
16-bit data
Reset
0x0
Access
RW
REGISTER CHECK
Address: 0x03, Reset: 0x000000, Name: REGCHECK
The register check register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK bit
in the interface mode register must be set for this register to operate; otherwise, the register reads 0.
Table 30. Bit Descriptions for REGCHECK
Bits
[23:0]
Bit Name
REGISTER_CHECK
Settings
Description
This register contains the 24-bit checksum of user registers when the
REG_CHECK bit is set in the interface mode register.
Reset
0x000000
Access
R
DATA REGISTER
Address: 0x04, Reset: 0x000000, Name: DATA
The data register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the
BI_UNIPOLARx bits in the setup configuration registers. Reading the data register brings the RDY bit and the RDY output high ifthey
are low. The ADC result can be read multiple times; however, because the RDY output has been brought high, it is not possible to know if
another ADC result is imminent. After the command to read the ADC register is received, the ADC does not write a new result into the
data register.
Table 31. Bit Descriptions for DATA
Bits
[23:0]
Bit Name
DATA
Settings
Description
This register contains the ADC conversion result. If DATA_STAT is set in
the interface mode register, the status register is appended to this
register when read, making this a 32-bit register. If WL16 is set in the
interface mode register, this register is reduced to 16 bits.
Rev. B | Page 51 of 61
Reset
0x000000
Access
R
AD7172-4
Data Sheet
GPIO CONFIGURATION REGISTER
Address: 0x06, Reset: 0x0800, Name: GPIOCON
The GPIO configuration register controls the general-purpose input/output pins of the ADC.
Table 32. Bit Descriptions for GPIOCON
Bits
15
14
Bit Name
RESERVED
PDSW
13
OP_EN2_3
12
MUX_IO
11
SYNC_EN
Settings
0
1
[10:9]
ERR_EN
00
01
10
11
8
ERR_DAT
7
6
5
GP_DATA3
GP_DATA2
IP_EN1
0
1
Description
These bits are reserved; set these bits to 0.
This bit enables/disables the power-down switch function. Setting the bit allows
the pin to sink current. This function can be used for bridge sensor applications
where the switch controls the power-up/power-down of the bridge.
This bit enables the GPO2 and GPO3 pins. Outputs are referenced between AVDD1
and AVSS.
This bit allows the ADC to control an external multiplexer, using GPIO0/GPIO1/ GPO2 in
sync with the internal channel sequencing. The analog input pins used for a channel
can still be selected on a per channel basis. Therefore, it is possible to have a 8channel multiplexer in front of each analog input pair (AIN0/AIN1 to AIN6/AIN7),
giving a total of 32 differential channels. However, only 8 channels at a time can be
automatically sequenced. Following the sequence of 8 channels, the user must employ
an SPI command to change the selected analog input pair before it sequences through
the next 8 channels supplied by the external multiplexer.
There is a delay function that allows extra time for the analog input to settle, in
conjunction with any switching from an external multiplexer (see the delay bits in the
ADC Mode Register section).
This bit enables the SYNC pin as a sync input. When the pin is low, this bit holds
the ADC and filter in reset until the SYNC pin goes high. An alternative operation
of the SYNC pin is available when the ALT_SYNC bit in the interface mode register
is set. This mode only works when multiple channels are enabled. In this case, a
low on the SYNC pin does not immediately reset the filter/modulator. Instead, if
the SYNC pin is low when the channel is due to be switched, the modulator and
filter are prevented from starting a new conversion. Bringing SYNC high begins the
next conversion. This alternative sync mode allows SYNC to be used while cycling
through channels.
Disabled.
Enabled.
These bits enable the ERROR pin as an error input/output.
Disabled.
ERROR is an error input. The (inverted) readback state is OR'ed with other error
sources and is available in the ADC_ERROR bit in the status register. The ERROR pin
state can also be read from the ERR_DAT bit in this register.
ERROR is an open-drain error output. The status register error bits are OR'ed,
inverted, and mapped to the ERROR pin. The ERROR pins of multiple devices can
be wired together to a common pull-up resistor so that an error on any device can
be observed.
ERROR is a general-purpose output. The status of the pin is controlled by the
ERR_DAT bit in this register. This output is referenced between IOVDD and DGND,
as opposed to the AVDD1 and AVSS levels used by the GPIO pins. The ERROR pin
has an active pull-up in this case.
This bit determines the logic level at the ERROR pin if the pin is enabled as a
general-purpose output. This bit reflects the readback status of the pin if the pin is
enabled as an input.
This bit is the write data for GPO3.
This bit is the write data for GPO2.
This bit turns GPIO1 into an input. Inputs are referenced to AVDD1 or AVSS.
Disabled.
Enabled.
Rev. B | Page 52 of 61
Reset
0x0
0x0
Access
R
RW
0x0
RW
0x0
RW
0x1
RW
0x0
RW
0x0
RW
0x0
0x0
0x0
W
W
RW
Data Sheet
Bits
4
Bit Name
IP_EN0
AD7172-4
Settings
0
1
3
OP_EN1
0
1
2
OP_EN0
0
1
1
0
GP_DATA1
GP_DATA0
Description
This bit turns GPIO0 into an input. Inputs are referenced to AVDD1 or AVSS.
Disabled.
Enabled.
This bit turns GPIO1 into an output. Outputs are referenced between AVDD1 and AVSS.
Disabled.
Enabled.
This bit turns GPIO0 into an output. Outputs are referenced between AVDD1 and AVSS.
Disabled.
Enabled.
This bit is the readback or write data for GPIO1.
This bit is the readback or write data for GPIO0.
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
0x0
RW
RW
ID REGISTER
Address: 0x07, Reset: 0x205X, Name: ID
The ID register returns a 16-bit ID. For the AD7172-4, this ID is 0x205X.
Table 33. Bit Descriptions for ID
Bits
[15:0]
Bit Name
ID
Settings
0x205X
Description
The ID register returns a 16-bit ID code that is specific to the ADC.
AD7172-4
Rev. B | Page 53 of 61
Reset
0x205X
Access
R
AD7172-4
Data Sheet
CHANNEL REGISTER 0
Address: 0x10, Reset: 0x8001, Name: CH0
The channel registers are 16-bit registers that select which channels are currently active, which inputs are selected for each channel, and
which setup is used to configure the ADC for that channel.
Table 34. Bit Descriptions for CH0
Bits
15
Bit Name
CH_EN0
Settings
0
1
[14:12]
SETUP_SEL0
000
001
010
011
100
101
110
111
[11:10]
[9:5]
RESERVED
AINPOS0
00000
00001
00010
00011
00100
00101
00110
00111
01000
10011
10100
10101
10110
[4:0]
AINNEG0
00000
00001
00010
00011
00100
00101
00110
00111
01000
10011
10100
10101
10110
Description
This bit enables Channel 0. If more than one channel is enabled, the ADC
automatically sequences between them.
Disabled
Enabled (default)
These bits identify which of the eight setups are used to configure the ADC for this
channel. A setup comprises a set of four registers: the setup configuration register, the
filter configuration register, the offset register, and the gain register. All channels can
use the same setup, in which case the same 2-bit value must be written to these bits on
all active channels, or up to eight channels can be configured differently.
Setup 0
Setup 1
Setup 2
Setup 3
Setup 4
Setup 5
Setup 6
Setup 7
These bits are reserved; set these bits to 0.
These bits select which input is connected to the positive input of the ADC for this
channel.
AIN0 (default)
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
((AVDD1 − AVSS)/5)+ (analog input buffers must be enabled)
((AVDD1 − AVSS)/5)− (analog input buffers must be enabled)
REF+
REF−
These bits select which input is connected to the negative input of the ADC for this
channel.
AIN0
AIN1 (default)
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
((AVDD1 − AVSS)/5)+
((AVDD1 − AVSS)/5)−
REF+
REF−
Rev. B | Page 54 of 61
Reset
0x1
Access
RW
0x0
RW
0x0
0x0
R
RW
0x1
RW
Data Sheet
AD7172-4
CHANNEL REGISTER 1 TO CHANNEL REGISTER 7
Address: 0x11 to 0x17, Reset: 0x0001, Name: CH1 to CH7
The remaining seven channel registers share the same layout as Channel Register 0.
Table 35. CH1 to CH7 Register Map
Reg.
0x11
Name
CH1
Bits
[15:8]
[7:0]
Bit 7
CH_EN1
0x12
CH2
[15:8]
[7:0]
CH_EN2
[15:8]
[7:0]
CH_EN3
[15:8]
[7:0]
CH_EN4
[15:8]
[7:0]
CH_EN5
[15:8]
[7:0]
CH_EN6
[15:8]
[7:0]
CH_EN7
0x13
0x14
0x15
0x16
0x17
CH3
CH4
CH5
CH6
CH7
Bit 6
Bit 5
SETUP_SEL1
Bit 4
AINPOS1[2:0]
Bit 3
Bit 2
RESERVED
AINNEG1
Bit 1
Bit 0
AINPOS1[4:3]
Reset
0x0001
RW
RW
SETUP_SEL2
RESERVED
AINNEG2
AINPOS2[4:3]
0x0001
RW
SETUP_SEL3
RESERVED
AINNEG3
AINPOS3[4:3]
0x0001
RW
SETUP_SEL4
RESERVED
AINNEG4
AINPOS4[4:3]
0x0001
RW
SETUP_SEL5
RESERVED
AINNEG5
AINPOS5[4:3]
0x0001
RW
SETUP_SEL6
RESERVED
AINNEG6
AINPOS6[4:3]
0x0001
RW
SETUP_SEL7
RESERVED
AINNEG7
AINPOS7[4:3]
0x0001
RW
AINPOS2[2:0]
AINPOS3[2:0]
AINPOS4[2:0]
AINPOS5[2:0]
AINPOS6[2:0]
AINPOS7[2:0]
Rev. B | Page 55 of 61
AD7172-4
Data Sheet
SETUP CONFIGURATION REGISTER 0
Address: 0x20, Reset: 0x1000, Name: SETUPCON0
The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC.
Table 36. Bit Descriptions for SETUPCON0
Bits
[15:13]
12
Bit Name
RESERVED
BI_UNIPOLAR0
Settings
0
1
11
REFBUF0+
0
1
10
REFBUF0−
0
1
9
AINBUF0+
0
1
8
AINBUF0−
0
1
7
BURNOUT_EN0
6
[5:4]
RESERVED
REF_SEL0
00
01
11
[3:0]
RESERVED
Description
These bits are reserved; set these bits to 0.
This bit sets the output coding of the ADC for Setup 0.
Unipolar coded output
Bipolar coded output (offset binary)
This bit enables or disables the REF+ input buffer.
REF+ buffer disabled
REF+ buffer enabled
This bit enables or disables the REF− input buffer.
REF− buffer disabled
REF− buffer enabled
This bit enables or disables the AIN+ input buffer.
AIN+ buffer disabled
AIN+ buffer enabled
This bit enables or disables the AIN− input buffer.
AIN− buffer disabled
AIN− buffer enabled
This bit enables a 10 μA current source on the positive analog input
selected and a 10 μA current sink on the negative analog input selected.
The burnout currents are useful in diagnosis of an open wire, whereby
the ADC result goes to full scale. Enabling the burnout currents during
measurement results in an offset voltage on the ADC. The best strategy
for diagnosing an open wire is turning on the burnout currents at
intervals, before or after precision measurements.
These bits are reserved; set these bits to 0.
These bits allow the user to select the reference source for ADC
conversion on Setup 0.
External reference supplied to the REF+ and REF− pins.
External Reference 2 supplied to AIN1/REF2+ and AIN0/REF2− pins.
AVDD1 − AVSS. This can be used to as a diagnostic to validate other
reference values.
These bits are reserved; set these bits to 0.
Rev. B | Page 56 of 61
Reset
0x0
0x1
Access
R
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x00
R
0x00
0x0
R
RW
0x0
R
Data Sheet
AD7172-4
SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7
Address: 0x21 to 0x27, Reset: 0x1000, Name: SETUPCON1 to SETUPCON7
The remaining seven setup configuration registers share the same layout as Setup Configuration Register 0.
Table 37. SETUPCON1 to SETUPCON7 Register Map
Reg.
0x21
Name
SETUPCON1
0x22
SETUPCON2
0x23
0x24
0x25
0x26
0x27
SETUPCON3
SETUPCON4
SETUPCON5
SETUPCON6
SETUPCON7
Bits
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
Bit 7
BURNOUT_EN1
BURNOUT_EN2
BURNOUT_EN3
BURNOUT_EN4
BURNOUT_EN5
BURNOUT_EN6
BURNOUT_EN7
Bit 6
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Bit 5
Bit 4
BI_UNIPOLAR1
REF_SEL1
BI_UNIPOLAR2
REF_SEL2
BI_UNIPOLAR3
REF_SEL3
BI_UNIPOLAR4
REF_SEL4
BI_UNIPOLAR5
REF_SEL5
BI_UNIPOLAR6
REF_SEL6
BI_UNIPOLAR7
REF_SEL7
Rev. B | Page 57 of 61
Bit 3
REFBUF1+
REFBUF2+
REFBUF3+
REFBUF4+
REFBUF5+
REFBUF6+
REFBUF7+
Bit 2
Bit 1
REFBUF1−
AINBUF1+
RESERVED
REFBUF2−
AINBUF2+
RESERVED
REFBUF3−
AINBUF3+
RESERVED
REFBUF4−
AINBUF4+
RESERVED
REFBUF5−
AINBUF5+
RESERVED
REFBUF6−
AINBUF6+
RESERVED
REFBUF7−
AINBUF7+
RESERVED
Bit 0
AINBUF1−
Reset
0x1000
RW
RW
AINBUF2−
0x1000
RW
AINBUF3−
0x1000
RW
AINBUF4−
0x1000
RW
AINBUF5−
0x1000
RW
AINBUF6−
0x1000
RW
AINBUF7−
0x1000
RW
AD7172-4
Data Sheet
FILTER CONFIGURATION REGISTER 0
Address: 0x28, Reset: 0x0500, Name: FILTCON0
The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers
resets any active ADC conversion and restarts converting at the first channel in the sequence.
Table 38. Bit Descriptions for FILTCON0
Bits
15
Bit Name
SINC3_MAP0
[14:12]
11
RESERVED
ENHFILTEN0
Settings
0
1
[10:8]
ENHFILT0
010
011
101
110
7
[6:5]
RESERVED
ORDER0
00
11
[4:0]
ODR0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
Description
If this bit is set, the mapping of the filter register changes to directly
program the decimation rate of the sinc3 filter for Setup 0. All other
options are eliminated. This allows fine tuning of the output data rate and
filter notch for rejection of specific frequencies. The data rate when on a
single channel equals fMOD/(32 × FILTCON0[14:0]).
These bits are reserved; set these bits to 0.
This bit enables various postfilters for enhanced 50 Hz and 60 Hz rejection
for Setup 0. The ORDER0 bits must be set to 00 to select the sinc5 + sinc1
filter for this to work.
Disabled
Enabled
These bits select between various postfilters for enhanced 50 Hz and
60 Hz rejection for Setup 0.
27 SPS, 47 dB rejection, 36.7 ms settling
21.25 SPS, 62 dB rejection, 40 ms settling
20 SPS, 86 dB rejection, 50 ms settling
16.67 SPS, 92 dB rejection, 60 ms settling
This bit is reserved; set this bit to 0.
These bits control the order of the digital filter that processes the
modulator data for Setup 0.
Sinc5 + sinc1 (default)
Sinc3
These bits control the output data rate of the ADC and, therefore, the
settling time and noise for Setup 0. Rates shown are for the sinc5 + sinc1
filter. See Table 20 to Table 23.
31,250
31,250
31,250
31,250
31,250
31,250
15,625
10,417
5208
2597
1007
503.8
381
200.3
100.2
59.52
49.68
20.01
16.63
10
5
2.5
1.25
Rev. B | Page 58 of 61
Reset
0x0
Access
RW
0x0
0x0
R
RW
0x5
RW
0x0
0x0
R
RW
0x0
RW
Data Sheet
AD7172-4
FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7
Address: 0x29 to 0x2F, Reset: 0x0500, Name: FILTCON1 to FILTCON7
The remaining seven filter configuration registers share the same layout as Filter Configuration Register 0.
Table 39. FILTCON1 to FILTCON7 Register Map
Reg.
0x29
Name
FILTCON1
Bits
[15:8]
[7:0]
Bit 7
SINC3_MAP1
RESERVED
0x2A
FILTCON2
[15:8]
[7:0]
SINC3_MAP2
RESERVED
RESERVED
ORDER2
ENHFILTEN2
[15:8]
[7:0]
SINC3_MAP3
RESERVED
RESERVED
ORDER3
ENHFILTEN3
[15:8]
[7:0]
SINC3_MAP4
RESERVED
RESERVED
ORDER4
ENHFILTEN4
[15:8]
[7:0]
SINC3_MAP5
RESERVED
RESERVED
ORDER5
ENHFILTEN5
[15:8]
[7:0]
SINC3_MAP6
RESERVED
RESERVED
ORDER6
ENHFILTEN6
[15:8]
[7:0]
SINC3_MAP7
RESERVED
RESERVED
ORDER7
ENHFILTEN7
0x2B
0x2C
0x2D
0x2E
0x2F
FILTCON3
FILTCON4
FILTCON5
FILTCON6
FILTCON7
Bit 6
Bit 5
RESERVED
ORDER1
Bit 4
Bit 3
ENHFILTEN1
Bit 2
Bit 1
ENHFILT1
Bit 0
Reset
0x0500
RW
RW
ENHFILT2
0x0500
RW
ENHFILT3
0x0500
RW
ENHFILT4
0x0500
RW
ENHFILT5
0x0500
RW
ENHFILT6
0x0500
RW
ENHFILT7
0x0500
RW
ODR1
ODR2
ODR3
ODR4
ODR5
ODR6
ODR7
OFFSET REGISTER 0
Address: 0x30, Reset: 0x800000, Name: OFFSET0
The offset (zero-scale) registers are 24-bit registers that compensate for any offset error in the ADC or in the system.
Table 40. Bit Descriptions for OFFSET0
Bits
[23:0]
Bit Name
OFFSET0
Settings
Description
Offset calibration coefficient for Setup 0.
Reset
0x800000
Access
RW
OFFSET REGISTER 1 TO OFFSET REGISTER 7
Address: 0x31 to 0x33, Reset: 0x800000, Name: OFFSET1 to OFFSET7
The remaining seven offset registers share the same layout as Offset Register 0.
Table 41. OFFSET1 to OFFSET7 Register Map
Reg.
0x31
0x32
0x33
0x34
0x35
0x36
0x37
Name
OFFSET1
OFFSET2
OFFSET3
OFFSET4
OFFSET5
OFFSET6
OFFSET7
Bits
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
OFFSET1[23:0]
OFFSET2[23:0]
OFFSET3[23:0]
OFFSET4[23:0]
OFFSET5[23:0]
OFFSET6[23:0]
OFFSET7[23:0]
Rev. B | Page 59 of 61
Reset
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
RW
RW
RW
RW
RW
RW
RW
RW
AD7172-4
Data Sheet
GAIN REGISTER 0
Address: 0x38, Reset: 0x5XXXX0, Name: GAIN0
The gain (full-scale) registers are 24-bit registers that compensate for any gain error in the ADC or in the system.
Table 42. Bit Descriptions for GAIN0
Bits
[23:0]
Bit Name
GAIN0
Settings
Description
Gain calibration coefficient for Setup 0.
Reset
0x5XXXX0
Access
RW
GAIN REGISTER 1 TO GAIN REGISTER 7
Address: 0x39 to 0x3F, Reset: 0x5XXXX0, Name: GAIN1 to GAIN7
The remaining seven gain registers share the same layout as Gain Register 0.
Table 43. GAIN1 to GAIN7 Register Map
Reg.
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
Name
GAIN1
GAIN2
GAIN3
GAIN4
GAIN5
GAIN6
GAIN7
Bits
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
GAIN1[23:0]
GAIN2[23:0]
GAIN3[23:0]
GAIN4[23:0]
GAIN5[23:0]
GAIN6[23:0]
GAIN7[23:0]
Rev. B | Page 60 of 61
Reset
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
RW
RW
RW
RW
RW
RW
RW
RW
Data Sheet
AD7172-4
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
32
25
1
24
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
8
17
TOP VIEW
0.80
0.75
0.70
TOP VIEW
PKG-004570
SEATING
PLANE
0.50
0.40
0.30
16
9
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.
02-22-2017-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 72. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD7172-4BCPZ
AD7172-4BCPZ-RL
AD7172-4BCPZ-RL7
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12676-0-4/17(B)
Rev. B | Page 61 of 61
Package Option
CP-32-12
CP-32-12
CP-32-12
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