AD7192

4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA AD7192 FEATURES RMS noise: 11 nV @ 4.7 Hz (gain = 128) 15.5 noise-free bits @ 2.4 kHz (gain = 128) Up to 22 noise-free bits (gain = 1) Offset drift: 5 nV/°C Gain drift: 1 ppm/°C Specified drift over time 2 differential/4 pseudo differential input channels Automatic channel sequencer Programmable gain (1 to 128) Output data rate: 4.7 Hz to 4.8 kHz Internal or external clock Simultaneous 50 Hz/60 Hz rejection 4 general-purpose digital outputs Power supply AVDD: 3 V to 5.25 V DVDD: 2.7 V to 5.25 V Current: 4.35 mA Temperature range: –40°C to +105°C Package: 24-lead TSSOP Temperature measurement Chromatography PLC/DCS analog input modules Data acquisition Medical and scientific instrumentation GENERAL DESCRIPTION The AD7192 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC. The device can be configured to have two differential inputs or four pseudo differential inputs. The on-chip channel sequencer allows several channels to be enabled, and the AD7192 sequentially converts on each enabled channel. This simplifies communication with the part. The on-chip 4.92 MHz clock can be used as the clock source to the ADC or, alternatively, an external clock or crystal can be used. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz. The device has two digital filter options. The choice of filter affects the rms noise/noise-free resolution at the programmed output data rate, the settling time, and the 50 Hz/60 Hz rejection. For applications that require all conversions to be settled, the AD7192 includes a zero latency feature. The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 4.35 mA. It is housed in a 24-lead TSSOP package. INTERFACE 3-wire serial SPI, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK APPLICATIONS Weigh scales Strain gage transducers Pressure measurement AGND AVDD FUNCTIONAL BLOCK DIAGRAM DVDD DGND REFIN1(+) REFIN1(–) REFERENCE DETECT AIN1 AIN2 AIN3 AIN4 AINCOM AVDD AD7192 MUX PGA Σ-Δ ADC SERIAL INTERFACE AND CONTROL LOGIC DOUT/RDY DIN SCLK CS SYNC AGND BPDSW TEMP SENSOR CLOCK CIRCUITRY P3 P2 MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. 07822-001 AGND AD7192 TABLE OF CONTENTS Features .............................................................................................. 1 Interface ............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics..................................................................... 7 Circuit and Timing Diagrams..................................................... 7 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 RMS Noise and Resolution............................................................ 14 Sinc Chop Disabled ................................................................... 14 Sinc Chop Disabled ................................................................... 15 Sinc Chop Enabled .................................................................... 16 Sinc Chop Enabled .................................................................... 17 On-Chip Registers .......................................................................... 18 Communications Register ......................................................... 18 Status Register ............................................................................. 19 Mode Register ............................................................................. 19 Configuration Register .............................................................. 21 Data Register ............................................................................... 23 ID Register ................................................................................... 23 GPOCON Register ..................................................................... 24 3 4 3 4 Offset Register ............................................................................ 24 Full-Scale Register ...................................................................... 24 ADC Circuit Information.............................................................. 25 Overview ..................................................................................... 25 Filter, Output Data Rate, and Settling Time ........................... 25 Digital Interface .......................................................................... 28 Circuit Description......................................................................... 32 Analog Input Channel ............................................................... 32 Programmable Gain Array (PGA) ........................................... 32 Bipolar/Unipolar Configuration .............................................. 32 Data Output Coding .................................................................. 32 Clock ............................................................................................ 32 Burnout Currents ....................................................................... 33 Reference ..................................................................................... 33 Reference Detect ......................................................................... 33 Reset ............................................................................................. 34 System Synchronization ............................................................ 34 Temperature Sensor ................................................................... 34 Bridge Power-Down Switch ...................................................... 34 Logic Outputs ............................................................................. 34 Enable Parity ............................................................................... 35 Calibration................................................................................... 35 Grounding and Layout .............................................................. 36 Applications Information .............................................................. 37 Weigh Scales ................................................................................ 37 Outline Dimensions ....................................................................... 38 Ordering Guide .......................................................................... 38 REVISION HISTORY 5/09—Rev. 0 to Rev. A Change to Gain Error Specification ............................................... 3 Changes to Table 3 ............................................................................ 9 5/09—Revision 0: Initial Version Rev. A | Page 2 of 40 AD7192 SPECIFICATIONS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = AVDD, REFINx(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter ADC Output Data Rate AD7192B 4.7 to 4800 1.17 to 1200 1.56 to 1600 24 24 Unit Hz nom Hz nom Hz nom Bits min Bits min Test Conditions/Comments1 Chop disabled Chop enabled, sinc4 filter Chop enabled, sinc3 filter FS > 1, sinc4 filter3 FS > 4, sinc3 filter3 See the RMS Noise and Resolution section See the RMS Noise and Resolution section ±2 ppm typical, AVDD = 5 V ±2 ppm typical, AVDD = 3 V ±5 ppm typical, AVDD = 5 V ±12 ppm typical, AVDD = 3 V Chop disabled Chop enabled Gain = 1 to 16; chop disabled Gain = 32 to 128; chop disabled Chop enabled Gain > 32 AVDD = 5 V, gain = 1, TA = 25°C (factory calibration conditions) Gain = 128, before full-scale calibration (see Table 23) Gain > 1, after internal full-scale calibration, AVDD ≥ 4.75 V. Gain > 1, after internal full-scale calibration, AVDD < 4.75 V Gain = 1. Gain = 1, VIN = 1 V. Gain > 1, VIN = 1 V/gain, 110 dB typ. Gain = 1, VIN = 1 V. Gain > 1, VIN = 1 V/gain. 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz (60 Hz output data rate). No Missing Codes2 Resolution RMS Noise and Output Data Rates Integral Nonlinearity Gain = 12 Gain > 1 Offset Error4, 5 Offset Error Drift vs. Temperature Offset Error Drift vs. Time Gain Error4 ±10 ±15 ±30 ±30 ±150/gain ±0.5 ±150/gain ±5 ±5 25 ±0.001 −0.39 ±0.003 ±0.005 ppm of FSR max ppm of FSR max ppm of FSR max ppm of FSR max μV typ μV typ nV/°C typ nV/°C typ nV/°C typ nV/1000 hours typ % typ % typ % typ % typ ppm/°C typ ppm/1000 hours typ dB typ dB min dB min dB min dB min dB min Gain Drift vs. Temperature Gain Drift vs. Time Power Supply Rejection Common-Mode Rejection @ DC2 @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 Normal Mode Rejection2 Sinc4 Filter Internal Clock @ 50 Hz, 60 Hz ±1 10 90 95 100 110 120 120 100 74 96 97 dB min dB min dB min dB min @ 50 Hz @ 60 Hz 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, 50 ± 1 Hz. 60 Hz output data rate, 60 ± 1 Hz. Rev. A | Page 3 of 40 AD7192 Parameter External Clock @ 50 Hz, 60 Hz AD7192B 120 82 120 120 Unit dB min dB min dB min dB min Test Conditions/Comments1 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, 50 ± 1 Hz. 60 Hz output data rate, 60 ± 1 Hz. @ 50 Hz @ 60 Hz 3 Sinc Filter Internal Clock @ 50 Hz, 60 Hz 75 60 70 70 100 67 95 95 ± VREF/gain ± (AVDD – 1.25 V)/gain dB min dB min dB min dB min dB min dB min dB min dB min V nom V min/max V min V max V min V max @ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, 50 ± 1 Hz. 60 Hz output data rate, 60 ± 1 Hz. 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, 50 ± 1 Hz. 60 Hz output data rate, 60 ± 1 Hz. VREF = REFINx(+) − REFINx(−), gain = 1 to 128. Gain > 1. @ 50 Hz @ 60 Hz ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Unbuffered Mode Buffered Mode Analog Input Current Buffered Mode Input Current2 Input Current Drift Unbuffered Mode Input Current AGND − 50 mV AVDD + 50 mV AGND + 250 mV AVDD − 250 mV ±2 ±3 ±5 ±3.5 ±1 ±0.05 ±1.6 AVDD 1 AVDD GND – 50 mV AVDD + 50 mV 4.5 nA max nA max pA/°C typ μA/V typ μA/V typ nA/V/°C typ nA/V/°C typ V nom V min V max V min V max μA/V typ Gain = 1. Gain > 1. Input Current Drift REFERENCE INPUT REFIN Voltage Gain = 1, input current varies with input voltage. Gain > 1. External clock. Internal clock. REFIN = REFINx(+) − REFINx(−). The differential input must be limited to ±(AVDD – 1.25 V)/gain when gain > 1. Absolute REFIN Voltage Limits2 Average Reference Input Current Rev. A | Page 4 of 40 AD7192 Parameter Average Reference Input Current Drift Normal Mode Rejection2 Common-Mode Rejection Reference Detect Levels TEMPERATURE SENSOR Accuracy Sensitivity BRIDGE POWER-DOWN SWITCH RON Allowable Current2 BURNOUT CURRENTS AIN Current DIGITAL OUTPUTS (P0 to P3) Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current2 Floating-State Output Capacitance INTERNAL/EXTERNAL CLOCK Internal Clock Frequency Duty Cycle External Clock/Crystal Frequency Input Low Voltage VINL Input High Voltage, VINH Input Current LOGIC INPUTS Input High Voltage, VINH2 Input Low Voltage, VINL2 Hysteresis2 Input Currents LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH2 Output Low Voltage, VOL2 Output High Voltage, VOH2 Output Low Voltage, VOL2 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding AD7192B ±0.03 ±1.3 Same as for analog inputs 100 0.3 0.6 ±2 2815 10 30 500 Unit nA/V/°C typ nA/V/°C typ dB typ V min V max °C typ Codes/°C typ Ω max mA max nA nom Applies after user calibration at 25°C. Bipolar mode. Test Conditions/Comments 1 External clock. Internal clock. Continuous current. Analog inputs must be buffered and chop disabled. AVDD = 3 V, ISOURCE = 100 μA. AVDD = 3 V, ISINK = 100 μA. AVDD = 5 V, ISOURCE = 200 μA. AVDD = 5 V, ISINK = 800 μA. AVDD − 0.6 0.4 4 0.4 ±100 10 V min V max V min V max nA max pF typ 4.92 ± 4% 50:50 4.9152 2.4576/5.12 0.8 0.4 2.5 3.5 ±10 2 0.8 0.1/0.25 ±10 DVDD − 0.6 0.4 4 0.4 ±10 10 Offset binary MHz min/max % typ MHz nom MHz min/max V max V max V min V min μA max V min V max V min/V max μA max V min V max V min V max μA max pF typ DVDD = 3 V, ISOURCE = 100 μA. DVDD = 3 V, ISINK = 100 μA. DVDD = 5 V, ISOURCE = 200 μA. DVDD = 5 V, ISINK = 1.6 mA. DVDD = 5 V. DVDD = 3 V. DVDD = 3 V. DVDD = 5 V. Rev. A | Page 5 of 40 AD7192 Parameter SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS 7 Power Supply Voltage AVDD − AGND DVDD − DGND Power Supply Currents AIDD Current AD7192B 1.05 × FS −1.05 × FS 0.8 × FS 2.1 × FS Unit V max V min V min V max Test Conditions/Comments 1 3/5.25 2.7/5.25 0.6 0.85 3.2 3.6 4.5 5 0.4 0.6 1.5 3 V min/max V min/max mA max mA max mA max mA max mA max mA max mA max mA max mA typ μA max 0.53 mA typical, gain = 1, buffer off. 0.75 mA typical, gain = 1, buffer on. 2.5 mA typical, gain = 8, buffer off. 3 mA typical, gain = 8, buffer on. 3.5 mA typical, gain = 16 to 128, buffer off. 4 mA typical, gain = 16 to 128, buffer on. 0.35 mA typical, DVDD = 3 V. 0.5 mA typical, DVDD = 5 V. External crystal used. DIDD Current IDD (Power-Down Mode) 1 2 Temperature range: −40°C to +105°C. Specification is not production tested but is supported by characterization data at initial product release. 3 FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system fullscale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 5 The analog inputs are configured for differential mode. 6 REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection. 7 Digital inputs equal to DVDD or DGND. Rev. A | Page 6 of 40 AD7192 TIMING CHARACTERISTICS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2. Parameter t3 t4 READ OPERATION t1 Limit at TMIN, TMAX (B Version) 100 100 0 60 80 0 60 80 10 80 0 10 0 30 25 0 Unit ns min ns min ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min ns min ns min ns min ns min Conditions/Comments 1, 2 SCLK high pulse width SCLK low pulse width CS falling edge to DOUT/RDY active time DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V SCLK active edge to data valid delay 4 DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V Bus relinquish time after CS inactive edge SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high CS falling edge to SCLK active edge setup time4 Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time t2 3 t5 5, 6 t6 t7 WRITE OPERATION t8 t9 t10 t11 1 2 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. CIRCUIT AND TIMING DIAGRAMS ISINK (1.6mA WITH DVDD = 5V, 100µA WITH DVDD = 3V) TO OUTPUT PIN 50pF 1.6V ISOURCE (200µA WITH DVDD = 5V, 100µA WITH DVDD = 3V) Figure 2. Load Circuit for Timing Characterization Rev. A | Page 7 of 40 07822-002 AD7192 CS (I) t1 DOUT/RDY (O) MSB LSB t6 t5 t2 t3 SCLK (I) t7 t4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t8 SCLK (I) t11 t9 t10 DIN (I) MSB LSB 07822-004 I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev. A | Page 8 of 40 07822-003 AD7192 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to AGND DVDD to AGND AGND to DGND Analog Input Voltage to AGND Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND AIN/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Temperature, Soldering Reflow Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V 10 mA −40°C to +105°C −65°C to +150°C 150°C 260°C THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 24-Lead TSSOP θJA 128 θJC 42 Unit °C/W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 9 of 40 AD7192 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS MCLK1 1 MCLK2 2 SCLK 3 CS 4 P3 5 P2 6 P1/REFIN2(+) 7 P0/REFIN2(–) 8 NC 9 AINCOM 10 AIN1 11 AIN2 12 24 23 22 DIN DOUT/RDY SYNC DVDD AVDD DGND AGND BPDSW REFIN1(–) REFIN1(+) AIN4 07822-005 AD7192 TOP VIEW (Not to Scale) 21 20 19 18 17 16 15 14 13 AIN3 NC = NO CONNECT Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 Mnemonic MCLK1 MCLK2 Description When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. Master Clock Signal for the Device. The AD7192 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7192 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected. Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data. Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as REFIN2(−). This reference input can lie anywhere between AGND and AVDD − 1 V. No Connect. This pin should be tied to AGND. Analog inputs AIN1 to AIN4 are referenced to this input when configured for pseudodifferential operation. Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN2 or as a pseudodifferential input when used with AINCOM. Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN1 or as a pseudodifferential input when used with AINCOM. 3 SCLK 4 CS 5 6 7 P3 P2 P1/REFIN2(+) 8 P0/REFIN2(−) 9 10 11 12 NC AINCOM AIN1 AIN2 Rev. A | Page 10 of 40 AD7192 Pin No. 13 14 15 Mnemonic AIN3 AIN4 REFIN1(+) Description Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN4 or as a pseudodifferential input when used with AINCOM. Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudodifferential input when used with AINCOM. Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. Bridge Power-Down Switch to AGND. Analog Ground Reference Point. Digital Ground Reference Point. Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with AVDD at 5 V or vice versa. Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V with DVDD at 5 V or vice versa. Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7192 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to DVDD. Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register. 16 17 18 19 20 21 22 REFIN1(−) BPDSW AGND DGND AVDD DVDD SYNC 23 DOUT/RDY 24 DIN Rev. A | Page 11 of 40 AD7192 TYPICAL PERFORMANCE CHARACTERISTICS 8,388,884 8,388,882 8,388,880 8,388,878 CODE 45 40 35 30 25 20 15 10 5 07822-006 8,388,876 8,388,874 8,388,872 8,388,870 8,388,868 8,388,866 0 200 400 SAMPLE 600 800 1000 OCCURRENCE 8,388,870 8,388,890 CODE 8,388,910 8,388,930 Figure 6. Noise (VREF = AVDD = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) 200 Figure 9. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc4 Filter) 8,389,050 8,389,000 150 OCCURRENCE 8,388,950 8,388,900 CODE 100 8,388,850 8,388,800 50 8,388,750 8,388,700 07822-007 8,388,869 8,388,873 8,388,877 CODE 8,388,881 8,388,885 0 200 400 SAMPLE 600 800 1000 Figure 7. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) 8,388,940 8,388,930 8,388,920 8,388,910 8,388,900 CODE Figure 10. Noise (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) 15 8,388,890 8,388,880 8,388,870 8,388,860 8,388,850 07822-008 OCCURRENCE 10 5 0 200 400 SAMPLE 600 800 1000 8,388,800 8,388,860 8,388,920 8,388,980 8,389,040 CODE Figure 8. Noise (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc4 Filter) Figure 11. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) Rev. A | Page 12 of 40 07822-011 8,388,840 0 8,388,740 07822-010 0 8,388,865 8,388,650 07822-009 0 8,388,850 AD7192 5 4 3 INL (ppm of FSR) 0.4 0.2 0 –0.2 2 1 0 OFFSET (µV) –0.4 –0.6 –0.8 –1.0 –1 –2 –4 –1.2 07822-115 –3 –2 –1 0 VIN (V) 1 2 3 4 07822-112 –1.4 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 12. INL (Gain = 1) 20 15 10 INL (ppm of FSR) Figure 15. Offset Error (Gain = 128, Chop Disabled) 1.000008 1.000006 1.000004 1.000002 5 0 –5 –10 GAIN 1.000000 0.999998 0.999996 0.999994 0.999992 –15 –20 –0.03 0.999990 –0.02 –0.01 0 VIN (V) 0.01 0.02 0.03 07822-113 07822-116 07822-117 0.999988 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 13. INL (Gain = 128) 170 168 166 OFFSET (µV) 128.004 128.002 128.000 127.998 Figure 16. Gain Error (Gain = 1) 164 162 160 158 156 154 –60 GAIN 07822-114 127.996 127.994 127.992 127.990 127.988 –60 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. Offset Error (Gain = 1, Chop Disabled) Figure 17. Gain Error (Gain = 128) Rev. A | Page 13 of 40 AD7192 RMS NOISE AND RESOLUTION The AD7192 has a choice of two filter types: sinc4 and sinc3. In addition, the AD7192 can be operated with chop enabled or chop disabled. The following tables show the rms noise of the AD7192 for some of the output data rates and gain settings with chop disabled and enabled for the sinc4 and sinc3 filters. The numbers given are for the bipolar input range with the external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting on a single channel. The effective resolution is also shown, and the output peak-to-peak (p-p) resolution, or noise-free resolution, is listed in parentheses. It is important to note that the effective resolution is calculated using the rms noise, whereas the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there is no code flicker. These numbers are typical and are rounded to the nearest ½ LSB. SINC4 CHOP DISABLED Table 6. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 120 150 300 960 2400 4800 Settling Time (ms) 852.5 533 400 80 66.7 33.3 26.7 13.3 4.17 1.67 0.83 Gain of 1 350 425 490 2000 2100 2400 2500 3100 4800 7500 16,300 Gain of 8 50 62 85 260 273 315 335 420 690 1100 2200 Gain of 16 30 36 43 134 139 175 185 240 390 640 1200 Gain of 32 18 21 23 73 77 95 110 145 240 390 670 Gain of 64 13 15 17 46 48 64 71 95 170 273 427 Gain of 128 11 13 15 34 38 51 58 81 145 235 345 Table 7. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 120 150 300 960 2400 4800 Settling Time (ms) 852.5 533 400 80 66.7 33.3 26.7 13.3 4.17 1.67 0.83 Gain of 1 1 24 (22) 24 (22) 24 (21.5) 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 20.5 (18) 20 (17.5) 19 (16.5) Gain of 81 24 (22) 24 (21.5) 23.5 (21) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21.5 (19) 20.5 (18) 20 (17.5) 19 (16.5) Gain of 161 24 (21.5) 24 (21.5) 23.5 (21) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 20.5 (18) 19.5 (17) 19 (16.5) Gain of 321 24 (21.5) 23.5 (21) 23.5 (21) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 20 (17.5) 19.5 (17) 18.5 (16) Gain of 641 23.5 (21) 23 (20.5) 23 (20.5) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 19 (16.5) 18.5 (16) Gain of 1281 22.5 (20) 22.5 (20) 22 (19.5) 21 (18.5) 20.5 (18) 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 18 (15.5) 17.5 (15) The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. A | Page 14 of 40 AD7192 SINC3 CHOP DISABLED Table 8. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 120 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 25 20 10 3.13 1.25 0.625 Gain of 1 350 440 500 2000 2100 2400 2500 3100 5300 55800 446,000 Gain of 8 51 62 87 255 273 315 335 425 745 7100 55,400 Gain of 16 30 36 45 134 139 168 185 235 415 3600 28,000 Gain of 32 18 22 26 73 77 96 105 136 250 1750 14,000 Gain of 64 15 18 19 47 49 66 73 100 180 910 7000 Gain of 128 12 15 17 36 40 55 62 86 156 500 3500 Table 9. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 120 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 25 20 10 3.13 1.25 0.625 Gain of 1 1 24 (22) 24 (21.5) 24 (21.5) 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 20.5 (18) 17 (14.5) 14 (11.5) Gain of 81 24 (22) 24 (21.5) 23.5 (21) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21.5 (19) 20.5 (18) 17 (14.5) 14 (11.5) Gain of 161 24 (21.5) 24 (21.5) 23.5 (21) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 20.5 (18) 17 (14.5) 14 (11.5) Gain of 321 24 (21.5) 23.5 (21) 23.5 (21) 22 (19.5) 21.5 (19) 21.5 (19) 21.5 (19) 21 (18.5) 20 (17.5) 17 (14.5) 14 (11.5) Gain of 641 23 (20.5) 23 (20.5) 22.5 (20) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 17 (14.5) 14 (11.5) Gain of 1281 22.5 (20) 22 (19.5) 22 (19.5) 21 (18.5) 20.5 (18) 20 (17.5) 20 (17.5) 19.5 (17) 18.5 (16) 17 (14.5) 14 (11.5) The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. A | Page 15 of 40 AD7192 SINC4 CHOP ENABLED Table 10. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 Output Data Rate (Hz) 1.175 1.875 2.5 12.5 15 30 37.5 75 240 600 1200 Settling Time (ms) 1702 1067 800 160 133 66.7 53.3 26.7 8.33 3.33 1.67 Gain of 1 248 301 347 1420 1490 1700 1770 2200 3400 5310 11,600 Gain of 8 36 44 61 184 194 223 237 297 488 780 1560 Gain of 16 22 26 31 95 99 124 131 170 276 453 849 Gain of 32 13 15 17 52 55 68 78 103 170 276 474 Gain of 64 9 11 13 33 34 46 51 68 121 194 302 Gain of 128 8 10 11 25 27 37 42 58 103 167 244 Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 1 Output Data Rate (Hz) 1.175 1.875 2.5 12.5 15 30 37.5 75 240 600 1200 Settling Time (ms) 1702 1067 800 160 133 66.7 53.3 26.7 8.33 3.33 1.67 Gain of 1 1 24 (22.5) 24 (22.5) 24 (22) 22.5 (20) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 21 (18.5) 20.5 (18) 19.5 (17) Gain of 81 24 (22.5) 24 (22) 24 (21.5) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 22 (19.5) 21 (18.5) 20.5 (18) 19.5 (17) Gain of 161 24 (22) 24 (22) 24 (21.5) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 21.5 (19) 21 (18.5) 20 (17.5) 19.5 (17) Gain of 321 24 (22) 24 (21.5) 24 (21.5) 22.5 (20) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 20.5 (18) 20 (17.5) 19 (16.5) Gain of 641 24 (21.5) 23.5 (21) 23.5 (21) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 20 (17.5) 19.5 (17) 19 (16.5) Gain of 1281 23 (20.5) 23 (20.5) 22.5 (20) 21.5 (19) 21 (18.5) 21 (18.5) 20.5 (18) 20 (17.5) 19.5 (17) 18.5 (16) 18 (15.5) The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. A | Page 16 of 40 AD7192 SINC3 CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 Output Data Rate (Hz) 1.56 2.5 3.33 16.6 20 40 50 100 320 800 1600 Settling Time (ms) 1282 800 600 120 100 50 40 20 6.25 2.5 1.25 Gain of 1 248 312 354 1415 1485 1698 1768 2193 3748 39500 315,400 Gain of 8 37 44 62 181 194 223 237 301 527 5020 39,200 Gain of 16 22 26 32 95 99 119 131 167 294 2546 19,800 Gain of 32 13 16 19 52 55 68 75 97 177 1240 9900 Gain of 64 11 13 14 34 35 47 52 71 128 644 4950 Gain of 128 9 11 13 26 29 39 44 61 111 354 2500 Table 13. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 40 32 16 5 2 1 1 Output Data Rate (Hz) 1.56 2.5 3.33 16.6 20 40 320 100 320 800 1600 Settling Time (ms) 1282 800 600 120 100 50 40 20 6.25 2.5 1.25 Gain of 1 1 24 (22.5) 24 (22) 24 (22) 22.5 (20) 22.5 (20) 22.5 (20) 22 (19.5) 22(19.5) 21 (18.5) 17.5 (15) 14.5 (12) Gain of 81 24 (22.5) 24 (22) 24 (21.5) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 22 (19.5) 20.5 (18) 17.5 (15) 14.5 (12) Gain of 161 24 (22) 24 (22) 24 (21.5) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 21.5 (19) 20.5 (18) 17.5 (15) 14.5 (12) Gain of 321 24 (22) 24 (21.5) 24 (21.5) 22.5 (20) 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 20 (17.5) 17.5 (15) 14.5 (12) Gain of 641 23.5 (21) 23.5 (21) 23 (20.5) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 19.5 (17) 17.5 (15) 14.5 (12) Gain of 1281 23 (20.5) 22.5 (20) 22.5 (20) 21.5 (19) 21 (18.5) 20.5 (18) 20.5 (18) 20 (17.5) 18.5 (16) 17.5 (15) 14.5 (12) The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. A | Page 17 of 40 AD7192 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages. In the following descriptions, “set” implies a Logic 1 state and “cleared” implies a Logic 0 state, unless otherwise noted. or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 40 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 14 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting that the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation and in which register this operation takes place. For read or write operations, when the subsequent read CR7 WEN(0) CR6 R/W(0) CR5 RS2(0) CR4 RS1(0) CR3 RS0(0) CR2 CREAD(0) CR1 0(0) CR0 0(0) Table 14. Communications Register Bit Designations Bit Location CR7 Bit Name WEN Description Write enable bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to the communications register. Idling the DIN pin high between data transfers minimizes the effects of spurious SCLK pulses on the serial interface. A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next operation is a read from the designated register. Register address bits. These address bits are used to select which registers of the ADC are selected during the serial interface communication (see Table 15). Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for subsequent data reads. To enable continuous read, the Instruction 01011100 must be written to the communications register. To disable continuous read, the Instruction 01011000 must be written to the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low until an instruction is to be written to the device. These bits must be programmed to Logic 0 for correct operation. CR6 CR5 to CR3 CR2 R/W RS2 to RS0 CREAD CR1 to CR0 0 Table 15. Register Selection RS2 0 0 0 0 0 1 1 1 1 RS1 0 0 0 1 1 0 0 1 1 RS0 0 0 1 0 1 0 1 0 1 Register Communications register during a write operation Status register during a read operation Mode register Configuration register Data register/data register plus status information ID register GPOCON register Offset register Full-scale register Register Size 8 bits 8 bits 24 bits 24 bits 24 bits/32 bits 8 bits 8 bits 24 bits 24 bits Rev. A | Page 18 of 40 AD7192 STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 16 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. SR7 RDY(1) SR6 ERR(0) SR5 NOREF(0) SR4 PARITY(0) SR3 0(0) SR2 CHD2(0) SR1 CHD1(0) SR0 CHD0(0) Table 16. Status Register Bit Designations Bit Location SR7 Bit Name RDY Description Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register is read, or a period of time before the data register is updated, with a new conversion result to indicate to the user that the conversion data should not be read. It is also set when the part is placed in power-down mode or idle mode or when SYNC is taken low. The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. ADC error bit. This bit is written to at the same time as the RDY bit. This bit is set to indicate that the result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange or underrange or the absence of a reference voltage. This bit is cleared when the result written to the data register is within the allowed analog input range again. No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled by setting the REFDET bit in the configuration register to 1. Parity check of the data register. If the ENPAR bit in the mode register is set, the PARITY bit is set if there is an odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. This bit is set to 0. These bits indicate which channel corresponds to the data register contents. They do not indicate which channel is presently being converted but indicate which channel was selected when the conversion contained in the data register was generated. SR6 ERR SR5 NOREF SR4 PARITY SR3 SR2 to SR0 0 CHD2 to CHD0 MODE REGISTER (RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060) The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the output data rate, and the clock source. Table 17 outlines the bit designations for the mode register. MR0 through MR23 indicate the bit locations, MR denoting that the bits are in the mode register. MR23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and filter and sets the RDY bit. MR23 MD2(0) MR15 SINC3(0) MR7 FS7(0) MR22 MD1(0) MR14 0 MR6 FS6(1) MR21 MD0(0) MR13 ENPAR(0) MR5 FS5(1) MR20 DAT_STA(0) MR12 CLK_DIV(0) MR4 FS4(0) MR19 CLK1(1) MR11 SINGLE(0) MR3 FS3(0) MR18 CLK0(0) MR10 REJ60(0) MR2 FS2(0) MR17 0 MR9 FS9(0) MR1 FS1(0) MR16 0 MR8 FS8(0) MR0 FS0(0) Rev. A | Page 19 of 40 AD7192 Table 17. Mode Register Bit Designations Bit Location MR23 to MR21 MR20 Bit Name MD2 to MD0 DAT_STA Description Mode select bits. These bits select the operating mode of the AD7192 (see Table 18). This bit enables the transmission of status register contents after each data register read. When DAT_STA is set, the contents of the status register are transmitted along with each data register read. This function is useful when several channels are selected because the status register identifies the channel to which the data register value corresponds. These bits are used to select the clock source for the AD7192. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7192 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7192. CLK1 CLK0 ADC Clock Source 0 0 External crystal. The external crystal is connected from MCLK1 to MCLK2. 0 1 External clock. The external clock is applied to the MCLK2 pin. 1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated. 1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2. These bits must be programmed with a Logic 0 for correct operation. Sinc3 filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set, the sinc3 filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time. For a given output data rate, fADC, the sinc3 filter has a settling time of 3/fADC while the sinc4 filter has a settling time of 4/fADC when chop is disabled. The sinc4 filter, due to its deeper notches, gives better 50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no missing codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc4 filter gives better performance than the sinc3 filter for rms noise and no missing codes. This bit must be programmed with a Logic 0 for correct operation. Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. Clock Divide by 2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, this bit should be set to 0. When performing internal full-scale calibrations, this bit must be set when AVDD is less than 4.75 V. The calibration accuracy is optimized when chop is enabled and a low output data rate is used while performing the calibration. When AVDD is greater than or equal to 4.75 V, it is not compulsory to set the CLK_DIV bit when performing internal full-scale calibrations. Single cycle conversion enable bit. When this bit is set, the AD7192 settles in one conversion cycle so that it functions as a zero-latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected. This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/ 60 Hz rejection. Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter cut-off frequency, the position of the first notch of the filter, and the output data rate for the part. In association with the gain selection, they also determine the output noise (and, therefore, the effective resolution) of the device (see Table 6 through Table 13). When chop is disabled and continuous conversion mode is selected, Output Data Rate = (MCLK/1024)/FS where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz. With chop disabled, the first notch frequency is equal to the output data rate when converting on a single channel. When chop is enabled, Output Data Rate = (MCLK/1024)/(N x FS) where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The sinc filter’s first notch frequency is equal to N × output data rate. The chopping introduces notches at odd integer multiples of (output data rate/2). MR19, MR18 CLK1, CLK0 MR17, MR16 MR15 0 SINC3 MR14 MR13 0 ENPAR MR12 CLK_DIV MR11 SINGLE MR10 REJ60 MR9 to MR0 FS9 to FS0 Rev. A | Page 20 of 40 AD7192 Table 18. Operating Modes MD2 0 MD1 0 MD0 0 Mode Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the communications register to 1, which enables continuous read. When continuous read is enabled, the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each conversion by writing to the communications register. After power-on, a reset, or a reconfiguration of the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are available at the selected output data rate, which is dependent on filter choice. Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in the data register. RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register until another conversion is performed. RDY remains active (low) until the data is read or another conversion is performed. Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are still provided. Power-down mode. In power-down mode, all AD7192 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7192 for settling reasons. The external crystal, if selected, remains active. Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the fullscale error. When AVDD is less than 4.75 V, the CLK_DIV bit must be set when performing the internal full-scale calibration. System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required each time the gain of a channel is changed. System full-scale calibration. The user should connect the system full-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed. 0 0 1 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0 1 1 1 CONFIGURATION REGISTER (RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117) The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel. Table 19 outlines the bit designations for the filter register. CON0 through CON23 indicate the bit locations. CON denotes that the bits are in the configuration register. CON23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. CON23 CHOP(0) CON15 CH7(0) CON7 BURN(0) CON22 0(0) CON14 CH6(0) CON6 REFDET(0) CON21 0(0) CON13 CH5(0) CON5 0(0) CON20 REFSEL(0) CON12 CH4(0) CON4 BUF(1) CON19 0(0) CON11 CH3(0) CON3 U/B (0) CON18 0(0) CON10 CH2(0) CON2 G2(1) CON17 0(0) CON9 CH1(0) CON1 G1(1) CON16 (0) CON8 CH0(1) CON0 G0(1) Rev. A | Page 21 of 40 AD7192 Table 19. Configuration Register Bit Designations Bit Location CON23 Bit Name CHOP Description Chop enable bit. When the CHOP bit is cleared, chop is disabled. When the CHOP bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed. However, this increases the conversion time and settling time of the ADC. For example, when FS = 96 decimal and the sinc4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word of 96 decimal and the sinc4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and offset drift. These bits must be programmed with a Logic 0 for correct operation. Reference select bits. The reference source for the ADC is selected using these bits. REFSEL Reference Voltage 0 External reference applied between REFIN1(+) and REFIN1(−). 1 External reference applied between the P1/REFIN2(+) and P0/REFIN2(−) pins. These bits must be programmed with a Logic 0 for correct operation. Channel select bits. These bits are used to select which channels are enabled on the AD7192 (see Table 20). Several channels can be selected, and the AD7192 automatically sequences them. The conversion on each channel requires the complete settling time. When performing calibrations or when accessing the calibration registers, only one channel can be selected. When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When BURN = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and when chop is disabled. Enables the reference detect function. When set, the NOREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference detect circuitry operates only when the ADC is active. This bit must be programmed with a Logic 0 for correct operation. Enables the buffer on the analog inputs. If cleared, the analog inputs are unbuffered, lowering the power consumption of the device. If this bit is set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the system. With the buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AVDD. When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin must be limited to 250 mV within the power supply rails. Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar operation is selected. Gain select bits. These bits are written by the user to select the ADC input range as follows: G2 G1 G0 Gain ADC Input Range (5 V Reference) 0 0 0 1 ±5 V 0 0 1 Reserved 0 1 0 Reserved 0 1 1 8 ±625 mV 1 0 0 16 ±312.5 mV 1 0 1 32 ±156.2 mV 1 1 0 64 ±78.125 mV 1 1 1 128 ±39.06 mV CON22, CON21 CON20 0 REFSEL CON19 to CON16 CON15 to CON8 0 CH7 to CH0 CON7 BURN CON6 REFDET CON5 CON4 0 BUF CON3 CON2 to CON0 U/B G2 to G0 Rev. A | Page 22 of 40 AD7192 Table 20. Channel Selection Channel Enable Bits in the Configuration Register CH7 CH6 CH5 CH4 CH3 CH2 CH1 1 1 1 1 1 1 1 CH0 1 Channel Enabled Positive Input Negative Input AIN(+) AIN(−) AIN1 AIN2 AIN3 AIN4 Temperature sensor AIN2 AIN2 AIN1 AINCOM AIN2 AINCOM AIN3 AINCOM AIN4 AINCOM Status Register Bits CHD[2:0] 000 001 010 011 100 101 110 111 Calibration Register Pair 0 1 None 0 0 1 2 3 DATA REGISTER (RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000) The conversion result from the ADC is stored in this data register. This is a read-only, 24-bit register. On completion of a read operation from this register, the RDY pin/bit is set. When the DAT_STA bit in the mode register is set to 1, the contents of the status register are appended to each 24-bit conversion. This is advisable when several analog input channels are enabled because the three LSBs of the status register (CHD2 to CHD0) identify the channel from which the conversion originated. ID REGISTER (RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xX0) The identification number for the AD7192 is stored in the ID register. This is a read-only register. Rev. A | Page 23 of 40 AD7192 GPOCON REGISTER (RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00) The GPOCON register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the general-purpose digital outputs. GP7 0(0) GP6 BPDSW(0) GP5 GP32EN(0) GP4 GP10EN(0) Table 21 outlines the bit designations for the GPOCON register. GP0 through GP7 indicate the bit locations. GP denotes that the bits are in the GPOCON register. GP7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. GP3 P3DAT(0) GP2 P2DAT(0) GP1 P1DAT(0) GP0 P0DAT(0) Table 21. Register Bit Designations Bit Location GP7 GP6 Bit Name 0 BPDSW Description This bit must be programmed with a Logic 0 for correct operation. Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge power– down switch. When the ADC is placed in power-down mode, the bridge power-down switch remains active. Digital Output P3 and Digital Output P2 enable. When GP32EN is set, the P3 and P2 digital outputs are active. When GP32EN is cleared, the P3 and P2 pins are tristated, and the P3DAT and P2DAT bits are ignored. Digital Output P1 and Digital Output P0 enable. When GP10EN is set, the P1 and P0 digital outputs are active. When GP10EN is cleared, the P1 and P0 outputs are tristated, and the P1DAT and P0DAT bits are ignored. The P1 and P0 pins can be used as a reference input to REFIN2 when the REFSEL bit in the configuration register is set to 1. Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the P3 general-purpose output pin. When P3DAT is high, the P3 output pin is high. When P3DAT is low, the P3 output pin is low. When the GPOCON register is read, the P3DAT bit reflects the status of the P3 pin if GP32EN is set. Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the P2 general-purpose output pin. When P2DAT is high, the P2 output pin is high. When P2DAT is low, the P2 output pin is low. When the GPOCON register is read, the P2DAT bit reflects the status of the P2 pin if GP32EN is set. Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the P1 general-purpose output pin. When P1DAT is high, the P1 output pin is high. When P1DAT is low, the P1 output pin is low. When the GPOCON register is read, the P1DAT bit reflects the status of the P1 pin if GP10EN is set. Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the P0 general-purpose output pin. When P0DAT is high, the P0 output pin is high. When P0DAT is low, the P0 output pin is low. When the GPOCON register is read, the P0DAT bit reflects the status of the P0 pin if GP10EN is set. GP5 GP4 GP32EN GP10EN GP3 P3DAT GP2 P2DAT GP1 P1DAT GP0 P0DAT OFFSET REGISTER (RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000) The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The AD7192 has four offset registers; therefore, each channel has a dedicated offset register (see Table 20). Each of these registers is a 24-bit read/write register. This register is used in conjunction with its associated full-scale register to form a register pair. The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7192 must be placed in powerdown mode or idle mode when writing to the offset register. FULL-SCALE REGISTER (RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0) The full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the ADC. The AD7192 has four fullscale registers; therefore, each channel has a dedicated full-scale register (see Table 20). The full-scale registers are read/write registers. However, when writing to the full-scale registers, the ADC must be placed in power-down mode or idle mode. These registers are configured at power-on with factory-calibrated full-scale calibration coefficients, the calibration being performed at gain = 1. Therefore, every device has different default coefficients. The default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user or if the full-scale register is written to. Rev. A | Page 24 of 40 AD7192 ADC CIRCUIT INFORMATION 5V REFIN1(+) AGND IN+ OUT– OUT+ AIN1 AIN2 AIN3 AIN4 AINCOM MUX AVDD DVDD DGND REFERENCE DETECT AVDD DOUT/RDY DIN SCLK CS SYNC AGND IN– PGA Σ-Δ ADC SERIAL INTERFACE AND CONTROL LOGIC REFIN1(–) BPDSW TEMP SENSOR CLOCK CIRCUITRY P3 P2 AD7192 AGND MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) Figure 18. Basic Connection Diagram OVERVIEW The AD7192 is an ultralow noise ADC that incorporates a Σ-Δ modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals such as those in pressure transducers, weigh scales, and strain gage applications. The part can be configured to have two differential inputs or four pseudo differential inputs that can be buffered or unbuffered. Figure 18 shows the basic connections required to operate the part. fADC = fCLK/(1024 × FS[9:0]) where: fADC is the output data rate. fCLK = master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. The output data rate can be programmed from 4.7 Hz to 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023. The previous equation is valid for both the sinc3 and sinc4 filters. The settling time for the sinc4 filter is equal to tSETTLE = 4/fADC and the settling time for the sinc3 filter is equal to tSETTLE = 3/fADC Figure 19 and Figure 20 show the frequency response of the sinc4 filter and sinc3 filter, respectively, for an output data rate of 50 Hz. 0 –10 –20 FILTER, OUTPUT DATA RATE, AND SETTLING TIME A Σ-Δ ADC consists of a modulator followed by a digital filter. The AD7192 has two filter options: a sinc3 filter and a sinc4 filter. The filter is selected using the SINC3 bit in the mode register. When the SINC3 bit is set to 0 (default value), the sinc4 filter is selected. The sinc3 filter is selected when the SINC3 bit is set to 1. At low output data rates (