AD7228LN

LC2MOS Octal 8-Bit DAC AD7228 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM MSB 13 DATA (8-BIT) LSB 20 DATA BUS Eight 8-bit DACs with output amplifiers Operates with single or dual supplies Microprocessor-compatible (95 ns WR pulse) No user trims required Skinny 24-lead PDIP, CERDIP, and SOIC packages, and a 28-lead PLCC surface-mount package VREF VDD 11 1 LATCH 1 DAC 1 LATCH 2 DAC 2 LATCH 3 DAC 3 LATCH 4 DAC 4 LATCH 5 DAC 5 LATCH 6 DAC 6 LATCH 7 DAC 7 LATCH 8 DAC 8 1 9 VOUT1 2 8 VOUT2 3 7 VOUT3 4 6 VOUT4 5 5 VOUT5 6 4 VOUT6 7 3 VOUT7 8 2 VOUT8 WR 21 AD7228 CONTROL LOGIC A0 24 10 12 VSS GND 13034-001 A2 22 A1 23 Figure 1. GENERAL DESCRIPTION The AD7228 contains eight 8-bit voltage mode digital-to- analog converters (DACs), with output buffer amplifiers and interface logic on a single monolithic chip. No external trims are required to achieve the full specified performance for the device. Separate on-chip latches are provided for each of the eight DACs. Data is transferred into the data latches through a common 8-bit, TTL/CMOS-compatible input port (5 V). The A0, A1, and A2 address inputs determine which latch is loaded when WR goes low. The control logic is speed compatible with most 8-bit microprocessors. Specified performance is guaranteed for input reference voltages from 2 V to 10 V when using dual supplies. The device is also specified for single-supply operation using a reference of 10 V. Each output buffer amplifier is capable of developing 10 V across a 2 kΩ load. The AD7228 is fabricated on an all ion implanted, high speed, linear-compatible CMOS (LC2MOS) process, specifically Rev. D developed to integrate high speed digital logic circuits and precision analog circuits on the same chip. PRODUCT HIGHLIGHTS 1. 2. 3. The single chip design of eight 8-bit DACs and amplifiers allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. The PDIP, CERDIP, and SOIC pinout is aimed at optimizing board layout with all analog inputs and outputs at one side of the package and all digital inputs at the other. The voltage mode configuration of the DACs allows single supply operation of the AD7228. The device can also be operated with dual supplies giving enhanced performance for some parameters. The AD7228 has a common 8-bit data bus with individual DAC latches, providing a versatile control architecture for simple interface to microprocessors. All latch enable signals are level triggered and speed compatible with most high performance 8-bit microprocessors. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©1992–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7228 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Switching Characteristics .............................................................5 Functional Block Diagram .............................................................. 1 Absolute Maximum Ratings ............................................................6 General Description ......................................................................... 1 ESD Caution...................................................................................6 Product Highlights ........................................................................... 1 Pin Configurations and Function Descriptions ............................7 Revision History ............................................................................... 2 Theory of Operation .........................................................................8 Specifications..................................................................................... 3 Circuit Information .......................................................................8 Dual Supply ................................................................................... 3 Outline Dimensions ....................................................................... 14 Single Supply ................................................................................. 4 Ordering Guide .......................................................................... 15 REVISION HISTORY 10/2017—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 15 12/2015—Rev. B to Rev. C Changes to Features Section............................................................ 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Deleted LCCC Pin Configuration ...................................................4 Changes to Table 3.............................................................................5 Changes to Absolute Maximum Ratings Section and Table 4 .....6 Added Table 5; Renumbered Sequentially .....................................7 Added 5 V Single-Supply Operation Section ............................. 12 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 15 Rev. D | Page 2 of 15 Data Sheet AD7228 SPECIFICATIONS DUAL SUPPLY VDD = 10.8 V to 16.5 V, VSS = −5 V ± 10%, GND = 0 V, VREF = 2 V to 10 V, RL = 2 kΩ, CL = 100 pF, unless otherwise noted. All specifications TMIN to TMAX, −40°C to +85°C unless otherwise noted. VOUT must be less than VDD by 3.5 V to ensure correct operation. Table 1. Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error (TUE) 1 Relative Accuracy Differential Nonlinearity Full-Scale Error 2 Zero Code Error at 25°C TMIN to TMAX Minimum Load Resistance REFERENCE INPUT Voltage Range Input Resistance Input Capacitance 3 AC Feedthrough DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current Input Capacitance3 Input Coding DYNAMIC PERFORMANCE3 Voltage Output Slew Rate Voltage Output Settling Time Positive Full-Scale Change Negative Full-Scale Change Digital Feedthrough Digital Crosstalk 4 POWER SUPPLIES VDD Range VSS Range IDD at 25°C TMIN to TMAX ISS at 25°C TMIN to TMAX K and B Versions L and C Versions Unit 8 ±2 ±1 ±1 ±1 8 ±1 ±1/2 ±1 ±1/2 Bits LSB max LSB max LSB max LSB max ±25 ±30 2 ±15 ±20 2 mV max mV max kΩ min VOUT = 10 V 2/10 2 500 −70 2/10 2 500 −70 V min/V max kΩ min pF max dB typ Occurs when each DAC is loaded with all 1s VREF = 8 V p-p sine wave at 10 kHz 2.4 0.8 ±1 8 Binary 2.4 0.8 ±1 8 Binary V min V max µA max pF max 2 2 V/µs min 5 5 50 50 5 5 50 50 µs max µs max nV-sec typ nV-sec typ VREF = 10 V; settling time to ±1/2 LSB VREF = 10 V; settling time to ±1/2 LSB Code transition all 0s to all 1s, VREF = 0 V; WR = VDD Code transition all 0s to all 1s, VREF = 10 V; WR = 0 V 10.8/16.5 −4.5/−5.5 10.8/16.5 −4.5/−5.5 V min/V max V min/V max For specified performance For specified performance Outputs unloaded; VIN = VINL or VINH 16 20 16 20 mA max mA max 14 18 14 18 mA max mA max Test Conditions/Comments VDD = 15 V ± 10%, VREF = 10 V Guaranteed monotonic Typical temperature coefficient is 5 ppm/°C with VREF = 10 V Typical temperature coefficient is 30 µV/°C VIN = 0 V or VDD Outputs unloaded; VIN = VINL or VINH Total unadjusted error includes zero code error, relative accuracy, and full-scale error. Calculated after zero code error is adjusted out. Sample tested at TA = 25°C to ensure compliance. 4 The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter. 1 2 3 Rev. D | Page 3 of 15 AD7228 Data Sheet SINGLE SUPPLY VDD = 15 V ± 10%, VSS = GND, GND = 0 V, VREF = 10 V, RL = 2 kΩ, CL = 100 pF, unless otherwise noted. All specifications TMIN to TMAX, −40°C to +85°C, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error 1 Differential Nonlinearity Minimum Load Resistance REFERENCE INPUT Input Resistance Input Capacitance 2 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current Input Capacitance2 Input Coding DYNAMIC PERFORMANCE2 Voltage Output Slew Rate Voltage Output Settling Time Positive Full-Scale Change Negative Full-Scale Change Digital Feedthrough Digital Crosstalk 3 POWER SUPPLIES VDD Range IDD at 25°C TMIN to TMAX K and B Versions L and C Versions Unit Test Conditions/Comments 8 ±2 ±1 2 8 ±1 ±1 2 Bits LSB max LSB max kΩ min Guaranteed monotonic VOUT = 10 V 2 500 2 500 kΩ min pF max Occurs when each DAC is loaded with all 1s 2.4 0.8 ±1 8 Binary 2.4 0.8 ±1 8 Binary V min V max µA max pF max 2 2 V/µs min 5 7 50 50 5 7 50 50 µs max µs max nV-sec typ nV-sec typ Settling time to ±1/2 LSB Settling time to ±1/2 LSB Code transition all 0s to all 1s, VREF = 0 V, WR = VDD Code transition all 0s to all 1s, VREF = 10 V, WR = 0 V 13.5/16.5 13.5/16.5 V min/V max For specified performance Outputs unloaded; VIN = VINL or VINH 16 20 16 20 mA max mA max VIN = 0 V or VDD Total unadjusted error includes zero code error, relative accuracy and full-scale error. Sample tested at TA = 25°C to ensure compliance. 3 The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter. 1 2 Rev. D | Page 4 of 15 Data Sheet AD7228 SWITCHING CHARACTERISTICS See Figure 8 and Figure 2; VDD = 5 V ± 5% or 10.8 V to 16.5 V; VSS = 0 V or –5 V ± 10%. Sample tested at 25°C to ensure compliance. All input rise and fall times measured from 10% to 90% of 5 V, tR = tF = 5 ns. Timing measurement reference level is (VINH + VINL)/2. Table 3. Limit at 25°C, All Grades 0 0 70 10 95 Limit at TMIN, TMAX, K, L, B, and C Versions 0 0 90 10 120 Unit ns min ns min ns min ns min ns min t1 t2 Description Address to WR setup time Address to WR hold time Data valid to WR setup time Data valid to WR hold time Write pulse width 5V ADDRESS 0V t5 5V WR 0V t3 DATA t4 VINH VINL 5V 0V NOTES 1. THE SELECTED INPUT LATCH IS TRANSPARENT WHILE WR IS LOW, THUS INVALID DATA DURING THIS TIME CAN CAUSE SPURIOUS OUTPUTS. Figure 2. Write Cycle Timing Diagram Rev. D | Page 5 of 15 13034-003 Parameter t1 t2 t3 t4 t5 AD7228 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 4. Parameter VDD to GND VDD to VSS Digital Input Voltage to GND VREF to GND VOUTx to GND1 Power Dissipation (Any Package) to 75°C Derates Above 75°C by Operating Temperature Range Commercial Industrial Storage Temperature Range Lead Temperature (Soldering, 10 sec) 1 Rating −0.3 V to +17 V −0.3 V to +24 V −0.3 V to VDD −0.3 V to VDD VSS, VDD 1000 mW 2.0 mW/°C ESD CAUTION −40°C to +85°C −40°C to +85°C −65°C to +150°C 300°C Outputs can be shorted to any voltage in the range VSS to VDD provided that the power dissipation of the package is not exceeded. Typical short-circuit current fora short to GND or VSS is 50 mA. Rev. D | Page 6 of 15 Data Sheet AD7228 A1 A2 4 3 2 1 28 27 26 VOUT6 4 21 WR VOUT6 5 25 WR VOUT5 5 20 DB0 (LSB) VOUT5 6 24 DB0 VOUT4 7 AD7228 23 DB1 TOP VIEW (Not to Scale) 22 DNC VOUT4 6 VOUT3 7 AD7228 TOP VIEW (Not to Scale) 19 DB1 18 DB2 DNC 8 VOUT1 11 19 DB4 GND 12 13 DB7 (MSB) 12 13 14 15 16 17 18 DB5 14 DB6 DB6 DB3 VREF 11 DB7 DB2 20 DNC 21 VOUT2 10 GND VOUT3 9 15 DB5 VSS 16 DB4 VSS 10 VREF 17 DB3 VOUT1 9 13034-004 VOUT2 8 DNC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 13034-005 A0 22 A2 DNC 23 A1 VOUT7 3 VDD 24 A0 VOUT8 VD0 1 VOUT8 2 VOUT7 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. 28-Lead PLCC Pin Configuration Figure 3. 24-Lead PDIP, CERDIP, and SOIC Pin Configuration Table 5. Pin Function Descriptions Pin No. 24-Lead PDIP, CERDIP, and SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 28-Lead PLCC 2 3 4 5 6 7 1, 8, 15, 22 9 10 11 12 13 14 16 17 18 19 20 21 23 24 25 Mnemonic VDD VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 DNC VOUT3 VOUT2 VOUT1 VSS VREF GND DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 WR 22 23 24 26 27 28 A2 A1 A0 Description Positive Supply Voltage This device can be operated from a supply of 10.8 V to 16.5 V. Analog Output Voltage of DAC 8. Analog Output Voltage of DAC 7. Analog Output Voltage of DAC 6. Analog Output Voltage of DAC 5. Analog Output Voltage of DAC 4. Do Not Connect. Do not connect to this pin. Analog Output Voltage of DAC 3. Analog Output Voltage of DAC 2. Analog Output Voltage of DAC 1. Negative Supply Voltage. This device can be operated from a supply of −5.5 V to −4.5 V. DAC Reference Voltage Input. Ground Pin. Parallel Data Bit 7. Parallel Data Bit 6. Parallel Data Bit 5. Parallel Data Bit 4. Parallel Data Bit 3. Parallel Data Bit 2. Parallel Data Bit 1. Parallel Data Bit 0. Write Control Digital Input In, Active Low. WR transfers shift register data to the DAC register on the rising edge. The signal level on this pin must be ≤ VDD + 0.3 V. Address Pin 2. The signal level on this pin must be ≤ VDD + 0.3 V. Address Pin 1. The signal level on this pin must be ≤ VDD + 0.3 V. Address Pin 0. The signal level on this pin must be ≤ VDD + 0.3 V. Rev. D | Page 7 of 15 AD7228 Data Sheet THEORY OF OPERATION CIRCUIT INFORMATION DACs The AD7228 contains eight identical, 8-bit, voltage mode DACs. The output voltages from the converters have the same polarity as the reference voltage, allowing single-supply operation. A novel DAC switch pair arrangement on the AD7228 allows a reference voltage range from 2 V to 10 V. Each DAC consists of a highly stable, thin film, R-2R ladder and eight high speed NMOS switches. The simplified circuit diagram for one channel is shown in Figure 5. Note that VREF and GND are common to all eight DACs. slightly longer than the settling time for dual supply operation. Additionally, to ensure that the output voltage can go to 0 V in single-supply operation, a transistor on the output acts as a passive pull-down as the output voltage nears 0 V. As a result, the sink capability of the amplifier is reduced as the output voltage nears 0 V in single-supply operation. In dual supply operation, the full sink capability of 400 μA at 25°C is maintained over the entire output voltage range. The single-supply output sink capability is shown in Figure 6. The negative VSS also gives improved output amplifier performance, allowing an extended input reference voltage range and giving an improved slew rate at the output. 600 2R R VOUT R 2R 2R 2R 2R DB0 DB5 DB6 DB7 TA = +25°C 13034-006 NOTES 1. SHOWN FOR ALL 1s ON DAC. TA = –55°C 400 VREF GND VDD = +15V VSS = 0V 500 ISINK (µA) R TA = +125°C 300 200 Figure 5. DAC Simplified Circuit Diagram 0 1 2 3 4 5 6 7 8 9 Figure 6. Single Supply Sink Current The output broadband noise from the amplifier is 300 μV p-p. Figure 7 shows a plot of noise spectral density vs. frequency. 700 VOUTx = DN × VREF where DN is a fractional representation of the digital input code and can vary from 0 to 255/256. The output impedance is that of the output buffer amplifier as described in the Op Amp section. VDD = +15V VSS = –5V TA = 25°C 600 500 400 300 200 100 0 100 Op Amp 1k 10k 100k FREQUENCY (Hz) The AD7228 can be operated from single or dual supplies. Operating the device from single or dual supplies has no effect on the positive going settling time. However, the negative going settling time to voltages near 0 V in single-supply operation is 13034-008 Consider each VOUTX pin as a digitally programmable voltage source with an output voltage. Each voltage mode DAC output is buffered by a unity-gain, noninverting, CMOS amplifier. This buffer amplifier is tested with a 2 kΩ and 100 pF load, but typically drives a 2 kΩ and 500 pF load. 10 OUTPUT VOLTAGE (V) 13034-007 100 NOISE SPECTRAL DENSITY (nV/√Hz) The input impedance at the VREF pin of the AD7228 is the parallel combination of the eight individual DAC reference input impedances. It is code dependent and can vary from 2 kΩ to infinity. The lowest input impedance occurs when all eight DACs are loaded with digital code 01010101. Therefore, it is important that the external reference source presents a low output impedance to the VREF terminal of the AD7228 under changing load conditions. Due to transient currents at the reference input during digital code changes, a 0.1 μF (or greater) decoupling capacitor is recommended on the VREF input for dc applications. The nodal capacitance at the reference terminal is also code dependent and typically varies from 120 pF to 350 pF. Figure 7. Noise Spectral Density vs. Frequency Digital Inputs The AD7228 digital inputs are compatible with either TTL or 5 V CMOS levels. All logic inputs are static protected MOS gates with typical input currents of less than 1 nA. Internal input protection is achieved by on-chip distributed diodes. Rev. D | Page 8 of 15 Data Sheet AD7228 Interface Logic Information 16 The A0, A1, and A2 address lines select which DAC accepts data from the input port. Table 6 shows the selection table for the eight DACs and Figure 8 shows the input control logic. When the WR signal is low, the input latch of the selected DAC is transparent, and its output responds to activity on the data bus. The data is latched into the addressed DAC latch on the rising edge of WR. While WR is high, the analog outputs remain at the value corresponding to the data held in their respective latches. 12 POWER SUPPLY CURRENT (mA) 10 8 6 4 2 0 –2 –4 –6 ISS –8 High A2 X1 A1 X A0 X Low Low to High Low Low Low Low Low Low Low Low Low Low Low Low High High High High Low Low Low High High Low Low High High Low Low High Low High Low High Low High Operation No operation, device not selected DAC 1 transparent DAC 1 latched DAC 2 transparent DAC 3 transparent DAC 4 transparent DAC 5 transparent DAC 6 transparent DAC 7 transparent DAC 8 transparent –40 –20 0 20 40 60 120 140 Applying the AD7228 Unipolar Output Operation Unipolar output operation is the basic mode of operation for each channel of the AD7228 and the output voltage has the same positive polarity as VREF. Connections for unipolar output operation are shown in Figure 10. The AD7228 can be operated from single or dual supplies. The voltage at the reference input must never be negative with respect to GND. Failure to observe this precaution may cause parasitic transistor action and possible device destruction. The code table for unipolar output operation is shown in Table 7. +12V TO +15V VREF TO DAC 1 LATCH 11 1 VDD TO DAC 2 LATCH TO DAC 3 LATCH 1-OF-8 DECODER LATCH 1 DAC 1 LATCH 2 DAC 2 LATCH 3 DAC 3 LATCH 4 DAC 4 LATCH 5 DAC 5 LATCH 6 DAC 6 LATCH 7 DAC 7 LATCH 8 DAC 8 1 9 VOUT1 2 8 VOUT2 3 7 VOUT3 4 6 VOUT4 5 5 VOUT5 6 4 VOUT6 7 3 VOUT7 8 2 VOUT8 TO DAC 4 LATCH TO DAC 5 LATCH TO DAC 6 LATCH WR MSB Figure 8. Input Control Logic 13 DATA BUS Supply Current The AD7228 has a maximum IDD specification of 20 mA and a maximum ISS of 18 mA over the −40°C to +85°C temperature range. Figure 9 shows a typical plot of power supply current vs. temperature. LSB 20 DATA BUS TO DAC 8 LATCH 13034-002 TO DAC 7 LATCH WR 21 A2 22 A1 23 AD7228 CONTROL LOGIC A0 24 10 VSS 12 GND 0V OR –5V Figure 10. Unipolar Output Circuit Rev. D | Page 9 of 15 13034-010 A0 A2 100 Figure 9. Power Supply Current vs. Temperature X means don’t care. A1 80 TEMPERATURE (°C) 13034-009 –12 –14 –60 Control Inputs 1 IDD –10 Table 6. AD7228 Truth Table WR VDD = +15V VSS = –5V 14 AD7228 Data Sheet Table 8. Bipolar Code Table Table 7. Unipolar Code Table DAC Latch Contents MSB LSB1 1111 1111 1000 0001 1000 0000 Analog Output +VREF(255/256) +VREF(129/256) 0111 0000 0000 +VREF(127/256) +VREF(1/256) 0V V  128   = + REF 256 2   +VREF  1111 0001 0000 Analog Output +VREF(127/128) +VREF(1/128) 0V −VREF(1/128) −VREF(127/128) −VREF(128/128) = −VREF Mismatch between R1 and R2 causes gain and offset errors; therefore, these resistors must match and track over temperature. 1 LSB = (VREF)(2−8) = VREF (1/256). The AD7228 can be operated from a single supply or from dual supplies. Table 8 shows the digital code vs. output voltage relationship for the circuit of Figure 11 with R1 = R2. Bipolar Output Operation Each of the DACs on the AD7228 can be individually configured for bipolar output operation. This is possible using one external amplifier and two resistors per channel. Figure 11 shows a circuit used to implement offset binary coding (bipolar operation) with DAC 1 of the AD7228. In this case, AC Reference Signal In some applications, it may be desirable to have an ac signal applied as the reference input to the AD7228. The AD7228 has multiplying capability within the upper (10 V) and lower (2 V) limits of reference voltage when operated with dual supplies. Therefore, ac signals must be ac-coupled and biased up before being applied to the reference input. Figure 12 shows an ac signal applied to the reference input of the AD7228. For input frequencies up to 50 kHz, the output distortion typically remains less than 0.1%. The typical 3 dB bandwidth for small signal inputs is 800 kHz. R2   R2  × (V ) VOUT = 1 +  × (D1 × VREF ) −   REF R1    R1  With R1 = R2, VOUT = (2D1 − 1) × (VREF) where D1 is a fractional representation of the digital word in Latch 1 of the AD7228 (0 ≤ D1 ≤ 255/256). VREF R1 10kΩ ±0.1% 11 VREF 1 VDD R2 10kΩ ±0.1% +15V 9 VOUT VOUT1 DAC 1 –15V AD7228* 12 10 VSS GND 13034-011 *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 11. Bipolar Output Circuit +15V +10V +4V 15kΩ REFERENCE INPUT –4V +2V 10kΩ 11 +15V VDD VREF 1 9 VOUT1 DAC 1 AD7228* 10 12 VSS *ADDITIONAL PINS OMITTED FOR CLARITY. –5V Figure 12. Applying an AC Signal to the AD7228 Rev. D | Page 10 of 15 GND 13034-012 1 DAC Latch Contents MSB LSB 1111 1111 1000 0001 1000 0000 0111 1111 0000 0001 0000 0000 Data Sheet AD7228 Timing Deskew DAC 1 is the most significant or coarse DAC. Data is first loaded to this DAC to coarsely set the output voltage. DAC 2 is then used to fine tune this output voltage. Varying the ratio of R1 to R2 varies the relative effect of the coarse and fine DACs on the output voltage. For the resistor values shown, DAC 2 has a resolution of 150 μV in a 10 V output range. Because each DAC on the AD7228 is guaranteed monotonic, the coarse adjustment and fine adjustment are each monotonic. One application for this is as a setpoint controller (see the AN-317 Application Note, “Circuit Applications of the AD7226 Quad CMOS DAC,” available from Analog Devices, Inc.). Signal edges slowing or rounding off by the time they reach the pin driver circuitry is a common problem in automated test equipment (ATE) applications. Square up the edge at the pin driver to overcome this problem. However, because each edge is not rounded off by the same extent, this squaring up may lead to incorrect timing relationship between signals. This effect is shown in Figure 13. HIGH-SPEED BUFFER 11 VREF 1 VDD 51.2kΩ VOUT1 13034-013 BUFFER TRIGGER POINT 9 200Ω 200Ω DAC 1 A1 VOUT Figure 13. Time Skewing Due to Slowing of Edges POSITION OF THIS EDGE PROGRAMMED BY CODE TO DAC1 8 DAC 2 AD7228* 10 12 VSS GND –5V *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 15. Coarse/Fine Adjust Circuit Self Programmable Reference The circuit of Figure 16 shows how one DAC of the AD7228, in this case DAC 1, can be used in a feedback configuration to provide a programmable reference for itself and the other seven converters. The relationship of VREF to VIN is expressed by VREF  HIGH-SPEED COMPARATORS VOUT2 51.2kΩ (1  G )  VIN (1  G  D1 ) where G = R2/R1. 1 VDD AD7228* VSS GND 10 12 1 VREF VDD AD7228* VOUT1 9 VOUT1 9 VOUT2 8 *ADDITIONAL PINS OMITTED FOR CLARITY. 13034-014 11 POSITION OF THIS EDGE PROGRAMMED BY CODE TO DAC2 11 VSS GND 10 12 VIN A1 R1 R2 –5V *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 14. AD7228 Timing Deskew Circuit Figure 16. Self Programmable Reference Coarse/Fine Adjust Pair the DACs on the AD7228 together to form a coarse/fine adjust function as shown in Figure 15. The function is achieved using one external op amp and a few resistors per pair of DACs. Rev. D | Page 11 of 15 13034-016 +15V VREF 13034-015 The circuit of Figure 14 shows how two DACs of the AD7228 can help overcome the problem of time skewing. The same two signals are applied to this circuit as are applied in Figure 14. The output of each DAC is applied to one input of a high speed comparator, and the signals are applied to the other inputs. Varying the output voltage of the DAC effectively varies the trigger point at which the comparator flips. Therefore, the timing relationship between the two signals can be programmably corrected (or deskewed) by varying the code to the DAC of the AD7228. In a typical application, the code is loaded to the DACs for correct timing relationships during the calibration cycle of the instrument. AD7228 Data Sheet 4.0 VDD = +15V VSS = –5V 1.0 TA = 25°C VDD = 5V VSS = 0V VREF = 1.23V 0.5 ERROR (LSB) Figure 17 shows typical plots of VREF vs. digital code, D1, for three different values of G. With VIN = 2.5 V and G = 3, the voltage at the output varies between 2.5 V and 10 V, giving an effective 10-bit dynamic range to the other seven converters. For correct operation of the circuit, it is recommended that VSS is equal to −5 V and R1 be greater than 6.8 kΩ. 0 3.5 –0.5 R2 = 3.1Ω 1.0 2.5 0 32 64 R2 = 2.1Ω 128 160 192 224 255 INPUT CODE Figure 18. Relative Accuracy at VDD = 5 V R2 = 1Ω 2.0 96 13034-018 VREF (VIN) 3.0 Microprocessor Interfacing 1.5 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255 DIGITAL CODE (Decimal Equivalent) ADDRESS BUS A8 8085A1/ Z80 Figure 17. Variation of VREF with Feedback Configuration MREQ2 EN ADDRESS DECODE 5 V Single-Supply Operation The AD7228 can be operated from a single 5 V power supply, resulting in only slightly degraded accuracy performance from the device. Figure 18 shows a typical plot of relative accuracy for the device with VDD = 5 V and a reference voltage of 1.23 V. Differential nonlinearity is an important parameter that retains its specified performance and remains monotonic over the output voltage range. The output transfer function sits on top of the amplifier offset voltage; there is an initial offset voltage, and the voltage coming from the output transfer function is added on top of this offset voltage. Because the reference voltage is reduced, the offset voltage equals a few LSBs. For devices with a true negative offset (when VSS = −5 V), the transfer function does not move off the bottom rail for the first few LSBs of code. After this, the transfer function continues as normal. The relative accuracy plot of Figure 18 is for a device with a true positive offset. Maintain the required overhead voltage of 3.5 V between VDD and the reference voltage, which limits the reference voltage range. However, operating the device from a single 5 V supply reduces the power dissipation considerably (typically to 50 mW). The digital input threshold levels and digital input currents are not affected by operating the device from the single 5 V supply. A0 A1 A2 AD72283 WR WR DB7 DB0 D7 DATA BUS D0 1FOR 8085A, DATA BUS NEEDS TO BE DEMULTIPLEXED. 2Z80 ONLY. 3ADDITIONAL PINS OMITTED FOR CLARITY. Figure 19. AD7228 to 8085A/Z80 Interface A15 ADDRESS BUS A0 6809/ 6502 R/W EN A0 A1 A2 ADDRESS DECODE AD7228* WR E OR (1)2 DB7 DB0 D7 D0 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY. Rev. D | Page 12 of 15 Figure 20. AD7228 to 6809/6502 Interface 13034-020 0 13034-019 1.0 13034-017 A15 Data Sheet P3.0 P3.1 P3.2 P3.3 ADDRESS BUS A1 68008 AS EN ADDRESS DECODE A0 A1 A2 AD7228* 8051 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 AD7228* WR R/W DTACK WR A0 A1 A2 DB7 DB0 D7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 *ADDITIONAL PINS OMITTED FOR CLARITY. DATA BUS D0 *ADDITIONAL PINS OMITTED FOR CLARITY. 13034-021 Figure 22. AD7228 to 8051 Interface Figure 21. AD7228 to 68008 Interface Rev. D | Page 13 of 15 13034-022 A23 AD7228 AD7228 Data Sheet OUTLINE DIMENSIONS 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 24 13 1 12 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 071006-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 23. 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) 0.098 (2.49) MAX 0.005 (0.13) MIN 24 13 1 12 PIN 1 0.200 (5.08) MAX 0.310 (7.87) 0.220 (5.59) 1.280 (32.51) MAX 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.290 (7.37) 0.150 (3.81) MIN 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.070 (1.78) SEATING 0.030 (0.76) PLANE 15° 0° 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 24. 24-Lead Ceramic Dual In-Line Package [CERDIP] Narrow Body (Q-24-1) Dimensions shown in inches and (millimeters) Rev. D | Page 14 of 15 100808-A 0.200 (5.08) 0.125 (3.18) Data Sheet AD7228 15.60 (0.6142) 15.20 (0.5984) 13 24 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10.00 (0.3937) 12 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 1.27 (0.0500) BSC SEATING PLANE 8° 0° 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) 12-09-2010-A COMPLIANT TO JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 25. 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches) 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 4 0.048 (1.22) 0.042 (1.07) 5 PIN 1 IDENTIFIER 26 25 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC TOP VIEW (PINS DOWN) 11 12 0.020 (0.51) MIN 0.032 (0.81) 0.026 (0.66) 19 18 0.456 (11.582) SQ 0.450 (11.430) 0.495 (12.57) SQ 0.485 (12.32) 0.120 (3.04) 0.090 (2.29) 0.430 (10.92) 0.390 (9.91) BOTTOM VIEW (PINS UP) 0.045 (1.14) R 0.025 (0.64) COMPLIANT TO JEDEC STANDARDS MO-047-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 042508-A 0.048 (1.22) 0.042 (1.07) Figure 26. 28-Lead Plastic Leaded Chip Carrier [PLCC] (P-28) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model 1 AD7228BQ AD7228CQ AD7228KN AD7228KNZ AD7228KP AD7228KP-REEL AD7228KPZ AD7228KR AD7228KRZ AD7228LNZ AD7228LPZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Maximum TUE (LSB) ±2 ±1 ±2 ±2 ±2 ±2 ±2 ±2 ±2 ±1 ±1 Z = RoHS Compliant Part. ©1992–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13034-0-10/17(D) Rev. D | Page 15 of 15 Package Description 24-Lead CERDIP 24-Lead CERDIP 24-Lead PDIP 24-Lead PDIP 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead PDIP 28-Lead PLCC Package Option Q-24-1 Q-24-1 N-24-1 N-24-1 P-28 P-28 P-28 RW-24 RW-24 N-24-1 P-28