AD7277BUJ-REEL

PRELIMINARY TECHNICAL DATA a Preliminary Technical Data FEATURES Fast Throughput Rate: 3MSPS Specified for VDD of 2.35 V to 3.6V Low Power: 13.5 mW max at 3MSPS with 3V Supplies TBD mW typ at 1.5MSPS with 3V Supplies Wide Input Bandwidth: 70dB SNR at 1MHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPITM/QSPITM/MICROWIRETM/DSP Compatible Power Down Mode: 1µA max 6-Lead TSOT Package 8-lead MSOP Package AD7476 and AD7476A pin compatible APPLICATIONS Battery-Powered Systems Personal Digital Assistants Medical Instruments Mobile Communications Instrumentation and Control Systems Data Acquisition Systems High-Speed Modems Optical Sensors V IN 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT AD7276/AD7277/AD7278 FUNCTIONAL BLOCK DIAGRAM V DD T/H 8-/10-/12-BIT SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC SDATA &6 AD7276/AD7277/AD7278 GND GENERAL DESCRIPTION The AD7276/AD7277/AD7278 are 12-bit, 10-bit and 8bit, high speed, low power, successive-approximation ADCs respectively. The parts operate from a single 2.35V to 3.6 V power supply and feature throughput rates up to 3 MSPS. The parts contain a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of TBD MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The AD7276/AD7277/AD7278 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus the analog input range for the part is 0 to VDD. The conversion rate is determined by the SCLK. REV. PrF (6/04) Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered tradermarks are the property of their respective companies. PRODUCT HIGHLIGHTS 1. 3MSPS ADCs in a 6-lead TSOT package. 2. AD7476/77/78 and AD7476A/77A/78A pin compatible. 3. High Throughput with Low Power Consumption. 4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced when a power-down mode is used while not converting. The part also features a power-down mode to maximize power efficiency at lower throughput rates. Current consumption is 1 µA max when in Power-Down mode. 5. Reference derived from the power supply. 6. No Pipeline Delay. The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2004 PRELIMINARY TECHNICAL DATA AD7278-SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity 2 Differential Nonlinearity 2 Offset Error 2 Gain Error 2 Total Unadjusted Error (TUE)2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS VDD I DD Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) Power Dissipation 4 Normal Mode (Operational) Full Power-Down NOTES 1 Temperature range from –40°C to +85°C. 2 See Terminology. 3 Guaranteed by characterization. 4 See Power Versus Throughput Rate section. Specifications subject to change without notice. (VDD=+2.35 V to +3.6 V, fSCLK=52 MHz, fSAMPLE=3 MSPS unless otherwise noted; TA=TMIN to TMAX, unless otherwise noted.) B Grade1 49 -65 -65 -76 -76 TBD TBD TBD TBD 8 ±0.3 ±0.3 ±0.5 ±TBD ±0.5 ±TBD ±TBD 0 to VDD ±0.5 TBD 0.7(V DD ) 2 0.2(V DD ) 0.8 ±0.5 ±TBD 10 Units dB min dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB typ LSB max LSB typ LSB max Volts µA max pF typ V min V min V max V max µA max µA max pF max 2.35V Vdd 2.7V 2.7V < Vdd 3.6V 2.35V V dd< 2.7V 2.7V Vdd 3.6V Typically TBD nA, VIN= 0 V or VDD fa= TBD kHz, fb= TBD kHz fa= TBD kHz, fb= TBD kHz Test Conditions/Comments fIN= 1MHz Sine Wave @ 3 dB @ 0.1dB Guaranteed No Missed Codes to 8 Bits VDD - 0.2 V min 0.2 V max ±1 µA max 10 pF max Straight (Natural) Binary 192 50 3 2.35/3.6 2.5 4.5 1 TBD ns max ns max MSPS max Vmin/max mA mA µA mA typ max max typ ISOURCE= 200 µA,VDD= 2.35 V to 3.6V I SINK= 200µA 10 SCLK Cycles with SCLK at 52 MHz Digital I/Ps= 0V or VDD VDD= 2.35V to 3.6V, SCLK On or Off VDD= 2.35V to 3.6V, fSAMPLE = 3MSPS SCLK On or Off, typically TBD nA V DD= 3V, f SAMPLE = 1 MSPS V DD= 3V, f SAMPLE = 3 MSPS V DD = 3V 13.5 3 mW max µW max – 2– REV. PrF PRELIMINARY TECHNICAL DATA AD7277-SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity 2 Differential Nonlinearity 2 Offset Error 2 Gain Error 2 Total Unadjusted Error (TUE)2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time 2 Throughput Rate POWER REQUIREMENTS VDD I DD Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode(Static) Full Power-Down Mode(Dynamic) Power Dissipation 4 Normal Mode (Operational) Full Power-Down NOTES 1 Temperature range from –40°C to +85°C. 2 See Terminology. 3 Guaranteed by Characterization. 4 See Power Versus Throughput Rate section. Specifications subject to change without notice. (VDD=+2.35 V to +3.6 V, fSCLK=52 MHz, fSAMPLE=3MSPS unless otherwise noted; TA=TMIN to TMAX, unless otherwise noted.) B Grade1 61 -73 -74 -82 -82 TBD TBD TBD TBD 10 ±0.5 ±0.5 ±1 ±TBD ±1 ±TBD ±TBD 0 to VDD ±0.5 TBD 0.7(V DD ) 2 0.2(V DD ) 0.8 ±0.5 ±TBD 10 Units dB min dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ Bits LSB LSB LSB LSB LSB LSB LSB fa= TBD kHz, fb= TBD kHz fa= TBD kHz, fb= TBD kHz Test Conditions/Comments fIN = 1 MHz Sine Wave @ 3 dB @ 0.1dB max max max typ max typ max Guaranteed No Missed Codes to 10 Bits Volts µA max pF typ V min V min V max V max µA max µA max pF max 2.35V V dd 2 .7V 2.7V