8-Channel, Li-Ion,
Battery Monitoring System
AD7284
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
8 analog input channels, integrated secondary monitor
±3 mV maximum cell voltage accuracy, TUE, 14-bit ADC
Very low measurement latency across 96 cells
Stack voltage measurement
±16 mV typical battery stack voltage (TUE) accuracy
Cell balancing interface, with individually programmable
on time
4 auxiliary analog input channels, 14-bit ADC
Suitable for thermistor inputs and external diagnostics
Buffered reference output for ratiometric measurements
Internal temperature sensor
VDD operating range: 10 V to 40 V
On-chip 5 V regulator
Watchdog timer
IDD matching current: 100 μA
Robust, proprietary daisy-chain interface
SPI to host controller
CRC protection on read and write commands
2 general-purpose outputs
64-lead low profile quad flat package, exposed pad (LQFP_EP)
Junction temperature range: −30°C to +120°C
Qualified for automotive applications
VDD
CB1 TO CB8
CELL BALANCE
INTERFACE
DAISY-CHAIN
INTERFACE
D_UP
D_UP
TEMP
VPIN0 TO VPIN8
VPAUX1 TO VPAUX4
MUX
+
–
5V REG
ADC
DV CC
VDRIVE
VREFBUF
VREF1
REF1
CLK1
REF2
CLK2
REFGND1/REFGND2
VREF2
VSIN0 TO VSIN8
MUX
ADC
CONTROL
LOGIC
REGISTERS
AND TIMERS
SPI
INTERFACE
GPOP1
GPOP2
MASTER
RESET
SCLK
SDI
SDO
CS
CCM
AD7284
VSS AGND1/
AGND2
VREG5
AV CC
DAISY-CHAIN
INTERFACE
D_DWN
D_DWN
DGND
Figure 1.
APPLICATIONS
Li-Ion battery monitoring
Electric and hybrid electric vehicles
Stationary power applications
GENERAL DESCRIPTION
The AD7284 contains all the functions required for the generalpurpose monitoring of stacked Li-Ion batteries, as used in
hybrid electric vehicles and battery backup applications.
There are two on-chip 2.5 V voltage references: one reference
for the primary measurement path, and one for the secondary
measurement path.
The AD7284 has multiplexed cell voltage and auxiliary, analogto-digital converter (ADC) measurement channels supporting
four to eight cells of battery management. The device provides a
maximum total unadjusted error, TUE, (cell voltage accuracy) of
±3 mV that includes all the internal errors from input to
output. The primary ADC resolution is 14 bits.
The AD7284 operates from one VDD supply, ranging from 10 V
to 40 V. The device provides eight differential analog input
channels to accommodate large common-mode signals across
the full VDD range. Each channel allows an input signal range,
VPINx − VPIN(x − 1) and VSINx – VSIN(x − 1), of 0 V to 5 V,
where x = 0 to 8. The input pins assume a series stack of eight
cells. The AD7284 includes four auxiliary ADC input channels
that can be used for temperature measurement or system
diagnostics.
The AD7284 also includes an integrated secondary measurement
path that validates the data on the primary ADC. Other diagnostic
features include the detection of open inputs, communication,
and power supply related faults.
The AD7284 cell balancing interface outputs control the
external field effect transistors (FETs) to allow discharging of
individual cells.
Rev. C
The AD7284 has a differential daisy-chain interface that allows
multiple devices to be stacked without the need for individual
device isolation. By design, this interface allows both device
to device communication within the same module and
communication between devices on different modules.
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14703-001
FEATURES
AD7284
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Modes of Operation ................................................................... 25
Applications ....................................................................................... 1
Active Mode, Power-Up ............................................................ 25
Functional Block Diagram .............................................................. 1
Reset ............................................................................................. 26
General Description ......................................................................... 1
Power-Down ............................................................................... 26
Revision History ............................................................................... 2
Watchdog Timer ............................................................................. 28
Specifications..................................................................................... 3
Serial Peripheral Interface (SPI) ................................................... 29
ADC Timing Specifications ........................................................ 6
Register Write and Register Read Operations ............................ 29
Serial Peripheral Interface (SPI) Timing Specifications .......... 7
Conversion Data Readback Operation.................................... 30
Absolute Maximum Ratings............................................................ 8
CRC Pseudocode Examples ...................................................... 31
Thermal Data ................................................................................ 8
Daisy-Chain Interface .................................................................... 32
Thermal Resistance ...................................................................... 8
Daisy-Chain Physical Interface ................................................ 32
ESD Caution .................................................................................. 8
Daisy-Chain Protocol ................................................................ 32
Pin Configuration and Function Descriptions ............................. 9
Daisy-Chain Debug Mode ........................................................ 32
Typical Performance Characteristics ........................................... 11
Register Map ................................................................................... 33
Terminology .................................................................................... 14
Page Addressing.......................................................................... 33
Theory of Operation ...................................................................... 15
Page 0 Addresses......................................................................... 35
Circuit Information .................................................................... 15
Page 1 Addresses......................................................................... 36
Converter Operation .................................................................. 16
Registers Common to Page 0 and Page 1 ................................ 40
Internal Temperature Sensor .................................................... 17
Examples of Interfacing with the AD7284 .................................. 41
Auxiliary ADC Inputs ................................................................ 17
Register Write and Register Read Operations Examples ...... 41
Voltage References ...................................................................... 17
Conversion Data Readback Operation Examples .................. 42
Cell Connections ........................................................................ 18
Applications Information .............................................................. 44
ADC Conversions Sequence ..................................................... 19
Typical Connection Diagrams .................................................. 44
Converting with a Single AD7284 ............................................ 20
Hot Plug ....................................................................................... 47
Converting with a Chain of AD7284 Devices ......................... 21
Service Disconnect (SD) ........................................................... 47
Conversion Data Readback ....................................................... 22
Transformer Configuration ...................................................... 48
Cell Balancing Outputs .............................................................. 23
Outline Dimensions ....................................................................... 49
Open Input Detection ................................................................ 24
Ordering Guide .......................................................................... 49
Power Management ........................................................................ 25
Automotive Products ................................................................. 49
AD7284 Supplies ......................................................................... 25
REVISION HISTORY
10/2019—Rev. B to Rev. C
Changes to Table 5 ............................................................................ 8
Changes to Figure 26 ...................................................................... 18
Changes to Figure 41 ...................................................................... 45
Changes to Figure 42 ...................................................................... 46
Changes to Figure 43 and Figure 44............................................. 47
4/2018—Rev. A to Rev. B
Changes to Table 1.............................................................................3
5/2017—Revision 0: Initial Version
Rev. C | Page 2 of 49
Data Sheet
AD7284
SPECIFICATIONS
VDD = 10 V to 40 V, VSS = 0 V, DVCC = AVCC = VREG5, VDRIVE = 3.0 V to 5.5 V, unless otherwise noted. TJ = −30°C to +120°C, where TJ is
the junction temperature, unless otherwise noted. See the Thermal Data section for more details.
Table 1.
Parameter
PRIMARY ADC DC ACCURACY
(VPIN0 to VPIN8)
Resolution1
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ADC Unadjusted Error1
TUE2, 3
VPINx − VPIN(x − 1) Range
2 V to 3.6 V
2 V to 4.3 V
0 V to 5 V1
PRIMARY ADC CELL VOLTAGE INPUTS
(VPIN0 to VPIN8)
Pseudo Differential Input Voltage
Range
VPINx − VPIN(x − 1)
Static Leakage Current
Dynamic Leakage Current
Input Capacitance
PRIMARY ADC DC ACCURACY
(VPAUX1 to VPAUX4)
Resolution
INL1
DNL1
ADC Unadjusted Error1
TUE2
VPAUXx Range
0 V to 2.5 V1
0 V to 5 V1
PRIMARY ADC AUXILIARY INPUTS
(VPAUX1 to VPAUX4)
Input Voltage Range1
Static Leakage Current
Dynamic Leakage Current
Input Capacitance
PRIMARY ADC DC ACCURACY (VSTK4)
Resolution1
TUE2
Battery Stack Voltage (VSTK) Range
10 V to 28.8 V1
7.5 V to 40 V1
VSTK Voltage Accuracy
VSTK Range
10 V to 28.8 V1
7.5 V to 40 V1
Min
Typ
Max
Unit
Test Conditions/Comments
Bits
LSB
LSB
mV
No missing codes, 305 μV/LSB
±3
±5
±10
mV
mV
mV
10°C ≤ TJ ≤ 75°C
−10°C ≤ TJ ≤ +105°C
7.5 V ≤ VDD ≤ 40 V
5
±100
V
nA
nA
14
±1.4
±0.8
±1
±1
±1
±1
0
±30
±3
Convert start command
issued every 100 ms
15
pF
Bits
LSB
LSB
mV
No missing codes, 305 μV/LSB
±1.5
±0.8
±2
±5
±10
mV
mV
−10°C ≤ TJ ≤ +105°C
7.5 V ≤ VDD ≤ 40 V
5
±100
V
nA
nA
14
±2
±2
0
±80
±3
15
pF
14
±16
±16
Convert start command
issued every 100 ms
±24
±50
Bits
No missing codes, 4.88 mV/LSB
mV
mV
10°C ≤ TJ ≤ 75°C
Relative to the sum of the cells
±2
±2
±15
±30
Rev. C | Page 3 of 49
mV
mV
10°C ≤ TJ ≤ 75°C
AD7284
Parameter
SECONDARY ADC DC ACCURACY
(VSIN0 to VSIN8)
Resolution
INL
DNL
TUE2, 3
SECONDARY ADC CELL VOLTAGE
INPUTS (VSIN0 to VSIN8)
Pseudo Differential Input Voltage
VSINx − VSIN(x − 1)
Static Leakage Current
Dynamic Leakage Current
Data Sheet
Min
Typ
Max
Unit
Test Conditions/Comments
No missing codes, 4.88 mV/LSB
±25
Bits
LSB
LSB
mV
10
±1
±0.8
±15
0
±5
±3
Input Capacitance
REFERENCE (VREF1, VREF2)
Reference Voltage
Reference Temperature Coefficient
5
±100
V
nA
nA
15
pF
2.5
±3
V
ppm/°C
Output Voltage Hysteresis
Long-Term Drift5
160
320
Turn On Settling Time
5
ppm
ppm/
2000 hours
ms
REFERENCE BUFFER OUTPUT (VREFBUF)
Output Voltage Accuracy
Output Current
Load Regulation
Turn On Settling Time
REGULATOR OUTPUT (VREG5)
Output Voltage
Output Current
Line Regulation
Load Regulation
Internal Short-Circuit Protection Limit
CELL BALANCING OUTPUTS6
Output Voltage
High, VOH
Low, VOL
Ramp-Up and Ramp-Down Time
INTERNAL TEMPERATURE SENSOR
Accuracy1
Resolution
LOGIC INPUTS (EXCEPT RESET)
Input Voltage
High, VINH
Low, VINL
Input Current, IIN
Input Capacitance, CIN
−4.5
±1
+4.5
1
0.25
5
4.8
5
2
0.5
0.5
30
5.2
mV
mA
mV/mA
ms
7.5 V ≤ VDD ≤ 40 V
Convert start command
issued every 100 ms
Included in the TUE
specification
Primary reference
CREF1 = 1 μF//100 nF,
CREF2 = 1 μF//100 nF
Relative to VREF1 output voltage
CREFBUF = 1 μF
V
mA
mV/V
mV/mA
mA
CB1 to CB8 output
3.7
5
0
100
5.3
0.09
±3
0.03125
V
V
μs
°C
°C/LSB
VDRIVE × 0.7
VDRIVE × 0.3
10
5
Rev. C | Page 4 of 49
V
V
μA
pF
ISOURCE = 20 μA
For a 80 pF load
Measures junction
temperature
−30°C ≤ TJ ≤ +120°C
Data Sheet
Parameter
LOGIC OUTPUTS
Output Voltage
High, VOH
Low, VOL
Floating State
Leakage Current
Output Capacitance
RESET
tRESET
Leakage Current
POWER REQUIREMENTS
VDD Operating Range
Current Consumption on the
VDD Pin (IDD)
IDD During Conversion
IDD During Conversion Data
Readback
IDD During Cell Balancing
AD7284
Min
Max
Unit
Test Conditions/Comments
0.4
V
V
ISOURCE = 200 μA
ISINK = 200 μA
VDRIVE × 0.9
1
5
μA
pF
100
ns
60
10
Pulse width to reset or wake
up the AD7284 (VDRIVE high)
μA
40
V
Applies to master and slave
configurations
14
15
15
16.5
17
18
mA
mA
13
14
13
14
16
14
15
mA
mA
mA
12
30
100
14
40
mA
μA
μA
−4.5
−0.35
0.12
−4.0
−4.9
−0.32
0.56
−4.5
mA
mA
mA
mA
5.5
V
V
μA
IDD Idle
12
IDD Partial Power-Down Mode
IDD Full Power-Down Mode
IDD Matching Current
11
22
TXIBAL
IDIODE
RXIBAL
IMASTER
Master Configuration Only
VDRIVE
VDRIVE Threshold
IDRIVE
Typ
−3.9
−0.39
−3.5
3.0
0.8
15
1
Continuous readback
Device in partial power-down
To support transformerbased communications
Similar supply and
temperature conditions
across devices
Bit D6 in Control Register 2
Bit D5 in Control Register 2
Bit D4 in Control Register 2
Bit D3 in Control Register 2
Typically 3.3 V or 5 V
To wake up the master device
Guaranteed by design and/or characterization.
TUE includes the INL of the ADC, the gain and offset errors of the input channels, as well as the reference error; that is, the difference between the ideal and actual
reference voltage and the temperature coefficient of the reference.
3
These specifications assume that all cells are in the same input voltage range, for example, VPINx – VPIN(x – 1) range = 2 V to 3.6 V.
4
VSTK, the battery stack voltage, is scaled down internally by a factor of 16 before being applied to the ADC for measurement.
5
Data generated from high temperature operating life (HTOL) reliability testing.
6
For CB1 to CB5, the CBx output can be set to 0 V to 5 V with respect to the negative terminal of the cell being balanced. For CB6 to CB8, the CBx output can be set to
0 V to −5 V with respect to the positive terminal of the cell being balanced.
2
Rev. C | Page 5 of 49
AD7284
Data Sheet
ADC TIMING SPECIFICATIONS
Table 2. ADC Timing for Three Devices in a Chain
Parameter1
tCONV
tACQ
Min
tSTART
tDELAY
32
Max
Unit
ns
ns
ns
ns
ns
μs
ns
35
Description
ADC conversion time
ADC acquisition time, Bits[D1:D0] of Control Register 2 set to 00
ADC acquisition time, Bits[D1:D0] of Control Register 2 set to 01
ADC acquisition time, Bits[D1:D0] of Control Register 2 set to 10
ADC acquisition time, Bits[D1:D0] of Control Register 2 set to 11
Delay from rising edge of CS (conversion command issued) to the first conversion
Propagation delay between two devices in the daisy chain
All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load
capacitance.
TO INITIATE A CONVERSION,
SET B0 HIGH IN THE
ADCFUNC REGISTER
CS
CS HELD HIGH
DURING ADC CONVERSIONS
tACQ
tSTART
tCONV
INTERNAL ADC
CONVERSIONS
PART 1
DUMMY
CONVERSION
tDELAY
INTERNAL ADC
CONVERSIONS
PART 2
CELL7
INTERNAL TEMPERATURE
SENSOR
tDELAY
DUMMY
CONVERSION
tDELAY
INTERNAL ADC
CONVERSIONS
PART 3
CELL 8
CELL 16
CELL 15
tDELAY
DUMMY
CONVERSION
CELL 24
INTERNAL TEMPERATURE
SENSOR
tDELAY
CELL 23
Figure 2. ADC Timing Diagram for Three Devices in a Chain
Rev. C | Page 6 of 49
INTERNAL TEMPERATURE
SENSOR
14703-002
1
Typ
1040
400
800
1600
3200
33.6
100
Data Sheet
AD7284
SERIAL PERIPHERAL INTERFACE (SPI) TIMING SPECIFICATIONS
Table 3.
Parameter1
fSCLK
Min
t1
t23
t3
t4
t54
t6
t7
t8
t9
t105
t11
t12
200
Typ
500
7252
7252
Max
20
10
10
40
20
0.5 × tSCLK
0.5 × tSCLK
100
10
400
1.5
Unit
kHz
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Frequency of the serial read clock on the SCLK pin for write and read registers
Frequency of the serial read clock on the SCLK pin for write registers only
Frequency of the serial read clock on the SCLK pin for read conversion data on slave devices
CS falling edge to SCLK rising edge
Delay from CS falling edge to SDO active
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
Data access time after SCLK rising edge
SCLK to data valid hold time
SCLK high pulse width
SCLK low pulse width
CS rising edge to SCLK rising edge
CS rising edge to SDO high impedance
CS high time
Time from falling edge of last SCLK to rising edge of CS
1
All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load
capacitance.
Setting Bit D26 of the register address (see the Register Address section and Table 10) to 1 allows SCLK to increase to 725 kHz, as described in the Register Write and
Register Read Operations section.
3
Guaranteed by design and/or characterization.
4
Time required for the output to cross 0.4 V or 2.4 V.
5
t10 applies when using a continuous SCLK signal. Guaranteed by design.
2
t12
CS
2
3
t2
SDO
SDI
TRISTATE
4
32
t8
t5
MSB
t3
MSB – 1
t6
t4
MSB
t10
LSB
MSB – 1
LSB
Figure 3. SPI Timing Diagram for a 32-Bit CS Frame
Rev. C | Page 7 of 49
TRISTATE
14703-003
1
SCLK
t11
t9
t7
t1
AD7284
Data Sheet
ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings are defined with respect to the
normal operating specifications and not to other maximum
rating specifications. The mnemonics listed in the rating column
refer to the values as defined in the Specifications section only.
Table 4.
Parameter
VDD
MASTER
VDRIVE, VREG52
ADCGND1 to ADCGND2 to VSS
VPIN0, VSIN0
VPIN1 to VPIN7, VSIN1 to VSIN7
VPIN8, VSIN8
Pseudo Differential Input Voltage3
VPINx − VPIN(x − 1)
VPAUX1 to VPAUX4
CB1
CB2 to CB7
CB8
Relative Input/Output Voltages
CBx − VPINx − 1, x = 2 to 5
CBx − VPINx, x = 6 to 8
D_UP, D_UP
D_DWN, D_DWN
Digital Input Voltage
Digital Output Voltage
Analog Outputs (VREF1, VREFBUF, CCM)
ESD Human Body Model (HBM) Rating
ANSI/ESDA/JEDEC JS-001-2010
(Standard HBM), All Pins
Operating Junction Temperature Range
Absolute Maximum Junction
Temperature
Storage Temperature
Reflow Profile
Rating
VSS1 − 0.3 V to VSS + 48 V
VSS − 0.3 V to VDD + 0.3 V
VSS − 0.3 V to VSS + 6 V
−0.3 V to +0.3 V
VSS − 0.3 V to VSS + 0.3 V
VSS −0.3 V to VDD + 0.3 V
VDD −0.3 V to VDD +1 V
−0.3 V to +6 V
VSS − 0.3 V to VREG5 + 0.3 V
VSS − 0.3 V to VREG5 + 0.3 V
VSS to VDD
VDD − 6 V to VDD
−0.3 V to +6 V
−6 V to +0.3 V
VSS − 0.3 V to VDD + 7 V
VSS − 0.3 V to VREG5 + 0.3 V
VSS − 0.3 V to VDRIVE + 0.3 V
VSS − 0.3 V to VDRIVE + 0.3 V
VSS − 0.3 V to VREG5 +0.3 V
2.5 kV
The IPC 2221 industrial standard recommends the use of
conformal coating on high voltage pins.
THERMAL DATA
The junction temperature (TJ) refers to the temperature of the
silicon die within the package of the device when the device is
powered. The AD7284 parameters are specified over a junction
temperature range of −30°C to +120°C.
The absolute maximum junction temperature of the AD7284
is 150°C. The AD7284 may be damaged when the junction
temperature limit is exceeded. Monitoring of the junction
temperature, or the ambient temperature in conjunction with
an accurate thermal model, guarantees that TJ is within the
specified temperature limits.
Measure the junction temperature using the internal temperature
sensor.
Use the junction temperature (TJ) and the power dissipation
(PD) to calculate the ambient temperature (TA) by
TA = TJ − (PD × θJA)
where θJA is the junction to ambient thermal resistance of the
package.
THERMAL RESISTANCE
The AD7284 is in a 64-lead LQFP_EP package with an exposed
pad. The exposed pad is added for thermal performance purposes.
Thermal performance is directly linked to PCB design and
operating environment. Close attention to PCB thermal design
is required.
Table 5. Thermal Resistance1
−40°C to +120°C
150°C
Package Type
SW-64-2
1
150°C
J-STD 20 (JEDEC)
VSS, DGND, AGND1, AGND2, REFGND1, and REFGND2 are internally shorted
on chip and must be connected together on the printed circuit board (PCB).
See the pin descriptions of these pins in the Pin Configuration and Function
Descriptions section for additional information.
2
VREG5, AVCC, and DVCC are internally shorted on chip and must be connected
together on the PCB. See the pin descriptions of these pins in the Pin
Configuration and Function Descriptions section for additional information.
3
Applies to primary and secondary analog voltage inputs; x = 1 to 8.
θJC3
5
Unit
°C/W
Thermal impedance values take into account the localized heat distribution
on the die.
Test Condition 1: thermal impedance simulated values are based on a JEDEC 2S2P
thermal test board with 25 thermal vias. See the JEDEC51 standard.
3
Estimated value based on measurements from similar packages.
2
1
θJA2
32
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 8 of 49
Data Sheet
AD7284
ADCGND2
REFGND2
AGND2
DNC
VREG5
DNC
D_UP
D_UP
CB8
CB7
CB6
CB5
VSIN5
VSIN6
VSIN7
VSIN8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDD 1
48
VREF2
VDD 2
47
DNC
VPIN8 3
46
MASTER
VPIN7 4
45
DGND
VPIN6 5
44
GPOP1
VPIN5 6
43
GPOP2
42
DVCC
41
CCM
40
RESET
VPIN1 10
39
VDRIVE
VPIN0 11
38
CS
VSS 12
37
SCLK
VSS 13
36
SDI
AGND1 14
35
SDO
CB1 15
34
D_DWN
CB2 16
33
D_DWN
VPIN4 7
AD7284
VPIN3 8
TOP VIEW
(Not to Scale)
VPIN2 9
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
2. THE EXPOSED PAD IS PROVIDED FOR THERMAL PURPOSES AND MUST BE SOLDERED DOWN TO THE BOARD.
THE EXPOSED PAD IS INTERNALLY CONNECTED TO VSS ON THE DIE AND MUST BE CONNECTED TO THE
VSS PIN OF THE DEVICE ON THE PCB.
14703-004
AVCC
VPAUX4
VPAUX3
VPAUX2
VPAUX1
VREF1
VREFBUF
REFGND1
ADCGND1
VISIN0
VISIN1
VISIN2
VISIN3
VISIN4
CB4
CB3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1, 2
Mnemonic
VDD
3 to 11
VPIN8 to VPIN0
12, 13
VSS
14, 51
AGND1, AGND2
15 to 18, 57
to 60
CB1 to CB8
19 to 23,61
to 64
VSIN0 to VSIN8
24, 49
ADCGND1,
ADCGND2
REFGND1,
REFGND2
VREFBUF
25, 50
26
Description
Positive Power Supply Voltage. These pins are connected to the top of the battery stack. Place 4.6 μF to
4.8 μF decoupling capacitors on the VDD pins. It is also recommended that a current limiting resistor be
connected between VDD and the top of the stack.
Primary Analog Voltage Inputs for Monitoring Up to Eight Cells. Connect VPIN0 to the base of the series
of the connected battery cells and, therefore, to the bottom of Cell 1. Connect VPIN1 to the top of Cell 1,
connect VPIN2 to the top of Cell 2, and so on.
Negative Power Supply Voltage. These pins are connected to the bottom of the battery stack. These
inputs must be at the same potential as all the analog and digital grounds of the device.
Analog Ground Pins. These pins are the ground reference point for most of the analog circuitry on the
AD7284. These inputs must be at the same potential as VSS.
Cell Balance Outputs for Balancing Up to Eight Cells. These pins provide a voltage output that can supply
the gate drive of an external cell balancing transistor. The CB1 to CB5 outputs provide a 0 V to 5 V voltage
output referenced to the absolute voltage of the negative terminal of the battery cell that is being
balanced. The CB6 to CB8 outputs provide a 0 V to −5 V voltage output referenced to the absolute
voltage of the positive terminal of the battery cell that is being balanced.
Secondary Analog Voltage Inputs for Monitoring Up to Eight Cells. These pins can connect directly to the
corresponding primary analog voltage inputs, or they can connect separately to the battery cells. If
connected separately to the battery cells, connect VSIN0 to the base of the series connected battery cells
and, therefore, to the bottom of Cell 1. Connect VSIN1 to the top of Cell 1, connect VSIN2 to the top of
Cell 2, and so on.
Analog Grounds for the Primary and Secondary ADCs. These pins must be at the same potential as VSS.
Reference Grounds. These pins are the ground reference points for the primary and secondary internal
band gap references. These pins must be at the same potential as VSS.
2.5 V Reference Buffer Output Voltage. A 1 μF decoupling capacitor connected to REFGND1 is recommended
on this pin.
Rev. C | Page 9 of 49
AD7284
Data Sheet
Pin No.
27
Mnemonic
VREF1
28 to 31
VPAUX1 to
VPAUX4
AVCC
32
33, 34
D_DWN,
D_DWN
35
SDO
36
SDI
37
SCLK
38
CS
39
VDRIVE
40
RESET
41
CCM
42
DVCC
43, 44
GPOP2, GPOP1
45
DGND
46
MASTER
47, 52, 54
48
DNC
VREF2
53
VREG5
55, 56
D_UP, D_UP
Exposed Pad
Description
2.5 V Primary Reference Output Voltage. A 1 μF capacitor in parallel with a 100 nF decoupling capacitor
connected to REFGND1 is recommended on this pin. VREF1 can be driven from an external reference, but
it must not be used to drive any other circuit.
Primary Auxiliary ADC Inputs (0 V to 5 V, Single-Ended). If any of these inputs are not required in the
application, it is recommended that these pins be connected to VREG5 or VSS through a 10 kΩ resistor.
Analog Supply Voltage. Decouple this supply pin to AGND1 with a 100 nF decoupling capacitor and
connect this pin to the VREG5 output pin.
Daisy-Chain Lower Interface Ports. On slave devices, terminate these pins with a 50 Ω resistor connected
to the CCM pin. These pins are connected to the D_UP and D_UP pins on the AD7284 device below it in
the daisy chain. On a master device, these pins are not used; connect these pins to VSS via a 1 kΩ resistor
instead.
Serial Data Output When Master Device. On a slave AD7284 device, this pin is not used and can be left
unconnected.
Serial Data Input When Master Device. On a slave AD7284 device, this pin is not used and can be pulled
low to DGND via a 1 kΩ resistor.
Serial Clock Input When Master Device. On a slave AD7284 device, this pin is not used and can be pulled
low to DGND via a 1 kΩ resistor.
Chip Select Input When Master Device. On a slave AD7284 device, this input is not used and can be
connected to VSS via a 1 kΩ resistor.
Digital Input/Output Supply Input. On a master device, connect an external voltage supply to the VDRIVE pin.
The voltage supplied at this pin determines the voltage at which the SPI interface operates. Decouple
this pin to DGND with a 100 nF decoupling capacitor. On a master device, pulling VDRIVE low powers down
the device unless an active power-down timer is running. After the expiration of the power-down timer,
the device powers down. On a slave device, connect the VDRIVE pin to VREG5.
Digital Input. An active high signal causes the device to reset to the power-on state. This input is internally
pulled down. When this input is not used, an external 1 kΩ pull-down resistor to DGND is recommended.
Common-Mode Decoupling Capacitor Port. This pin supplies a 2 V level used for the daisy-chain
common mode. A 1 μF decoupling capacitor to VSS is required on this pin.
Digital Supply Voltage. Connect the DVCC supply pin to the VREG5 output pin. Decouple this digital supply
to DGND with a 100 nF decoupling capacitor.
General-Purpose Outputs. These pins provide a voltage output level of 0 V for a low signal and a voltage
output level of VDRIVE for a high signal.
Digital Ground. This pin is the ground reference point for all digital circuitry on the AD7284. This pin
must be at the same potential as VSS.
Voltage Input. When the AD7284 acts as a master, connect this pin to the VDD supply pin through a 10 kΩ
resistor. When the AD7284 acts as a slave, connect this pin to the VSS supply pin of the same AD7284 device
through a 10 kΩ resistor.
Do Not Connect. Do not connect to these pins.
2.5 V Secondary Reference Output Voltage. A 1 μF capacitor in parallel with a 100 nF decoupling
capacitor to REFGND2 is recommended on this pin. VREF2 can not be driven externally and must not be
used to drive any other circuit.
5 V Analog Voltage Output. The internally generated VREG5 voltage provides the supply voltage for the
ADC core. A 100 nF decoupling capacitor to AGND2 is required on the VREG5 pin.
Daisy-Chain Upper Interface Ports. Terminate these pins with a 50 Ω resistor connected to the VDD pin
directly for configurations using transformer isolation or via a capacitor when using the direct coupled
configuration. The D_UP pin is connected to the D_DWN pin of the AD7284 device above it in the daisy
chain, and the D_UP pin is connected to the D_DWN pin of the AD7284 device above it in the daisy chain.
Exposed Pad. The exposed pad is provided for thermal purposes and must be soldered down to the
board. The exposed pad is internally connected to VSS on the die and must be connected to the VSS pin of
the device on the PCB.
Rev. C | Page 10 of 49
Data Sheet
AD7284
600
3
500
2
400
1
TUE (mV)
300
–1
200
13103
13104
13105
13106
13107
13108
–3
–40
14703-005
0
13109
CODE
–20
0
20
40
60
80
100
120
140
JUNCTION TEMPERATURE (°C)
Figure 8. TUE vs. Junction Temperature, Preassembly, VDD = 18 V
Figure 5. Typical Code Noise for VPIN1 Through VPIN8, VDD = 32 V, TJ = 60°C
3
500
2
400
1
TUE (mV)
600
300
14703-008
–2
100
HITS
0
0
–1
200
–2
100
6551
6552
6553
6554
6555
6556
–3
–40
14703-006
0
6557
CODE
–20
0
20
40
60
80
100
120
140
JUNCTION TEMPERATURE (°C)
14703-009
HITS
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. TUE vs. Junction Temperature, Postassembly, VDD = 18 V
Figure 6. Typical Code Noise for VSTK, VDD = 32 V, TJ = 60°C
5
3.0
4
2.5
ERROR (°C)
2.0
3
1
2
3
4
5
2
TUE (mV)
DUT
DUT
DUT
DUT
DUT
1.5
1.0
1
0
–1
–2
–3
0.5
–20
0
20
40
60
80
100
INTERNAL TEMPERATURE (°C)
120
140
Figure 7. Error vs. Internal Temperature for Various Devices Under Test (DUT)
Rev. C | Page 11 of 49
–5
–40
–20
0
20
40
60
80
100
120
140
JUNCTION TEMPERATURE (°C)
Figure 10. TUE vs. Junction Temperature, Preassembly, VDD = 32 V
14703-010
0
–40
14703-007
–4
AD7284
Data Sheet
5.20
5
4
5.15
3
10.0V
18.0V
25.6V
32.0V
39.8V
5.10
5.05
1
VREG5 (V)
TUE (mV)
2
0
–1
5.00
4.95
–2
4.90
–3
–20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
140
4.80
–40
14703-011
–5
–40
–20
0
20
40
60
80
100
14703-016
4.85
–4
120
JUNCTION TEMPERATURE (°C)
Figure 14. Preassembly 5 V Voltage Regulator Output (VREG5) vs. Junction
Temperature
Figure 11. TUE vs. Junction Temperature, Postassembly, VDD = 32 V
5.20
2.505
5.15
2.501
10.0V
18.0V
25.6V
32.0V
39.8V
5.10
10.0V
18.0V
25.6V
32.0V
39.8V
5.05
VREG5 (V)
VREF1 (V)
2.503
2.499
5.00
4.95
4.90
2.497
–20
0
20
40
60
80
100
4.80
–40
14703-012
120
JUNCTION TEMPERATURE (°C)
Figure 12. Preassembly Primary Voltage Reference, VREF1 vs. Junction
Temperature
20
40
60
80
100
120
Figure 15. Postassembly 5 V Voltage Regulator Output (VREG5) vs. Junction
Temperature
2.505
10.0V
18.0V
25.6V
32.0V
39.8V
2.503
2.503
2.501
VREF1 (V)
VREF1 (V)
0
JUNCTION TEMPERATURE (°C)
2.505
2.499
2.497
10.0V
25.6V
32.0V
39.8V
2.501
2.499
2.497
–20
0
20
40
60
80
100
2.495
–40
14703-013
2.495
–40
–20
120
JUNCTION TEMPERATURE (°C)
Figure 13. Postassembly Primary Voltage Reference, VREF1 vs. Junction
Temperature
–20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
Figure 16. Preassembly Buffered Voltage Reference, VREF1 vs. Junction
Temperature
Rev. C | Page 12 of 49
14703-018
2.495
–40
14703-017
4.85
Data Sheet
AD7284
2.503
2.505
2.501
VREF1 (V)
2.501
2.499
2.500
2.499
2.497
–20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (°C)
2.497
0
100
200
300
400
500
TIME (Hours)
Figure 18. VREF1 vs. Time,
0 Hours to 500 Hours Accelerated Lifetime Drift (HTOL)
Figure 17. Postassembly Buffered Voltage Reference, VREF1 vs.
Junction Temperature
Rev. C | Page 13 of 49
600
14703-120
2.495
–40
2.498
14703-019
VREF1 (V)
2.502
10.0V
18.0V
25.6V
32.0V
39.8V
2.503
AD7284
Data Sheet
TERMINOLOGY
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (a point 1 LSB
below the first code transition) and full scale (a point 1 LSB above
the last code transition).
Offset Code Error
Offset code error applies to straight binary output coding. It is
the deviation of the first code transition (00 … 000) to (00 …
001) from the ideal, that is, AGND + 1 LSB.
Gain Error
Gain error applies to straight binary output coding. It is the
deviation of the last code transition (111 … 110) to (111 … 111)
from the ideal (that is 2 × VREF1 − 1 LSB) after adjusting for the
offset error.
ADC Unadjusted Error
ADC unadjusted error includes INL errors, as well as offset and
gain errors of the ADC and measurement channel.
Total Unadjusted Error (TUE)
TUE is the maximum deviation of the output code from the
ideal. TUE includes INL errors, offset and gain errors, and
reference errors. Reference errors include the difference
between the actual and ideal reference voltage (that is, 2.5 V)
and the reference voltage temperature coefficient.
Reference Voltage Temperature Coefficient
The reference voltage temperature coefficient (tempco) is
derived from the maximum and minimum reference output
voltage (VREF) measured between TMIN and TMAX. It is expressed
in ppm/°C using the following equation:
Tempco VREF (ppm/°C) =
V REF ( MAX ) VREF ( MIN )
2.5 V (TMAX TMIN )
× 10 6
Output Voltage Hysteresis
Output voltage hysteresis, or thermal hysteresis, is defined as
the absolute maximum change of the reference output voltage
after the device is cycled through temperature from either
T_HYS+ or T_HYS−, where
T_HYS+ = 25°C to TMAX to 25°C
T_HYS− = 25°C to TMIN to 25°C
It is expressed in ppm using the following equation:
VREF
VHYS (ppm) =
(25C)
VREF (T _ HYS)
VREF (25C)
× 106
where:
VREF (25°C) = VREF at 25°C.
VREF (T_HYS) is the maximum change of VREF at T_HYS+ or
T_HYS−.
Static Leakage Current
Static leakage current is the current that is measured on the cell
voltage and/or the auxiliary ADC inputs when the device is
static, that is, not converting.
Dynamic Leakage Current
Dynamic leakage current is the current measured on the cell
voltage and/or the auxiliary ADC inputs, when converting, with
the static leakage current subtracted. The dynamic leakage
current is specified with a convert start command issued every
100 ms. Calculate the dynamic leakage current for a different
conversion using the following equation:
I
DYN (B)
I
DYN (A)
f
CNVST (B)
fCNVST (A)
where:
IDYN (B) is the dynamic leakage at the desired convert start
frequency, fCNVST (B).
IDYN (A) is the dynamic leakage at convert start frequency, fCNVST (A).
where:
VREF (MAX) is the maximum VREF between TMIN and TMAX.
VREF (MIN) is the minimum VREF between TMIN and TMAX.
TMAX = 120°C.
TMIN = −30°C.
Rev. C | Page 14 of 49
Data Sheet
AD7284
THEORY OF OPERATION
The AD7284 is a Li-Ion battery monitoring device that can
monitor eight series connected Li-Ion battery cells and four
additional voltage inputs.
The AD7284 consists of a primary measurement path and a
secondary measurement path, allowing the host microcontroller to
perform a comparison of the two sets of acquired data.
Take the VDD and VSS supplies required by the AD7284 from the
battery cells being monitored by the device. An internal VREG5 rail
is generated to provide power for the internal AD7284 core.
The AD7284 includes two on-chip 2.5 V reference output voltages,
VREF1 and VREF2. Additionally, the VREFBUF analog output voltage
provides a buffered version of the VREF1 primary reference to
allow the connection of external thermistors and to provide a
ratiometric temperature measurement using the four primary
auxiliary inputs, VPAUX1 to VPAUX4.
The primary measurement path consists of a voltage input
multiplexer and a successive approximation register (SAR) ADC,
providing 14 bits of resolution. The primary analog voltage inputs,
VPIN0 to VPIN8, with a set of external filtering components,
allow the individual voltage monitoring of eight cells, plus a
stack voltage measurement. The primary auxiliary inputs,
VPAUX1 to VPAUX4, can monitor temperatures or be used for
external diagnostics. The primary measurement path also
measures VREG5, VREF2, and the internal temperature sensor. The
VREF2 measurement allows the host microcontroller to verify the
operation of the primary measurement path.
The secondary measurement path consists of a voltage input
multiplexer and a SAR ADC providing 10 bits of resolution.
The secondary analog voltage inputs, VSIN0 to VSIN8, allow
a second set of voltage measurements on the eight cells. The
secondary analog voltage inputs can connect with a second set of
external filtering components, or these inputs can connect
directly to VPIN0 to VPIN8 on the primary measurement path
to minimize the use of external components, if desired. The
secondary measurement path also measures VREG5 and VREF1. The
VREF1 measurement allows the host microcontroller to verify the
operation of the secondary measurement ADC.
The AD7284 provides eight outputs to control external transistors
as part of a cell balancing circuit. The CB1 to CB5 outputs
provide a 0 V to 5 V output voltage referenced to the absolute
voltage of the negative terminal of the battery cell that is being
balanced. The CB6 to CB8 outputs provide a 0 V to −5 V output
voltage referenced to the absolute voltage of the positive
terminal of the battery cell that is being balanced.
The AD7284 features a differential daisy-chain interface. A
chain of AD7284 devices can monitor the cell voltages and
temperatures of a larger number of cells, as shown in Figure 19.
The conversion data from each AD7284 in the chain passes
through the master device to the system controller via a single
SPI interface. Control data can be similarly passed via the single
SPI interface to the master AD7284 device and up the differential
daisy-chain interface to each individual AD7284 device in the
daisy chain.
+HV
BATTERY
PACKS
AD7284
SLAVE N
AD7284
SLAVE 1
2-WIRE DAISY CHAIN
AD7284
MASTER
SPI
HOST
MICROCONTROLLER
–HV
14703-021
CIRCUIT INFORMATION
Figure 19. Simplified System Diagram with Multiple AD7284 Devices
(Additional Circuitry Omitted for Clarity)
The AD7284 also has a VDRIVE feature to control the voltage at
which the serial interface operates. VDRIVE allows the AD7284 to
interface to both the 3.3 V and the 5 V processors.
In the event of communication loss, a watchdog timer places
the unresponsive devices in the chain into power-down mode.
Rev. C | Page 15 of 49
AD7284
Data Sheet
CONVERTER OPERATION
Converter Configurations
The primary and secondary conversion paths of the AD7284
each consist of an input multiplexer and a SAR ADC.
The two converters on the AD7284 are SAR ADCs. They are
composed of a comparator, SAR control logic, and two
capacitive digital-to-analog converters (DACs).
Multiplexer Configuration
Each multiplexer selects a pair of analog inputs to convert:
VPIN0 to VPIN8 for the primary path and VSIN0 to VSIN8 for
the secondary path. The voltage of each individual cell is
measured by converting the difference between the adjacent
analog inputs, that is, VPIN1 − VPIN0, VPIN2 − VPIN1, and
so on (see Figure 20 and Figure 21).
Figure 22 shows a simplified schematic of the SAR ADC. During
the acquisition phase, the SW1, SW2, and SW3 switches are
closed. The sampling capacitor array, CS, acquires the signal on
the input during this phase.
CAPACITIVE
DAC
CS
VxIN8
SW1
VxIN7
ADC VIN–
VxIN5
SW2
SW4
SW3
CONTROL
LOGIC
CS
ADC V IN+
CAPACITIVE
DAC
ADC V IN–
NOTES
1. THE CONVERTER INPUTS ARE ADC VIN+ AND ADC V IN–.
VxIN4
14703-024
VxIN6
COMPARATOR
ADC V IN+
VxIN3
Figure 22. SAR ADC Configuration During the Acquisition Phase
VxIN2
When the ADC starts a conversion, SW1, SW2, and SW3 open,
and SW4 closes, causing the comparator to become unbalanced
(see Figure 23). The control logic and capacitive DACs add and
subtract fixed amounts of charge to return the comparator to a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. This output code is then stored in the appropriate
register for the converted input.
14703-022
VxIN1
VxIN0
Figure 20. Multiplexer Configuration During VxIN8 to VxIN7 Sampling (Cell 8)
VxIN8
VxIN7
VxIN5
CAPACITIVE
DAC
ADC V IN+
CS
COMPARATOR
ADC VIN+
ADC V IN–
SW1
VxIN4
ADC V IN–
SW2
SW4
SW3
CS
VxIN3
CAPACITIVE
DAC
VxIN2
NOTES
1. THE CONVERTER INPUTS ARE ADC VIN+ AND ADC V IN–.
14703-023
VxIN1
VxIN0
CONTROL
LOGIC
14703-025
VxIN6
Figure 23. SAR ADC Configuration During the Conversion Phase
Figure 21. Multiplexer Configuration During VxIN7 to VxIN6 Sampling (Cell 7)
Transfer Function
The conversion data readback for each voltage measurement
consists of 14 bits. The output coding of the AD7284 primary
measurement path is in 14-bit, straight binary format. The output
coding of the AD7284 secondary measurement path is in 10-bit,
straight binary format. The result is inverted so that it is easily
distinguished from the primary measurement and is preceded
by four data bits set to 0000.
Rev. C | Page 16 of 49
Data Sheet
AD7284
The LSB size is dependent on whether the primary measurement
path or the secondary measurement is used. The analog input
range of the voltage inputs is 0 V to 5 V. The designed code
transitions occur at successive integer LSB values (that is, 1 LSB,
2 LSBs, and so on). The ideal transfer characteristic is shown in
Figure 24.
The AD7284 provides four single-ended analog inputs to the
primary ADC, VPAUX1 to VPAUX4. The input voltage range is
0 V to 5 V with respect to VSS. These inputs can convert other
voltages within the system, such as converting the voltage
output of a thermistor temperature measurement circuit.
Table 7. LSB Size for the Analog Input Range
VOLTAGE REFERENCES
1
Full-Scale Range1
5 V/16,384
5 V/1,024
Input Range
0 V to 5 V
0 V to 5 V
The AD7284 contains two identical 1.2 V band gap voltage
references. These references are internally buffered and gained
to provide 2.5 V reference voltages to the primary (VREF1) and
secondary (VREF2) ADCs, as shown in Figure 25.
LSB Size
305 μV
4.88 mV
The 16,384 and 1,024 values in this column represent the number of codes
available for each ADC.
The provision of two reference voltages is a diagnostic feature
and enables validation of the behavior of the measurement
paths and the references. For example, the secondary ADC
measures the primary reference, VREF1. Similarly, the primary
ADC measures the secondary reference, VREF2.
ADC CODE
111...111
111...110
111...000
An external 2.5 V reference can overdrive the reference for the
primary path, VREF1. When an external reference is used, set
Bit D4 of Control Register 1 to disable the VREF1 buffer. The
secondary measurement path measures the external reference
in this case.
011...111
AGNDx + 1LSB
5V – 1LSB
ANALOG INPUT
14703-026
000...010
000...001
000...000
The primary reference is further buffered and provided as a
reference output, VREFBUF, to bias external thermistors. This
buffer is capable of driving currents up to 1 mA, allowing the
user to connect up to four 10 kΩ thermistor circuits in parallel.
The primary conversion includes a measure of this voltage level.
Figure 24. Ideal Transfer Characteristic
INTERNAL TEMPERATURE SENSOR
The AD7284 contains an on-chip temperature sensor. The
temperature measurement updates with each conversion
request and is provided as part of each conversion frame.
Decouple the VREFBUF pin to ADCGND1 using a 1 μF capacitor.
Decouple the VREF1 pin to ADCGND1 using a 1 μF capacitor
with a 100 nF capacitor in parallel. Decouple the VREF2 pin to
ADCGND2 using a 1 μF capacitor with 100 nF capacitor in
parallel.
The temperature sensor measures the junction temperatures in
the −30°C to +120°C range with a typical accuracy of ±3°C.
The output coding of the temperature sensor is twos complement,
with a resolution of 32 LSB/°C. Code 0 corresponds to 25°C
(junction temperature).
Larger decoupling capacitors can be used to decouple VREF1 and
VREF2; however, this results in the reference taking longer to
power up. The turn on settling time is typically 5 ms with the
recommended decoupling capacitor values.
REFERENCE BUFFER
VREFBUF
+1
1µF
REFGND1
PRIMARY
2.5V
BAND GAP
1.2V
LOW
VOLTAGE
MULTIPLEXER
PRIMARY
ADC
VREF1
SW
1µF
REFGND2
SECONDARY
BAND GAP
1.2V
ADCGND1
100nF
EXTERNAL
2.5V
VREF
ADCGND1
2.5V
VREF2
LOW
VOLTAGE
MULTIPLEXER
SECONDARY
ADC
1µF
Figure 25. Internal References and Optional External Reference
Rev. C | Page 17 of 49
100nF
ADCGND2
14703-027
Measurement
Path
Primary
Secondary
AUXILIARY ADC INPUTS
AD7284
Data Sheet
The analog voltage inputs must be filtered externally with a
single-ended low-pass filter approach. The resistors, RF, in
series with the VPIN0 to VPIN8 and VSIN0 to VSIN8 inputs
provide protection for the analog inputs in the event of an
overvoltage or undervoltage condition on those inputs (for
example, if any of the cell voltage inputs are incorrectly shorted
to VDD or VSS). The resistors also provide protection during the
initial connection of the daisy chain of AD7284 devices to the
battery stack. The CF capacitors, in conjunction with the RF
resistors, act as a low-pass filter. CF capacitor values between
100 nF and 1 μF are recommended. The cutoff frequency of the
low-pass filter when using an RF of 1 kΩ and a CF capacitor of
1 μF is 160 Hz. The cutoff frequency of the low-pass filter when
using a CF capacitor of 100 nF is 1600 Hz.
CELL CONNECTIONS
The AD7284 can monitor four to eight battery cells connected
in series.
Typical Eight Cell Configuration
Figure 26 shows the typical connections to the AD7284 supply
and cell monitoring inputs in an eight cell configuration.
100nF
VDD
CVDD
RF
CELL 8
CELL 7
CELL 6
CELL 5
CELL 4
CELL 3
CELL 2
CELL 1
VDD
VPIN8
CF
RF
VPIN7
CF
RF
The time constant of the RF and CF filters on the primary and
secondary paths must match the time constant on the VDD pins
fairly closely (for example, 100 nF (CF) and 1 kΩ (RF) on the
inputs, and 4.7 μF (CVDD) and 20 Ω (RVDD) on VDD).
VPIN6
CF
RF
VPIN5
CF
RF
VPIN4
Connection to Fewer Voltage Cells
CF
RF
While the AD7284 provides eight input channels for battery cell
voltage measurement, it can also be used in applications that
require fewer than eight cell voltage measurements. When used
in this manner, ensure that the sum of the individual cell voltages
still exceeds the minimum VDD supply voltage (10 V).
VPIN3
CF
RF
VPIN2
CF
RF
VPIN1
CF
RF
The minimum number of cells connected to each AD7284 is
four. Figure 27 shows the recommended connections to
monitor four cells. The unused inputs are connected together
and connected between Cell 2 and Cell 3 via a resistor. The
resistor minimizes the leakage from the unused inputs.
VPIN0
CF
RF
CF
CF
CF
CF
CF
CF
CF
CF
CF
AD7284
VSIN8
VSIN7
Irrespective of how many cells are connected, the AD7284
acquires and converts all eight voltages. All conversion results
are available for readback; results of the unused voltage channels
are zero.
VSIN6
VSIN5
VSIN4
VSIN3
VSIN2
VPIN8
VSIN1
VPIN7
VSIN0
VPIN6
VSS
VPIN5
VSS
VPIN4
Figure 26. Typical Cells and Supply Connections (Additional Circuitry
Omitted for Clarity)
VPIN3
A series resistor, RVDD (10 Ω to 40 Ω), is recommended from the
top of the battery into the VDD supply pins. The total decoupling
capacitors on the supply pins, CVDD, must be 4.7 μF.
VPIN1
AD7284
VPIN2
VPIN0
14703-029
TRANSIENT
PROTECTION
14703-028
RVDD
Figure 27. Typical Connection with Minimum Cells Connected (Additional
Circuitry Omitted for Clarity)
Rev. C | Page 18 of 49
Data Sheet
AD7284
Connection of Unused Secondary Channel Inputs
In applications where the secondary path is not used, connect
the VSINx pins directly to the corresponding VPINx pins.
By default, the two ADCs convert simultaneously. To minimize
the discharge of the CF capacitor during the acquisition phase,
enable the delay mode between conversions. The ADC delay
mode is controlled by Control Register 3, Bit 6.
Acquisition Time
The time required to acquire an input signal depends on how
quickly the sampling capacitor is charged. This, in turn, depends
on the input impedance and any external components placed on
the analog inputs. The default acquisition time of the AD7284 on
initial power-up is 400 ns. To accommodate the use of alternative
input filter configurations, the acquisition time can be set to
400 ns, 800 ns, 1600 ns, or 3200 ns using Bits[D1:D0] in
Control Register 2 (see Table 22).
Calculate the minimum acquisition time required, tACQ, by
tACQ = 10 × ((RSOURCE + R) × C)
where:
RSOURCE includes any extra source impedance on the analog
input between the external capacitors and the input pins. It does
not include any extra source impedance, for example, the 1 kΩ
series resistors, which are between the battery cells and the
external capacitors.
R is the internal switch and path resistance, typically 620 Ω.
C is the sampling capacitance, typically 15 pF.
The secondary path consists of 10 measurements available in
the following order:
1.
2.
3.
To read back one measurement from the secondary path, all
10 measurements must be read back for each device (see the
Conversion Data Readback section).
The results are read back via the 4-wire SPI.
Internal Voltage Measurements
Table 8 and Table 9 show the range of the expected measured
reference values that are returned on each measurement cycle.
Detecting one of these values outside of the indicated range
indicates a fault condition.
Table 8. Primary Internal Voltage Measurement
Parameter
VREF2
VREG5 × 2/3
VREFBUF
VREG5 × 2/3
Min
2.485
3.200
2.486
3.200
Max
2.515
3.421
2.514
3.421
Unit
V
V
V
V
Register
0x12
0x13
0x1C
0x1D
Table 9. Secondary Internal Voltage Measurement
Parameter
VREF1
VREG5 × 4/5
ADC CONVERSIONS SEQUENCE
Upon completion of a conversion sequence, the primary and
secondary path measurements are available for read back. The
primary path measurements must be read first. Reading the
secondary path measurements is optional.
The primary path consists of 18 measurements available in the
following order:
1.
2.
3.
4.
5.
6.
7.
8.
Cell Voltage 1 to Cell Voltage 8.
Primary path reference voltage.
VREG5 voltage scaled by 4/5.
Cell Voltage 1 to Cell Voltage 8.
Stack voltage scaled down by 16.
Secondary path reference voltage.
VREG5 voltage scaled by 2/3.
Primary Auxiliary Input 1 to Primary Auxiliary Input 4.
Reference buffer output voltage.
Repeated VREG5 voltage scaled by 2/3.
Internal temperature sensor.
All 18 measurements must be read back on each device as
described in the Conversion Data Readback section.
Rev. C | Page 19 of 49
Min
2.475
3.865
Max
2.525
4.135
Unit
V
V
Register
0x31
0x34
AD7284
Data Sheet
Similarly, calculate the conversion time for eight cell voltages by
CONVERTING WITH A SINGLE AD7284
Conversion Time per Eight Primary Cells = (tACQ + tCONV) × 9
Conversions are initiated on the AD7284 by setting Bit D0 high
in the ADC functional control register. A single conversion
command initiates conversions on all channels of the AD7284.
The conversions on the primary measurement path and the
secondary measurement path occur in parallel, as shown in
Figure 28. As described in the Converter Operation section, the
voltage of each individual battery cell is measured by converting
the difference between the adjacent analog inputs. The first
conversion starts tSTART after the conversion start command.
This conversion is a dummy conversion that has the same
timing as a normal conversion and provides additional acquisition
time for the first cell conversion. The first cell converted is Cell 8
(VPIN8 − VPIN7), then Cell 7 (VPIN7 − VPIN6), and so on, as
shown in Figure 28.
where the 9th conversion is the dummy conversion.
The device conversion time includes the internal temperature
sensor channel, which requires a longer acquisition and conversion
time (typically 276 μs). Therefore, calculate the conversion time
per device by
Conversion Time per Device = tSTART + ((tACQ + tCONV) × 18) + 276 μs
where:
tSTART is the time between the rising edge of CS to the dummy
conversion. See Table 2.
tACQ is the analog input acquisition time. See Table 2.
tCONV is the conversion time. See Table 2.
Factor 18 is the one dummy conversion plus seventeen
measurements.
Calculate the conversion time per channel by
Conversion Time per Channel = tACQ + tCONV
With an acquisition time set to 400 ns, the conversion time per
device is typically 336 μs.
TO INITIATE A CONVERSION,
SET BIT D0 HIGH IN THE
ADCFUNC REGISTER
CS HELD HIGH
DURING ADC CONVERSIONS
CS
tACQ
tSTART
tCONV
DUMMY
CONVERSION
CELL 8
CELL7
INTERNAL SECONDARY
ADC CONVERSIONS
DUMMY
CONVERSION
CELL 8
CELL7
Figure 28. ADC Conversions with a Single Device
Rev. C | Page 20 of 49
INTERNAL TEMPERATURE
SENSOR
CELL6
LDO
14703-030
INTERNAL PRIMARY
ADC CONVERSIONS
Data Sheet
AD7284
The latency across all cells is the delay between the start of
converting the first cell and the start of converting on the last
cell of a battery stack, as shown in Figure 30. Calculate this
latency by
CONVERTING WITH A CHAIN OF AD7284 DEVICES
The AD7284 provides a daisy-chain interface that allows up
to 30 AD7284 devices to stack. One feature of the daisy-chain
interface is the ability to initiate conversions on all devices in
the daisy-chain stack with a single convert start command. The
convert start command transfers up the daisy chain from the
master device to each AD7284 in turn. The delay time between
each AD7284 is tDELAY, as shown in Figure 29. Note that this
diagram is simplified to show the primary measurement path
only.
Latency Across All Cells = (Conversion Time of Seven Cells) +
((N − 1) × tDELAY)
With an acquisition time set to 400 ns, the latency across 96 cells is
typically 13 μs.
Calculate the total conversion time for all channels by
Total Conversion Time = (Conversion Time per Device) +
((N − 1) × tDELAY)
where:
N is the number of AD7284 devices in the daisy chain.
tDELAY is the delay time when transferring the convert start
command between adjacent AD7284 devices, as specified in
Table 2.
TOTAL CONVERSION TIME = (CONVERSION TIME PER DEVICE) + ((N – 1) × tDELAY )
INTERNAL ADC
CONVERSIONS
PART 2
INTERNAL ADC
CONVERSIONS
PART 3
INTERNAL TEMPERATURE
SENSOR
DUMMY
CONVERSION
DUMMY
CONVERSION
INTERNAL TEMPERATURE
SENSOR
INTERNAL TEMPERATURE
SENSOR
DUMMY
CONVERSION
14703-031
INTERNAL ADC
CONVERSIONS
PART 1
Figure 29. ADC Conversions with a Chain of Three Devices
LATENCY ACROSS ALL CELLS =
(CONVERSION TIME OF SEVEN CELLS) + ((N – 1) × tDELAY)
INTERNAL ADC
CONVERSIONS
PART 1
INTERNAL ADC
CONVERSIONS
PART 2
DUMMY
CONVERSION
CELL 8
CELL 7
CELL 2
CELL 1
tDELAY
DUMMY
CONVERSION
CELL 16
CELL 10
CELL 15
CELL 9
(N – 2) × tDELAY
DUMMY
CONVERSION
CELL (N × 8)
CELL (N × 8) – 1
Figure 30. Latency Across All Cells
Rev. C | Page 21 of 49
CELL (N × 8) – 6 CELL (N × 8) – 7
14703-032
7 CONVERSIONS
INTERNAL ADC
CONVERSIONS
PART N
AD7284
Data Sheet
Following a conversion, the primary conversion data for all
devices in the daisy chain is available for readback. To enable
secondary conversion data readback, a command is issued as
shown in Figure 32. This is the only 32-bit command that can
be issued while in 64-bit mode.
CONVERSION DATA READBACK
A sequence with ADC conversions and a readback operation is
shown in Figure 31. The user issues a command to the device to
start the conversion. The conversion data is available for read
back when the channel acquisition and conversion times complete.
The data returned from a conversion results readback operation
is contained within multiple 64-bit packs, as described in the
Conversion Data Readback Operation section.
TO INITIATE A CONVERSION,
ISSUE A CONVERT START
COMMAND TO
CS HELD HIGH
ADC FUNCTIONAL CONTROL
DURING
REGISTER BIT D0
ADC CONVERSIONS
The sequence to read back primary and secondary data is
described in the Example 5: Convert and Read All Conversion
Data section.
CS USED TO FRAME
DATA READBACK
FROM CHAIN
TO INITIATE A NEW CONVERSION,
EXIT 64-BIT MODE USING BIT D2
OF THE ADC FUNCTIONAL CONTROL
REGISTER IN THE LAST FRAME
FOLLOWED BY THE
CONVERT START COMMAND
CS
tSTART
tSTART
INTERNAL ADC
CONVERSIONS
CELL
8
CELL
8
CELL
7
CELL
7
DUMMY
CONVERSION
DATA READBACK, ALL DEVICES
SERIAL READ
OPERATION
14703-033
ALL PRIMARY*
DEVICE ENTERS 64-BIT INTERFACE MODE
*NOTE: ONLY PRIMARY READBACK SHOWN HERE
Figure 31. ADC Conversions and Readback of Primary Data and Initiation of a Second Conversion
TO INITIATE A CONVERSION,
ISSUE A CONVERT START
COMMAND TO ADC
CS HELD HIGH
FUNCTIONAL CONTROL
DURING ADC CONVERSIONS
REGISTER BIT D0
TO READ BACK SECONDARY DATA,
CS USED TO FRAME
DATA READBACK ISSUE A COMMAND TO LOAD THE SECONDARY DATA HERE BY
SETTING
BIT
D1
OF THE ADC FUNCTIONAL CONTROL REGISTER
FROM CHAIN
IN LAST 32-BIT WORD OF PRIMARY READBACK
CS
tSTART
CELL CELL
8
7
DUMMY
CONVERSION
SERIAL READ
OPERATION
TO EXIT 64-BIT MODE, SET BIT D2 OF THE ADC
FUNCTIONAL CONTROL REGISTER IN LAST 32-BIT
WORD OF READBACK
DATA READBACK, ALL DEVICES
ALL PRIMARY
ALL SECONDARY
DEVICE ENTERS 64-BIT INTERFACE MODE
Figure 32. ADC Conversions and Readback of Primary and Secondary Data and Exit of 64-Bit Readback Mode
Rev. C | Page 22 of 49
14703-034
INTERNAL ADC
CONVERSIONS
Data Sheet
AD7284
The AD7284 provides eight cell balance outputs that can drive
the gates of the external transistors as part of a cell balancing
circuit. The cell balance feature can be used while converting
cell voltage measurements; however, the accuracy of the
conversions degrades. Cell balancing is also available while
the AD7284 is in partial power-down mode.
Cell Balance Connections
The simplified internal configuration of the cell balance circuit
(CB1 to CB5) is shown in Figure 34.
RF
CELL (x)
CF
10kΩ
CF
10kΩ
CF
10kΩ
CF
10kΩ
CF
10kΩ
CF
10kΩ
10kΩ
SW2
SW1
5µA
SW3
CBx
RF
VPIN(x – 1)
CF
VSS
VPIN4
AD7284
Cell Balance Outputs Interface
Three bits are used to control the cell balancing feature:
VPIN3
CB3
RF
CF
10kΩ
VPIN2
CB2
RF
CF
10kΩ
VPIN1
CB1
RF
CF
VPIN0
14703-035
CELL 1
VPIN5
CB4
RF
CELL 2
VPIN6
CB5
RF
CELL 3
VPIN7
CB6
RF
CELL 4
125nA
When cell balancing is disabled, SW1 is closed, SW2 and SW3
are open, the negative channel metal oxide semiconductor
(NMOS) switch is on, and the CBx pin is pulled to VPIN(x − 1).
When enabled, SW1 is open, SW2 and SW3 are closed, the
NMOS switch is off, and the CBx voltage increases as current
charges the gate of an external FET. The internal clamp ensures
that CBx stays within approximately 5 V of VPIN(x − 1) and
provides a path for some of the 40 μA out of VPIN(x − 1),
which causes a voltage drop on VPIN(x − 1). The voltage drop
depends on the value of the input resistor. CB6 to CB8 use an
equivalent positive channel metal oxide semiconductor (PMOS)
circuit.
CB7
RF
CELL 5
VPIN8
CB8
RF
CELL 6
40µA
Figure 34. Simplified Internal Configuration of the
Cell Balancing Circuit (CB1 to CB5)
RF
CELL 7
VPINx
CF
As shown in Figure 33, five of the cell balance outputs (CB1
to CB5) are capable of driving an N channel, metal oxide
semiconductor field effect transistor (MOSFET), while the
other three (CB6 to CB8) drive a P channel MOSFET. These
outputs are designed to drive 20 μA (typical) into the external
FET, enabling turn on within 100 μs.
CELL 8
VDD
AD7284
14703-036
CELL BALANCING OUTPUTS
Figure 33. Cell Balancing Configuration
In an application with two or more AD7284 devices in a directly
connected daisy chain, it is recommended to place 10 kΩ series
resistors between the CBx outputs of the AD7284 and the gates
of the external cell balancing transistors. These resistors, in
conjunction with the internal 5 V clamps, help protect the
CBx outputs and gates of the external cell balancing transistors
during the initial connection of the monitoring circuitry to the
battery stack.
The cell balance power-down bit, CBPDB, in Control
Register 1 (see Table 21) controls the cell balance output
drivers. The default value of this bit at power-up is 0, and
the drivers are disabled. Turn off the drivers when cell
balancing is not used to reduce power consumption and
maintain accuracy on cell monitoring.
The general output enable bit, GOE_CB, in Control
Register 3 (see Table 24) allows the host microcontroller/
DSP to control the state of all cell balance outputs with one
write command while still maintaining the current state of
the cell balance control register. The default value of this
bit at power-up is 0, which corresponds to the cell balance
outputs off state.
The cell balance bits, CBx, in the cell balance control
register (see Table 26) allow the user to individually
configure the state of the cell balance output. The default
value of this register at power-up is 0x00, and each of the
cell balance outputs are disabled.
To enable cell balancing on one or multiple cells, the CBPDB bit,
the GOE_CB bit, and the corresponding CBx bit(s) must be set
to 1.
Rev. C | Page 23 of 49
AD7284
Data Sheet
Programmable On Time
Open Input Sense
To enable individual programmable on times, activate the
corresponding CBx output(s) as described in the Cell Balance
Outputs Interface section. Programming an on time for a
disabled CBx output has no effect.
The open input sense (OIS) technique allows the detection of an
open wire at the board edge or at the device input.
The AD7284 offers eight cell balance timer (CBTx) registers to
individually program the on time of the CBx output pins. On
times of 0 minutes (the output stays turned on) to 8.5 hours
can be programmed with a two minute resolution. All CBTx
registers are 0x00 by default. The values programmed in the
CBTx registers are compared with a single timer. The default
value of the timer is 0x00. The current value of the timer is
available in the current cell balance count state (CBCNT)
register.
The timer starts from 0x00 when a CBTx register is written to.
When the value in the timer reaches the value of any of the
CBTx registers, the corresponding CBx output is switched off.
The timer stops when the largest value programmed in the
enabled CBTx registers is equal to the timer. CBTx registers
settings are maintained following a timeout event.
The timer restarts from 0x00 on a write to any of the active
CBTx registers. Writing zero causes the corresponding cell
balance output to switch off and the timer to restart. A write to
the CBCTRL register while the timer is active causes the timer
to restart from 0x00. The CBCNT register can adjust the values
of previously enabled cell balance timers. Individual or all CBx
output(s) can be switched off before the timer reaches its or
their programmed value(s) by disabling the CBx output(s) as
described in the Cell Balance Outputs Interface section.
The cell balance timer is independent of the power-down timer.
Use the power-down timer to allow cell balancing to occur for a
set time before powering down the AD7284.
Note that the power-down timer can be used instead of the
watchdog timer when using the cell balancing timer to prevent
the need to service the watchdog timer.
When enabled, the OIS diagnostics cause a small current to sink
(or source, in the case of VPIN0 and VSIN0) from the selected
primary or secondary voltage sense pin. A delay is also introduced
between the primary and secondary conversions. If an input
wire disconnects, the OIS current sources from or sinks into the
input filter capacitor, causing the input voltage to shift. This
shift is seen as a difference between the primary and secondary
measurements.
The size of the voltage shift depends on the size of the input
filter capacitor, the delay between primary and secondary
measurements (1000 μs), and the OIS current (100 μA).
For a 100 nF filter capacitor, a shift of 500 mV is expected. If
the input pins are connected correctly, a voltage drop of
approximately 100 mV is measured between the primary
and secondary inputs when using a 1 kΩ input resistor, RF.
Cell Balance Sense
An alternative method is using the cell balance function.
This technique is useful for detecting board edge open wire
conditions. When enabled, a cell balance FET that is off for the
first conversion is switched on for the second conversion. If the
input wire disconnects, the enabled FET causes the input that
disconnected to pull toward the pin on the opposite side of the
enabled FET.
Sequence of Operations
To perform an open wire diagnostic on an input, use the
following procedure:
1.
2.
OPEN INPUT DETECTION
Two methods are available to detect an open wire condition
between the cell and an ADCs input pin: open input sense
and cell balance sense. These methods require the use of the
secondary path and independent filters on the ADC inputs.
3.
The host controller initiates the diagnostic request. It then reads
back conversion results from primary and secondary inputs
from which it is possible to determine an open input condition.
4.
Rev. C | Page 24 of 49
Enable the OISx bit for the cell connection under investigation
using the OISCTRL control register and/or the OISGPOP
control register, or set the appropriate cell balance enable bit in
the cell balance control register.
In the Control 3 register, select the appropriate input
sense function via the IN_SNSE bits, set the ADC delay
bit (ADCDLY), and select the conversion order with the
ADCORDR bit. If not in delay mode, the GOE_x bits gate
the respective cell balance or the OISCTRL register
settings.
Set the CBPDB bit in Control Register 1 for the cell balance
method.
Initiate a conversion and read back the primary and
secondary data.
Data Sheet
AD7284
POWER MANAGEMENT
AD7284 SUPPLIES
MODES OF OPERATION
The AD7284 is powered from the cell stack. The device
connects to the cell stack positive terminal (+HV) through the
VDD pin and the cell stack negative terminal (−HV) through the
VSS pin. An internal regulator generates a 5 V supply (VREG5) for
the internal core of the AD7284, as shown in Figure 35.
The three modes of operation for the AD7284 include the
following: active mode (power-up), software partial powerdown mode, and hardware full power-down mode.
In active mode, the AD7284 can be idle or perform the
following tasks:
+HV
BATTERY
PACK
VPIN8
VPIN7
VDD
VREG5
AVCC
DVCC
VDRIVE
5V
REG
VPIN6
POWER-ON
RESET
ANALOG
ADC conversions.
Conversion data readback.
Register read and write.
Cell balancing (cell balancing and register reads or writes,
can also be performed in partial power-down mode).
The current consumption is specified in Table 1.
DIGITAL
SERIAL
INTERFACE
ACTIVE MODE, POWER-UP
VPIN2
VPIN1
VSS
AGNDx*
DGND
AD7284
–HV
*6 × ANALOG GROUND PINS
Figure 35. Power Supply Overview (External Circuitry Omitted for Clarity)
A total decoupling capacitance of 4.7 μF is recommended on the
VDD pins. Optionally, use 2.2 μF in parallel with 100 nF on each
of the VDD pins.
It is required that 100 nF be present on the regulator output pin,
VREG5, and on each of the low voltage supplies, AVCC and DVCC.
Connect these three pins together on the PCB.
VDRIVE
For the master device only, an external VDRIVE supply is required
to power the digital input/output pins to ensure interface
compatibility with host supplies operating at 3.3 V or 5 V.
Therefore, do not drive the digital input pins when VDRIVE is low.
VDRIVE is also an integral part of the power-up/power-down scheme
within the AD7284, as described in the Active Mode, Power-Up
section and the Power-Down section. Pulling VDRIVE low places
the AD7284 into the lowest power mode, unless an active
power-down timer is running.
A 100 nF decoupling capacitor is recommended on the VDRIVE pin
for the master device only.
On slave devices, connect VDRIVE directly to VREG5 at all times. In
this configuration, all currents supplied by the low voltage pins,
such as VREFBUF, GPOP1, and GPOP2, are supplied by the internal
regulator. This regulator delivers 2 mA typically for use external
to the AD7284.
14703-037
VPIN0
Connect the VDRIVE pin on the AD7284 master device to an
external voltage supply. A rising edge on the VDRIVE supply
signals the AD7284 master device to power up. If VDRIVE is
already held high, an alternate method of powering up the
master is via a pulse of 100 ns minimum on the RESET pin.
Power-Up Time
The time required for an AD7284 master device to power up
and to receive SPI communications is typically 200 μs with a
total capacitance of 300 nF on VREG5 (100 nF on each pin). The
time required to perform accurate ADC conversions is typically
5 ms. These figures apply when VREF1 and VREF2 are decoupled
with a 1 μF in parallel with 100 nF.
The AD7284 slave devices power up through a slave wake-up
signal that is automatically transmitted through the daisy chain.
The master device transmits the slave wake-up signal to the first
slave device, the first slave device transmits the wake-up signal
to the device above it in the daisy chain, and so on. Each device
transmits a slave wake-up signal typically within 100 μs of
receiving its own wake-up signal. The time required for a slave
device to power up and perform accurate ADC conversions is
typically 5 ms (see Figure 36).
Calculate the total power-up time for a chain of AD7284
devices connected in the direct current configuration by
Total Power-Up Time = 5 ms + ((N − 1) × 100 μs)
where N is the number of AD7284 devices in the daisy chain.
Connect the VDRIVE pin on each slave device to its own
VREG5 pin.
Multiple dummy register writes are required to wake up the
chain in a configuration with an isolated daisy chain.
Rev. C | Page 25 of 49
AD7284
Data Sheet
POWER-DOWN
ALL DEVICES IN DAISY CHAIN
IN POWERED DOWN STATE
USER
The following features are available to allow flexible power
savings on the AD7284:
BRING VDRIVE TO MASTER
DEVICE HIGH
MASTER REGULATOR
POWERS UP
A software (partial) power-down option.
A hardware (full) power-down option.
A power-down timer that controls when the device enters
hardware power-down mode.
Software (Partial) Power-Down Mode
MASTER SENDS
WAKE UP SIGNAL TO SLAVE1
AFTER 100µs
During software (partial) power-down mode, cell balancing and
register reads or writes can be performed. The registers stay
configured and the primary reference and LDO stay powered up
to ensure accurate measurements can be performed immediately
after wake up. Additionally, the watchdog timer remains active,
as does the daisy chain so that communication is available to
wake up the device.
SLAVE1 REGULATOR
POWERS UP
DEVICE
SLAVE1 SENDS
WAKE UP SIGNAL TO SLAVE2
AFTER 100µs
Hardware (Full) Power-Down Mode
In hardware (full) power-down mode, the regulator powers off.
When placing the device into full power-down mode, all digital
inputs on the AD7284 master device must return to 0 V within
a similar timescale to VDRIVE going low.
SLAVE(x) REGULATOR
POWERS UP
SLAVE(x) SENDS
WAKE UP SIGNAL TO SLAVE(x + 1)
AFTER 100µs
WHERE N = NUMBER OF DEVICES IN CHAIN
The power-down timer register allows the user to configure a set
time after which the AD7284 enters hardware power-down mode.
14703-038
ALL DEVICES IN THE SYSTEM
ARE POWERED UP
DEVICES READY TO CONVERT IN:
TIME = 5ms + ((N – 1) × 100µs)
Power-Down Timer
Figure 36. Power-Up Flowchart for a Direct Coupled Daisy Chain
RESET
An optional RESET input can reset the AD7284, which is an
active high input and is provided primarily for use in resetting
the master device. Resetting the master device reverts it to the
default state on power-up. The hardware reset signal is not
physically communicated to the slave devices. A software reset
command to the slave devices is required to implement a full
chain reset. Note that a software reset does not reset the device
identification.
The RESET pin of a master device can wake up a chain of
devices, as described in the Active Mode, Power-Up section.
For debug purposes, assert the RESET pin on an individual
slave device to reset that device. Appropriate isolation is
required.
The power-down timer can be set to 0 hours to 8.5 hours, with
a resolution of two minutes, and the user can read back the
current value of the power-down timer by reading the powerdown counter register. The power-down timer starts to count
up when the HWPD bit in Control Register 1 is set (and if the
power-down timer register is not equal to 0x00). If the powerdown timer register is written to after the counter starts, the
counter is reset and then restarts automatically, counting to
the new value in the power-down timer register. When the
timer reaches the value in the power-down counter register,
the device enters power-down mode after checking for the
following conditions:
For a master device, VDRIVE must be low.
For a slave device, the HWPD bit in Control Register 1
must be set.
See the Power-Down Entry Sequences section for more details.
The default value of the power-down timer register at power-up
and reset is 0x00, or there is no timer delay.
Rev. C | Page 26 of 49
Data Sheet
AD7284
Power-Down Entry Sequences
Enter power-down by using two methods: controlling the
watchdog timer as described in the Watchdog Timer section,
or by configuring the HWPD bit in Control Register 1 and the
power-down timer, as described in this section.
Depending on whether the device is configured as a master or a
slave, there are two methods for enabling the full power-down
mode:
A slave device is set to full power-down mode by
configuring the power-down timer first (optional) and
setting Bit D2 of Control Register 1, HWPD.
A master device is set to full power-down mode by pulling
the VDRIVE pin low. Delay entry into full power-down mode
by using the power-down timer and the HWPD bit. The
master device enters full power-down mode immediately
after VDRIVE is pulled low if the timer value is 0. With the
VDRIVE pin held high, the HWPD bit only controls the start
of the power-down timer.
Powering Down a Chain of Devices
To power down a chain of devices without using a timer, use the
following procedure:
1.
2.
To power down a chain of devices using the power-down timer,
use the following procedure:
1.
2.
3.
If VDRIVE is not low when the power-down timer expires, set the
HWPD bit of the master to 0 or reset the master device. The
slave devices continue to power down following power-down
timeout, as long as the HWPD bit is set high.
ALL DEVICES IN DAISY CHAIN
IN POWERED UP STATE
WRITE TO POWER-DOWN TIMER
REGISTER ON ALL DEVICES TO SET
POWER-DOWN TIMER VALUE
(OPTIONAL)
SET HWPD BIT ON EACH
DEVICE IN CHAIN
HOLD VDRIVE LOW ON
MASTER DEVICE
NO
POWER-DOWN
TIMER EXPIRED?
DEVICE
14703-039
YES
DEVICES POWER DOWN—FULL POWER-DOWN MODE
Write to the power-down timer (PDT) register on all
devices to set a power-down timer value.
Set Bit D2 of Control Register 1 to 1 on all devices to select
a hardware power-down, which activates the power-down
timer.
Pull VDRIVE low on the master device.
All devices power down on the expiration of the power-down
timer.
Figure 37 shows a sequence to fully power down a chain of devices.
USER
Set Bit D2 of Control Register 1 to 1 on all devices to select
a hardware power-down.
Pull VDRIVE low on the master device.
Figure 37. Entry in Full Power-Down Mode
Rev. C | Page 27 of 49
AD7284
Data Sheet
WATCHDOG TIMER
The watchdog timer (WDT) register allows the user to
configure a set time after which the AD7284 is automatically
powered down if communication to the device is lost.
The AD7284 allows the user to set the watchdog timer to a
maximum value of 1040 ms and with a resolution of 8.192 ms.
Service the watchdog timer by regularly writing a timeout value
to the watchdog timer register before it expires to restart the
timer and prevent the device from powering down.
At power-up, the watchdog timer is enabled with a default value
of 0x0C (98.304 ms).
Disabling the watchdog timer may be required for a long cell
balancing period, where the cell balancing timer and powerdown timer are used. In this scenario, enable the power-down
timer before disabling the watchdog timer.
The sequence to disable the watchdog timer involves three
consecutive register write operations:
1.
2.
3.
Write 0x00 to the watchdog timer register.
Write 0x5A to the watchdog key register.
Write 0x00 again to the watchdog timer register.
Any intermediate SPI command resets the process of
disabling the watchdog timer, reducing the risk of disabling
it unintentionally. See the Example 3: Disabling the Watchdog
Timer section for more details.
If the watchdog timer is enabled and the device is placed in partial
power-down mode, the device enters full power-down mode,
unless a nonzero value is written to the watchdog timer register
before the watchdog timer times out.
If the watchdog timer times out, the device (or the chain of devices)
enters full power-down mode. The master stays in this mode
until either VDRIVE or RESET are toggled.
Rev. C | Page 28 of 49
Data Sheet
AD7284
SERIAL PERIPHERAL INTERFACE (SPI)
The AD7284 SPI is Mode 1 SPI compatible, that is, the clock
polarity (CPOL) is 0, and the clock phase (CPHA) is 1. The
interface consists of four signals: CS, SCLK, SDI, and SDO, as
shown in Figure 3. The SDI line transfers data into the on-chip
registers, and the SDO line reads the on-chip registers and
conversion result registers. SCLK is the serial clock input for the
device, and all data transfers, either on SDI or on SDO, take
place with respect to SCLK. Data clocks into the AD7284 on the
SCLK falling edge, and data clocks out of the AD7284 on the
SCLK rising edge. The CS input frames the serial data being
transferred to or from the device. The register data and the
ADC conversion readback data can be framed by CS in 32-bit
or 16-bit SCLK bursts, allowing the greatest flexibility for
connecting to processors.
All register reads and writes are configured as 32 bits of data,
while all conversion results are configured as 64-bits words.
The AD7284 powers up in 32-bit mode and automatically enters
64-bit mode when conversions initiate. The device remains in
64-bit mode until returned to 32-bit mode by writing 0x04 to
the ADC functional control register. Conversion data cannot be
reread from the AD7284; if an attempt is made to reread data, it
reads as 0. The life counter value is identical to the previous
read because it increments between conversion sets.
REGISTER WRITE AND REGISTER READ OPERATIONS
Up to 30 AD7284 devices can be daisy-chained together to
allow monitoring up to 240 individual Li-Ion cell voltages. The
AD7284 SPI interface, in combination with the daisy-chain
interface, allows any register in the 30 AD7284 stack to be
updated using one 32-bit write command.
All register write and read operations are performed via the SPI
using a 32-bit data packet. The format of the 32-bit data packet
is described in Table 10.
Each register access must include a device address and a register
address, in addition to the data to be written. The AD7284 also
requires a 12-bit cyclic redundancy check (CRC) to be included
in each 32-bit write command.
Register Read Operation
To read back a register from a chain of AD7284 devices, write
the address of the desired register to be read back to the read
register (Register 0x3F).
Follow this with null frames (0x00000000) for each device in
the daisy chain. For example, eight null frames for an eight
device chain. Each of these frame returns the register content of
each device, starting with the master. See the Examples of
Interfacing with the AD7284 section for more details.
It is not possible to read one register from one device in the
chain, that register in all devices in the chain must be read.
Device Address
The device address is a 5-bit address that allows each individual
AD7284 in the battery monitoring stack to be uniquely identified.
A maximum of 30 devices can be supported in one chain. On
initial power-up, each AD7284 is configured with a default
address of 0x00. A simple sequence of commands allows each
AD7284 to recognize its unique device address in the stack (see
the Example 1: Initialize All Devices in a Daisy Chain section).
This device address can then be locked to the AD7284 and is
used in subsequent read and write commands. A unique device
address of 0x1F is used to address all devices in the stack.
Register Address
As shown in Table 10, D25 to D20 form a 6-bit register address.
Register addresses can be found in Table 14.
Write and Write/Read
As shown in Table 10, Bit D26 controls the data transfer mode
on the daisy chain, unidirectional (write) or bidirectional
(write/read) communication.
With D26 high, the next communication in the chain is
unidirectional, and the master transmits the SPI command to
the slaves up the chain. D26 is typically high for register write
operations. The maximum SCLK frequency is 725 kHz when
the daisy chain operates in unidirectional mode.
With D26 low, the next communication in the chain is
bidirectional. The master transmits the SPI command to the
slaves and then switches to receive mode, expecting data back
from the slaves. The slaves start in receive mode and switch to
transmit mode after reception of the command.
A minimum delay of 50 μs is required prior to switching from
bidirectional to unidirectional mode (not applicable for the
master only setup). The maximum SCLK frequency is 500 kHz
when the daisy chain operates in bidirectional mode.
Examples of register read and register write operations can be
found in the Examples of Interfacing with the AD7284 section.
Register Data
As shown in Table 10, the register data field (Bits[D19:D12])
contains the data to be written into the register during a register
write operation. All AD7284 registers are 8 bits wide and are
listed in Table 14 in the Register Map section.
12-Bit CRC
The AD7284 includes a 12-bit CRC with a Hamming distance of
six on all write commands to either individual devices or to a chain
of devices. An AD7284 that receives an invalid CRC in the write
command does not execute the command. The CRC on the write
command is calculated based on Bits[D31:D12] of the write
command, which includes the device address, the register address,
and the register data. The CRC polynomial ((0xB41) in Koopman’s
notation) used when writing to or reading from the AD7284 is
x12 + x10 + x9 + x7 + x1 + 1
Rev. C | Page 29 of 49
AD7284
Data Sheet
CONVERSION DATA READBACK OPERATION
Channel Addresses
The data returned from a conversion result read operation is
contained within a 64-bit packet. The data returned includes
the device address, the channel addresses, a life counter, and a
16-bit CRC, in addition to the two conversions results, which
are each 14 bits. The 64-bit read conversion result packet is
shown in Table 11.
The channel address allows individual measurement results to
be uniquely identified. Each channel address is six bits wide and
two channel addresses are contained within each 64-bit read
cycle. The address for each channel is detailed in the register
map for the AD7284 (see Table 14).
When reading back conversion data from a daisy chain of
AD7284 devices, the conversion data is first read from the
primary measurement path on the master device, followed by
the primary measurement path from the first slave device, and
so on. When all the conversion data is returned for the primary
measurements, the device can then be configured to read back
the secondary measurement data.
As shown in see Table 14, the life counter is a 3-bit counter that
increments every time a successful sequence of conversions is
completed. After the counter reaches 7, it wraps around and
starts counting again from 0. This feature allows the detection
of a conversion sequence that is not complete. The life counter
is cleared on a software reset or hardware power-down.
Life Counter
Conversion Data
When reading conversion results from a chain of 12 devices
monitoring 96 cells, the readback time is of the region of 9.5 ms
when using the higher SCLK rate of 725 kHz (tSCLK = 1.38 μs).
For 12 devices, the total number of primary conversions is,
12 × 18 = 216
Two conversion sets are packed into a 64-bit frame; therefore,
the number of bits transferred is
As shown in see Table 14, the conversion data readback consists
of 14 bits. When reading back a conversion result from the
primary measurement path, the 14-bit conversion result is
included. When reading back a conversion result from the
secondary measurement path, an inverted 10-bit conversion
result plus 4 MSB data bits set to 0 make up the 14-bit data
value returned.
Device Address
216 ÷ 2 × 64 = 6912
The transfer time is the number of bits transferred multiplied by
the bit period defined by SCLK, 6912 Bits × tSCLK = 9.5 ms.
The device address is described in the Register Write and
Register Read Operations section.
Within a single device, the device converts all 18 primary and
10 secondary channels. All 18 primary conversions must be
read back, which may be followed by optional read back of all
10 secondary conversions as required.
16-Bit CRC
See the Example 5: Convert and Read All Conversion Data
section for more details. The 64-bit conversion data packets
can be read back in 4 × 16-bit or 2 × 32-bit frames.
The AD7284 includes a 16-bit CRC with a Hamming distance
of six within the 64-bit pack and is calculated based on
Bits[D63:D16] of the read conversion result cycle. The CRC
calculations include Channel Address 1, the life counter,
Channel Address 2, Conversion Data 1, the device address,
and Conversion Data 2. The CRC polynomial ((0xC86C) in
Koopman’s notation) used when reading conversion data from
the AD7284 is
x16 + x15 + x12 + x7 + x6 + x4 + x3 + 1
Table 10. 32-Bit Register Write/Read Operations
Device Address
D31 to D27
5 bits
Write and Write/Read
D26
1 bit
Register Address
D25 to D20
6 bits
Register Data
D19 to D12
8 bits
CRC
D11 to D0
12 bits
Table 11. 64-Bit Read Conversion Result Packet
Channel Address 1
D63 to D58
6 bits
Life Counter
D57 to D55
3 bits
Channel Address 2
D54 to D49
6 bits
Conversion Data 1
D48 to D35
14 bits
Rev. C | Page 30 of 49
Device Address
D34 to D30
5 bits
Conversion Data 2
D29 to D16
14 bits
CRC
D15 to D0
16 bits
Data Sheet
AD7284
CRC PSEUDOCODE EXAMPLES
16-Bit CRC
The following pseudocode examples show how to calculate the
CRC for two types of data packets.
To calculate the CRC value from the preceding 48 bits of data,
use the following pseudocode:
for (i=63; i>=16; i--)
{
xor_0 = data_in[i] ^ shft[15] ;
shft[15] = shft[14] ^ xor_0;
shft[14] = shft[13];
shft[13] = shft[12];
shft[12] = shft[11] ^ xor_0;
shft[11] = shft[10];
shft[10] = shft[9];
shft[9] = shft[8];
shft[8] = shft[7];
shft[7] = shft[6] ^ xor_0;
shft[6] = shft[5] ^ xor_0;
shft[5] = shft[4];
shft[4] = shft[3] ^ xor_0;
shft[3] = shft[2] ^ xor_0;
shft[2] = shft[1];
shft[1] = shft[0];
shft[0] = xor_0;
}
crc16calc = shft;
The following variables must first be declared:
12-Bit CRC
To calculate the CRC value from the preceding 20 bits of data,
use the following pseudocode, where sfht[n] corresponds to
CRC_x in Figure 38 and Figure 39:
for (i=31; i>=12; i--)
{
xor_0 = data_in[i] ^ shft[11];
shft[11] = shft[10];
shft[10] = shft[9] ^ xor_0;
shft[9] = shft[8] ^ xor_0;
shft[8] = shft[7];
shft[7] = shft[6] ^ xor_0;
shft[6] = shft[5];
shft[5] = shft[4];
shft[4] = shft[3];
shft[3] = shft[2];
shft[2] = shft[1];
shft[1] = shft[0] ^ xor_0;
shft[0] = xor_0;
}
crc12calc = shft;
CRC_1
D Q
DATA_IN
D Q
CRC_2
D Q
CRC_3
D Q
CRC_4
D
Q
CRC_5
D Q
CRC_7
D Q
CRC_0
D Q
CRC_10
D Q
D Q
CRC_6
D Q
CRC_8
D Q
CRC_9
SCLK
Figure 38. 12-Bit CRC Implementation
CRC_0
DATA_IN
D Q
CRC_1
D Q
CRC_4
D Q
D Q
CRC_2
D Q
CRC_3
CRC_7
D Q
D Q
CRC_5
D Q
CRC_8
D Q
CRC_6
SCLK
Figure 39. 16-Bit CRC Implementation
Rev. C | Page 31 of 49
CRC_9
D Q
CRC_10
D Q
CRC_12
D Q
D Q
CRC_11
CRC_13
D Q
CRC_15
D Q
D Q
CRC_14
14703-041
i is an integer variable.
shft[xx] are an integer variables.
data_in represents the data bits that the CRC is calculated
on (Bits[D31:D12]). This data supplies the input to the first
XOR gate.
xor_0 is an integer variables. The outputs of the shift
registers start at the leftmost shift register in the circuit
implementation. With the exception of data_in, initialize
all variables to 0.
14703-040
AD7284
Data Sheet
DAISY-CHAIN INTERFACE
D_UP
AD7284
CCM
50Ω
DAISY-CHAIN PHYSICAL INTERFACE
50Ω
1µF
10kΩ
The internal common-mode amplifier provides a CCM voltage of
typically 2 V above the VSS rail, which biases the daisy-chain
paths. The CCM pin requires a 1 μF capacitor to VSS.
50Ω
50Ω
1µF
ON-BOARD
CONNECTION
D_UP
D_UP
VDD
VDD
MASTER
10Ω
TO BATTERY
When communicating between devices located on the same
board, the daisy chain requires a single pair of external
termination resistors (50 Ω) connected to the CCM pin.
D_DWN
SLAVE N
CCM
VSS
VSS
50Ω
1µF
AD7284
D_DWN
TO BATTERY
VDD
VDD
MASTER
TO BATTERY
D_UP
50Ω
The daisy-chain interface consists of a differential daisy chain
for up paths (D_UP/D_UP) and down paths (D_DWN/D_DWN).
When multiple devices are configured in a chain, the up paths
from the master are connected to the down paths of the
adjacent slave. Similarly, the up paths on the other side of the
slave device interfaces to the down path of the next adjacent
slave device, and so on, as shown in Figure 40.
BOARD TO BOARD
CONNECTION
D_UP
10kΩ
The AD7284 daisy-chain interface is a fully differential, 2-wire,
half-duplex interface enabling minimal interconnects and
robust communication between devices in a chain.
D_DWN
SLAVE N + 1
D_DWN
TO BATTERY
VSS
VSS
MASTER
Each AD7284 device is powered from the top and bottom
terminals of the cell pack. The supply voltage of each device is
offset from the adjacent device in the chain by as much as 40 V.
D_UP
TO D_DWN/D_DWN OF NEXT SLAVE DEVICE
To minimize isolation requirements and simplify the interface
between the host processor and each battery monitoring device,
the master AD7284 device is the only communication port to
the host processor. All slave devices interface via the master
device using a 2-wire daisy-chain interface.
AD7284
MASTER
Additional protection circuitry beyond what is shown in Figure 40
may be required on the daisy-chain pins for hot plug and service
disconnect (see the Hot Plug section and the Service
Disconnect (SD) section).
An alternative approach is using a transformer to provide
isolation, as described in the Transformer Configuration
section.
DAISY-CHAIN PROTOCOL
The daisy chain uses a proprietary protocol with a preamble or
start condition, a Manchester encoded data packet, including a
CRC and a stop condition. The data bit rate is 3.125 Mbps typical.
The daisy-chain interface operates in unidirectional mode for
register write and conversion data readback operation, or in
bidirectional mode for register read operation.
TO BATTERY
VSS
VSS
14703-042
When interfacing between devices across boards, pairs of 50 Ω
terminations are required on each sides of the daisy chain. A
low value capacitor (≤100 nF) is required from the termination
center point to the VDD rail.
Figure 40. AD7284 Daisy-Chain Interconnection Examples
(Additional Circuitry Omitted for Clarity)
DAISY-CHAIN DEBUG MODE
The AD7284 incorporates a debug feature using the two
GPOPx pins (GPOP1 and GPOP2) that allow the user to
monitor the daisy-chain communications between devices. The
daisy chain is a current-based interface. The debug feature
translates the daisy-chain communications into a single-ended
voltage relative to the logic levels of the corresponding device.
Configuration of the debug feature involves setting Bit D0
(GPOP SEL) of the OISGPOP control register (see Table 28) to
enable the feature.
Table 12. Daisy-Chain Debug Configuration
Device
Master
Slave
Rev. C | Page 32 of 49
GPOP1
Commands transmitted to
device above
Commands received from
device below
GPOP2
Data received from
device above
Data received from
device above
Data Sheet
AD7284
REGISTER MAP
PAGE ADDRESSING
Page Register
The AD7284 uses page addressing to maximize register
addressing space. Page 0 is the default page on power-on.
To access a particular page, first write the relevant page number
to the page register (Register 0x3E); this gives access to the
registers contained within that page. To access further registers
from the currently selected page, it is not necessary to rewrite
the page selection.
Page 0 initiates a conversion and accesses primary or secondary
ADC data. Page 1 contains all the configuration and diagnostic
register space, see Table 14.
Throughout the register map, there is reserved register address
space. This space does not provide any user functions; it is
reserved space to support future software compatibility.
Table 13. Page Register (Register 0x3E)
Bits
[D7:D2]
[D1:D0]
Name
Not applicable
Page
Description
Reserved
00: Page 0
01: Page 1
Table 14. Register Map
Page Number
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09 to 0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18 to 0x1B
0x1C
0x1D
0x1E
0x1F to 0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29 to 0x30
0x31
0x32 to 0x33
0x34
0x35 to 0x3C
0x3D
0x3E
0x3F
Register Description
Null frame
Primary Cell Voltage 1
Primary Cell Voltage 2
Primary Cell Voltage 3
Primary Cell Voltage 4
Primary Cell Voltage 5
Primary Cell Voltage 6
Primary Cell Voltage 7
Primary Cell Voltage 8
Reserved
Stack voltage
VREF2 voltage
VREG5 Voltage 1
Primary Auxiliary ADC 1
Primary Auxiliary ADC 2
Primary Auxiliary ADC 3
Primary Auxiliary ADC 4
Reserved
Reference buffer
VREG5 Voltage 2
Temperature sensor
Reserved
Secondary Cell Voltage 1
Secondary Cell Voltage 2
Secondary Cell Voltage 3
Secondary Cell Voltage 4
Secondary Cell Voltage 5
Secondary Cell Voltage 6
Secondary Cell Voltage 7
Secondary Cell Voltage 8
Reserved
VREF1 voltage
Reserved
VREG5 Voltage 3
Reserved
ADC functional control
Page register
Read register
Register Name1
N/A
VPIN1
VPIN2
VPIN3
VPIN4
VPIN5
VPIN6
VPIN7
VPIN8
N/A
VSTK
VREF2
VREG5_1
AUXP1
AUXP2
AUXP3
AUXP4
N/A
REFBUF
VREG5_2
TMPSNR
N/A
VSIN1
VSIN2
VSIN3
VSIN4
VSIN5
VSIN6
VSIN7
VSIN8
N/A
VREF1
N/A
VREG5_3
N/A
ADCFUNC
Page
RDREG
Rev. C | Page 33 of 49
Data Bits1
N/A
D13 to D0
D13 to D0
D13 to D0
D13 to D0
D13 to D0
D13 to D0
D13 to D0
D13 to D0
N/A
D13 to D0
D13 to D0
D13 to D0
D13 to D0
D13 to D0
D13 to D0
D13 to D0
N/A
D13 to D0
D13 to D0
D13 to D0
N/A
D9 to D0
D9 to D0
D9 to D0
D9 to D0
D9 to D0
D9 to D0
D9 to D0
D9 to D0
N/A
D9 to D0
N/A
D9 to D0
N/A
D7 to D0
D7 to D0
D7 to D0
Access1
N/A
Read
Read
Read
Read
Read
Read
Read
Read
Reserved
Read
Read
Read
Read
Read
Read
Read
Reserved
Read
Read
Read
Reserved
Read
Read
Read
Read
Read
Read
Read
Read
Reserved
Read
Reserved
Read
Reserved
Write/read
Write/read
Write/read
Power-On Default/Reset1
N/A
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x000
0x000
0x000
0x000
0x000
0x000
0x000
0x000
0x000
0x000
0x000
0x000
0x000
0x00
0x00
0xFF
AD7284
Data Sheet
Page Number
1
1
1
Address
0x00
0x01
0x02
1
0x03
1
0x04
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0x05 to 0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C to 0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19 to 0x20
0x21
0x22
0x23
0x24
0x25 to 0x3D
0x3E
0x3F
1
Register Description
Null frame
Fault register
Current cell balance
count state
Current power-down
count state
Current watchdog count
state
Reserved
Control Register 1
Control Register 2
Control Register 3
Control Register 4
Cell balance control
Reserved
OIS control
OIS GPOPx control
Power-down timer
CB Timer 1
CB Timer 2
CB Timer 3
CB Timer 4
CB Timer 5
CB Timer 6
CB Timer 7
CB Timer 8
Reserved
Watchdog timer
Watchdog key
Storage Register 1
Storage Register 2
Reserved
Page register
Read register
Register Name1
N/A
Fault
CBCNT
Data Bits1
N/A
D7 to D0
D7 to D0
Access1
N/A
Read
Read
Power-On Default/Reset1
N/A
0xFF
0x00
PDCNT
D7 to D0
Read
0x00
WDCNT
D7 to D0
Read
0x00
N/A
CTRL1
CTRL2
CTRL3
CTRL4
CBCTRL
N/A
OISCTRL
OISGPOP
PDT
CBT1
CBT2
CBT3
CBT4
CBT5
CBT6
CBT7
CBT8
N/A
WDT
WDKY
STRG1
STRG2
N/A
Page
RDREG
N/A
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
N/A
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
N/A
D6 to D0
D7 to D0
D7 to D0
D7 to D0
N/A
D7 to D0
D7 to D0
Reserved
Write/read
Write/read
Write/read
Write/read
Write/read
Reserved
Write/read
Write/read
Write/read
Write/read
Write/read
Write/read
Write/read
Write/read
Write/read
Write/read
Write/read
Reserved
Write/read
Write/read
Write/read
Write/read
Reserved
Write/read
Write/read
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0C
0x00
0x00
0x00
0x00
0x00
0xFF
N/A means not applicable.
Rev. C | Page 34 of 49
Data Sheet
AD7284
Primary Path Conversion Results Registers
Table 15 shows examples of output codes and corresponding
junction temperature.
Page 0 contains the 18 registers, as follows, for the primary path:
Table 15. Internal Temperature Sensor Output Codes Examples
Junction Temperature (°C)
−30
0
+24.96875
+25
+25.03125
+120
PAGE 0 ADDRESSES
The cell voltage registers (VPIN1 to VPIN8) store the
conversion result from each cell input to the primary
measurement path.
The stack voltage register (VSTK) stores the conversion
result from the battery stack input to the primary
measurement path.
The VREF2 voltage register (VREF2) stores the conversion
result of the secondary reference input to the primary
measurement path.
The VREG5 Voltage 1 register (VREG5_1) stores the conversion
result of the regulated LDO voltage input to the primary
measurement path through an odd multiplexer channel. A
scaling factor of 2/3 is applied to the conversion result.
The auxiliary ADC registers (AUXP1 to AUXP4) store the
conversion result of each auxiliary ADC input to the
primary measurement path.
The reference buffer register (REFBUF) stores the
conversion result of the thermistor buffer voltage VREFBUF
supply, which can be used for the external thermistor
circuitry.
The VREG5 Voltage 2 register (VREG5_2) stores the conversion
result of the regulated LDO voltage input to the primary
measurement path through an even multiplexer channel. A
scaling factor of 2/3 is applied to the conversion result.
The temperature sensor register (TMPSNR) stores the
conversion result of the internal temperature sensor input
to the primary measurement path.
The conversion results are in 14-bit straight binary format,
except for the conversion result of the temperature sensor,
which is in 14-bit, twos complement format.
Code 0 of the temperature sensor corresponds to 25°C with
32 LSB/°C of resolution.
Binary Output Code
11 1001 0010 0000
11 1100 1110 0000
11 1111 1111 1111
00 0000 0000 0000
00 0000 0000 0001
00 1011 1110 0000
Secondary Path Conversion Results Registers
Page 0 contains the 10 registers for the secondary path, as follows:
The cell voltage registers (VSIN1 to VSIN8) store the
conversion result from each cell input to the secondary
measurement path.
The VREF1 voltage register (VREF1) stores the conversion
result of the primary reference input to the secondary
measurement path.
The LDO Voltage 3 register (VREG5_3) stores the conversion
result of the regulated LDO voltage input to the secondary
measurement path through an even multiplexer channel. A
scaling factor of 4/5 is applied to the conversion result.
The conversion results are inverted and in 10-bit straight binary
format with four leading zeros.
ADC Functional Control Register
The ADC functional control (ADCFUNC) register allows
initiation of a conversion sequence and selection of primary or
secondary data.
Table 16. ADCFUNC Register Settings (Register 0x3D)
Bits
[D7:D3]
D2
D1
D0
Rev. C | Page 35 of 49
Name
Reserved
EXIT64
SPIRLD
CONVST
Description
Reserved, set to 0.
Set to 1 to exit 64-bit data packet mode.
Set to 1 to load the secondary ADC results.
Trigger convert start; set to 1 to initiate
the trigger convert start.
AD7284
Data Sheet
PAGE 1 ADDRESSES
Current Watchdog Count State Register
Fault Register
The current watchdog count state (WDCNT) register stores the
current running value of the watchdog timer counter.
The fault register (fault) allows the user to read the stored
operational fault flags. The fault register is updated at the end of
every conversion sequence. The fault register is reset to 0x00
after the user reads back from it. The default value of the fault
register on power-up is 0xFF.
Table 20. WDCNT Register Settings (Register 0x04)
Bits
D7
[D6:D0]
Name
Not applicable
WDCOUNT
Table 17. Fault Register Settings (Register 0x01)
Bits
D7
Name
PORFLAG
D6
WDFAULT
D5
LDOFAULT
D4
D3
Reserved
FUSECRC
D2
CCMFAULT
D1
CFGFAULT
D0
OSCDRIFT
Description
Power-on reset flag. Set to 1 to indicate that
a power-on reset (POR) has occurred.
Watchdog power-down fault. Set to 1 when
the watchdog timer times out.
Set to 1 if the internal LDO supply is out of
range, typically 5.2 V.
Reserved, set to 0.
Set to 1 when the fuse CRC does not match
the programmed fuse CRC value.
Set to 1 when the voltage on the CCM pin
exceeds the overvoltage threshold that is
set to 2.5 V typically. Also, set this bit to 1
when the voltage on the CCM pin exceeds the
undervoltage threshold that is set to 1.5 V
typically.
Set to 1 if in an illegal configuration occurs.
Issue a reset to restart the device in a user
configuration state.
The AD7284 has two internal oscillators
which are trimmed to the same frequency.
The oscillators are compared to each other
and, if they differ by more than 3.9%, this bit
is set to 1.
Control Register 1
Control Register 1 (CTRL1) gives the user control of the
various power-down features of the AD7284, the software reset
functionality, and over the primary reference to allow it to be
overdriven by an external source.
Table 21. CTRL1 Register Settings (Register 0x07)
Bits
[D7:D5]
D4
Name
Reserved
PREF
D3
CBPDB
D2
HWPD
D1
SWPD
D0
SWRST
Current Cell Balance Count State Register
The current cell balance count (CBCNT) register stores the
current value of the cell balance timer. The default value is 0x00.
Table 18. CBCNT Register Setting (Register 0x02)
Bits
[D7:D0]
Name
CBCOUNT
Description
LSB = 2 minutes. This register contains
a value between 0x00 and 0xFF. The
maximum value is 510 minutes.
Current Power-Down Count State Register
The current power-down count state (PDCNT) register is used
in conjunction with the power-down modes that use the powerdown timer register. The power-down counter register stores
the current value of the power-down counter. If the power-down
counter register is zero and the power-down is set, the slave device
powers down immediately. See the Power-Down section for more
details.
Table 19. PDCNT Register Setting (Register 0x03)
Bits
[D7:D0]
Name
PDCOUNT
Description
Reserved.
LSB = 8.192 ms. This register contains
a value between 0x00 and 0x7F. The
maximum value is 1040.384 ms.
Description
LSB = 2 minutes. This register contains a
value between 0x00 and 0xFF. The
maximum value is 510 minutes.
Rev. C | Page 36 of 49
Description
Reserved, set to 0.
Primary reference overdrive.
0: normal mode, no overdrive.
1: overdrive mode. The primary
reference can be driven externally.
Cell balance power-down.
0: cell balance powered down.
1: cell balance powered up.
Hardware (full) power-down.
0: do not enter full power-down mode
when the power-down timer is 0x00
(default).
1: if a value other than 0x00 is in the
power-down timer register, start the
power-down timer. Enter full powerdown mode when the power-down
timer reaches its timeout (also dependent
on VDRIVE for the master). If the powerdown timer register is already at 0x00,
power down the device (also dependent
on VDRIVE for the master). The HWPD bit
takes precedence over the SWPD bit.
Software (partial) power-down.
0: do not enter partial power-down
mode (default).
1: enter partial power-down mode
immediately.
Software reset.
0: bring out of reset (default).
1: reset.
Data Sheet
AD7284
Control Register 2
Control Register 2 (CTRL2) sets the acquisition time of the
ADC and provides current matching control of the daisy chain.
See Table 23 for the appropriate setting for Bits[D6:D3].
Table 23. Recommended Configuration for Control Register 2,
Bits[D6:D3]
Bits
[D6:D3]
Setting
0000
Table 22. CTRL2 Register Settings (Register 0x08)
0000
Bits
D7
D6
0000
D5
D4
D3
D2
[D1:D0]
Name
Reserved
TXIBAL
IDIODE
RXIBAL
IMASTER
Reserved
ACQTME
Description
Reserved, set to 0.
Additional current equivalent to the
transmit bias current.
0: matching on.
1: marching off.
An additional 400 μA forward bias current
is used for the service disconnect (SD) diode.
0: bias current enabled.
1: bias current disabled.
A level shifting current is required for the
data receive circuit (120 μA).
0: current enabled.
1: current disabled.
Master mode.
0: enable the transceiver (4.5 mA) and the
receiver (3 mA) bias currents.
1: disable the transceiver and the receiver
bias currents.
Reserved, set to 0.
Set acquisition time.
00: 400 ns (default).
01: 800 ns.
10: 1600 ns.
11: 3200 ns.
Rev. C | Page 37 of 49
0100
0100
0100
1010
1010
1110
1110
1110
1110
1111
Description
Master in a dc-coupled chain; service
disconnect diodes used
Master in a chain with mixed coupling;
service disconnect diodes used
Slave in a mixed chain with a transformer
coupled connection to the device directly
below; service disconnect diodes used
Master in a dc-coupled chain; no service
disconnect diodes
Master in a chain with mixed coupling; no
service disconnect diodes
Slave in a mixed chain with a transformer
coupled connection directly below; no
service disconnect diodes
Slave in a dc coupled chain; service
disconnect diodes used
Slave in a mixed chain with a dc
connection directly below; service
disconnect diodes used
Master in a transformer coupled chain; no
service disconnect diodes
Slave in a dc-coupled chain; no service
disconnect diodes
Slave in a transformer coupled chain; no
service disconnect diodes
Slave in a mixed chain with a dc-coupled
connection directly below; no service
disconnect diodes
Master only; no daisy chain
AD7284
Data Sheet
Control Register 3
Control Register 3 (CTRL3) is used for input sense control and
also provides the general output enabling functions on Bit D4,
Bit D3, and Bit D2.
Table 24. CTRL3 Register Settings (Register 0x09)
Bits
D7
D6
Name
Reserved
ADCDLY
D5
ADCORDR
D4
GOE_CB
D3
GOE_OSS
D2
GOE_OSP
[D1:D0]
IN_SNSE
Description
Reserved, set to 0.
ADC delay mode.
0: normal mode, no delay.
1: delay mode. The primary and secondary
measurements are delayed by 1000 μs,
relative to each other, as dictated by Bit D5.
Sets the order of the ADC conversions in
delay mode.
0: primary followed by secondary.
1: secondary followed by primary.
General output enable for cell balance.
0: disabled (default).
1: enabled.
General output enable for open input
sense on secondary path.
0: disabled.
1: enabled.
General output enable for open input
sense on primary path.
0: disabled.
1: enabled.
Selection of input sense function. These
bits determine which outputs are turned
on for the duration of the sense signal.
00: function off.
01: cell balance sense active.
10: primary open input sense active.
11: secondary open input sense active.
Asserting Bit D0 (the device ID increment bit) initiates the
device ID setup process, which assigns an ID to the devices in
the chain that are incremented from the master ID. After the ID
process completes, D0 clears and Bit D1 (the device ID lock bit)
is internally set. The user can read back from the control register of
each device to confirm the device ID has locked. Unlock the
device ID by writing a 0 to D1; keep the device ID locked by
writing 1 to D1 on any subsequent writes.
Bits[D0:D1] are mutually exclusive and, in the event that both
bits are set in one command, the device ID lock bit, Bit D1,
takes precedence over the increment bit, and the device does
not start the increment sequence.
The device ID bits written to the control register of the master
device are directly used as that device ID. The slave device IDs
are stored in a different register. A readback of the control
register of any slave device returns the master device ID. The
actual device ID is the first five bits of each 32-bit SDO frame.
A 25 μs delay per device is required between initiating the
device ID setup process and a new register write command. The
device ID is not cleared by a software reset.
Table 25. CTRL4 Register Settings (Register 0x0A)
Bits
D7
D6
D5
D4
D3
D2
D1
Name
Reserved
DEVID, Bit 4
DEVID, Bit 3
DEVID, Bit 2
DEVID, Bit 1
DEVID, Bit 0
DEVIDLOCK
D0
DEVIDINC
Control Register 4
The master device ID bits, Bits[D6:D2] in Control Register 4
(CTRL4), can configure the devices with unique IDs in a single
daisy chain with the master having an address settable between
0 and 30. An address of 31 (0x1F) is not allowed by either
master or slave and, if attempted, is ignored, with the existing
address being kept. In the event the master is assigned an
address of 30, any following slaves are assigned 0, 1, 2, and so
on. Address 31 is reserved for the address all command and is
not assigned to any single device.
On power-on, the user can configure the device IDs by first
writing the appropriate ID to Bits[D6:D2] of the master device.
These bits are set to zero by default.
Analog Devices, Inc., recommends programming the master
device with an address other than 0 so that if a POR event
occurs, it is detectable due to the master address reverting back
to 0 on a reset.
Rev. C | Page 38 of 49
Description
Reserved.
Master device ID, Bit 4.
Master device ID, Bit 3.
Master device ID, Bit 2.
Master device ID, Bit 1.
Master device ID, Bit 0.
Device ID lock. Read this bit to check if
device ID has locked.
0: device is not locked to its device address.
If no device address is received, the device
continues to operate with default device
address, 0x0.
1: device is locked to its device address. It is
set automatically by the device when the
device ID setup is complete.
Device ID increment.
0: do not initialize the assign ID setup process.
1: initialize the device ID setup process.
Assigns and auto increments the device ID
for all devices discovered on the daisy chain.
Data Sheet
AD7284
Cell Balance Control Register
OIS Control Registers
The cell balance control (CBCTRL) register determines
the state of each of the cell balance outputs (CB1 to CB8)
individually. The default value of the cell balance control
register on power-up is 0x00, and the cell balance outputs
are off.
The OIS control registers (OISCTRL and OISGPOP) control
the switching of a current into each analog voltage input
(100 μA). The nine OISx outputs can be individually enabled by
setting an appropriate bit in the OIS control registers. Setting a
bit to Logic 1 enables the current in conjunction with the open
input sense GOE bits (D2 or D3), as detailed in Table 24.
Table 26. CBCTRL Register Settings (Register 0x0B)
Bits
D7
Name
CB8
D6
CB7
D5
CB6
D4
CB5
D3
CB4
D2
CB3
D1
CB2
D0
CB1
Description
This bit sets the CB8 output.
0: output off.
1: output on.
This bit sets the CB7 output.
0: output off.
1: output on.
This bit sets the CB6 output.
0: output off.
1: output on.
This bit sets the CB5 output.
0: output off.
1: output on.
This bit sets the CB4 output.
0: output off.
1: output on.
This bit sets the CB3 output.
0: output off.
1: output on.
This bit sets the CB2 output.
0: output off.
1: output on.
This bit sets the CB1 output.
0: output off.
1: output on.
Table 27. OISCTRL Register Settings (Register 0x0E)
Bits
D7
Name
OIS8
D6
OIS7
D5
OIS6
D4
OIS5
D3
OIS4
D2
OIS3
D1
OIS2
D0
OIS1
Description
OIS 8 control. Set this bit to 1 to pull current
from either VPIN8 or VSIN8, depending on
the CTRL3 setting, to VSS.
OIS 7 control. Set this bit to 1 to pull current
from Pin VPIN7 or Pin VSIN7 , depending on
the CTRL3 setting, to VSS.
OIS 6 control. Set this bit to 1 to pull current
from Pin VPIN6 or Pin VSIN6, depending on
the CTRL3 setting, to VSS.
OIS 5 control. Set this bit to 1 to pull current
from Pin VPIN5 or Pin VSIN5, depending on
the CTRL3 setting, to VSS.
OIS 4 control. Set this bit to 1 to pull current
from Pin VPIN4 or Pin VSIN4, depending on
the CTRL3 setting, to VSS.
OIS 3 control. Set this bit to 1 to pull current
from Pin VPIN3 or Pin VSIN3, depending on
the CTRL3 setting, to VSS.
OIS 2 control. Set this bit to 1 to pull current
from Pin VPIN2 or VSIN2, depending on the
CTRL3 setting, to VSS.
OIS 1 control. Set this bit to 1 to pull current
from Pin VPIN1 or Pin VSIN1, depending on
the CTRL3 setting, to VSS.
Table 28. OISGPOP Register Settings (Register 0x0F)
Bits
D7
Name
OIS0
[D6:D3]
D2
Reserved
GPOP2
D1
GPOP1
D0
GPOP SEL
Rev. C | Page 39 of 49
Description
OIS 0 control. Set this bit to 1 to pull
current from AVCC.
Reserved.
User defined General-Purpose Output
Signal 2.
User defined General-Purpose Output
Signal 1.
GPOPx configuration.
0: user defined GPOPx.
1: GPOPx pins configured for daisy-chain
debug, see the Daisy-Chain Debug Mode
section for further details.
AD7284
Data Sheet
Power-Down Timer Register
Table 31. WDT Register Settings (Register 0x21)
The power-down timer (PDT) register allows the user to
configure a set time after which the AD7284 is powered down.
The AD7284 allows the user to set the power-down timer to a
value from 0 hours to 8.5 hours (510 minutes, maximum). The
resolution of the power-down timer is 2 minutes. When using
the power-down timer in conjunction with the CBx timers, it is
recommended that the value programmed to the power-down
timer exceed the time programmed to the CBx timer by at least
2 minutes because the power-down timer takes priority over the
CBx timers and the device powers down. The default value of
the power-down timer register on power-up is 0x00.
Bits
D7
[D6:D0]
The power-down timer does not begin counting until the
HWPD bit in Control Register 1 is set. Clearing the HWPD bit
does not stop the power-down timer; stop the power-down
timer by writing 0x00 to the register.
Table 32. WDKY Register Setting (Register 0x22)
During a count, a new value can be written to the power-down
timer register. This causes the power-down timer to restart and
count to the new value.
Storage Register 1 and Storage Register 2
Table 29. PDT Register Setting (Register 0x10)
Bits
[D7:D0]
Name
PD_T
Description
LSB = 2 minutes. Selectable between
0x00 and 0xFF. The maximum value =
510 minutes.
Watchdog Key Register
The watchdog key (WDKY) register allows the user to disable the
watchdog timer. To disable the watchdog timer, write 0x00 to the
watchdog timer register, then write 0x5A to the watchdog key
register, and finally write 0x00 to the watchdog timer register. The
default value of the watchdog key register on power-up is 0x00.
Bits
[D7:D0]
Name
WDKEY
Description
Key = 0x5A
Storage Register 1 and Storage Register 2 (STRG1 and STRG2)
are available for user storage purposes. These registers are
volatile.
Bits
[D7:D0]
Name
STRG1
Description
Storage Register 1
Table 34. STRG2 Register Setting (Register 0x24)
The CB Timer 1 to CB Timer 8 (CBT1 to CBT8) registers allow
the user to program individual times for each of the eight cell
balance outputs. The AD7284 allows the user to set the CBx
timer to a value from 0 minutes to 8.5 hours. The resolution of
the CBx timers is 2 minutes. The default value of the CBx timer
registers on power-up is 0x00. When the CBx timer value is set
to 0x00, the CBx timer is not activated; that is, the CBx outputs are
all controlled by the contents of the cell balance register only.
Table 30. CBT1 Register to CBT8 Register Settings
(Register 0x11 to Register 0x18)
Name
CB_T
Description
Reserved; set this bit to 0.
LSB = 8.192 ms. Selectable between 0x00
and 0x7F. The maximum value is 1040 ms.
Table 33. STRG1 Register Setting (Register 0x23)
CB Timer 1 to CB Timer 8 Registers
Bits
[D7:D0]
Name
Reserved
WDT
Description
LSB = 2 minutes. Selectable between
0x00 and 0xFF. The maximum value is
510 minutes.
Watchdog Timer Register
The watchdog timer (WDT) register allows the user to
configure a set time after which the AD7284 is automatically
powered down if communications to the AD7284 is lost. The
AD7284 allows the user to set the watchdog timer to a maximum
value of 1040 ms with a resolution of 8.192 ms.
Bits
[D7:D0]
Name
STRG2
Description
Storage Register 2
REGISTERS COMMON TO PAGE 0 AND PAGE 1
Page Register
The page (page) register can be written to independently of the
current page selection.
Read Register
The read (RDREG) register defines the read operation of the
AD7284. The read register can be written to independently of
the page addressing. To read back a register from a chain of
AD7284 devices, first write the desired register to the read register
on all devices. Issue a null write command (0x00000000) per
device to read back the register contents of each device in the
daisy chain. The readback starts with the master device, then
the first slave device, and so on. The read register is not used for
reading back conversion results. See the Example 5: Convert
and Read All Conversion Data section for more details. The
default value of the read register on power-up is 0xFF.
The default value of the watchdog timer register on power-up is
0x0C (98.304 ms).
Rev. C | Page 40 of 49
Data Sheet
AD7284
EXAMPLES OF INTERFACING WITH THE AD7284
Example 2: Reading the Device ID
REGISTER WRITE AND REGISTER READ
OPERATIONS EXAMPLES
In this section, Example 1 and Example 3 illustrate register
write operations. Example 2 illustrates a register read operation.
See Table 36. This sequence is similar for any register read
operation. To verify the device IDs are set and locked, take the
following steps to read Control Register 4:
Example 1: Initialize All Devices in a Daisy Chain
1.
See Table 35. By default, the device ID on the AD7284 is 0. This
example demonstrates how to set the master ID to 2 and to
increment the device ID of slaves up the chain. Changing the
master device ID allows identification of each device in a
system containing more than one master.
1.
2.
Write 1. Write 0x01 to the page register on all devices to
give access to Control Register 4 in Page 1. The 32-bit write
command is 0xFFE013B2.
Write 2. Write to the Control Register 4 at Address 0x0A.
Set the master ID and increment the IDs up the chain. The
master ID is set by writing a 5-bit code to Bits[D6:D2] (0x02
in this example). Set the device increment bit (D0) to 1 and
the device lock bit (D1) to 0. The 32-bit write command is
0xFCA0983D.
2.
3.
Write 1. Write 0x01 to the page register on all devices to
give access to Control Register 4 in Page 1. The 32-bit write
command is 0xFFE013B2.
Write 2. Write 0x0A into the read register (the address
corresponding to Control Register 4). The 32-bit write
command is 0xFBF0A43F. The write/write, read bit must be 0.
Write 3. Apply a CS low pulse that frames 32 SCLKs for each
slave in the chain to be read back. Verify in the register
data field that the device ID is locked for each device in the
daisy chain by ensuring Bit D1 (the device ID lock bit) is
set high on each Control Register 4 readback. Also, in this
example, a device ID of 2 is returned for the master device
signified by the first five bits, a device ID of three for the
first slave device by the first five bits, and so on. The 32-bit
write command is 0x00000000. In Table 36, n is the
number of devices in the chain.
Table 35. Example 1: Initializing All Devices in a Daisy Chain
Write Command
Write 1
Write 2
Device Address
11111
11111
Write/Write, Read
1
1
Register Address
111110
001010
Data
00000001
00001001
12-Bit CRC
001110110010
100000111101
32-Bit Write Command
0xFFE013B2
0xFCA0983D
Data
00000001
00001010
00000000
12-Bit CRC
001110110010
010000111111
000000000000
32-Bit Write Command
0xFFE013B2
0xFBF0A43F
0x00000000
Table 36. Example 2: Reading the Device ID for a Chain of Devices
Write Command
Write 1
Write 2
Write 3 (×n)
Device Address
11111
11111
00000
Write/Write, Read
1
0
0
Register Address
111110
111111
000000
Rev. C | Page 41 of 49
AD7284
Data Sheet
Example 3: Disabling the Watchdog Timer
See Table 37.
CONVERSION DATA READBACK OPERATION
EXAMPLES
1.
Example 4: Convert and Read Primary Conversion Data
2.
3.
4.
Write 1. Write 0x01 to the page register on all devices to
give access to the watchdog timer registers in Page 1. The
32-bit write command is 0xFFE013B2.
Write 2. To start the watchdog timer disable routine, write
0x00 to the watchdog timer register. The 32-bit write
command is 0xFE100F8E.
Write 3. Write the correct key value, 0x5A, to the watchdog
key register. The 32-bit write command is 0xFE25A8DC.
Write 4. Complete the routine by writing 0x00 to the
watchdog timer register. The 32-bit write command is
0xFE100F8E.
See Table 38.
1.
2.
3.
4.
Write 1. Write Data 0x00 to the page register on all devices.
The 32-bit write command is 0xFFE00531.
Write 2. Initiate conversions through the software convert
start bit by asserting the LSB of the ADC functional control
register. The 32-bit write command is 0xFFD01420. Allow
sufficient time for all conversions to be completed, as
described in the Converting with a Chain of AD7284
Devices section. Note that, after conversions are initiated,
the device automatically enters 64-bit read mode and
remains in 64-bit mode until commanded to exit.
Write 3. Following the completion of all conversions, apply
a CS low pulse that frames 32 SCLKs for each primary
conversion result to be read back. For a daisy chain of three
devices with 18 primary measurements on each device, this
equates to 54 frames in total. All frames, except the last
one, input a 32-bit write command of 0x00000000. In the
table, n is the number of devices in the chain.
Write 4. The last frame (the 54th frame for a daisy chain of
three devices) inputs 0xFFD04E2C. This command writes
the value of 0x04 to the ADC functional control register,
returning the interface protocol back to 32-bit mode such
that the devices are ready to receive configuration changes
or further software convert start requests.
Table 37. Example 3: Disabling the Watchdog Timer
Write Command
Write 1
Write 2
Write 3
Write 4
Device Address
11111
11111
11111
11111
Write/Write, Read
1
1
1
1
Register Address
111110
100001
100010
100001
Data
00000001
00000000
01011010
00000000
12-Bit CRC
001110110010
111110001110
100011011100
111110001110
32-Bit Write Command
0xFFE013B2
0xFE100F8E
0xFE25A8DC
0xFE100F8E
Table 38. Example 4: Convert and Read Primary Conversion Data
Write Command
Write 1
Write 2
Write 3 × (n × 18) − 1
Write 4
Device Address
11111
11111
00000
11111
Write/Write, Read
1
1
0
1
Register Address
111110
111101
000000
111101
Rev. C | Page 42 of 49
Data
00000000
00000001
00000000
00000100
12-Bit CRC
010100110001
010000100000
000000000000
111000101100
32-Bit Write Command
0xFFE00531
0xFFD01420
0x00000000
0xFFD04E2C
Data Sheet
AD7284
Example 5: Convert and Read All Conversion Data
4.
See Table 39.
1.
2.
3.
Write 1. Write Data 0x00 to the page register on all devices.
The 32-bit write command is 0xFFE00531.
Write 2. Initiate conversions through the software convert
start bit by asserting the LSB of the ADC functional control
register. The 32-bit write command is 0xFFD01420. Allow
sufficient time for all conversions to be completed as
described in the Converting with a Chain of AD7284
Devices section. Note that, after conversions are initiated,
the device automatically enters 64-bit read mode and
remains in 64-bit mode until commanded to exit.
Write 3. Following the completion of all conversions, apply
a CS low pulse that frames 32 SCLKs for each primary and
secondary conversion result to be read back. For a single
device, with 18 primary and 10 secondary measurements,
this equates to 28 frames in total. All frames, except for
the 18th and 28th, input the 32-bit write command of
0x00000000. For a daisy chain of three devices with
18 primary and 10 secondary measurements on each
device, this equates to 84 frames in total. In this case, all
frames, except for the 54th and 84th, input a 32-bit write
command of 0x00000000.
5.
Write 4. During the last primary readback frame, input
0xFFD02FA5. This command writes the value of 0x02 to
the ADC functional control register, selecting the secondary
conversion data results. For a single device, this is the 18th
frame. For a daisy chain of three devices, this is the 54th
frame.
Write 5. During the last secondary read back frame, write
0xFFD04E2C. This command writes the value of 0x04 to
the ADC functional control register, returning the interface
protocol back to 32-bit mode such that the devices are ready
to receive configuration changes or further software convert
start requests. For a single device, this is the 28th frame.
For a daisy chain of three devices, this is the 84th frame.
Table 39. Example 5: Convert and Read All Conversion Data
Write Command
Write 1
Write 2
Write 3 × (n × 18) − 1
Write 4
Write 3 × (n × 10) − 1
Write 5
Device Address
11111
11111
00000
11111
00000
11111
Write/Write-Read
1
1
0
1
0
1
Register Address
111110
111101
000000
111101
000000
111101
Rev. C | Page 43 of 49
Data
00000000
00000001
00000000
00000010
00000000
00000100
12-Bit CRC
010100110001
010000100000
000000000000
111110100101
000000000000
111000101100
32-Bit Write Command
0xFFE00531
0xFFD01420
0x00000000
0xFFD02FA5
0x00000000
0xFFD04E2C
AD7284
Data Sheet
APPLICATIONS INFORMATION
The AD7284 can be used in many different system architectures,
from a system with a single device, to a chain of devices connected
with or without transformers, multiple devices on one board,
or single devices on multiple boards. Each of these system
architectures present different external components
requirements.
TYPICAL CONNECTION DIAGRAMS
This section summarizes the different hardware recommendations
from the previous sections, presents a typical diagram for a
single device, and a typical diagram for a chain of three devices
on separate boards.
Master Only
Figure 41 shows an example of components for a master device,
monitoring eight cells using two independent filters (on the
primary and secondary path), and monitoring temperature
on four thermistors.
The following notes refer to the notes detailed in Figure 41 and
Figure 42:
1.
2.
3.
4.
5.
A 100 nF decoupling capacitor placed close to the battery
cell connector.
A transient protection, rated appropriately, capable of
limiting the voltage at the device to within the absolute
maximum ratings.
Ferrite bead to filter supply noise. Typically, 1 kΩ ferrite
(100 MHz) is recommend in the VDD path. If a ferrite is
required in the VSS line, it is recommended to use a value
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