3 V/5 V, Rail-to-Rail
Quad, 8-Bit DAC
AD7304/AD7305
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
VREFB VREFA
VDD
PWR-ON
RESET
INPUT 8
REG A
DAC A 8
REG
DAC A
VOUTA
INPUT 8
REG B
DAC B 8
REG
DAC B
VOUTB
INPUT 8
REG C
DAC C 8
REG
DAC C
VOUTC
INPUT 8
REG D
DAC D 8
REG
DAC D
VOUTD
CS
SDI/SHDN
SERIAL
REG
CLK
APPLICATIONS
AD7304
Automotive output span voltage
Instrumentation, digitally controlled calibration
Pin-compatible AD7226 replacement when VDD < 5.5 V
VSS
CLR LDAC VREFC VREFD
Figure 1.
VREF
VDD
GENERAL DESCRIPTION
The AD7304/AD73051 are quad, 8-bit DACs that operate from
a single +3 V to +5 V supply, or ±5 V supplies. The AD7304 has
a serial interface, while the AD7305 has a parallel interface.
Internal precision buffers swing rail-to-rail. The reference input
range includes both supply rails, allowing for positive or negative
full-scale output voltages. Operation is guaranteed over the
supply voltage range of 2.7 V to 5.5 V, consuming less than
9 mW from a 3 V supply.
GND
01114-001
8
PWR-ON
RESET
DB0
DB1
DB2
DB3
DB4
DB5
DB6
WR
A0/SHDN
A1
INPUT 8
REG A
DAC A 8
REG
DAC A
VOUTA
INPUT 8
REG B
DAC B 8
REG
DAC B
VOUTB
INPUT 8
REG C
DAC C 8
REG
DAC C
VOUTC
INPUT 8
REG D
DAC D 8
REG
DAC D
VOUTD
8
8
DECODE
AD7305
LDAC
VSS
01114-002
Four 8-bit DACs in one package
+3 V, +5 V, and ±5 V operation
Rail-to-rail REF input to voltage output swing
2.6 MHz reference multiplying bandwidth
Internal power-on reset
SPI serial interface-compatible—AD7304
Fast parallel interface—AD7305
40 µA power shutdown
GND
The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail VREF input to
DAC VOUT allows for a full-scale voltage set equal to the positive
supply, VDD, the negative supply, VSS, or any value in between.
When operating from less than 5.5 V, the AD7305 is
pin-compatible with the popular industry-standard AD7226.
The AD7304’s doubled-buffered serial data interface offers high
speed, 3-wire, SPI®-, and microcontroller-compatible inputs
using data in (SDI), clock (CLK), and chip select (CS) pins.
Additionally, an internal power-on reset sets the output to zero
scale.
An internal power-on reset places both parts in the zero-scale
state at turn-on. A 40 µA power shutdown (SHDN) feature is
activated on both parts by three-stating the SDI/SHDN pin on
the AD7304 and three-stating the A0/SHDN address pin on the
AD7305.
The parallel input AD7305 uses a standard address decode
along with the WR control line to load data into the input
registers.
The AD7304/AD7305 are specified over the extended industrial
−40°C to +85°C and the automotive −40°C to +125°C
temperature ranges. AD7304s are available in a wide-body
16-lead SOIC (R-16) package. The parallel input AD7305 is
available in the wide-body 20-lead SOIC (R-20) surface-mount
package. For ultracompact applications, the thin 1.1 mm,
16-lead TSSOP (RU-16) package is available for the AD7304,
while the 20-lead TSSOP (RU-20) houses the AD7305.
The double-buffered architecture allows all four input registers
to be preloaded with new values, followed by an LDAC control
strobe that copies all the new data into the DAC registers,
thereby updating the analog output values.
Figure 2.
_____________________________________________________
1
Protected under Patent No. 5684481.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD7304/AD7305
TABLE OF CONTENTS
Specifications..................................................................................... 3
AD7304/AD7305 Power-On Reset .......................................... 15
Timing Specifications .................................................................. 4
Power up sequence..................................................................... 15
Absolute Maximum Ratings............................................................ 5
AD7305 Parallel Data Interface .................................................... 16
ESD Caution.................................................................................. 5
AD7226 Pin Compatibility ....................................................... 16
Pin Configurations and Function Descriptions ........................... 8
AD7305 Hardware Shutdown SHDN...................................... 16
Typical Performance Characteristics ........................................... 10
ESD Protection Circuits ............................................................ 16
Circuit Operation ........................................................................... 14
Applications..................................................................................... 17
DAC Section................................................................................ 14
Outline Dimensions ....................................................................... 18
AD7304 Serial Data Interface ....................................................... 15
Ordering Guide .......................................................................... 19
AD7304 Hardware Shutdown SHDN...................................... 15
Revision History
11/04—Data Sheet Changed from Rev. B to Rev. C
Update Format ....................................................................Universal
Update Features ................................................................................ 1
Changes to Figure 35...................................................................... 15
Add Power-Up Sequence............................................................... 15
Changes to Figure 36...................................................................... 16
Change to Figure 37 ....................................................................... 16
Updated Outline Dimensions ....................................................... 18
2/04—Data Sheet Changed from Rev. A to Rev. B
Renumber TPCs and Figures ............................................Universal
Deleted N-16 and N-20 packages.....................................Universal
Changes to Absolute Maximum Ratings ....................................... 3
Changes to Ordering Guide ............................................................ 4
Updated Outline Dimensions ....................................................... 14
3/98—Changed from Rev. 0 to Rev. A
2/98—Revision 0: Initial Version
Rev. C | Page 2 of 20
AD7304/AD7305
SPECIFICATIONS
@ VDD = 3 V or 5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS ≤ VREF ≤ VDD, −40°C < TA < +85°C/+125°C, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution1
Integral Nonlinearity2
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Temperature
Coefficient3
REFERENCE INPUT
VREFIN Range
Input Resistance (AD7304)
Input Resistance (AD7305)
Input Capacitance3
ANALOG OUTPUTS
Output Voltage Range
Output Current Drive
Shutdown Resistance
Capacitive Load3
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current5
Input Capacitance3
AC CHARACTERISTICS3
Output Slew Rate
Reference Multiplying
Total Harmonic Distortion
Settling Time6
Shutdown Recovery Time
Time to Shutdown
DAC Glitch
Digital Feedthrough
Feedthrough
SUPPLY CHARACTERISTICS
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Down
Power Supply Sensitivity
Symbol
N
INL
DNL
VZSE
VFSE
TCVFS
VREFIN
RREFIN
RREFIN
CREFIN
VOUT
IOUT
ROUT
CL
Condition
Monotonic, all codes 0 to 0xFF
Data = 0x00
Data = 0xFF
Code = 0x55
All DACs at code = 0x55
Code = 0x80, ∆VOUT < 1 LSB
DAC outputs placed in shutdown
state
No oscillation
VIL
VIH
IIL
CIL
SR
BW
THD
tS
tSDR
tSDN
Q
Q
VOUT/VREF
Code = 0x00 to 0xFF to 0x00
Small signal, VSS = –5 V
VREF = 4 V p-p, VSS = –5 V, f = 1 kHz
To ±0.1% of full scale
To ±0.1% of full scale
IDD
ISS
PDISS
IDD_SD
PSS
VLOGIC = 0 V or VDD, no load
VSS = –5 V
VLOGIC = 0 V or VDD, no load
SDI/SHDN = floating
∆VDD = ±10%
3 V ± 10%
5 V ± 10%
±5 V ± 10%
Unit
8
±1
±1
15
±4
5
8
±1
±1
15
±4
5
8
±1
±1
±15
±4
5
Bits
LSB max
LSB max
mV max
LSB max
ppm/°C typ4
VSS/VDD
28
7.5
5
VSS/VDD
28
7.5
5
VSS/VDD
28
7.5
5
V min/max
kΩ typ
kΩ typ
pF typ
VSS/VDD
±3
120
VSS/VDD
±3
120
VSS/VDD
±3
120
V min/max
mA typ
kΩ typ
200
200
200
pF typ
0.6
2.1
±10
8
0.8
2.4
±10
8
0.8
2.4
±10
8
V min
V max
µA max
pF max
1/2.7
1/3.6
1.1/2
2
15
15
2
1.0/2
2
15
15
2
1.0/3.6
2.6
0.025
1.0/2
2
15
15
2
−65
V/µs min/typ
MHz typ
%
µs typ/max
µs max
µs typ
nVs typ
nVs typ
dB
6
6
15
40
0.004
30
40
0.004
6
6
60
40
0.004
mA max
mA max
mW max
µA typ
%/%
Code = 0x00, VREF = 1 V p-p, f = 100 kHz
1
One LSB = VREF/256.
The first three codes (0x00, 0x01, 0x10) are excluded from the integral nonlinearity error measurement in single-supply operation 3 V or 5 V.
These parameters are guaranteed by design and not subject to production testing.
4
Typical specifications represent average readings measured at 25°C.
5
The SDI/SHDN and A0/SHDN pins have a 30 µA maximum IIL input leakage current.
6
The settling time specification does not apply for negative going transitions within the last three LSBs of ground in single-supply operation.
2
3
Rev. C | Page 3 of 20
AD7304/AD7305
+5V
VREF = 10V p-p
f = 20kHz
+5V
0V
0V
–5V
–5V
(IN)
(OUT)
01114-003
VOUT = 10V p-p
Figure 3. Rail-to-Rail Reference Input to Output at 20 kHz
TIMING SPECIFICATIONS
@ VDD = 3 V or 5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS ≤ VREF ≤ VDD, –40°C < TA < +85°C/+125°C, unless otherwise noted.
Table 2.
Parameter
INTERFACE TIMING SPECIFICATIONS1, 2
AD7304 Only
Clock Width High
Clock Width Low
Data Setup
Data Hold
Load Pulse Width
Load Setup
Load Hold
Clear Pulse Width
Select
Deselect
AD7305 Only
Data Setup
Data Hold
Address Setup
Address Hold
Write Width
Load Pulse Width
Load Setup
Load Hold
1
2
Symbol
3 V ± 10%
5 V ± 10%
±5 V ± 10%
Unit
tCH
tCL
tDS
tDH
tLDW
tLD1
tLD2
tCLWR
tCSS
tCSH
70
70
50
30
70
40
40
60
30
60
55
55
40
20
60
30
30
60
20
40
55
55
40
20
60
30
30
60
20
40
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
tDS
tDH
tAS
tAH
tWR
tLDW
tLS
tLH
60
30
60
30
60
60
60
30
40
20
40
20
50
50
40
20
40
20
40
20
50
50
40
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
These parameters are guaranteed by design and not subject to production testing.
All input control signals are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Rev. C | Page 4 of 20
AD7304/AD7305
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VDD to GND
VSS to GND
VREFX to GND
Logic Inputs to GND
VOUTX to GND
IOUT Short-Circuit to GND
Package Power Dissipation
Thermal Resistance θJA
16-Lead SOIC Package (R-16)
16-Lead TSSOP Package (RU-16)
20-Lead SOIC Package (R-20)
20-Lead TSSOP Package (RU-20)
Maximum Junction Temperature (TJ MAX)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 sec)
R-16, R-20, RU-16, RU-20 (Infrared, 15 sec)
Rating
−0.3 V, +8 V
+0.3 V, −8 V
VSS, VDD
−0.3 V, VDD + 0.3 V
−0.3 V, VDD + 0.3 V
50 mA
(TJ MAX – TA)/θJA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
73°C/W
180°C/W
74°C/W
155°C/W
150°C
−40°C to +85°C
−65°C to +150°C
235°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 5 of 20
AD7304/AD7305
SA
SDI
SI
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
CLK
tCSS
tCSH
CS
tLD2
LDAC
tLD1
SDI
tDS
tDH
tCL
CLK
tCH
tLDW
LDAC
CLR
tCLRW
tS
FS
01114-004
±1 LSB
ERROR BAND
VOUT
ZS
tS
Figure 4. AD7304 General Timing Diagram
tSDN
tSDR
01114-005
SDI/SHDN
IDD
Figure 5. AD7304 Timing Diagram Zoom In
Table 4. AD7304 Control Logic Truth Table
CS 1
CLK1
LDAC
CLR1
Serial Shift Register Function
Input REG Function
DAC Register Function
H
L
↑+
H
H
H
X
↑+
L
X
X
X
H
H
H
L
H
H
H
H
H
H
↓–
↑+
No effect
Data advanced 1 bit
No effect
No effect
No effect
No effect
No effect
No effect
Updated with SR contents2
Latched with SR contents2
Loaded with 0x00
Latched with 0x00
No effect
No effect
No effect
All input register contents transferred3
Loaded with 0x00
Latched with 0x00
1
2
3
↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.
One input register receives the data bits D7–D0 decoded from the SR address bits (A1, A0), where REG A = (0, 0), B = (0, 1), C = (1, 0), and D = (1, 1).
LDAC is a level-sensitive input.
Table 5. AD7304 Serial Input Register Data Format, Data is Loaded in MSB-First Format
AD7304
MSB
B11
SAC
B10
SDC
B9
A1
B8
A0
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
LSB
B0
D0
If B11 (SAC), Shutdown All Channels, is set to logic low, all DACs are placed in a power shutdown mode, and all output voltages become
high resistance. If B10 (SDC), Shutdown Decoded Channel, is set to logic low, only the DAC decoded by Address Bits A1 and A0 is placed
in shutdown mode.
Rev. C | Page 6 of 20
AD7304/AD7305
Table 6. AD7305 Control Logic Truth Table
WR 1
A1
A0
LDAC2
Input Register Function
DAC Register Function
L
↑+
L
↑+
L
↑+
L
↑+
H
L
H
H
L
L
L
L
H
H
H
H
X
X
X
X
L
L
H
H
L
L
H
H
X
X
X
X
H
H
H
H
H
H
H
H
L
L
↑+
H
Register A loaded with DB0 to DB7
Register A latched with DB0 to DB7
Register B loaded with DB0 to DB7
Register B latched with DB0 to DB7
Register C loaded with DB0 to DB7
Register C latched with DB0 to DB7
Register D loaded with DB0 to DB7
Register D latched with DB0 to DB7
No effect
Input register x transparent to DB0 to DB7
No effect
No effect, device not selected
Latched with previous contents, no change
Latched with previous contents, no change
Latched with previous contents, no change
Latched with previous contents, no change
Latched with previous contents, no change
Latched with previous contents, no change
Latched with previous contents, no change
Latched with previous contents, no change
All input register contents loaded, register transparent
Register transparent
All input register contents latched
No effect, device not selected
↑+ positive logic transition; ↓– negative logic transition; X don’t care.
LDAC is a level-sensitive input.
tWR
WR
tAS
tAH
tDS
tDH
A0, A1
D0–D7
tLS
tLH
tLDW
LDAC
tS
±1 LSB
ERROR BAND
VOUT
Figure 6. AD7305 General Timing Diagram
tSDN
tSDR
A0/SHDN
IDD
01114-007
2
01114-006
1
Figure 7. AD7305 Timing Diagram Zoom In
Rev. C | Page 7 of 20
AD7304/AD7305
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VOUTB 1
16 VOUTC
VOUTA 2
VSS 3
15 VOUTD
AD7304
14 VDD
13 VREFC
TOP VIEW
VREFB 5 (Not to Scale) 12 VREFD
11 SDI/SHDN
GND 6
LDAC 7
CLR 8
10 CLK
9
CS
01114-008
VREFA 4
Figure 8. AD7304 Pin Configuration
Table 7. AD7304 Pin Function Descriptions
Pin No.
1
Mnemonic
VOUTB
2
VOUTA
3
4
5
6
7
VSS
VREFA
VREFB
GND
LDAC
8
CLR
9
CS
10
11
CLK
SDI/SHDN
12
13
14
15
VREFD
VREFC
VDD
VOUTD
16
VOUTC
Description
Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFB pin.
Output is open circuit when SHDN is enabled.
Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFA pin.
Output is open circuit when SHDN is enabled.
Negative Power Supply Input. Specified range of operation is 0 V to −5.5 V.
Channel A Reference Input. Establishes VOUTA full-scale voltage. Specified range of operation is VSS < VREFA < VDD.
Channel B Reference Input. Establishes VOUTB full-scale voltage. Specified range of operation is VSS < VREFB < VDD.
Common Analog and Digital Ground.
Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the
corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See
Table 4 for operation.
Clears All Input and DAC Registers to the Zero Condition. Asynchronous active low input. The serial register is
not effected.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial input register data to
the decoded input register when CS returns high. Does not effect LDAC operation.
Clock Input, Positive Edge Clocks Data into Shift Register. Disabled by chip select CS.
Serial Data Input Loads Directly into the Shift Register, MSB First. Hardware shutdown (SHDN) control input,
active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as
power is present on VDD.
Channel D Reference Input. Establishes VOUTD full-scale voltage. Specified range of operation is VSS < VREFD < VDD.
Channel C Reference Input. Establishes VOUTC full-scale voltage. Specified range of operation is VSS VREFC < VDD.
Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.
Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFD pin.
Output is open circuit when SHDN is enabled.
Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFC pin.
Output is open circuit when SHDN is enabled.
Rev. C | Page 8 of 20
AD7304/AD7305
VOUTB
1
20
VOUTA
2
19
VOUTD
VSS 3
18
VDD
17
A0/SHDN
16
A1
VREF
4
GND
5
LDAC
6
15
WR
DB7
7
14
DB0
DB6
8
13
DB1
DB5
9
12
DB2
DB4 10
11
DB3
TOP VIEW
(Not to Scale)
01114-009
AD7305
VOUTC
Figure 9. AD7305 Pin Configuration
Table 8. AD7305 Pin Function Description
Pin No.
1
Mnemonic
VOUTB
2
VOUTA
3
4
5
6
VSS
VREF
GND
LDAC
7
8
9
10
11
12
13
14
15
16
17
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
WR
A1
A0/SHDN
18
19
VDD
VOUTD
20
VOUTC
Description
Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFB pin. Output is
open circuit when SHDN is enabled.
Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFA pin. Output is
open circuit when SHDN is enabled.
Negative Power Supply Input. Specified range of operation is 0 V to –5.5 V.
Channel B Reference Input. Establishes VOUT full-scale voltage. Specified range of operation is VSS < VREF < VDD.
Common Analog and Digital Ground.
Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the
corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See Table 6
for operation.
MSB Digital Input Data Bit.
Data Bit 6.
Data Bit 5.
Data Bit 4.
Data Bit 3.
Data Bit 2.
Data Bit 1.
LSB Digital Input Data Bit.
Write Data into Input Register Control Line, Active Low. See Table 6 for operation.
Address Bit 1.
Address Bit 0/Hardware Shutdown (SHDN) Control Input, Active When Pin Is Left Floating by a Three-State Logic
Driver. Does not effect DAC register contents as long as power is present on VDD.
Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.
Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFD pin. Output is
open circuit when SHDN is enabled.
Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFC pin. Output is
open circuit when SHDN is enabled.
Rev. C | Page 9 of 20
AD7304/AD7305
TYPICAL PERFORMANCE CHARACTERISTICS
144
1.0
VDD = +5V
VSS = –5V
VREF = VDD
DATA = 0x00
0.6
DAC D
96
0.2
INL (LSB)
72
–0.2
DAC C
DAC B
48
–0.6
01114-010
24
0
VDD = +5V
VSS = –5V
DATA = 0x80
TA = +25°C
0
6
3
9
12
–1.0
–5.0
15
–1.0
–3.0
VOUT (mV)
3.0
5.0
Figure 13. INL vs. Reference Input Voltage
–35
0.500
VDD = +5V
VSS = –5V
VREF = VDD
DATA = 0xFF
–28
VDD = +5V
VSS = –5V
VREF = +2.5V
0.375
0.250
0.125
DNL (LSB)
–21
–14
0
–0.125
–0.250
–7
4.2
4.4
4.6
–0.500
5.0
4.8
01114-014
–0.375
01114-011
0
4.0
0
32
64
96
VOUT OUTPUT VOLTAGE (V)
160
192
224
256
Figure 14. DNL vs. Code
+1
4.0
0
DAC A
+1
0
DAC B
–1
+1
0
VDD = +5V
VSS = –5V
VREF = +2.5V
TA = +25°C
DAC C
–1
01114-012
+1
0
DAC D
0
32
64
96
128
160
192
224
256
3.6
VDD = 5.5V
VSS = 0V
VREF = 5.45V
3.2
2.8
2.4
2.0
–55
01114-015
ZERO-SCALE VOLTAGE (mV)
–1
–1
128
CODE (Decimal)
Figure 11. IOUT SOURCE vs. VOUT Rail-to-Rail Performance
INL (LSB)
1.0
REFERENCE INPUT VOLTAGE (V)
Figure 10. IOUT Sink vs. VOUT Rail-to-Rail Performance
IOUT SOURCE CURRENT (mA)
DAC A
01114-013
IOUT SINK CURRENT (mA)
120
–35
–15
5
25
45
65
85
105
CODE (Decimal)
TEMPERATURE (°C)
Figure 12. INL vs. Code, All DAC Channels
Figure 15. Zero-Scale Voltage vs. Temperature
Rev. C | Page 10 of 20
125
AD7304/AD7305
VOUT
VDD = 5V
VREF = 4V
DATA = 0x00
CS
NO LOAD
0xFF
VDD = 5V
CL = 150pF
RL = 70kΩ
RL = 10kΩ
0V
VOUT
5V
01114-019
0V
01114-016
CS
2µs/DIV
5µs/DIV
Figure 19. Time to Shutdown
Figure 16. Large-Signal Settling Time
CS
+5V
DATA = 0xFF
VREFIN
(±5V @
50kHz)
IDD
1mA/V
0V
–5V
+5V
VDD = 5V
0V
VOUT
VOUTA
01114-017
01114-020
–5V
2µs/DIV
Figure 20. Shutdown Recovery Time (Wakeup)
Figure 17. Multiplying Mode Step Response and Output Slew Rate
10
6
VDD = +5V
VSS = –5V
DATA = 0xFF
VREF = 100mV rms
4
VDD = +5V
VSS = –5V
THD (%)
0
f–3dB = 2.6MHz
0.1
–4
0.01
–8
10k
100k
1M
10M
0.001
10m
01114-021
–6
01114-018
GAIN (dB)
1
1
2
3
4
5
6
7
8
VREF AMPLITUDE (V p-p)
FREQUENCY (Hz)
Figure 21. THD vs. Reference Input Amplitude
Figure 18. Multiplying Mode Gain vs. Frequency
Rev. C | Page 11 of 20
9
10
AD7304/AD7305
1
VDD = +5V
VSS = –5V
0.1
VDD = +5V
VSS = –5V
VREF = +2.5V
F = 1MHz
DATA = 0x80
THD (%)
VOUT
0x7F
0.01
01114-022
0.001
20
01114-025
CS
1k
100
10k
100k
FREQUENCY (Hz)
Figure 25. Midscale Transition Glitch
Figure 22. THD vs. Frequency
40
3.0
VDD = +5V
VSS = –5V
VREF = +4V
DATA = 0xFF
CROSS TALK (dB)
0
1.8
1.2
–20
VDD = +5V
VSS = –5V
VREF = 50mV rms
DAC A DATA = 0xFF
DAC B, DAC C, DAC D DATA = 0x00
–40
–60
–80
–100
0.6
CT = 20 LOG
0
1
10
100
1k
10k
VOUTB
VREF
01114-026
01114-023
–120
–140
–160
100
100k
100k
10k
1k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. Output Noise Voltage Density vs. Frequency
Figure 26. Crosstalk vs. Frequency
10M
60
–PSRR, VSS = –5V ± ∆10%
+PSRR, VDD = +5V ± ∆10%
50
40
PSRR (dB)
VOUTB
VDD = +5V
VSS = –5V
VREF = +2.5V
DAC A = 0xFF
DAC B = 0x00
F = 2MHz
–PSRR, VSS = –3V ± ∆10%
30
+PSRR, VDD = +3V ± ∆10%
20
10
50ns/DIV
0
10
DATA = 0x80
TA = +25°C
100
1k
10k
FREQUENCY (Hz)
50ns/DIV
Figure 27. Power-Supply Rejection vs. Frequency
Figure 24. Digital Feedthrough
Rev. C | Page 12 of 20
100k
01114-027
CLK
01114-024
NOISE DENSITY (µV/ Hz)
2.4
20
AD7304/AD7305
80
12
VDD = +5V
VSS = –5V
VREF = +2.5V
A0 = +5V
ALL OTHER DIGITAL
PINS VARYING
8
IDD
4
60
50
40
ISS
30
01114-028
2
0
0
2
1
3
4
20
–55
5
01114-031
6
VDD = +5.5V
VSS = –5.5V
VREF = +2.5V
PIN A0 FLOATING
70
SHUTDOWN SUPPLY (µA)
SUPPLY CURRENT (mA)
10
–15
–35
Figure 28. Supply Current vs. Digital Input Voltage
45
65
85
105
125
Figure 31. Shutdown Supply Current vs. Temperature
0.08
NORMALIZED TOTAL UNADJUSTED
ERROR DRIFT (LSB)
10
1
VDD = +5V
VSS = –5V
VREF = +2.5V
ALL DIGITAL PINS VARY,
EXCEPT A0 = +5V
0.1
IDD
0.01
READING MADE AT TA = +25°C
SAMPLE SIZE = 924 UNITS
0.04
VDD = +2.7V
0
VDD = +5.5V
–0.04
ISS
01114-029
0.001
0.0001
0
2
1
3
4
VDD = +5V
VSS = –5V
VREF = +2.5V
IDD AND ISS
3.2
01114-030
2.6
–35
–15
5
25
45
65
168
252
336
420
504
Figure 32. Normalized TUE Drift Accelerated by Burn-In Hours
of Operation @ 150°C
5.0
2.0
–55
84
TEMPERATURE (°C)
Figure 29. Shutdown Supply Current vs. Digital Input Voltage (A0 Only)
3.8
–0.08
0
5
DIGITAL INPUT VOLTAGE (V)
4.4
01114-032
SUPPLY CURRENT (mA)
25
TEMPERATURE (°C)
DIGITAL INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
5
85
105
125
TEMPERATURE (°C)
Figure 30. Supply Current vs. Temperature
Rev. C | Page 13 of 20
AD7304/AD7305
CIRCUIT OPERATION
The AD7304/AD7305 are 4-channel, 8-bit, voltage output
DACs, differing primarily in digital logic interface and number
of reference inputs. Both parts share the same internal DAC
design and true rail-to-rail output buffers. The AD7304 contains
four independent multiplying reference inputs, while the
AD7305 has one common reference input. The AD7304 uses a
3-wire SPI-compatible serial data interface, while the AD7305
offers an 8-bit parallel data interface.
DAC SECTION
Each part contains four voltage-switched R-2R ladder DACs.
Figure 33 shows a typical equivalent DAC. These DACs are
designed to operate both single-supply or dual-supply,
depending on whether the user supplies a negative voltage on
the VSS pin. In a single-supply application, the VSS is tied to
ground. In either mode, the DAC output voltage is determined
by the VREF input voltage and the digital data (D) loaded into
the corresponding DAC register according to Equation 1.
VOUT = VREF D/256
(1)
Note that the output full-scale polarity is the same as the VREF
polarity for dc reference voltages.
VDD
VREF
DB7
DB6
VOUT
2R
R
2R
These DACs are also designed to accommodate ac reference
input signals. As long as the ac signals are maintained between
VSS < VREF < VDD, the user can expect 50 kHz of full power,
multiplying bandwidth performance. In order to use negative
input reference voltages, the VSS pin must be biased with a
negative voltage of equal or greater magnitude than the
reference voltage.
The reference inputs are code dependent, exhibiting worst-case
minimum resistance values specified in the parametric specification table. The DAC outputs VOUTA, VOUTB, VOUTC, and VOUTD
are each capable of driving 2 kΩ loads in parallel with up to 500 pF
loads. Output sink current and source current are shown in
Figure 10 and Figure 11, respectively. The output slew rate is
nominally 3.6 V/µs while operating from ±5 V supplies. The
low output impedance of the buffers minimizes crosstalk
between analog input channels. At 100 kHz, 65 dB of channelto-channel isolation exists (Figure 26). Output voltage noise is
plotted in Figure 23. In order to maintain good analog performance, power supply bypassing of 0.01 µF in parallel with 1 µF is
recommended. The true rail-to-rail capability of the AD7304/AD7305
allows the user to connect the reference inputs directly to the
same supply as the VDD or VSS pin (Figure 34). Under these
conditions, clean power supply voltages (low ripple, avoid
switching supplies) appropriate for the application should be
used.
VDD
VSS
Q1
VOUTX
2R
01114-033
Q2
2R
120kΩ
VSS
Figure 33. Typical Equivalent DAC Channel
01114-034
DB0
Figure 34. Equivalent DAC Amplifier Output Circuit
Rev. C | Page 14 of 20
AD7304/AD7305
AD7304 SERIAL DATA INTERFACE
VREFA
CS
CLK
SDI
Table 5 defines the 12 data-word bits. Data is placed on the
SDI/SHDN pin and clocked into the register on the positive
clock edge of CLK subject to the data setup and data hold time
requirements specified in the Timing Specifications section.
Data can only be clocked in while the CS chip select pin is
active low. Only the last 12-bits clocked into the serial register
are interrogated when the CS pin returns to the logic high state,
extra data bits are ignored. Since most microcontrollers output
serial data in 8-bit bytes, two right-justified data bytes can be
written to the AD7304. Keeping the CS line low between the
first and second byte transfer results in a successful serial
register update.
Once the data is properly aligned in the shift register, the
positive edge of the CS initiates either the transfer of new data
to the target DAC register, determined by the decoding of
Address Bits A1 and A0, or the shutdown features is activated
based on the SAC or SDC bits. When either SAC or SDC pins
are set (Logic 0), the loading of new data determined by Bits B9
to B0 are still loaded, but the results do not appear on the buffer
outputs until the device is brought out of the shutdown state.
The selected DAC output voltages become high impedance with
a nominal resistance of 120 kΩ to ground, see Figure 34. If
both the SAC and SDC pins are set, all channels are still placed
in shutdown mode. When the AD7304 has been programmed
into the power shutdown state, the present DAC register data is
maintained as long as VDD remains greater than 2.7 V. The
remaining characteristics of the software serial interface are
defined by Table 4, Table 5, and Figure 5.
VREFB
VREFC
VREFD
VDD
AD7304
EN
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
SDC
SAC
INPUT
REGISTER R
DAC A
OE
VOUTA
DAC B
REGISTER R
DAC B
OE
VOUTB
DAC C
REGISTER R
DAC C
OE
VOUTC
DAC D
REGISTER R
DAC D
OE
VOUTD
8
D Q
DAC A
B
2:4
C
DECODE
D
VDD
640kΩ
DAC A
REGISTER R
680kΩ
INPUT
REGISTER R
D Q
INPUT
REGISTER R
D Q
INPUT
REGISTER R
80kΩ
D Q
280kΩ
320kΩ
GND
POWERON
RESET
LDAC
CLR
VSS
01114-035
The AD7304 uses a 3-wire (CS, SDI, CLK) SPI-compatible
serial data interface. New serial data is clocked into the serial
input register in a 12-bit data-word format. MSB bits are loaded
first.
Figure 35. AD7304 Equivalent Logic Interface
AD7304 HARDWARE SHUTDOWN SHDN
If a three-state driver is used on the SDI/SHDN pin, the
AD7304 can be placed into a power shutdown mode when the
SDI/ SHDN pin is placed in a high impedance state. For proper
operation, no other termination voltages should be present on
this pin. An internal window comparator detects when the logic
voltage on the SHDN pin is between 28% and 36% of VDD. A
high impedance internal bias generator provides this voltage on
the SHDN pin. The four DAC output voltages become high
impedance with a nominal resistance of 120 kΩ to ground (see
Figure 34 for an equivalent circuit).
AD7304/AD7305 POWER-ON RESET
Two additional pins, CLR and LDAC, on the AD7304 provide
hardware control over the clear function and the DAC register
loading. If these functions are not needed, the CLR pin can be
tied to logic high, and the LDAC pin can be tied to logic low.
The asynchronous input CLR pin forces all input and DAC
registers to the zero-code state. The asynchronous LDAC pin
can be strobed to active low when all DAC registers need to be
updated simultaneously from their respective input registers.
When the VDD power supply is turned on, an internal reset
strobe forces all the input and DAC registers to the zero-code
state. The VDD power supply should have a monotonically
increasing ramp in order to have consistent results, especially in
the region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect
on the power-on reset performance. The DAC register data
stays at zero until a valid serial register software load takes
place. In the case of the double-buffered AD7305, the output
DAC register can only be changed once the LDAC strobe is
initiated.
The LDAC pin places the DAC register in a transparent mode
while in the logic low state.
POWER-UP SEQUENCE
It is recommended to power VDD/VSS first before applying any
voltage to the reference terminals to avoid potential latch up.
The ideal power-up sequence is in the following order: GND,
VDD, VSS, Digital Inputs, and VREFx. The order of powering
digital inputs and reference inputs is not important as long as
they are powered after VDD/VSS.
Rev. C | Page 15 of 20
AD7304/AD7305
AD7305 PARALLEL DATA INTERFACE
The AD7305 has an 8-bit parallel interface DB7 = MSB, DB0 =
LSB. Two address bits, A1 and A0, are decoded when an active
low write strobe is placed on the WR pin, see Table 6. The WR
is a level-sensitive input pin, therefore, the data setup and data
hold times defined in the Timing Specifications section need to
be adhered to.
VREF VDD
A0/SHDN
By tying the LDAC pin to ground, the AD7305 has the same pin
configuration and functionality as the AD7226, with the
exception of a lower power supply operating voltage.
AD7305
8
AD7305 HARDWARE SHUTDOWN SHDN
WR
A1
AD7226 PIN COMPATIBILITY
DAC A
B
C
2:4
DECODE D
VDD
640kΩ
INPUT
REGISTER R
DAC A
REGISTER R
DAC A
OE
VOUTA
INPUT
REGISTER
R
DAC B
REGISTER R
DAC B
OE
VOUTB
R
DAC C
REGISTER R
DAC C
OE
VOUTC
R
DAC D
REGISTER R
DAC D
OE
VOUTD
INPUT
REGISTER
680kΩ
INPUT
REGISTER
80kΩ
320kΩ
GND
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND). The VREF pins also contain a backbiased ESD protection Zener connected to VDD (see Figure 37).
POWERON
RESET
LDAC
VSS
01114-036
280kΩ
If a three-state driver is used on the A0/SHDN pin, the AD7305
can be placed into a power shutdown mode when the A0/SHDN
pin is placed in a high impedance state. For proper operation,
no other termination voltages should be present on this pin. An
internal window comparator detects when the logic voltage on
the SHDN pin is between 28% and 36% of VDD. A high impedance, internal-bias generator provides this voltage on the SHDN
pin. The four DAC output voltages become high impedance
with a nominal resistance of 120 kΩ to ground.
Figure 36. AD7305 Equivalent Logic Interface
DIGITAL
INPUTS
The LDAC pin provides the capability of simultaneously
updating all DAC registers with new data from the input
registers at the same time. This results in the analog outputs all
changing to their new values at the same time. The LDAC pin is
a level-sensitive input. If the simultaneous update feature is not
required, the LDAC pin can be tied to logic low. When the
Rev. C | Page 16 of 20
VDD
VREFX
GND
Figure 37. Equivalent ESD Protection Circuits
01114-037
DATA
DB0–DB7
LDAC is tied to Logic Low, the DAC registers become
transparent and the input register data determines the DAC
output voltage (see Figure 36 for an equivalent interface logic
diagram).
AD7304/AD7305
APPLICATIONS
the input data (D) is incremented from code zero (VOUT = –5 V)
to midscale (VOUT = 0 V) to full scale (VOUT = +5 V).
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing.
This is easily accomplished using an external true rail-to-rail op
amp, such as the OP295. Connecting the external amplifier with
two equal value resistors, as shown in Figure 38, results in a full
4-quadrant multiplying circuit. In this circuit, the amplifier
provides a gain of two, which increases the output span
magnitude to 10 V. The transfer equation of this circuit shows
that both negative and positive output voltages are created as
Rev. C | Page 17 of 20
VOUT =
D
× V REF
128 − 1
+5V
10kΩ
(2)
10kΩ
2.2pF
REF
AD7304
–5V < VOUT < +5V
01114-038
The AD7304/AD7305 are inherently 2-quadrant multiplying
DACs. That is, they can easily be set up for unipolar output
operation. The full-scale output polarity is the same as the
reference input voltage polarity.
Figure 38. 4-Quadrant Multiplying Application Circuit
AD7304/AD7305
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
5.10
5.00
4.90
9
16
7.60 (0.2992)
7.40 (0.2913)
9
4.50
4.40
4.30
10.65 (0.4193)
10.00 (0.3937)
8
1
16
6.40
BSC
1
1.27 (0.0500)
BSC
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.75 (0.0295)
× 45°
0.25 (0.0098)
8°
0.33 (0.0130) 0°
0.20 (0.0079)
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
1.27 (0.0500)
0.40 (0.0157)
0.30
0.19
0.65
BSC
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-013AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Figure 39. 16-Lead Standard Small Outline Package [SOIC]
Wide Body (R-16)
Dimensions shown in millimeters and (inches)
6.60
6.50
6.40
13.00 (0.5118)
12.60 (0.4961)
20
0.75
0.60
0.45
8°
0°
11
7.60 (0.2992)
7.40 (0.2913)
1
10
20
11
4.50
4.40
4.30
10.65 (0.4193)
10.00 (0.3937)
6.40 BSC
1
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
1.27
(0.0500)
BSC
8°
0.51 (0.0201) SEATING
0.33 (0.0130) 0°
0.31 (0.0122) PLANE
0.20 (0.0079)
0.75 (0.0295)
× 45°
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
SEATING
PLANE
0.20
0.09
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153AC
Figure 42. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Figure 40. 20-Lead Standard Small Outline Package [SOIC]
Wide Body (R-20)
Dimensions shown in millimeters and (inches)
Rev. C | Page 18 of 20
0.75
0.60
0.45
AD7304/AD7305
ORDERING GUIDE
Model
AD7304BR
AD7304BR-REEL
AD7304BRZ1
AD7304BRZ-REEL1
AD7304YR
AD7304YRZ1
AD7304BRU
AD7304BRU-REEL7
AD7305BR
AD7305BR-REEL
AD7305YR
AD7305YR-REEL
AD7305BRU
AD7305BRU-REEL7
AD7305BRUZ1
AD7305BRUZ-REEL71
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
16-Lead SOIC
16-Lead SOIC
16-Lead SOIC
16-Lead SOIC
16-Lead SOIC
16-Lead SOIC
16-Lead TSSOP
16-Lead TSSOP
20-Lead SOIC
20-Lead SOIC
20-Lead SOIC
20-Lead SOIC
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
Z = Pb-free part.
Rev. C | Page 19 of 20
Package Options
R-16
R-16
R-16
R-16
R-16
R-16
RU-16
RU-16
R-20
R-20
R-20
R-20
RU-20
RU-20
RU-20
RU-20
AD7304/AD7305
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A.
C01114-0-11/04(C)
Rev. C | Page 20 of 20
工商网监
湘ICP备2023018690号
