FEATURES
FUNCTIONAL BLOCK DIAGRAM
12-bit plus sign SAR ADC
True bipolar input ranges
Software-selectable input ranges
±10 V, ±5 V, ±2.5 V, 0 V to +10 V
500 kSPS throughput rate
8 analog input channels with channel sequencer
Single-ended, true differential, and pseudo differential
analog input capability
High analog input impedance
Low power: 18 mW
Temperature indicator
Full power signal bandwidth: 22 MHz
Internal 2.5 V reference
High speed serial interface
Power-down modes
20-lead TSSOP package
iCMOS process technology
VDD
REFIN/OUT
VCC
AD7327-EP
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
2.5V
VREF
I/P
MUX
T/H
13-BIT
SUCCESSIVE
APPROXIMATION
ADC
TEMPERATURE
INDICATOR
DOUT
CONTROL LOGIC
AND REGISTERS
CHANNEL
SEQUENCER
SCLK
CS
DIN
VDRIVE
AGND
VSS
DGND
Figure 1.
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Product change notification
Qualification data available on request
GENERAL DESCRIPTION
The AD7327-EP1 is an 8-channel, 12-bit plus sign successive
approximation ADC designed on the iCMOS® (industrial CMOS)
process. It enables the development of a wide range of high
performance analog ICs capable of 33 V operation in a footprint
that no previous generation of high voltage devices achieved.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can accept bipolar input signals while providing
increased performance, dramatically reduced power consumption,
and reduced package size.
The AD7327-EP can accept true bipolar analog input signals,
software-selectable from ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V.
Each analog input channel can be independently programmed
to one of the four input ranges. The analog input channels on
the AD7327-EP can be programmed to be single-ended, true
differential, or pseudo differential.
The ADC contains a 2.5 V internal reference. The AD7327-EP
also allows external reference operation. If a 3 V reference is
applied to the REFIN/OUT pin, the AD7327-EP can accept a
true bipolar ±12 V analog input. Minimum ±12 V VDD and VSS
supplies are required for the ±12 V input range. The ADC has a
high speed serial interface that can operate at throughput rates up
to 500 kSPS.
The AD7327-EP is housed in a 20-lead TSSOP with operation
specified from −55°C to +125°C. Additional application and
technical information can be found in the AD7327 data sheet.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
1
The AD7327-EP can accept true bipolar analog input
signals, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V (unipolar).
The eight analog inputs can be configured as eight singleended inputs, four true differential inputs, four pseudo
differential inputs, or seven pseudo differential inputs.
500 kSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™compatible interface.
Low power, 18 mW, at a maximum throughput rate of
500 kSPS.
Channel sequencer.
Protected by U.S. Patent No. 6,731,232.
Rev. C
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
12481-001
Enhanced Product
500 kSPS, 8-Channel, Software-Selectable,
True Bipolar Input, 12-Bit Plus Sign ADC
AD7327-EP
AD7327-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................8
Enhanced Product Features ............................................................ 1
ESD Caution...................................................................................8
General Description ......................................................................... 1
Pin Configuration and Function Descriptions..............................9
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ........................................... 10
Product Highlights ........................................................................... 1
Outline Dimensions ....................................................................... 14
Revision History ............................................................................... 2
Ordering Guide .......................................................................... 14
Specifications..................................................................................... 3
Timing Specifications .................................................................. 7
REVISION HISTORY
4/2018—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Changes to Ordering Guide .......................................................... 14
10/2014—Rev. 0 to Rev. A
Changes to Operating Temperature Range, Table 3 .....................8
9/2014—Revision 0: Initial Version
9/2015—Rev. A to Rev. B
Added Enhanced Product Features Section.................................. 1
Rev. C | Page 2 of 14
Enhanced Product
AD7327-EP
SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to 3.0 V internal/external, fSCLK =
10 MHz, fS = 500 kSPS, TA = TMAX to TMIN, unless otherwise noted.
Table 1.
Parameter 1
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR) 2
Signal-to-Noise + Distortion
(SINAD)2
Min
Typ
Max
76
75.5
72
dB
dB
dB
71.7
dB
75
dB
74
76
dB
dB
dB
72.5
dB
70.7
Total Harmonic Distortion (THD)2
−79.3
−78.8
−82
−76
−77.3
−80
Peak Harmonic or Spurious
Noise (SFDR)2
dB
dB
dB
dB
dB
dB
Test Conditions/Comments
fIN = 50 kHz sine wave
Differential mode, VCC = 4.75 V to 5.25 V
Differential mode, VCC < 4.75 V
Single-ended/pseudo differential mode; ±10 V,
±2.5 V and ±5 V ranges, VCC = 4.75 V to 5.25 V
Single-ended/pseudo differential mode; 0 V to 10 V
VCC = 4.75 V to 5.25 V and all ranges at VCC < 4.75 V
Differential mode; ±2.5 V and ±5 V ranges
Differential mode; 0 V to 10 V
Differential mode; ±10 V range
Single-ended/pseudo differential mode; ±2.5 V and
±5 V ranges
Single-ended/pseudo differential mode; 0 V to +10 V
and ±10 V ranges
Differential mode; ±2.5 V and ±5 V ranges
Differential mode; 0 V to 10 V ranges
Differential mode; ±10 V range
Single-ended/pseudo differential mode; ±5 V range
Single-ended/pseudo differential mode; ±2.5 V range
Single-ended/pseudo differential mode; 0 V to +10 V
and ±10 V ranges
Differential mode; ±2.5 V and ±5 V ranges
−80
dB
−80
−79
dB
dB
dB
dB
dB
−88
−90
7
50
−79
dB
dB
ns
ps
dB
Up to 100 kHz ripple frequency; see Figure 17
−72
22
5
dB
MHz
MHz
fIN on unselected channels up to 100 kHz; see Figure 14
At 3 dB
At 0.1 dB
−82
−77.2
−78.9
Intermodulation Distortion
(IMD)2
Second-Order Terms
Third-Order Terms
Aperture Delay 3
Aperture Jitter3
Common-Mode Rejection
(CMRR)2
Channel-to-Channel Isolation2
Full Power Bandwidth
Unit
Rev. C | Page 3 of 14
Differential mode; 0 V to 10 V ranges
Differential mode; ±10 V ranges
Single-ended/pseudo differential mode; ±5 V range
Single-ended/pseudo differential mode; ±2.5 V range
Single-ended/pseudo differential mode; 0 V to +10 V
and ±10 V ranges
fA = 50 kHz, fB = 30 kHz
AD7327-EP
Parameter 1
DC ACCURACY 4
Resolution
No Missing Codes
Enhanced Product
Min
Typ
Max
13
12-bit
plus sign
(13 bits)
11-bit
plus sign
(12 bits)
Test Conditions/Comments
Single-ended/pseudo differential mode 1 LSB =
FSR/4096, unless otherwise noted; differential mode
1 LSB = FSR/8192, unless otherwise noted
Bits
Bits
Differential mode
Bits
Single-ended/pseudo differential mode
±1.25
LSB
±1.2
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Differential mode; VCC = 3 V to 5.25 V, typical for VCC =
2.7 V
Single-ended/pseudo differential mode, VCC = 3 V to
5.25 V, typical for VCC = 2.7 V
Single-ended/pseudo differential mode (LSB =
FSR/8192)
Differential mode; guaranteed no missing codes to
13 bits
Single-ended mode; guaranteed no missing codes to
12 bits
Single-ended/pseudo differential mode
(LSB = FSR/8192)
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
±10
V
Reference = 2.5 V
VDD = +10 V min, VSS = −10 V min, VCC = +2.7 V to +5.25 V
±5
±2.5
0 to 10
V
V
V
VDD = +5 V min, VSS = −5 V min, VCC = +2.7 V to +5.25 V
VDD = +5 V min, VSS = −5 V min, VCC = +2.7 V to +5.25 V
VDD = +10 V min, VSS = AGND min, VCC = +2.7 V to +5.25 V
VDD = +16.5 V, VSS = −16.5 V, VCC = +5 V
±3.5
±6
±5
+3/−5
V
V
V
V
Reference = 2.5 V; range = ±10 V
Reference = 2.5 V; range = ±5 V
Reference = 2.5 V; range = ±2.5 V
Reference = 2.5 V; range = 0 V to +10 V
Integral Nonlinearity2
−0.7/+1.2
Differential Nonlinearity2
LSB
−0.99/+1.2
LSB
±0.99
LSB
−0.7/+1
Offset Error2, 5
LSB
−6/+10
−7/+11
±0.8
±0.5
±8
±15
±0.5
±0.5
±4
±8
±0.5
±0.5
±9
±8
±0.5
±0.5
±4
±7
±0.5
±0.5
Offset Error Match2, 5
Gain Error2, 5
Gain Error Match2, 5
Positive Full-Scale Error2, 6
Positive Full-Scale Error Match2, 6
Bipolar Zero Error2, 6
Bipolar Zero Error Match2, 6
Negative Full-Scale Error2, 6
Negative Full-Scale Error Match2, 6
ANALOG INPUT
Input Voltage Ranges2
(Programmed via Range
Registers)
Unit
Pseudo Differential VIN(−)
Input Range2
Rev. C | Page 4 of 14
Enhanced Product
Parameter 1
DC Leakage Current
AD7327-EP
Min
Typ
Reference Output Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN3
LOGIC OUTPUTS
Output High Voltage, VOH
2.5
3
±1
±5
V
µA
pF
V
mV
±10
mV
25
ppm/°C
10
2.5
3
7
Test Conditions/Comments
VIN = VDD or VSS
Per input channel, VIN = VDD or VSS
When in track, ±10 V range
When in track, ±5 V and 0 V to +10 V ranges
When in track, ±2.5 V range
When in hold, all ranges
ppm/°C
Ω
2.4
0.8
0.4
±1
10
VDRIVE −
0.2 V
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output
Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition
Time2, 3
Throughput Rate
POWER REQUIREMENTS
VDD2
VSS2
VCC2
VDRIVE
Normal Mode (Static)
Normal Mode (Operational)
IDD
ISS
ICC and IDRIVE
Autostandby Mode (Dynamic)
IDD
ISS
ICC and IDRIVE
Unit
nA
nA
pF
pF
pF
pF
3
13.5
16.5
21.5
3
Input Capacitance3
REFERENCE INPUT/OUTPUT
Input Voltage Range
Input DC Leakage Current
Input Capacitance
Reference Output Voltage
Reference Output Voltage Error
at 25°C
Reference Output Voltage
TMIN to TMAX
Reference Temperature
Coefficient
Max
±80
0.4
±1
5
V
V
V
µA
pF
VCC = 4.75 V to 5.25 V
VCC = 2.7 to 3.6 V
VIN = 0 V or VDRIVE
V
ISOURCE = 200 µA
V
µA
pF
ISINK = 200 µA
Straight natural binary
Twos complement
Coding bit set to 1 in control register
Coding bit set to 0 in control register
1.6
305
µs
ns
500
kSPS
16.5
−16.5
5.25
5.25
V
V
V
V
mA
16 SCLK cycles with SCLK = 10 MHz
Full-scale step input
Digital inputs = 0 V or VDRIVE
12
−12
2.7
2.7
0.9
195
215
2.3
µA
µA
mA
100
110
0.87
µA
µA
mA
Rev. C | Page 5 of 14
VDD/VSS = ±16.5 V, VCC/VDRIVE = 5.25 V
fSAMPLE = 500 kSPS
VDD = 16.5 V
VSS = −16.5 V
VCC/VDRIVE = 5.25 V
fSAMPLE = 250 kSPS
VDD = 16.5 V
VSS = −16.5 V
VCC/VDRIVE = 5.25 V
AD7327-EP
Parameter 1
Autoshutdown Mode (Static)
IDD
ISS
ICC and IDRIVE
Full Shutdown Mode
IDD
ISS
ICC and IDRIVE
POWER DISSIPATION
Normal Mode (Operational)
Full Shutdown Mode
Enhanced Product
Min
Typ
Max
Unit
1
1
1
µA
µA
µA
1
1
1
µA
µA
µA
Test Conditions/Comments
SCLK on or off
VDD = 16.5 V
VSS = −16.5 V
VCC/VDRIVE = 5.25 V
SCLK on or off
VDD = 16.5 V
VSS = −16.5 V
VCC/VDRIVE = 5.25 V
19
38.25
mW
µW
VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V
VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V
Temperature range is −55°C to +125°C.
See the terminology section of the AD7327 data sheet.
3
Sample tested during initial release to ensure compliance.
4
For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless
otherwise noted.
5
Unipolar 0 V to 10 V range with straight binary output coding.
6
Bipolar range with twos complement output coding.
1
2
Rev. C | Page 6 of 14
Enhanced Product
AD7327-EP
TIMING SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to 3.0 V internal/external,
TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted. Sample tested during initial release to ensure
compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
Table 2.
Parameter
fSCLK
tCONVERT
tQUIET
t1
t2 1
t3
t4
t5
t6
t7
t8
t9
t10
tPOWER-UP
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
µs max
µs typ
Description
VDRIVE ≤ VCC
tSCLK = 1/fSCLK
Minimum time between end of serial read and next falling edge of CS
Minimum CS pulse width
CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
Unipolar input range (0 V to 10 V)
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
SCLK falling edge to DOUT high impedance
DIN set-up time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power-up from autostandby
Power-up from full shutdown/autoshutdown mode, internal reference
Power-up from full shutdown/autoshutdown mode, external reference
When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50.
t1
CS
tCONVERT
t2
SCLK
t6
1
2
3
4
3 IDENTIFICATION BITS
t3
ADD1
DOUT
THREE- ADD2
t9
STATE
DIN
WRITE
REG
SEL1
ADD0
SIGN
5
t4
13
14
DB11
15
16
t5
t7
DB10
DB2
t8
DB1
t10
REG
SEL2
tQUIET
DB0
THREE-STATE
LSB
MSB
Figure 2. Serial Interface Timing Diagram
Rev. C | Page 7 of 14
DON’T
CARE
12481-002
1
Limit at TMIN, TMAX
VCC < 4.75 V VCC = 4.75 V to 5.25 V
50
50
10
10
16 × tSCLK
16 × tSCLK
75
60
12
5
25
20
45
35
26
14
57
43
0.4 × tSCLK
0.4 × tSCLK
0.4 × tSCLK
0.4 × tSCLK
13
8
40
22
10
9
4
4
2
2
750
750
500
500
25
25
AD7327-EP
Enhanced Product
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to AGND, DGND
VSS to AGND, DGND
VDD to VCC
VCC to AGND, DGND
VDRIVE to AGND, DGND
AGND to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to GND
REFIN to AGND
Input Current to Any Pin Except
Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Thermal Impedance
θJA
θJC
Pb-Free Temperature, Soldering
Reflow
ESD
1
Rating
−0.3 V to +16.5 V
+0.3 V to −16.5 V
VCC − 0.3 V to +16.5 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
VSS − 0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VCC + 0.3 V
±10 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
−55°C to +125°C
−65°C to +150°C
150°C
143°C/W
45°C/W
260(0)°C
2.5 kV
Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. C | Page 8 of 14
Enhanced Product
AD7327-EP
CS 1
20
SCLK
DIN 2
19
DGND
DGND 3
18
DOUT
17
VDRIVE
AGND 4
AD7327-EP
TOP VIEW
(Not to Scale)
16
VCC
VSS 6
15
VDD
VIN0 7
14
VIN2
8
13
VIN3
VIN4 9
12
VIN6
VIN5 10
11
VIN7
REFIN/OUT 5
VIN1
12481-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
CS
2
DIN
3, 19
DGND
4
AGND
5
REFIN/OUT
6
7 to 14
VSS
VIN0 to VIN7
15
16
VDD
VCC
17
VDRIVE
18
DOUT
20
SCLK
Description
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7327-EP
and frames the serial data transfer.
Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the AD7327-EP on
the falling edge of SCLK (see the Registers section of AD7327 data sheet).
Digital Ground. Ground reference point for all digital circuitry on the AD7327-EP. The DGND and AGND voltages,
ideally, share the same potential and must not be more than 0.3 V apart, even on a transient basis.
Analog Ground. Ground reference point for all analog circuitry on the AD7327-EP. Refer all analog input signals
and any external reference signal to this AGND voltage. The AGND and DGND voltages, ideally, share the same
potential and must not be more than 0.3 V apart, even on a transient basis.
Reference Input/Reference Output. The on-chip reference is available on this pin for external use to the AD7327-EP.
The nominal internal reference voltage is 2.5 V, which appears at this pin. Place a 680 nF capacitor on the reference
pin (see the Reference section of the AD7327 data sheet). Alternatively, the internal reference can be disabled and
an external reference applied to this input. On power-up, the external reference mode is the default condition.
Negative Power Supply Voltage. VSS is the negative supply voltage for the analog input section.
Analog Input 0 to Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold. The analog input
channel for conversion is selected by programming the Channel Address Bit ADD2 through Channel Address Bit ADD0
in the control register. The inputs can be configured as eight single-ended inputs, four true differential input pairs,
four pseudo differential inputs, or seven pseudo differential inputs. The configuration of the analog inputs is
selected by programming the mode bits, Bit Mode 1 and Bit Mode 0, in the control register. The input range on
each input channel is controlled by programming the range registers. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V
to +10 V can be selected on each analog input channel when a +2.5 V reference voltage is used (see the Registers
section of AD7327 data sheet).
Positive Power Supply Voltage. VDD is the positive supply voltage for the analog input section.
Analog Supply Voltage, 2.7 V to 5.25 V. VCC is the supply voltage for the ADC core on the AD7327-EP. Decouple
this supply to AGND.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
Decouple this pin to DGND. The voltage at this pin may be different to that at VCC, but VDRIVE must not exceed VCC by
more than 0.3 V.
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked
out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The data stream consists of
three channel identification bits, the sign bit, and 12 bits of conversion data. The data is provided MSB first (see the
Serial Interface section of AD7327 data sheet).
Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7327-EP.
This clock is also used as the clock source for the conversion process.
Rev. C | Page 9 of 14
AD7327-EP
Enhanced Product
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0
4096 POINT FFT
VCC = VDRIVE = 5V
VDD, VSS = ±15V
TA = 25°C
INT/EXT 2.5V REFERENCE
±10V RANGE
fIN = 50kHz
SNR = 77.30dB
SINAD = 76.85dB
THD = –86.96dB
SFDR = –88.22dB
SNR (dB)
–40
–60
–80
0.6
INL ERROR (LSB)
–20
VCC = VDRIVE = 5V INT/EXT 2.5V REFERENCE
TA = 25°C
±10V RANGE
VDD, VSS = ±15V
+INL = +0.55LSB
–INL = –0.68LSB
0.8
0.4
0.2
0
–0.2
–0.4
–100
–0.6
–120
0
50
100
150
200
250
FREQUENCY (kHz)
–1.0
12481-004
–140
0
Figure 4. FFT True Differential Mode
Figure 7. Typical INL True Differential Mode
1.0
0
4096 POINT FFT
VCC = VDRIVE = 5V
VDD, VSS = ±15V
TA = 25°C
INT/EXT 2.5V REFERENCE
±10V RANGE
fIN = 50kHz
SNR = 74.67dB
SINAD = 74.03dB
THD = –82.68dB
SFDR = –85.40dB
–40
–60
–80
0.8
0.6
DNL ERROR (LSB)
–20
0.4
0.2
0
–0.2
–0.4
–100
VCC = VDRIVE = 5V
±10V RANGE
TA = 25°C
+DNL = +0.79LSB
VDD, VSS = ±15V
–DNL = –0.38LSB
INT/EXT 2.5V REFERENCE
–0.6
–120
–0.8
0
50
100
150
200
250
FREQUENCY (kHz)
–1.0
12481-005
–140
Figure 5. FFT Single-Ended Mode
0
1024
2048
3072
4096
5120
6144
7168
8192
512
1536
2560
3584
4608
5632
6656
7680
CODE
12481-043
SNR (dB)
4096
5120
6144
7168
3072
2048
1024
8192
4608
5632
6656
7680
3584
2560
1536
512
CODE
12481-007
–0.8
Figure 8. Typical DNL Single-Ended Mode
1.0
1.0
0.8
0.8
0.6
0.6
INL ERROR (LSB)
0.2
0
–0.2
–0.8
–1.0
0
1024
2048
3072
4096
5120
6144
7168
8192
512
1536
2560
3584
4608
5632
6656
7680
CODE
0
–0.2
VCC = VDRIVE = 5V
TA = 25°C
VDD, VSS = ±15V
–0.6
INT/EXT 2.5V REFERENCE
±10V RANGE
–0.8
+INL = +0.87LSB
–INL = –0.49LSB
–1.0
0
1024
2048
3072
4096
5120
6144
7168
8192
512
1536
2560
3584
4608
5632
6656
7680
CODE
Figure 6. Typical DNL True Differential Mode
Figure 9. Typical INL Single-Ended Mode
Rev. C | Page 10 of 14
12481-044
–0.6
0.2
–0.4
VCC = VDRIVE = 5V
TA = 25°C
VDD, VSS = ±15V
INT/EXT 2.5V REFERENCE
±10V RANGE
+DNL = +0.72LSB
–DNL = –0.22LSB
–0.4
12481-006
DNL ERROR (LSB)
0.4
0.4
Enhanced Product
AD7327-EP
–50
75
±2.5V SE
–65
70
±10V DIFF
–75
0V TO +10V DIFF
–80
±5V SE
0V TO +10V SE
±2.5V DIFF
–90
±2.5V SE
100
1000
ANALOG INPUT FREQUENCY (kHz)
50
10
12481-060
–100
10
Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and
True Differential (Diff) Mode at 3 V VCC
–50
VCC = VDRIVE = 5V
VDD/VSS = ±12V
TA = 25°C
fS = 500kSPS
INTERNAL REFERENCE
0V TO +10V SE
THD (dB)
–65
±10V SE
–70
±10V DIFF
–75
0V TO +10V DIFF
–80
±5V SE
–85
±5V DIFF
–90
±2.5V SE
–95
–55
VCC = 3V
–60
VCC = 5V
–65
–70
–75
–80
VDD/VSS = ±12V
SINGLE-ENDED MODE
fS = 500kSPS
TA = 25°C
50kHz ON SELECTED CHANNEL
–85
–90
±2.5V DIFF
100
1000
ANALOG INPUT FREQUENCY (kHz)
–95
12481-061
–100
10
0
100
10k
±5V DIFF
±2.5V DIFF
±5V SE
±2.5V SE
0V TO +10V DIFF
70
±10V DIFF
±10V SE
65
0V TO +10V SE
60
VCC = VDRIVE = 3V
VDD/VSS = ±12V
TA = 25°C
fS = 500kSPS
INTERNAL REFERENCE
100
ANALOG INPUT FREQUENCY (kHz)
1000
8k
400
500
600
6k
5k
4k
3k
2k
0
Figure 12. SINAD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential (Diff) Mode at 3 V VCC
Rev. C | Page 11 of 14
VCC = 5V
VDD/VSS = ±12V
RANGE = ±10V
10k SAMPLES
TA = 25°C
7k
1k
12481-062
55
9469
9k
NUMBER OF OCCURRENCES
75
300
Figure 14. Channel-to-Channel Isolation
80
SINAD (dB)
200
FREQUENCY OF INPUT NOISE (kHz)
Figure 11. THD vs. Analog Input Frequency for Single-Ended (SE) and
True Differential (Diff) Mode at 5 V VCC
50
10
1000
Figure 13. SINAD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential (Diff) Mode at 5 V VCC
CHANNEL-TO-CHANNEL ISOLATION (dB)
–60
100
ANALOG INPUT FREQUENCY (kHz)
–50
–55
VCC = VDRIVE = 5V
VDD/VSS = ±12V
TA = 25°C
fS = 500kSPS
INTERNAL REFERENCE
55
–95
0V TO +10V DIFF
±10V SE
65
60
±5V DIFF
–85
±10V DIFF
12481-063
–70
SINAD (dB)
±10V SE
THD (dB)
±5V SE
0V TO +10V SE
12481-012
–60
±5V DIFF
±2.5V DIFF
228
303
0
0
–2
–1
0
1
2
CODE
Figure 15. Histogram of Codes, True Differential Mode
12481-013
–55
80
VCC = VDRIVE = 3V
VDD/VSS = ±12V
TA = 25°C
fS = 500kSPS
INTERNAL REFERENCE
AD7327-EP
Enhanced Product
8k
2.0
7600
VCC = 5V
VDD/VSS = ±12V
RANGE = ±10V
10k SAMPLES
TA = 25°C
6k
1.5
1.0
INL ERROR (LSB)
5k
4k
3k
–0.5
–1.5
23
–2
–1
0
11
0
2
3
1
–2.0
CODE
5
13
11
–50
–55
–55
–60
–60
–65
–65
PSRR (dB)
VCC = 5V
–75
VCC = 3V
–85
VCC = 5V
VCC = 3V
–70
–75
VDD = 12V
–80
–95
–100
0
200
400
600
800
1000
VSS = –12V
–90
1200
RIPPLE FREQUENCY (kHz)
–100
12481-055
–95
Figure 17. CMRR vs. Common-Mode Ripple Frequency
0
200
400
600
1.5
–55
–60
1.0
–65
THD (dB)
0.5
DNL = 500kSPS
0
–0.5
VCC = VDRIVE = 5V
VDD/VSS = ±12V
TA = 25°C
INTERNAL REF
RANGE = ±10V AND ±2.5V
fS = 500kSPS
DIFFERENTIAL MODE
±5V RANGE
VCC = VDRIVE = 5V
INTERNAL REFERENCE
SINGLE-ENDED MODE
–70
–75
±2.5V RANGE
RIN = 9000Ω
RIN = 5500Ω
RIN = 2000Ω
RIN = 100Ω
RIN = 12Ω
–80
–90
–95
11
13
15
17
19
±VDD/VSS SUPPLY VOLTAGE (V)
Figure 18. DNL Error vs. ±VDD/VSS Supply Voltage at 500 kSPS
–100
10
12481-049
–2.0
9
1200
±10V RANGE
RIN = 4000Ω
RIN = 3000Ω
RIN = 2000Ω
RIN = 1000Ω
RIN = 100Ω
RIN = 12Ω
–85
–1.0
7
1000
Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
–50
5
800
SUPPLY RIPPLE FREQUENCY (kHz)
2.0
–1.5
19
100mV p-p SINE WAVE ON EACH SUPPLY
NO DECOUPLING
SINGLE-ENDED MODE
fS = 500kSPS
–85
DIFFERENTIAL MODE
fIN = 50kHz
VDD/VSS = ±12V
fS = 500kSPS
TA = 25°C
–90
17
15
Figure 19. INL Error vs. ±VDD/VSS Supply Voltage at 500 kSPS
–50
–80
9
±VDD/VSS SUPPLY VOLTAGE (V)
Figure 16. Histogram of Codes, Single-Ended Mode
–70
7
12481-054
0
–3
12481-014
0
12481-050
±5V RANGE
VCC = VDRIVE = 5V
INTERNAL REFERENCE
SINGLE-ENDED MODE
1165
1k
CMRR (dB)
INL = 500kSPS
0
–1.0
2k
1201
DNL ERROR (LSB)
0.5
100
ANALOG INPUT FREQUENCY (kHz)
1000
12481-064
NUMBER OF OCCURENCES
7k
Figure 21. THD vs. Analog Input Frequency for Various Source Impedances,
True Differential Mode
Rev. C | Page 12 of 14
Enhanced Product
AD7327-EP
–50
THD (dB)
VCC = VDRIVE = 5V
–55 VDD/VSS = ±12V
TA = 25°C
–60 INTERNAL REF
RANGE = ±10V AND ±2.5V
–65 fS = 500kSPS
SINGLE-ENDED MODE
±10V RANGE
RIN = 4000Ω
RIN = 2000Ω
RIN = 1000Ω
RIN = 100Ω
RIN = 50Ω
–70
–75
±2.5V RANGE
RIN = 4700Ω
RIN = 3000Ω
RIN = 1000Ω
RIN = 100Ω
RIN = 50Ω
–80
–85
–90
–100
10
100
ANALOG INPUT FREQUENCY (kHz)
1000
12481-065
–95
Figure 22. THD vs. Analog Input Frequency for Various Source Impedances,
Single-Ended Mode
Rev. C | Page 13 of 14
AD7327-EP
Enhanced Product
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 23. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions show in millimeters
ORDERING GUIDE
Model 1
AD7327TRU-EP
AD7327TRU-EP-RL7
AD7327TRUZ-EP
AD7327TRUZ-EP-RL7
1
Temperature Range
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
Package Description
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
Z = RoHS Compliant Part.
©2014–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12481-0-4/18(C)
Rev. C | Page 14 of 14
Package Option
RU-20
RU-20
RU-20
RU-20
