AD73360ARZ

a Six-Input Channel Analog Front End AD73360 FEATURES Six 16-Bit A/D Converters Programmable Input Sample Rate Simultaneous Sampling 77 dB SNR 64 kS/s Maximum Sample Rate –83 dB Crosstalk Low Group Delay (25 ␮s Typ per ADC Channel) Programmable Input Gain Flexible Serial Port which Allows Multiple Devices to Be Connected in Cascade Single (+2.7 V to +5.5 V) Supply Operation 80 mW Max Power Consumption at +2.7 V On-Chip Reference 28-Lead SOIC and 44-Lead TQFP Packages metering or multichannel analog inputs. It features six 16-bit A/D conversion channels each of which provide 77 dB signal-tonoise ratio over a dc to 4 kHz signal bandwidth. Each channel also features a programmable input gain amplifier (PGA) with gain settings in eight stages from 0 dB to 38 dB. APPLICATIONS General Purpose Analog Input Industrial Power Metering Motor Control Simultaneous Sampling Applications A serial port (SPORT) allows easy interfacing of single or cascaded devices to industry standard DSP engines. The SPORT transfer rate is programmable to allow interfacing to both fast and slow DSP engines. The AD73360 is particularly suitable for industrial power metering as each channel samples synchronously, ensuring that there is no (phase) delay between the conversions. The AD73360 also features low group delay conversions on all channels. An on-chip reference voltage is included and is programmable to accommodate either 3 V or 5 V operation. The sampling rate of the device is programmable with four separate settings offering 64 kHz, 32 kHz, 16 kHz and 8 kHz sampling rates (from a master clock of 16.384 MHz). The AD73360 is available in 28-lead SOIC and 44-lead TQFP packages. GENERAL DESCRIPTION The AD73360 is a six-input channel analog front-end processor for general purpose applications including industrial power FUNCTIONAL BLOCK DIAGRAM VINP1 SIGNAL CONDITIONING 0/38dB PGA VINN1 ANALOG ⌺-⌬ MODULATOR DECIMATOR SDI SDIFS VINP2 0/38dB PGA ANALOG ⌺-⌬ MODULATOR DECIMATOR SIGNAL CONDITIONING 0/38dB PGA ANALOG ⌺-⌬ MODULATOR DECIMATOR VINN2 VINP3 SCLK SIGNAL CONDITIONING VINN3 RESET REFERENCE REFCAP AD73360 REFOUT MCLK SE VINP4 SIGNAL CONDITIONING 0/38dB PGA ANALOG ⌺-⌬ MODULATOR DECIMATOR SIGNAL CONDITIONING 0/38dB PGA ANALOG ⌺-⌬ MODULATOR DECIMATOR 0/38dB PGA ANALOG ⌺-⌬ MODULATOR VINN4 VINP5 SERIAL I/O PORT VINN5 SDO SDOFS VINP6 VINN6 Rev. B SIGNAL CONDITIONING DECIMATOR Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2000–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com (AVDD = 3 V ⴞ 10%; DVDD = 3 V ⴞ 10%; DGND = AGND = 0 V, fMCLK = 16.384 MHz, SCLK = 8.192 MHz, fS = 8 kHz; TA = TMIN to TMAX, unless otherwise noted.) AD73360–SPECIFICATIONS1 f Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, VREFOUT Minimum Load Resistance Maximum Load Capacitance Min 1.125 1.125 1 DC Offset Power Supply Rejection Group Delay4, 5 Input Resistance at VIN2, 4 FREQUENCY RESPONSE (ADC)7 Typical Output Frequency (Normalized to fS) 0 0.03125 0.0625 0.125 0.1875 0.25 0.3125 0.375 0.4375 > 0.5 1.25 50 1.375 130 1.25 1.375 100 ADC SPECIFICATIONS Maximum Input Range at VIN2, 3 Nominal Reference Level at VIN (0 dBm0) Absolute Gain PGA = 0 dB PGA = 38 dB Gain Tracking Error Signal to (Noise + Distortion) PGA = 0 dB PGA = 38 dB Total Harmonic Distortion PGA = 0 dB PGA = 38 dB Intermodulation Distortion Idle Channel Noise Crosstalk ADC-to-ADC AD73360A Typ Max 1.644 –2.85 1.1413 –6.02 –30 Test Conditions/Comments V ppm/°C 5VEN = 0 0.1 µF Capacitor Required from REFCAP to AGND2 Ω V kΩ pF Unloaded V p-p dBm V p-p dBm 5VEN = 0, Measured Differentially ± 0.1 dB dB dB 1.0 kHz 1.0 kHz 1.0 kHz, +3 dBm0 to –50 dBm0 77 62 dB dB 0 Hz to 4 kHz; fS = 8 kHz 0 Hz to 4 kHz; fS = 64 kHz –0.8 –0.8 73 Unit +0.8 +0.8 –83 –70 –76 –70 –83 –76 +10 –55 +45 dB dB dB dB dB mV dB 25 50 95 190 25 µs µs µs µs kΩ6 0 –0.1 –0.25 –0.6 –1.4 –2.8 –4.5 –7.0 –9.5 < –12.5 dB dB dB dB dB dB dB dB dB dB –2– 5VEN = 0, Measured Differentially PGA = 0 dB PGA = 0 dB ADC1 Input Signal Level: 1.0 kHz ADC2 Input at Idle PGA = 0 dB Input Signal Level at AVDD and DVDD Pins 1.0 kHz, 100 mV p-p Sine Wave 64 kHz Output Sample Rate 32 kHz Output Sample Rate 16 kHz Output Sample Rate 8 kHz Output Sample Rate DMCLK = 16.384 MHz REV. B AD73360 Parameter Min LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IIH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage Three-State Leakage Current POWER SUPPLIES AVDD1, AVDD2 DVDD IDD8 AD73360A Typ Max Unit VDD – 0.8 0 VDD 0.8 10 10 V V µA pF VDD – 0.4 0 –10 VDD 0.4 +10 V V µA 2.7 2.7 3.3 3.3 V V Test Conditions/Comments |IOUT| ≤ 100 µA |IOUT| ≤ 100 µA See Table I NOTES 1 Operating temperature range is as follows: –40°C to +85°C. Therefore, T MIN = –40°C and T MAX = +85°C. 2 Test conditions: Input PGA set for 0 dB gain (unless otherwise noted). 3 At input to sigma-delta modulator of ADC. 4 Guaranteed by design. 5 Overall group delay will be affected by the sample rate and the external digital filtering. 6 The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 10 11)/DMCLK. 7 Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier bypassed and input gain of 0 dB. 8 Test Conditions: no load on digital inputs, analog inputs ac coupled to ground. Specifications subject to change without notice. Table I. Current Summary (AVDD = DVDD = 3.3 V) Conditions ADCs Only On REFCAP Only On REFCAP and REFOUT Only On All Sections Off All Sections Off Analog Current Digital Current Total Current (Max) SE MCLK ON Comments 12 0.75 10 0.04 26.5 1.0 1 0 YES NO REFOUT Disabled REFOUT Disabled 3.3 0.01 0.01 0.04 1.2 0.03 4.5 1.5 0.1 0 0 0 NO YES NO MCLK Active Levels Equal to 0 V and DVDD Digital Inputs Static and Equal to 0 V or DVDD The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz. REV. B –3– (AVDD = 5 V ⴞ 10%; DVDD = 5 V ⴞ 10%; DGND = AGND = 0 V, fMCLK = 16.384 MHz, SCLK = 8.192 MHz, fS = 8 kHz; TA = TMIN to TMAX, unless otherwise noted.) AD73360–SPECIFICATIONS1 f Parameter Min REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, VREFOUT Minimum Load Resistance Maximum Load Capacitance ADC SPECIFICATIONS Maximum Input Range at VIN2, 3 AD73360A Typ Max Unit Test Conditions/Comments 1.25 2.5 50 V V ppm/°C 5VEN = 0 5VEN = 1 0.1 µF Capacitor Required from REFCAP to AGND2 130 1.25 2.5 Ω V V kΩ pF 2 100 3.2875 3.17 2.2823 0 V p-p dBm V p-p dBm 5VEN = 1, Measured Differentially 0.1 –0.5 ± 0.1 dB dB dB 1.0 kHz 1.0 kHz 1.0 kHz, +3 dBm0 to –50 dBm0 0 Hz to 4 kHz; fS = 8 kHz 0 Hz to 4 kHz; fS = 64 kHz Nominal Reference Level at VIN (0 dBm0) Absolute Gain PGA = 0 dB PGA = 38 dB Gain Tracking Error Signal to (Noise + Distortion) PGA = 0 dB PGA = 38 dB Total Harmonic Distortion PGA = 0 dB PGA = 38 dB Intermodulation Distortion Idle Channel Noise Crosstalk ADC-to-ADC 76 70 dB dB –86 –80 –79 –76 –85 dB dB dB dB dB DC Offset Power Supply Rejection 20 –55 mV dB Group Delay4, 5 25 50 95 190 25 µs µs µs µs kΩ6 0 –0.1 –0.25 –0.6 –1.4 –2.8 –4.5 –7.0 –9.5 < –12.5 dB dB dB dB dB dB dB dB dB dB Input Resistance at VIN2, 4 FREQUENCY RESPONSE (ADC)7 Typical Output Frequency (Normalized to fS) 0 0.03125 0.0625 0.125 0.1875 0.25 0.3125 0.375 0.4375 > 0.5 5VEN = 0, Unloaded 5VEN = 1, Unloaded 5VEN = 1 –4– 5VEN = 1, Measured Differentially PGA = 0 dB PGA = 0 dB ADC1 Input Signal Level: 1.0 kHz, 0 dBm0 ADC2 Input at Idle PGA = 0 dB Input Signal Level at AVDD and DVDD Pins 1.0 kHz, 100 mV p-p Sine Wave 64 kHz Output Sample Rate 32 kHz Output Sample Rate 16 kHz Output Sample Rate 8 kHz Output Sample Rate DMCLK = 16.384 MHz REV. B AD73360 Parameter Min LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IIH, Input Current CIN, Input Capacitance AD73360A Typ Max VDD – 0.8 0 VDD 0.8 V V µA pF VDD 0.4 V V µA 5.5 5.5 V V –0.5 10 LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage Three-State Leakage Current VDD – 0.4 0 POWER SUPPLIES AVDD1, AVDD2 DVDD IDD8 4.5 4.5 Unit –0.3 Test Conditions/Comments |IOUT| ≤ 100 µA |IOUT| ≤ 100 µA See Table II NOTES 1 Operating temperature range is as follows: –40°C to +85°C. Therefore, T MIN = –40°C and T MAX = +85°C. 2 Test conditions: Input PGA set for 0 dB gain (unless otherwise noted). 3 At input to sigma-delta modulator of ADC. 4 Guaranteed by design. 5 Overall group delay will be affected by the sample rate and the external digital filtering. 6 The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK. 7 Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier bypassed and input gain of 0 dB. 8 Test Conditions: no load on digital inputs, analog inputs ac coupled to ground. Specifications subject to change without notice. Table II. Current Summary (AVDD = DVDD = 5.5 V) Conditions ADCs Only On REFCAP Only On REFCAP and REFOUT Only On All Sections Off All Sections Off Analog Current Digital Current Total Current (Typ) SE MCLK ON Comments 16 0.8 16 0 32 0.8 1 0 YES NO REFOUT Disabled REFOUT Disabled 3.5 0.1 0 0 1.9 0.05 3.5 2.0 0.06 0 0 0 NO YES NO MCLK Active Levels Equal to 0 V and DVDD Digital Inputs Static and Equal to 0 V or DVDD The above values are in mA and are typical values unless otherwise noted. Table III. Signal Ranges 3 V Power Supply 5VEN = 0 VREFCAP VREFOUT ADC Maximum Input Range at VIN Nominal Reference Level REV. B 5 V Power Supply 5VEN = 0 5VEN = 1 1.25 V ± 10% 1.25 V ± 10% 1.25 V 1.25 V 2.5 V 2.5 V 1.64375 V p-p 1.1413 V p-p 1.64375 V p-p 1.1413 V p-p 3.2875 V p-p 2.2823 V p-p –5– AD73360 (AVDD = 3 V ⴞ 10%; DVDD = 3 V ⴞ 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise TIMING CHARACTERISTICS noted) Parameter Clock Signals t1 t2 t3 Serial Port t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Limit at TA = –40ⴗC to +85ⴗC Unit 61 24.4 24.4 ns min ns min ns min t1 0.4 × t1 0.4 × t1 20 0 10 10 10 10 30 ns min ns min ns min ns min ns min ns max ns min ns min ns max ns max Description See Figure 1 MCLK Period MCLK Width High MCLK Width Low See Figures 3 and 4 SCLK Period SCLK Width High SCLK Width Low SDI/SDIFS Setup Before SCLK Low SDI/SDIFS Hold After SCLK Low SDOFS Delay from SCLK High SDOFS Hold After SCLK High SDO Hold After SCLK High SDO Delay from SCLK High SCLK Delay from MCLK (AVDD = 5 V ⴞ 10%; DVDD = 5 V ⴞ 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise TIMING CHARACTERISTICS noted) Parameter Clock Signals t1 t2 t3 Serial Port t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Limit at TA = –40ⴗC to +85ⴗC Unit 61 24.4 24.4 ns min ns min ns min t1 0.4 × t1 0.4 × t1 20 0 10 10 10 10 30 ns min ns min ns min ns min ns min ns max ns min ns min ns max ns max –6– Description See Figure 1 MCLK Period MCLK Width High MCLK Width Low See Figures 3 and 4 SCLK Period SCLK Width High SCLK Width Low SDI/SDIFS Setup Before SCLK Low SDI/SDIFS Hold After SCLK Low SDOFS Delay from SCLK High SDOFS Hold After SCLK High SDO Hold After SCLK High SDO Delay from SCLK High SCLK Delay from MCLK REV. B AD73360 80 t1 t2 70 60 S/(N+D) – dB 50 t3 Figure 1. MCLK Timing 40 30 20 10 100␮A 0 IOL –10 –85 TO OUTPUT PIN –75 –65 –55 –45 –35 VIN – dBm0 +2.1V CL 15pF 100␮A –25 –15 –5 5 3.17 Figure 5a. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband Bandwidth (300 Hz–3.4 kHz) IOH 80 Figure 2. Load Circuit for Timing Specifications 70 60 t2 t3 50 S/(N+D) – dB t1 MCLK t 13 40 30 20 t5 SCLK* t6 10 t4 0 * SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE). –10 –85 –75 –65 –55 –45 –35 VIN – dBm0 Figure 3. SCLK Timing –25 –15 –5 5 3.17 Figure 5b. S/(N+D) vs. VIN (ADC @ 5 V) Over Voiceband Bandwidth (300 Hz–3.4 kHz) SE (I) SCLK (O) THREESTATE t7 SDIFS (I) t8 t8 t7 SDI (I) D15 THREESDOFS (O) STATE SDO (O) THREESTATE t9 D14 D1 D15 t 10 t 11 t 12 D15 D2 D1 Figure 4. Serial Port (SPORT) REV. B D0 –7– D0 D15 D14 AD73360 ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) AVDD, DVDD to GND . . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . . –0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C SOIC, θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD73360 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN CONFIGURATIONS RW-28 VINP4 VINP3 VINN4 VINN3 VINP2 VINN2 VINP1 VINN3 27 VINP3 44 43 42 41 40 39 38 37 36 35 34 VINP1 3 26 VINN4 VINN1 4 25 VINP4 REFOUT 5 24 VINN5 REFCAP 6 23 AVDD2 7 22 AGND2 8 DGND 9 NC 28 VINN2 2 NC VINP2 1 NC VINN1 SU-44 33 NC REFOUT 1 REFCAP 2 VINP5 AVDD2 3 VINN6 AVDD2 4 AGND2 5 AD73360 29 VINN6 20 AVDD1 AGND2 6 28 VINP6 DVDD 10 19 AGND1 AGND2 7 TOP VIEW (Not to Scale) RESET 11 18 SE AGND2 8 26 AVDD1 AD73360 TOP VIEW (Not to Scale) 21 VINP6 PIN 1 IDENTIFIER 32 VINN5 31 VINP5 30 NC 27 NC SCLK 12 17 SDI DGND 9 25 AVDD1 MCLK 13 16 SDIFS DGND 10 24 AGND1 SDO 14 15 SDOFS DVDD 11 23 AGND1 –8– SE NC SDI SDIFS SDOFS NC SDO SCLK MCLK NC NC = NO CONNECT RESET 12 13 14 15 16 17 18 19 20 21 22 REV. B AD73360 PIN FUNCTION DESCRIPTION Mnemonic Function VINP1 VINN1 VINP2 VINN2 VINP3 VINN3 VINP4 VINN4 VINP5 VINN5 VINP6 VINN6 REFOUT Analog Input to the Positive Terminal of Input Channel 1. Analog Input to the Negative Terminal of Input Channel 1. Analog Input to the Positive Terminal of Input Channel 2. Analog Input to the Negative Terminal of Input Channel 2. Analog Input to the Positive Terminal of Input Channel 3. Analog Input to the Negative Terminal of Input Channel 3. Analog Input to the Positive Terminal of Input Channel 4. Analog Input to the Negative Terminal of Input Channel 4. Analog Input to the Positive Terminal of Input Channel 5. Analog Input to the Negative Terminal of Input Channel 5. Analog Input to the Positive Terminal of Input Channel 6. Analog Input to the Negative Terminal of Input Channel 6. Buffered Reference Output, which has a nominal value of 1.25 V or 2.5 V, the value being dependent on the status of Bit 5VEN (CRC:7). A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed to this pin. This pin can be overdriven by an external reference if required. Analog Power Supply Connection. Analog Ground/Substrate Connection. Digital Ground/Substrate Connection. Digital Power Supply Connection. Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital circuitry. Output Serial Clock whose rate determines the serial transfer rate to/from the AD73360. It is used to clock data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the master clock (MCLK) divided by an integer number—this integer number being the product of the external master clock rate divider and the serial clock rate divider. Master Clock Input. MCLK is driven from an external clock signal. Serial Data Output of the AD73360. Both data and control information may be output on this pin and are clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low. Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in three-state when SE is low. Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and it is valid one SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low. Serial Data Input of the AD73360. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK. SDI is ignored when SE is low. SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at their original values (before SE was brought low); however, the timing counters and other internal registers are at their reset values. Analog Ground Connection. Analog Power Supply Connection. REFCAP AVDD2 AGND2 DGND DVDD RESET SCLK MCLK SDO SDOFS SDIFS SDI SE AGND1 AVDD1 REV. B –9– AD73360 TERMINOLOGY Absolute Gain ABBREVIATIONS ADC Analog-to-Digital Converter. Absolute gain is a measure of converter gain for a known signal. Absolute gain is measured (differentially) with a 1 kHz sine wave at 0 dBm0 for each ADC. The absolute gain specification is used for gain tracking error specification. BW Bandwidth. CRx A Control Register where x is a placeholder for an alphabetic character (A–E). There are eight read/write control registers on the AD73360— designated CRA through CRE. CRx:n A bit position, where n is a placeholder for a numeric character (0–7), within a control register; where x is a placeholder for an alphabetic character (A–E). Position 7 represents the MSB and Position 0 represents the LSB. DMCLK Device (Internal) Master Clock. This is the internal master clock resulting from the external master clock (MCLK) being divided by the onchip master clock divider. FSLB Frame Sync Loop-Back—where the SDOFS of the final device in a cascade is connected to the RFS and TFS of the DSP and the SDIFS of first device in the cascade. Data input and output occur simultaneously. In the case of nonFSLB, SDOFS and SDO are connected to the Rx Port of the DSP while SDIFS and SDI are connected to the Tx Port. PGA Programmable Gain Amplifier. SC Switched Capacitor. SNR Signal-to-Noise Ratio. SPORT Serial Port. THD Total Harmonic Distortion. VBW Voice Bandwidth. Crosstalk Crosstalk is due to coupling of signals from a given channel to an adjacent channel. It is defined as the ratio of the amplitude of the coupled signal to the amplitude of the input signal. Crosstalk is expressed in dB. Gain Tracking Error Gain tracking error measures changes in converter output for different signal levels relative to an absolute signal level. The absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz for each ADC. Gain tracking error at 0 dBm0 (ADC) is 0 dB by definition. Group Delay Group Delay is defined as the derivative of radian phase with respect to radian frequency, dø(f)/df. Group delay is a measure of average delay of a system as a function of frequency. A linear system with a constant group delay has a linear phase response. The deviation of group delay from a constant indicates the degree of nonlinear phase response of the system. Idle Channel Noise Idle channel noise is defined as the total signal energy measured at the output of the device when the input is grounded (measured in the frequency range 0 Hz–4 kHz). Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For final testing, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). Power Supply Rejection Power supply rejection measures the susceptibility of a device to noise on the power supply. Power supply rejection is measured by modulating the power supply with a sine wave and measuring the noise at the output (relative to 0 dB). Sample Rate The sample rate is the rate at which each ADC updates its output register. It is set relative to the DMCLK and the programmable sample rate setting. SNR + THD Signal-to-noise ratio plus harmonic distortion is defined to be the ratio of the rms value of the measured input signal to the rms sum of all other spectral components in a given frequency range, including harmonics but excluding dc. –10– REV. B AD73360 FUNCTIONAL DESCRIPTION General Description Analog Sigma-Delta Modulator The AD73360 is a six-channel, 16-bit, analog front end. It comprises six independent encoder channels each featuring signal conditioning, programmable gain amplifier, sigma-delta A/D convertor and decimator sections. Each of these sections is described in further detail below. Encoder Channel Each encoder channel consists of a signal conditioner, a switched capacitor PGA and a sigma-delta analog-to-digital converter (ADC). An on-board digital filter, which forms part of the sigma-delta ADC, also performs critical system-level filtering. Due to the high level of oversampling, the input antialias requirements are reduced such that a simple single pole RC stage is sufficient to give adequate attenuation in the band of interest. Signal Conditioner Each analog channel has an independent signal conditioning block. This allows the analog input to be configured by the user depending on whether differential or single-ended mode is used. The AD73360 input channels employ a sigma-delta conversion technique, which provides a high resolution 16-bit output with system filtering being implemented on-chip. Sigma-delta converters employ a technique known as oversampling, where the sampling rate is many times the highest frequency of interest. In the case of the AD73360, the initial sampling rate of the sigma-delta modulator is DMCLK/8. The main effect of oversampling is that the quantization noise is spread over a very wide bandwidth, up to fS/2 = DMCLK/16 (Figure 6a). This means that the noise in the band of interest is much reduced. Another complementary feature of sigma-delta converters is the use of a technique called noise-shaping. This technique has the effect of pushing the noise from the band of interest to an out-of-band position (Figure 6b). The combination of these techniques, followed by the application of a digital filter, reduces the noise in band sufficiently to ensure good dynamic performance from the part (Figure 6c). Programmable Gain Amplifier Each encoder section’s analog front end comprises a switched capacitor PGA that also forms part of the sigma-delta modulator. The SC sampling frequency is DMCLK/8. The PGA, whose programmable gain settings are shown in Table IV, may be used to increase the signal level applied to the ADC from low output sources such as microphones, and can be used to avoid placing external amplifiers in the circuit. The input signal level to the sigma-delta modulator should not exceed the maximum input voltage permitted. BAND OF INTEREST The PGA gain is set by bits IGS0, IGS1 and IGS2 in control Registers D, E and F. IxGS1 IxGS0 Gain (dB) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 6 12 18 20 26 32 38 BAND OF INTEREST FS/2 b. DMCLK/16 DIGITAL FILTER BAND OF INTEREST ADC Each channel has its own ADC consisting of an analog sigmadelta modulator and a digital antialiasing decimation filter. The sigma-delta modulator noise-shapes the signal and produces 1-bit samples at a DMCLK/8 rate. This bitstream, representing the analog input signal, is input to the antialiasing decimation filter. The decimation filter reduces the sample rate and increases the resolution. REV. B a. NOISE-SHAPING Table IV. PGA Settings for the Encoder Channel IxGS2 FS/2 DMCLK/16 –11– FS/2 c. DMCLK/16 Figure 6. Sigma-Delta Noise Reduction AD73360 Figure 7 shows the various stages of filtering that are employed in a typical AD73360 application. In Figure 7a we see the transfer function of the external analog antialias filter. Even though it is a single RC pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (DMCLK/8) that it takes care of any signals that could be aliased by the sampling frequency. This also shows the major difference between the initial oversampling rate and the bandwidth of interest. In Figure 7b, the signal and noise-shaping responses of the sigma-delta modulator are shown. The signal response provides further rejection of any high frequency signals while the noise-shaping will push the inherent quantization noise to an out-of-band position. The detail of Figure 7c shows the response of the digital decimation filter (Sinc-cubed response) with nulls every multiple of DMCLK/256, which is the decimation filter update rate. The final detail in Figure 7d shows the application of a final antialias filter in the DSP engine. This has the advantage of being implemented according to the user’s requirements and available MIPS. The filtering in Figures 7a through 7c is implemented in the AD73360. Decimation Filter The digital filter used in the AD73360 carries out two important functions. Firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator and secondly, it decimates the high frequency bitstream to a lower rate 15-bit word. The antialiasing decimation filter is a sinc-cubed digital filter that reduces the sampling rate from DMCLK/8 to DMCLK/ 256, and increases the resolution from a single bit to 15 bits. Its Z transform is given as: [(1–Z–32)/(1–Z–1)]3. This ensures a minimal group delay of 25 µs. ADC Coding The ADC coding scheme is in twos complement format (see Figure 8). The output words are formed by the decimation filter, which grows the word length from the single-bit output of the sigma-delta modulator to a 15-bit word, which is the final output of the ADC block. In 16-bit Data Mode this value is left shifted with the LSB being set to 0. For input values equal to or greater than positive full scale, however, the output word is set at 0x7FFF, which has the LSB set to 1. In mixed Control/Data Mode, the resolution is fixed at 15 bits, with the MSB of the 16-bit transfer being used as a flag bit to indicate either control or data in the frame. VREF + (VREF ⴛ 0.32875) ANALOG INPUT VINN VREF FSINIT = DMCLK/8 FB = 4kHz a. Analog Antialias Filter Transfer Function VREF – (VREF ⴛ 0.32875) VINP SIGNAL TRANSFER FUNCTION 10...00 00...00 01...11 ADC CODE DIFFERENTIAL VREF + (VREF ⴛ 0.6575) NOISE TRANSFER FUNCTION VINN ANALOG INPUT FSINIT = DMCLK/8 FB = 4kHz b. Analog Sigma-Delta Modulator Transfer Function VINP VREF – (VREF ⴛ 0.6575) 10...00 00...00 01...11 ADC CODE SINGLE-ENDED Figure 8. ADC Transfer Function Voltage Reference FB = 4kHz FSINTER = DMCLK/256 c. Digital Decimator Transfer Function The AD73360 reference, REFCAP, is a bandgap reference that provides a low noise, temperature-compensated reference to the ADC. A buffered version of the reference is also made available on the REFOUT pin and can be used to bias other external analog circuitry. The reference has a default nominal value of 1.25 V but can be set to a nominal value of 2.5 V by setting the 5VEN bit (CRC:7) of CRC. The 5 V mode is generally only usable when VDD = 5 V. The reference output (REFOUT) can be enabled for biasing external circuitry by setting the RU bit (CRC:6) of CRC. FB = 4kHz FSFINAL = 8kHz FSINTER = DMCLK/256 d. Final Filter LPF (HPF) Transfer Function Figure 7. DC Frequency Responses –12– REV. B AD73360 Serial Port (SPORT) The AD73360s communicate with a host processor via the bidirectional synchronous serial port (SPORT) which is compatible with most modern DSPs. The SPORT is used to transmit and receive digital data and control information. Multiple AD73360s be cascaded together (up to a limit of eight) to provide additional input channels. In both transmit and receive modes, data is transferred at the serial clock (SCLK) rate with the MSB being transferred first. Due to the fact that the SPORT of each AD73360 block uses a common serial register for serial input and output, communications between an AD73360 and a host processor (DSP engine) must always be initiated by the AD73360s themselves. In this configuration the AD73360s are described as being in Master mode. This ensures that there is no collision between input data and output samples. SPORT Overview The AD73360 SPORT is a flexible, full-duplex, synchronous serial port whose protocol has been designed to allow up to eight AD73360 devices to be connected in cascade, to a single DSP via a six-wire interface. It has a very flexible architecture that can be configured by programming two of the internal control registers in each device. The AD73360 SPORT has three distinct modes of operation: Control Mode, Data Mode and Mixed Control/Data Mode. an output sample event, which is when the serial register will be overwritten with the latest ADC sample word. Once the SPORT starts to output the latest ADC word, it is safe for the DSP to write new control words to the AD73360. In certain configurations, data can be written to the device to coincide with the output sample being shifted out of the serial register—see section on interfacing devices. The serial clock rate (CRB:2–3) defines how many 16-bit words can be written to a device before the next output sample event will happen. The SPORT block diagram, shown in Figure 9, details the blocks associated with AD73360 including the eight control registers (A–H), external MCLK to internal DMCLK divider and serial clock divider. The divider rates are controlled by the setting of Control Register B. The AD73360 features a master clock divider that allows users the flexibility of dividing externally available high frequency DSP or CPU clocks to generate a lower frequency master clock internally in the AD73360 which may be more suitable for either serial transfer or sampling rate requirements. The master clock divider has five divider options (÷ 1 default condition, ÷ 2, ÷ 3, ÷ 4, ÷ 5) that are set by loading the master clock divider field in Register B with the appropriate code (see Table VI). Once the internal device master clock (DMCLK) has been set using the master clock divider, the sample rate and serial clock settings are derived from DMCLK. MCLK (EXTERNAL) NOTE: As each AD73360 has its own SPORT section, the register settings in both SPORTs must be programmed. The registers which control SPORT and sample rate operation (CRA and CRB) must be programmed with the same values, otherwise incorrect operation may occur. In Program Mode (CRA:0 = 0), the device’s internal configuration can be programmed by writing to the eight internal control registers. In this mode, control information can be written to or read from the AD73360. In Data Mode (CRA:0 = 1), any information that is sent to the device is ignored, while the encoder section (ADC) data is read from the device. In this mode, only ADC data is read from the device. Mixed mode (CRA:0 = 1 and CRA:1 = 1) allows the user to send control information and receive either control information or ADC data. This is achieved by using the MSB of the 16-bit frame as a flag bit. Mixed mode reduces the resolution to 15 bits with the MSB being used to indicate whether the information in the 16-bit frame is control information or ADC data. The SPORT features a single 16-bit serial register that is used for both input and output data transfers. As the input and output data must share the same register there are some precautions that must be observed. The primary precaution is that no information must be written to the SPORT without reference to REV. B MCLK DIVIDER DMCLK (INTERNAL) SE RESET SDIFS SDI SCLK DIVIDER SERIAL PORT (SPORT) SDOFS SERIAL REGISTER SDO 2 3 8 CONTROL REGISTER A SCLK 8 8 CONTROL REGISTER B 8 8 8 CONTROL REGISTER C CONTROL REGISTER D CONTROL REGISTER E CONTROL REGISTER F CONTROL REGISTER G CONTROL REGISTER H Figure 9. SPORT Block Diagram The SPORT can work at four different serial clock (SCLK) rates: chosen from DMCLK, DMCLK/2, DMCLK/4 or DMCLK/8, where DMCLK is the internal or device master clock resulting from the external or pin master clock being divided by the master clock divider. Care should be taken when selecting Master Clock, Serial Clock and Sample Rate divider settings to ensure that there is sufficient time to read all the data from the AD73360 before the next sample interval. –13– AD73360 SPORT Register Maps setting to ensure correct operation (this is shown in the programming examples). The other six registers; CRC through CRH are used to hold control settings for the Reference, Power Control, ADC channel and PGA sections of the device. It is not necessary that the contents of CRC through CRH on each AD73360 are similar. Control registers are written to on the negative edge of SCLK. There are eight control registers for the AD73360, each eight bits wide. Table V shows the control register map for the AD73360. The first two control registers, CRA and CRB, are reserved for controlling the SPORT. They hold settings for parameters such as bit rate, internal master clock rate and device count. If multiple AD73360s are cascaded, registers CRA and CRB on each device must be programmed with the same Table V. Control Register Map Address (Binary) Name Description Type Width Reset Setting (Hex) 000 001 010 011 100 101 110 111 CRA CRB CRC CRD CRE CRF CRG CRH Control Register A Control Register B Control Register C Control Register D Control Register E Control Register F Control Register G Control Register H R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Table VI. Control Word Description 15 14 C/D R/W 13 12 11 DEVICE ADDRESSS 10 9 8 7 REGISTER ADDRESS 6 5 4 3 2 1 0 REGISTER DATA Control Frame Description Bit 15 Control/Data Bit 14 Read/Write Bits 13–11 Device Address Bits 10–8 Bits 7–0 Register Address Register Data When set high, it signifies a control word in Program or Mixed Program/Data Modes. When set low, it signifies an invalid control word in Program Mode. When set low, it tells the device that the data field is to be written to the register selected by the register field setting provided the address field is zero. When set high, it tells the device that the selected register is to be written to the data field in the serial register and that the new control word is to be output from the device via the serial output. This 3-bit field holds the address information. Only when this field is zero is a device selected. If the address is not zero, it is decremented and the control word is passed out of the device via the serial output. This 3-bit field is used to select one of the eight control registers on the AD73360. This 8-bit field holds the data that is to be written to or read from the selected register provided the address field is zero. –14– REV. B AD73360 Table VII. Control Register A Description CONTROL REGISTER A 7 6 5 4 3 2 1 0 RESET DC2 DC1 DC0 SLB – MM DATA/PGM Bit Name Description 0 1 2 3 4 5 6 7 Operating Mode (0 = Program; 1 = Data Mode) Mixed Mode (0 = OFF; 1 = Enabled) Must Be Programmed to Zero (0) SPORT Loop-Back Mode (0 = OFF; 1 = Enabled) Device Count (Bit 0) Device Count (Bit 1) Device Count (Bit 2) Software Reset (0 = OFF; 1 = Initiates Reset) DATA/PGM MM Reserved SLB DC0 DC1 DC2 RESET Table VIII. Control Register B Description 7 CEE CONTROL REGISTER B 6 MCD2 5 MCD1 4 MCD0 3 SCD1 2 SCD0 1 DR1 Bit Name Description 0 1 2 3 4 5 6 7 Decimation Rate (Bit 0) Decimation Rate (Bit 1) Serial Clock Divider (Bit 0) Serial Clock Divider (Bit 1) Master Clock Divider (Bit 0) Master Clock Divider (Bit 1) Master Clock Divider (Bit 2) Control Echo Enable (0 = OFF; 1 = Enabled) DR0 DR1 SCD0 SCD1 MCD0 MCD1 MCD2 CEE 0 DR0 Table IX. Control Register C Description 7 5VEN CONTROL REGISTER C REV. B 6 RU 5 PUREF 4 – 3 – 2 – 1 – 0 GPU Bit Name Description 0 1 2 3 4 5 6 7 Global Power-Up Device (0 = Power Down; 1 = Power Up) Must Be Programmed to Zero (0) Must Be Programmed to Zero (0) Must Be Programmed to Zero (0) Must Be Programmed to Zero (0) REF Power (0 = Power Down; 1 = Power Up) REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT) Enable 5 V Operating Mode (0 = Disable 5 V Mode; 1 = Enable 5 V Mode) GPU Reserved Reserved Reserved Reserved PUREF RU 5VEN –15– AD73360 Table X. Control Register D Description CONTROL REGISTER D 7 6 5 4 3 2 1 0 PUI2 I2GS2 I2GS1 I2GS0 PUI1 I1GS2 I1GS1 I1GS0 1 I3GS1 0 I3GS0 1 I5GS1 0 I5GS0 Bit Name Description 0 1 2 3 4 5 6 7 ADC1:Input Gain Select (Bit 0) ADC1:Input Gain Select (Bit 1) ADC1:Input Gain Select (Bit 2) Power Control (ADC1); 1 = ON, 0 = OFF ADC2:Input Gain Select (Bit 0) ADC2:Input Gain Select (Bit 1) ADC2:Input Gain Select (Bit 2) Power Control (ADC2); 1 = ON, 0 = OFF I1GS0 I1GS1 I1GS2 PUI1 I2GS0 I2GS1 I2GS2 PUI2 Table XI. Control Register E Description 7 PUI4 CONTROL REGISTER E 6 I4GS2 5 I4GS1 4 I4GS0 3 PUI3 2 I3GS2 Bit Name Description 0 1 2 3 4 5 6 7 ADC3:Input Gain Select (Bit 0) ADC3:Input Gain Select (Bit 1) ADC3:Input Gain Select (Bit 2) Power Control (ADC3); 1 = ON, 0 = OFF ADC4:Input Gain Select (Bit 0) ADC4:Input Gain Select (Bit 1) ADC4:Input Gain Select (Bit 2) Power Control (ADC4); 1 = ON, 0 = OFF I3GS0 I3GS1 I3GS2 PUI3 I4GS0 I4GS1 I4GS2 PUI4 Table XII. Control Register F Description 7 PUI6 CONTROL REGISTER F 6 I6GS2 5 I6GS1 4 I6GS0 3 PUI5 2 I5GS2 Bit Name Description 0 1 2 3 4 5 6 7 ADC5:Input Gain Select (Bit 0) ADC5:Input Gain Select (Bit 1) ADC5:Input Gain Select (Bit 2) Power Control (ADC5); 1 = ON, 0 = OFF ADC6:Input Gain Select (Bit 0) ADC6:Input Gain Select (Bit 1) ADC6:Input Gain Select (Bit 2) Power Control (ADC6); 1 = ON, 0 = OFF I5GS0 I5GS1 I5GS2 PUI5 I6GS0 I6GS1 I6GS2 PUI6 –16– REV. B AD73360 Table XIII. Control Register G Description CONTROL REGISTER G 7 6 5 4 3 2 1 0 SEEN RMOD CH6 CH5 CH4 CH3 CH2 CH1 2 CH3 1 CH2 0 CH1 Bit Name Description 0 1 2 3 4 5 6 7 Channel 1 Select Channel 2 Select Channel 3 Select Channel 4 Select Channel 5 Select Channel 6 Select Reset Analog Modulator Enable Single-Ended Input Mode CH1 CH2 CH3 CH4 CH5 CH6 RMOD SEEN Table XIV. Control Register H Description CONTROL REGISTER H 7 INV 6 TME 5 CH6 4 CH5 3 CH4 Bit Name Description 0 1 2 3 4 5 6 7 Channel 1 Select Channel 2 Select Channel 3 Select Channel 4 Select Channel 5 Select Channel 6 Select Test Mode Enable Enable Invert Channel Mode CH1 CH2 CH3 CH4 CH5 CH6 TME INV REGISTER BIT DESCRIPTIONS Control Register A CRA:0 CRA:1 CRA:2 CRA:3 CRA:4–6 CRA:7 Data/Program Mode. This bit controls the operating mode of the AD73360. If CRA:1 is 0, then a 0 in this bit places the part in Program Mode. If CRA:1 is 0, then a 1 in this bit places the part in Data Mode. Mixed Mode. If this bit is a 0, then the operating mode is determined by CRA:0. If this bit is a 1, then the part operates in Mixed Mode. Reserved. This bit is reserved and should be programmed to 0 to ensure correct operation. SPORT Loop Back. This is a diagnostic mode. This bit should be set to 0 to ensure correct operation. Device Count Bits. These bits tell the AD73360 how many devices are used in a cascade. All devices in the cascade should be programmed to the same value ensure correct operation. See Table XVIII. Reset. Writing a 1 to this bit will initiate a software reset of the AD73360. Control Register B CRB:0–1 CRB:2–3 CRB:4–6 CRB:7 REV. B Decimation Rate. These bits are used to set the decimation of the AD73360. See Table VII. Serial Clock Divider. These bits are used to set the serial clock frequency. See Table VI. Master Clock Divider. These bits are used to set the Master Clock Divider ratio. See Table V. Control Echo Enable. Setting this bit to a 1 will cause the AD73360 to write out any control words it receives. This is used as a diagnostic mode. This bit should be set to 0 for correct operation in Mixed Mode or Data Mode. –17– AD73360 Control Register C CRC:0 CRC:6 Global Power-Up. Writing a 1 to this bit will cause all six channels of the AD73360 to power-up regardless of the status of the Power Control Bits in CRD-CRF. If less than six channels are required, this bit should be set to 0 and the Power Control Bits of the relevant channels should be set to 1. Reserved. These bits are reserved and should be programmed to 0 to ensure correct operation. Power-Up Reference. This bit controls the state of the on-chip reference. A 1 in this bit will power up the reference. A 0 in this bit will power-down the reference. Note that the reference is automatically powered up if any channel is enabled. Reference Output. When this bit is set to 1, the REFOUT pin is enabled. CRC:7 5 V Enable. When this bit is set to 1, the 5 V operating mode is enabled. CRC:1–4 CRC:5 Control Register D CRD:0–2 CRD:3 CRD:4–6 CRD:7 Input Gain Selection. These bits select the input gain for ADC1. See Table IV. Power Control for ADC1. A 1 in this bit powers up ADC1. Input Gain Selection. These bits select the input gain for ADC2. See Table IV. Power Control for ADC2. A 1 in this bit powers up ADC2. Control Register E CRE:0-2 CRE:3 CRE:4–6 CRE:7 Input Gain Selection. These bits select the input gain for ADC3. See Table IV. Power Control for ADC3. A 1 in this bit powers up ADC3. Input Gain Selection. These bits select the input gain for ADC4. See Table IV. Power Control for ADC4. A 1 in this bit powers up ADC4. Control Register F CRF:0–2 CRF:3 CRF:4–6 CRF:7 Input Gain Selection. These bits select the input gain for ADC5. See Table IV. Power Control for ADC5. A 1 in this bit powers up ADC5. Input Gain Selection. These bits select the input gain for ADC6. See Table IV. Power Control for ADC6. A 1 in this bit powers up ADC6. Control Register G CRG:0–5 Channel Select. These bits are used in association with CRG:6 and CRG:7. If the Reset Analog Modulator bit (CRG:6) is 1, then a 1 in a Channel Select bit location will reset the Analog Modulator for that channel. If the Single-Ended Enable Mode bit (CRG:7) is 1, then a 1 in a Channel Select bit location will put that channel into Single-Ended Mode. If any channel has its Channel Select bit set to 0, the channel will be set for DifferentiallyEnded Mode and will not have its analog modulator reset regardless of the state of CRG:6 and CRG:7. CRG:6 Reset Analog Modulator. Setting this bit to a 1 will reset the Analog Modulators for any channel whose Channel Select bit (CRG:0–5) is set to 1. This bit should be set to 0 for normal operation. Single-Ended Enable Mode. Setting this bit to a 1 will enable Single-Ended Mode on any channel whose Channel Select bit (CRG:0–5) is set to 1. Setting this bit to 0 will select Differentially-Ended Input Mode for all channels. CRG:7 Control Register H CRH:0–5 CRH:6 CRH:7 Invert Select. These bits are used in association with CRH:7. If the Enable Invert Channel Mode bit (CRH:7) is 1, then a 1 in a Channel Select bit location will put that channel into Inverted Mode. If any channel has its Channel Select bit set to 0, the channel will not be inverted regardless of the state CRH:7. Test Mode Enable. This bit should be set to 0 to ensure normal operation. Enable Invert Channel Mode. Setting this bit to a 1 will enable invert any channel whose Channel Select bit (CRH:0–5) is set to 1. Setting this bit to 0 will select Noninverted (Normal) Mode for all channels. –18– REV. B AD73360 Master Clock Divider Decimation Rate Divider The AD73360 features a programmable master clock divider that allows the user to reduce an externally available master clock, at pin MCLK, by one of the ratios 1, 2, 3, 4 or 5 to produce an internal master clock signal (DMCLK) that is used to calculate the sampling and serial clock rates. The master clock divider is programmable by setting CRB:4-6. Table XV shows the division ratio corresponding to the various bit settings. The default divider ratio is divide-by-one. The AD73360 features a programmable decimation rate divider that allows users flexibility in matching the AD73360’s ADC sample rates to the needs of the DSP software. The maximum sample rate available is DMCLK/256 and the other available rates are: DMCLK/512, DMCLK/1024 and DMCLK/2048. The slowest rate (DMCLK/2048) is the default sample rate. The sample rate divider is programmable by setting bits CRB:0-1. Table XVII shows the sample rate corresponding to the various bit settings. Table XV. DMCLK (Internal) Rate Divider Settings Table XVII. Decimation Rate Divider Settings MCD2 MCD1 MCD0 DMCLK Rate 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MCLK MCLK/2 MCLK/3 MCLK/4 MCLK/5 MCLK MCLK MCLK The AD73360 features a programmable serial clock divider that allows users to match the serial clock (SCLK) rate of the data to that of the DSP engine or host processor. The maximum SCLK rate available is DMCLK and the other available rates are: DMCLK/2, DMCLK/4 and DMCLK/8. The slowest rate (DMCLK/8) is the default SCLK rate. The serial clock divider is programmable by setting bits CRB:2–3. Table XVI shows the serial clock rate corresponding to the various bit settings. SCD1 SCD0 SCLK Rate 0 0 1 1 0 1 0 1 DMCLK/8 DMCLK/4 DMCLK/2 DMCLK DR0 Sample Rate 0 0 1 1 0 1 0 1 DMCLK/2048 DMCLK/1024 DMCLK/512 DMCLK/256 OPERATION General Description Serial Clock Rate Divider Table XVI. SCLK Rate Divider Settings DR1 The AD73360 inputs and outputs data in a Time Division Multiplexing (TDM) format. When data is being read from the AD73360 each channel has a fixed time slot in which its data is transmitted. If a channel is not powered up, no data is transmitted during the allocated time slot and the SDO line will be three-stated. When the AD73360 is first powered up or reset it will be set to Program Mode and will output an SDOFS. After a reset the SDOFS will be asserted once every sample period (125 µs assuming 16.384 MHz master clock). If the AD73360 is configured in Frame Sync Loop-Back Mode, one control word can be transmitted after each SDOFS pulse. Figure 10a shows the SDO and SDOFS lines after a reset. The serial data sent by SDO will not contain valid ADC data until the AD73360 is put into Data Mode or Mixed Mode. Control Registers D through F allow channels to be powered up individually. This gives greater flexibility and control over power consumption. Figure 10b shows the SDOFS and SDO of the AD73360 when all channels are powered up and Figure 10c shows SDOFS and SDO with channels 1, 3 and 5 powered up. 1/FSAMPLE SE SDOFS SDO Figure 10a. Output Timing After Reset (Program Mode) SE SDOFS SDO CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 Figure 10b. Output Timing: All Channels Powered Up (Data/Mixed Mode) SE SDOFS SDO CHANNEL 1 CHANNEL 5 CHANNEL 3 Figure 10c. Output Timing: Channels 1, 3 and 5 Powered Up (Data/Mixed Mode) REV. B –19– AD73360 Resetting the AD73360 The RESET pin resets all the control registers. All registers are reset to zero indicating that the default SCLK rate (DMCLK/8) and sample rate (DMCLK/2048) are at a minimum to ensure that slow speed DSP engines can communicate effectively. As well as resetting the control registers using the RESET pin, the device can be reset using the RESET bit (CRA:7) in Control Register A. Both hardware and software resets require four DMCLK cycles. On reset, DATA/PGM (CRA:0) is set to 0 (default condition) thus enabling Program Mode. The reset conditions ensure that the device must be programmed to the correct settings after power-up or reset. Following a reset, the SDOFS will be asserted approximately 2070 master (MCLK) cycles after RESET goes high. The data that is output following the reset and during Program Mode is random and contains no valid information until either data or mixed mode is set. Power Management The individual functional blocks of the AD73360 can be enabled separately by programming the power control register CRC. It allows certain sections to be powered down if not required, which adds to the device’s flexibility in that the user need not incur the penalty of having to provide power for a certain section if it is not necessary to their design. The power control registers provide individual control settings for the major functional blocks on each analog front end unit and also a global override that allows all sections to be powered up/down by setting/clearing the bit. Using this method the user could, for example, individually enable a certain section, such as the reference (CRC:5), and disable all others. The global power-up (CRC:0) can be used to enable all sections but if power-down is required using the global control, the reference will still be enabled; in this case, because its individual bit is set. Refer to Table XII for details of the settings of CRC. CRD–CRF can be used to control the power status of individual channels allowing multiple channels to be powered down if required. Operating Modes There are three operating modes available on the AD73360. They are Program, Data and Mixed Program/Data. The device configuration—register settings—can be changed only in Program and Mixed Program/Data Modes. In all modes, transfers of information to or from the device occur in 16-bit packets, therefore the DSP engine’s SPORT will be programmed for 16bit transfers. Program (Control) Mode In Program Mode, CRA:0 = 0, the user writes to the control registers to set up the device for desired operation—SPORT operation, cascade length, power management, input/output gain, etc. In this mode, the 16-bit information packet sent to the device by the DSP engine is interpreted as a control word whose format is shown in Table VI. In this mode, the user must address the device to be programmed using the address field of the control word. This field is read by the device and if it is zero (000 bin), the device recognizes the word as being addressed to it. If the address field is not zero, it is then decremented and the control word is passed out of the device—either to the next device in a cascade or back to the DSP engine. This 3-bit address format allows the user to uniquely address any one of up to eight devices in a cascade. If the AD73360 is used in a standalone configuration connected to a DSP, the device address corresponds to 0. If, on the other hand, the AD73360 is configured in a cascade of multiple devices, its device address corresponds with its hardwired position in the cascade. Following reset, when the SE pin is enabled, the AD73360 responds by raising the SDOFS pin to indicate that an output sample event has occurred. Control words can be written to the device to coincide with the data being sent out of the SPORT, as shown in Figure 12 (Directly Coupled), or they can lag the output words by a time interval that should not exceed the sample interval (Indirectly Coupled). Refer to the Digital Interface section for more information. After reset, output frame sync pulses will occur at a slower default sample rate, which is DMCLK/2048, until Control Register B is programmed, after which the SDOFS will be pulsed at the selected rate. This is to allow slow controller devices to establish communication with the AD73360. During Program Mode, the data output by the device is random and should not be interpreted as ADC data. Data Mode Once the device has been configured by programming the correct settings to the various control registers, the device may exit Program Mode and enter Data Mode. This is done by programming the DATA/PGM (CRA:0) bit to a 1 and MM (CRA:1) to 0. Once the device is in Data Mode, the input data is ignored. When the device is in normal Data Mode (i.e., mixed mode disabled), it must receive a hardware reset to reprogram any of the control register settings. Appendix C details the initialization and operation of an analog front end cascade in normal Data Mode. Mixed Program/Data Mode This mode allows the user to send control words to the device while receiving ADC words. This permits adaptive control of the device whereby control of the input gains can be affected by reprogramming the control registers. The standard data frame remains 16 bits, but now the MSB is used as a flag bit to indicate that the remaining 15 bits of the frame represents control information. Mixed mode is enabled by setting the MM bit (CRA:1) to 1 and the DATA/PGM bit (CRA:0) to 1. In the case where control setting changes will be required during normal operation, this mode allows the ability to load control information with the slight inconvenience of formatting the data. Note that the output samples from the ADC will also have the MSB set to zero to indicate it is a data word. A description of a single device operating in mixed mode is detailed in Appendix B, while Appendix D details the initialization and operation of an analog front end cascade operating in mixed mode. Note that it is not essential to load the control registers in Program Mode before setting mixed mode active. Mixed mode may be selected with the first write by programming CRA and then transmitting other control words. –20– REV. B AD73360 INTERFACING The AD73360 can be interfaced to most modern DSP engines using conventional serial port connections and an extra enable control line. Both serial input and output data use an accompanying frame synchronization signal which is active high one clock cycle before the start of the 16-bit word or during the last bit of the previous word if transmission is continuous. The serial clock (SCLK) is an output from the AD73360 and is used to define the serial transfer rate to the DSP’s Tx and Rx ports. Two primary configurations can be used: the first is shown in Figure 11 where the DSP’s Tx data, Tx frame sync, Rx data and Rx frame sync are connected to the AD73360’s SDI, SDIFS, SDO and SDOFS respectively. This configuration, referred to as indirectly coupled or nonframe sync loop-back, has the effect of decoupling the transmission of input data from the receipt of output data. When programming the DSP serial port for this configuration, it is necessary to set the Rx frame sync as an input to the DSP and the Tx frame sync as an output generated by the DSP. This configuration is most useful when operating in mixed mode, as the DSP has the ability to decide how many words can be sent to the AD73360(s). This means that full control can be implemented over the device configuration in a given sample interval. The second configuration (shown in Figure 12) has the DSP’s Tx data and Rx data connected to the AD73360’s SDI and SDO, respectively, while the DSP’s Tx and Rx frame syncs are connected to the AD73360’s SDIFS and SDOFS. In this configuration, referred to as directly coupled or frame sync loop-back, the frame sync signals are connected together and the input data to the AD73360 is forced to be synchronous with the output data from the AD73360. The DSP must be programmed so that both the Tx and Rx frame syncs are inputs as the AD73360’s SDOFS will be input to both. This configuration guarantees that input and output events occur simultaneously and is the simplest configuration for operation in normal Data Mode. Note that when programming the DSP in this configuration it is advisable to preload the Tx register with the first control word to be sent before the AD73360 is taken out of reset. This ensures that this word will be transmitted to coincide with the first output word from the device(s). TFS DT ADSP-21xx DSP SDIFS SDI SCLK SCLK DR SDO RFS AD73360 SDOFS Figure 11. Indirectly Coupled or Nonframe Sync LoopBack Configuration TFS DT ADSP-21xx DSP SDIFS SDI SCLK SCLK DR SDO RFS AD73360 SDOFS Figure 12. Directly Coupled or Frame Sync LoopBack Configuration TFS DT ADSP-21xx DSP SDIFS SDI SCLK SCLK DR SDO RFS SDOFS FL0 RESET FL1 SE AD73360 ANALOG FRONT-END Figure 13. AD73360 Connected to ADSP-21xx Digital Interfacing The AD73360 is designed to easily interface to most common DSPs. The SCLK, SDO, SDOFS, SDI and SDIFS must be connected to the SCLK, DR, RFS, DT and TFS pins of the DSP respectively. The SE pin may be controlled from a parallel output pin or flag pin such as FL0–2 on the ADSP-21xx (or XF on the TMS320C5x) or, where SPORT power-down is not required, it can be permanently strapped high using a suitable pull-up resistor. The RESET pin may be connected to the system hardware reset structure or it may also be controlled using a dedicated control line. In the event of tying it to the global system reset, it is necessary to operate the device in mixed mode, which allows a software reset, otherwise there is no convenient way of resetting the device. Figures 11 and 12 show typical connections to an ADSP-2181 while Figures 13 and 14 show typical connections to an ADSP-21xx and a TMS320C5x, respectively. REV. B –21– FSX DX CLKX TMS320C5x DSP SDIFS SDI SCLK AD73360 ANALOG FRONT-END CLKR DR SDO FSR SDOFS XF RESET SE Figure 14. AD73360 Connected to TMS320C5x AD73360 SE SCLK SDOFS SDO UNDEFINED DATA UNDEFINED DATA CONTROL WORD CONTROL WORD SDIFS SDI Figure 15a. Interface Signal Timing for Program Mode Operation (Writing to a Register) SE SCLK SDOFS SDO UNDEFINED DATA READ RESULT REGISTER READ INSTRUCTION 0x7FFF OR CONTROL WORD SDIFS SDI Figure 15b. Interface Signal Timing for Program Mode Operation (Reading a Register) SE SCLK SDOFS SDO CHANNEL 1 ADC SAMPLE WORD CHANNEL 6 ADC SAMPLE WORD CONTROL WORD CONTROL WORD SDIFS SDI Figure 16a. Interface Signal Timing for Mixed Mode Operation SE SCLK SDOFS SDO CHANNEL 1 ADC SAMPLE WORD CHANNEL 6 ADC SAMPLE WORD DON'T CARE DON'T CARE SDIFS SDI Figure 16b. Interface Signal Timing for Data Mode Operation –22– REV. B AD73360 Cascade Operation The AD73360 has been designed to support up to eight devices in a cascade connected to a single serial port (see Figure 17). The SPORT interface protocol has been designed so that device addressing is built into the packet of information sent to the device. This allows the cascade to be formed with no extra hardware overhead for control signals or addressing. A cascade can be formed in either of the two modes previously discussed. SDIFS TFS MCLK DT ADSP-2181 DSP SDI SCLK DR RFS FL0 SCLK AD73360 SDO DEVICE 1 SE RESET SDOFS FL1 SDIFS MCLK SDI AD73360 SCLK SDO When multiple devices are connected in cascade there are also restrictions concerning which ADC channels can be powered up. In all cases the cascaded devices must all have the same channels powered up (i.e., for a cascade of two devices requiring Channels 1 and 2 on Device 1 and Channel 5 on Device 2, Channels 1, 2 and 5 must be powered up on both devices to ensure correct operation). Figure 18 shows the timing sequence for two devices in cascade. SE DEVICE 2 RESET SDOFS Q0 D0 D1 74HC74 In Cascade Mode, each device must know the number of devices in the cascade to be able to output data at the correct time. Control Register A contains a 3-bit field (DC0–2) that is programmed by the DSP during the programming phase. The default condition is that the field contains 000b, which is equivalent to a single device in cascade (see Table XVIII). However, for cascade operation this field must contain a binary value that is one less than the number of devices in the cascade. With a number of AD73360s in cascade each device takes a turn to send an ADC result to the DSP. For example, in a cascade of two devices the data will be output as Device 2-Channel 1, Device 1-Channel 1, Device 2-Channel 2, Device 1-Channel 2 etc. When the first device in the cascade has transmitted its channel data there is an additional SCLK period during which the last device asserts its SDOFS as it begins its transmission of the next channel. This will not cause a problem for most DSPs as they count clock edges after a frame sync and hence the extra bit will be ignored. Q1 CLK Table XVIII. Device Count Settings Figure 17. Connection of Two AD73360s Cascaded to ADSP-2181 There may be some restrictions in cascade operation due to the number of devices configured in the cascade and the serial clock rate chosen. The formula below gives an indication of whether the combination of sample rate, serial clock and number of devices can be successfully cascaded. This assumes a directly coupled frame sync arrangement as shown in Figure 12 and does not take any interrupt latency into account. 1 6 × [(( Device Count − 1) × 16) + 17] ≥ fS SCLK When using the indirectly coupled frame sync configuration in cascaded operation it is necessary to be aware of the restrictions in sending control word data to all devices in the cascade. The user should ensure that there is sufficient time for all the control words to be sent between reading the last ADC sample and the start of the next sample period. 1 2 3 4 5 DC2 DC1 DC0 Cascade Length 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7 8 Connection of a cascade of devices to a DSP, as shown in Figure 17, is no more complicated than connecting a single device. Instead of connecting the SDO and SDOFS to the DSP’s Rx port, these are now daisy-chained to the SDI and SDIFS of the next device in the cascade. The SDO and SDOFS of the final device in the cascade are connected to the DSP’s Rx port to complete the cascade. SE and RESET on all devices are fed from the signals that were synchronized with the MCLK using the circuit of Figure 19. The SCLK from only one device need be connected to the DSP’s SCLK input(s) as all devices will be running at the same SCLK frequency and phase. 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 DEVICE 2 - CHANNEL 1 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 DEVICE 1 - CHANNEL 1 Figure 18. Cascade Timing for a Two-Device Cascade REV. B –23– 6 7 8 DEVICE 2 - CHANNEL 2 AD73360 DSP CONTROL TO SE D Q The sampling rate can be varied by programming the Decimation Rate Divider settings in CRB. For a DMCLK of 16.384 MHz sample rates of 64 kHz, 32 kHz, 16 kHz and 8 kHz are available. Figure 21 shows the final spectral response of a signal sampled at 8 kHz using the maximum oversampling rate. SE SIGNAL SYNCHRONIZED TO MCLK 1/2 74HC74 MCLK CLK 0 DSP CONTROL TO RESET D Q RESET SIGNAL SYNCHRONIZED TO MCLK SNR = 80dBs (DC TO 4kHz) –20 1/2 74HC74 –40 CLK MCLK dBs –60 Figure 19. SE and RESET Sync Circuit for Cascaded Operation –80 –100 PERFORMANCE As the AD73360 is designed to provide high performance, low cost conversion, it is important to understand the means by which this high performance can be achieved in a typical application. This section will, by means of spectral graphs, outline the typical performance of the device and highlight some of the options available to users in achieving their desired sample rate, either directly in the device or by doing some post-processing in the DSP, while also showing the advantages and disadvantages of the different approaches. Encoder Section The encoder section samples at DMCLK/256, which gives a 64 kHz output rate for DMCLK equal to 16.384 MHz. The noise-shaping of the sigma-delta modulator also depends on the frequency at which it is clocked, which means that the best dynamic performance in a particular bandwidth is achieved by oversampling at the highest possible rate. If we assume that the signals of interest are in the voice bandwidth of dc–4 kHz, then sampling at 64 kHz gives a spectral response which ensures good SNR performance in the voice bandwidth, as shown in Figure 20. –120 –140 0 4 Figure 21. FFT (ADC 8 kHz Internally Decimated from 64 kHz) It is possible to generate lower sample rates through reducing the oversampling ratio by programming the DMCLK Rate Divider Settings in CRB (MCD2-MCD1) This will have the effect of spreading the quantization noise over a lesser bandwidth resulting in a degradation of dynamic performance. Figure 22 shows a FFT plot of a signal sampled at 8 kHz rate produced by reducing the DMCLK Rate. 0 SNR = 72.2dBs (DC TO fS/2) –20 –40 –60 dBs 0 SNR = 59.0dB (DC TO fS/2) SNR = 80.8dB (DC TO 4kHz) –20 –80 –100 –60 –120 –80 –140 0 dBs –40 –100 2 FREQUENCY – kHz 4 Figure 22. FFT (ADC 8 kHz Sampling with Reduced DMCLK Rate) –120 –140 0 2 FREQUENCY – kHz 8 16 FREQUENCY – kHz 24 32 Figure 20. FFT (ADC 64 kHz Sampling) –24– REV. B AD73360 Figure 23 shows a comparison of SNR results achieved by varying either the Decimation Rate Setting or the DMCLK Rate Settings. 81 DMCLK = MCLK 80 79 SNR – dBs 78 The AD73360’s on-chip 38 dB preamplifier can be enabled when there is not enough gain in the input circuit; the preamplifier is configured by bits IGS0–2 of CRD. The total gain must be configured to ensure that a full-scale input signal produces a signal level at the input to the sigma-delta modulator of the ADC that does not exceed the maximum input range. 77 76 REDUCED DMCLK 75 74 73 The dc biasing of the analog input signal is accomplished with an on-chip voltage reference. If the input signal is not biased at the internal reference level (via REFOUT), then it must be ac-coupled with external coupling capacitors. CIN should be 0.1 µF or larger. The dc biasing of the input can then be accomplished using resistors to REFOUT as in Figure 25. 72 71 8 16 24 32 40 48 SAMPLING FREQUENCY – kHz point at 34 kHz; these are the only filters that must be implemented external to the AD73360 to prevent aliasing of the sampled signal. Since the ADC uses a highly oversampled approach that transfers the bulk of the antialiasing filtering into the digital domain, the off-chip antialiasing filter need only be of a low order. It is recommended that for optimum performance the capacitors used for the antialiasing filter be of high quality dielectric (NPO). 56 64 Figure 23. Comparison of DMCLK and Decimation Rate Settings Encoder Group Delay CIN The AD73360 implementation offers a very low level of group delay, which is given by the following relationship: VIN Group Delay (Decimator) = Order × ((M–1)/2) × Tdec CIN 100⍀ VINPx 10k⍀ 100⍀ VINNx 10k⍀ 0.047␮F where: 0.047␮F TO INPUT BIAS CIRCUITRY Order is the order of the decimator (= 3), M is the decimation factor (= 32) and REFOUT 0.1␮F REFCAP VOLTAGE REFERENCE Tdec is the decimation sample interval (= 1/2.048e6) => Group Delay (Decimator) = 3 × (32–1)/2 × (1/2.048e6) = 22.7 µs Figure 25. Example Circuit for Differential Input (AC Coupling) If final filtering is implemented in the DSP, the final filter’s group delay must be taken into account when calculating overall group delay. Figures 26 and 27 detail ac- and dc-coupled input circuits for single-ended operation respectively. CIN 0.047␮F The AD73360 features six signal conditioning inputs. Each signal conditioning block allows the AD73360 to be used with either a single-ended or differential signal. The applied signal can also be inverted internally by the AD73360 if required. The analog input signal to the AD73360 can be dc-coupled, provided that the dc bias level of the input signal is the same as the internal reference level (REFOUT). Figure 24 shows the recommended differential input circuit for the AD73360. The circuit of Figure 24 implements first-order low-pass filters with a 3 dB VIN 100⍀ VINPx VIN DESIGN CONSIDERATIONS Analog Inputs 10k⍀ REFOUT 0.1␮F VINPx 100⍀ VINNx REFCAP VOLTAGE REFERENCE Figure 26. Example Circuit for Single-Ended Input (AC Coupling) 100⍀ VINPx 0.047␮F VINNx VIN 100⍀ VINNx REFOUT 0.047␮F TO INPUT BIAS CIRCUITRY 0.047␮F 0.1␮F REFOUT 0.1␮F REFCAP VOLTAGE REFERENCE VOLTAGE REFERENCE Figure 27. Example Circuit for Single-Ended Input (DC Coupling) Figure 24. Example Circuit for Differential Input (DC Coupling) REV. B REFCAP –25– AD73360 Digital Interface As there are a number of variations of sample rate and clock speeds that can be used with the AD73360 in a particular application, it is important to select the best combination to achieve the desired performance. High speed serial clocks will read the data from the AD73360 in a shorter time, giving more time for processing by at the expense of injecting some digital noise into the circuit. Digital noise can also be reduced by connecting resistors (typ