4-Channel, 4 MSPS, 16-Bit/14-Bit/12-Bit,
Dual, Simultaneous Sampling SAR ADCs
AD7386/AD7387/AD7388
Data Sheet
FEATURES
GENERAL DESCRIPTION
16-bit, 14-bit, or 12-bit dual simultaneous sampling SAR ADC
Single-ended analog inputs
4-channel with 2:1 multiplexers
Channel sequencer mode
High throughput rate of up to 4 MSPS
SNR (typical)
87.5 dB (AD7386), VREF = 3.3 V external
84 dB (AD7387), VREF = 3.3 V external
73.8 dB (AD7388)
93 dB with OSR = 8, VREF = 2.5 V internal (AD7386)
On-chip oversampling functions
INL (typical)
±1.5 LSB (AD7386)
±0.5 LSB (AD7387)
±0.2 LSB (AD7388)
Resolution boost function
2.5 V internal reference at 10 ppm/°C (maximum)
Alert function
−40°C to +125°C temperature range
16-lead, 3 mm × 3 mm LFCSP
The AD7386/AD7387/AD7388 are 16-bit, 14-bit, and 12-bit dual,
simultaneous sampling, high speed, successive approximation
register (SAR), analog-to-digital converters (ADCs) that operate
from a 3.0 V to 3.6 V power supply and feature throughput rates
of up to 4 MSPS. The analog input types are single-ended and
are sampled and converted on the falling edge of CS.
The AD7386/AD7387/AD7388 have an on-chip sequencer and
integrated on-chip oversampling block to improve dynamic
range and reduce noise at lower bandwidths. A buffered internal
2.5 V reference is included. Alternatively, an external reference up
to 3.3 V can be used. The conversion process and data
acquisition use standard control inputs, allowing interfacing to
microprocessors or digital signal processors (DSPs). The AD7386
is compatible with 1.8 V, 2.5 V, and 3.3 V interfaces by using the
separate logic supply.
The AD7386/AD7387/AD7388 are available in a 16-lead LFCSP
with operation specified from −40°C to +125°C.
PRODUCT HIGHLIGHTS
APPLICATIONS
1.
2.
3.
4.
5.
Motor control position feedback
Motor control current sense
Sonars
Power quality
Data acquisition systems
Erbium doped fiber amplifier (EDFA) applications
Inphase and quadrature demodulation
6.
7.
4-channel, dual simultaneous sampling ADC.
Pin-compatible product family.
High 4 MSPS throughput rate.
Space-saving, 3 mm × 3 mm LFCSP.
Integrated oversampling block to increase dynamic range
and SNR and to reduce SCLK speed requirements.
Single-ended analog inputs.
Small sampling capacitor reduces amplifier drive burden.
FUNCTIONAL BLOCK DIAGRAM
3.3V
3.3V
1µF
1µF
VCC
VLOGIC
VREF
R
C
VREF
AINA0
AINA1
R
C
0V
MUX
0V
OVERSAMPLING
ADC A
SDOA
REFIO
REFCAP
GND
REGCAP
OSCILLATOR
REFERENCE
CONTROL
LOGIC
LDO
VREF
C
0V
AINB0
AINB1
R
VREF
C
DIGITAL
CONTROLLER
ADC B
OVERSAMPLING
SDOB/ALERT
AD7386/AD7387/AD7388
GND
20799-001
R
MUX
0V
SCLK
SDI
CS
Figure 1.
Rev. A
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©2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD7386/AD7387/AD7388
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Modes of Operation ....................................................................... 20
Applications ....................................................................................... 1
Channel Selection....................................................................... 20
General Description ......................................................................... 1
Sequencer .................................................................................... 20
Product Highlights ........................................................................... 1
Oversampling .............................................................................. 21
Functional Block Diagram .............................................................. 1
Resolution Boost ........................................................................ 25
Revision History ............................................................................... 3
Alert ............................................................................................. 25
Specifications..................................................................................... 4
Power Modes ............................................................................... 26
AD7386 .......................................................................................... 4
Internal and External References ............................................. 26
AD7387 .......................................................................................... 5
Software Reset ............................................................................. 26
AD7388 .......................................................................................... 6
Diagnostic Self Test .................................................................... 26
All Devices ..................................................................................... 7
Interface ........................................................................................... 27
Timing Specifications .................................................................. 9
Reading Conversion Results ..................................................... 27
Absolute Maximum Ratings.......................................................... 11
Low Latency Readback .............................................................. 28
Thermal Resistance .................................................................... 11
Reading From Device Registers ............................................... 29
ESD Caution ................................................................................ 11
Writing to Device Registers ...................................................... 29
Pin Configuration and Function Descriptions ........................... 12
Registers ........................................................................................... 32
Typical Performance Characteristics ........................................... 13
Addressing Registers .................................................................. 32
Terminology .................................................................................... 16
CONFIGURATION1 Register ................................................. 33
Theory of Operation ...................................................................... 17
CONFIGURATION2 Register ................................................. 34
Circuit Information .................................................................... 17
Alert Register .............................................................................. 35
Converter Operation .................................................................. 17
ALERT_LOW_THRESHOLD Register .................................. 36
Analog Input Structure .............................................................. 17
ALERT_HIGH_THRESHOLD Register ................................. 36
ADC Transfer Function ............................................................. 18
Outline Dimensions ....................................................................... 37
Applications Information .............................................................. 19
Ordering Guide .......................................................................... 37
Power Supply ............................................................................... 19
Rev. A | Page 2 of 37
Data Sheet
AD7386/AD7387/AD7388
REVISION HISTORY
10/2019—Rev. 0 to Rev. A
Added AD7387 and AD7388............................................. Universal
Changes to Features Section, General Description Section, and
Figure 1 ............................................................................................... 1
Changes to Table 1 ........................................................................................4
Added Table 2; Renumbered Sequentially ..............................................5
Added Table 3 ................................................................................................6
Added Table 4 ................................................................................................7
Changes to Table 5 ........................................................................................8
Changes to Figure 8 Through Figure 10............................................... 13
Changes to Figure 11 Caption and Figure 12 Caption...................... 13
Changes to Figure 14 Caption and Figure 15 Caption ..................... 14
Changes to Figure 17, Figure 18, and Figure 19 ................................. 14
Changes to Figure 20 Caption Through Figure 22 Caption ............ 15
Deleted Figure 25; Renumbered Sequentially..................................... 15
Changes to Figure 23 and Figure 24 ...................................................... 15
Added Figure 25; Renumbered Sequentially ...................................... 15
Changes to Terminology Section ........................................................... 16
Changes to Circuit Information Section .............................................. 17
Changes to ADC Transfer Function, Table 9, and Figure 30 ...........18
Changes to Power Supply Section and Table 10 ..................................19
Changes to Normal Averaging Oversampling Section and
Table 11 ............................................................................................. 21
Added Table 12 ................................................................................ 21
Changes to Rolling Average Oversampling Section and Table 13
........................................................................................................... 23
Added Table 14 ................................................................................ 23
Added Oversampling in Sequencer Mode Section, Figure 35, and
Figure 36 .......................................................................................................24
Changes to Resolution Boost Section ....................................................25
Added Figure 39..........................................................................................26
Changes to Reading Conversion Results Section, Figure 41, and
Table 15 .........................................................................................................27
Changes to Resolution Boost Mode Section........................................28
Changes to Ordering Guide .....................................................................37
8/2019—Revision 0: Initial Version
Rev. A | Page 3 of 37
AD7386/AD7387/AD7388
Data Sheet
SPECIFICATIONS
AD7386
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, reference voltage (VREF) = 2.5 V internal, sampling frequency (fSAMPLE) = 4 MSPS, and
TA = −40°C to +125°C, no oversampling enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
THROUGHPUT
Conversion Rate
Single Channel Pair
Alternating Channels
DC ACCURACY
No Missing Codes
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Gain Error
Gain Error Temperature Drift
Gain Error Match
Offset Error
Offset Error Temperature Drift
Offset Error Match
AC ACCURACY
Dynamic Range
Oversampled Dynamic Range
Signal-to-Noise Ratio (SNR)
Test Conditions/Comments
Min
16
SEQ = 1
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
VREF = 3.3 V external
Signal-to-Noise-and-Distortion (SINAD)
fIN = 100 kHz
VREF = 3.3 V
Unit
Bits
4
2
MSPS
MSPS
±0.5
±1.5
±0.006
±1
+1.0
+3.5
+0.025
+3
−0.025
−0.6
−3
−0.5
±0.006
±0.1
±1
0.12
+0.025
+0.6
+3
+0.5
Input frequency (fIN) = 1 kHz
VREF = 3.3 V external
Normal averaging, OSR = 4, RES = 1
VREF = 3.3 V external
Max
16
−1.0
−3.5
−0.025
−3
85.5
83.5
Rolling averaging, OSR = 8, RES = 1
fIN = 100 kHz
Channel to Channel Isolation
Channel to Channel Memory
POWER SUPPLIES
VCC Current (IVCC)
VLOGIC Current (IVLOGIC)
Power Dissipation
Total Power (PTOTAL)
VCC Power (PVCC)
Typ
85
83
87.8
86
91.5
87.5
85.5
93
85.3
−100
−99
−98
−96
87.4
85.5
−109.7
−93.5
Bits
LSB
LSB
%FS
ppm/°
C
%FS
mV
µV/°C
mV
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Normal mode (operational)
1 kHz sine wave
Rev. A | Page 4 of 37
22
3.15
26
3.5
mA
mA
83
73
107
94
mW
mW
Data Sheet
AD7386/AD7387/AD7388
AD7387
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V internal, fSAMPLE = 4 MSPS, and TA = −40°C to +125°C, no oversampling enabled,
unless otherwise noted.
Table 2.
Parameter
RESOLUTION
THROUGHPUT
Conversion Rate
Single Channel Pair
Alternating Channels
DC ACCURACY
No Missing Codes
DNL
INL
Gain Error
Gain Error Temperature Drift
Gain Error Match
Offset Error
Offset Error Temperature Drift
Offset Error Match
AC ACCURACY
Dynamic Range
Oversampled Dynamic Range
SNR
Test Conditions/Comments
Min
14
SEQ = 1
TMIN to TMAX
fIN = 1 kHz
VREF = 3.3 V external
Normal averaging, OSR = 4, RES = 1
VREF = 3.3 V external
14
−1.0
−1.0
−0.026
−5
−0.026
−3.5
−5
−3.5
83
81.5
Rolling averaging, OSR = 8, RES = 1
fIN = 100 kHz
SFDR
THD
VREF = 3.3 V
SINAD
fIN = 100 kHz
VREF = 3.3 V
Channel to Channel Isolation
Channel to Channel Memory
POWER SUPPLIES
IVCC
IVLOGIC
Power Dissipation
PTOTAL
PVCC
Typ
82.5
81
±0.4
±0.5
±0.003
±1
±0.006
±1
±1
±1
Max
Unit
Bits
4
2
MSPS
MSPS
+1.0
+1.0
+0.026
+5
+0.026
+3.5
+5
+3.5
Bits
LSB
LSB
%FS
ppm/°C
%FS
LSB
µV/°C
LSB
84
83.1
88.7
84
83
90.5
82.7
−100
−99
−98
−96.1
83.5
82.5
−111.5
−93.2
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Normal mode (operational)
1 kHz sine wave
Rev. A | Page 5 of 37
22
2.4
26
3
mA
mA
81
73
105
94
mW
mW
AD7386/AD7387/AD7388
Data Sheet
AD7388
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V internal, fSAMPLE = 4 MSPS, and TA = −40°C to +125°C, no oversampling enabled,
unless otherwise noted.
Table 3.
Parameter
RESOLUTION
THROUGHPUT
Conversion Rate
Single Channel Pair
Alternating Channels
DC ACCURACY
No Missing Codes
DNL
INL
Gain Error
Gain Error Temperature Drift
Gain Error Match
Offset Error
Offset Error Temperature Drift
Offset Error Match
AC ACCURACY
Dynamic Range
Oversampled Dynamic Range
SNR
Test Conditions/Comments
Min
12
SEQ = 1
12
−0.5
−0.5
−0.04
−5
−0.05
−1.5
−5
−1.5
Normal averaging, OSR = 4, RES = 1
73.5
VREF = 3.3 V
fIN = 100 kHz
SINAD
Channel to Channel Isolation
Channel to Channel Memory
POWER SUPPLIES
IVCC
IVLOGIC
Power Dissipation
PTOTAL
PVCC
±0.25
±0.2
±0.01
±1
±0.01
±0.75
±1
±0.75
Max
Unit
Bits
4
2
MSPS
MSPS
+0.5
+0.5
+0.04
+5
+0.05
+1.5
+5
+1.5
Bits
LSB
LSB
% FS
ppm/°C
% FS
LSB
µV/°C
LSB
fIN = 1 kHz
Rolling averaging, OSR = 8, RES = 1
fIN = 100 kHz
SFDR
THD
Typ
73.5
74
76.6
73.8
80.5
73.7
−100
−99
−98
−96.1
73.8
−111.6
−93.3
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Normal mode (operational)
1 kHz sine wave
Rev. A | Page 6 of 37
22
2.2
26
2.7
mA
mA
80
73
104
94
mW
mW
Data Sheet
AD7386/AD7387/AD7388
ALL DEVICES
Table 4.
Parameter
ANALOG INPUT
Voltage Input Range
DC Leakage Current
Input Capacitance
SAMPLING DYNAMICS
Input Bandwidth
Aperture Delay
Aperture Delay Match
Aperture Jitter
REFERENCE INPUT AND OUTPUT
VREF Input
Voltage Range
Current
VREF Output Voltage
Test Conditions/Comments
Min
0
0.1
18
5
When in track mode
When in hold mode
At −0.1 dB
At −3 dB
5.3
22
2
300
20
Max
Unit
VREF
1
V
µA
pF
pF
450
MHz
MHz
ns
ps
ps
External reference
2.49
At 25°C
−40°C to +125°C
2.498
2.496
VREF Temperature Coefficient
VREF Regulation
Line
Load
VREF Noise
DIGITAL INPUTS (SCLK, SDI, CS)
0.47
2.5
2.5
1
3.4
0.51
2.502
2.505
10
−38
−106
7
Logic Levels
Input Voltage
Low (VIL)
High (VIH)
Input Current
Low (IIL)
High (IIH)
DIGITAL OUTPUTS (SDOA, SDOB/ALERT)
Output Voltage
Low (VOL)
High (VOH)
Typ
ppm/V
ppm/mA
µV rms
0.2 × VLOGIC
V
V
+1
+1
µA
µA
0.4
V
V
±1
µA
0.8 × VLOGIC
−1
−1
Sink current (ISINK) = 300 µA
Source current (ISOURCE) = −300 µA
V
mA
V
V
ppm/°C
VLOGIC − 0.3
Floating State
Leakage Current
Output Capacitance
10
Rev. A | Page 7 of 37
pF
AD7386/AD7387/AD7388
Parameter
POWER SUPPLIES
VCC
Data Sheet
Test Conditions/Comments
Min
Typ
Max
Unit
External reference = 3.3 V
3.0
3.15
1.65
3.3
3.3
3.6
3.6
3.6
V
V
V
2.2
100
3
200
mA
µA
10
10
200
200
nA
nA
7.3
330
10
720
mW
μW
33
33
720
720
nW
nW
VLOGIC
IVCC
Normal Mode (Static)
Shutdown Mode
IVLOGIC
Normal Mode (Static)
Shutdown Mode
Power Dissipation
PVCC
Normal Mode (Static)
Shutdown Mode
VLOGIC Power (PVLOGIC)
Normal Mode (Static)
Shutdown Mode
Rev. A | Page 8 of 37
Data Sheet
AD7386/AD7387/AD7388
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V internal, and TA = −40°C to +125°C, unless otherwise noted. All specifications
include a 10 pF load.
Table 5.
Parameter
tCYC
Min
Typ
Max
tSCLKED
250
500
0.8
ns
ns
ns
Description
Time between conversions
4 MSPS
Alternating conversion channels
CS falling edge to first SCLK falling edge
tSCLK
tSCLKH
tSCLKL
tCSH
12.5
5
5
10
ns
ns
ns
ns
SCLK period
SCLK high time
SCLK low time
CS pulse width
tQUIET
tSDOEN
10
ns
Interface quiet time prior to conversion
CS low to SDOA and SDOB/ALERT enabled
ns
ns
ns
VLOGIC ≥ 2.25 V
1.65 V ≤ VLOGIC < 2.3 V
SCLK rising edge to SDOA and SDOB/ALERT hold time
6
8
tSDOH
2
Unit
tSDOS
SCLK rising edge to SDOA and SDOB/ALERT setup time
6
8
8
tSDOT
tSDIS
tSDIH
tSCLKCS
1
1
0
tCONVERT
tRESET
190
250
800
tACQUIRE
tPOWERUP
tCONVERT0
tCONVERTx
tALERTS
4
7
VLOGIC ≥ 2.25 V
1.65 V ≤ VLOGIC < 2.3 V
CS rising edge to SDOA and SDOB/ALERT high impedance
ns
ns
ns
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
SCLK rising edge to CS rising edge
ns
ns
ns
ns
Conversion time
Valid time to start conversion after software reset (see Figure 39)
Valid time to start conversion after soft reset
Valid time to start conversion after hard reset
Acquire time
Supply active to conversion
First conversion allowed
Settled to within 1% with internal reference
Settled to within 1% with external reference
Supply active to register read write access allowed
Exiting power-down mode to conversion (see Figure 40)
Settled to within 1% with internal reference
Settled to within 1% with external reference
Conversion start time for first sample in normal averaging mode, not shown in Figure 6
Conversion time for xth sample in normal averaging mode
For the AD7386, at 3 MSPS
For the AD7387 and the AD7388, at 4 MSPS
Time from CS to ALERT indication (see Figure 38)
ns
ns
ns
110
tREGWRITE
tSTARTUP
ns
ns
ns
5
11
5
5
ms
ms
ms
ms
11
10
10
ms
µs
ns
tCONVERT0 + (320 × (x − 1))
tCONVERT0 + (250 × (x − 1))
200
tALERTC
12
ns
Time from CS to ALERT clear (see Figure 38)
tALERTS_NOS
12
ns
Time from internal conversion with exceeded threshold to ALERT indication (see Figure 38)
Rev. A | Page 9 of 37
AD7386/AD7387/AD7388
Data Sheet
Timing Diagrams
tCYC
tCSH
tSCLKL
tSCLKH
tSCLKED
tQUIET
tSCLK
tSCLKCS
CS
SDOA
SDOB/ALERT
TRISTATE
TRISTATE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB5
DB6
tSDOH
DB3
DB4
tSDOS
DB2
DB1
DB0
tSDOEN
SDI
DB15
DB13
DB14
DB12
DB11
DB10
DB9
DB7
DB8
DB6
DB3
DB4
DB5
TRISTATE
TRISTATE
tSDOT
DB2
DB1
20799-002
SCLK
DB0
tSDIH
tSDIS
Figure 2. Serial Interface Timing Diagram
tCONVERT
CS
CONVERSION
ACQUIRE
20799-003
CONVERSION
ACQUIRE
tACQUIRE
Figure 3. Internal Conversion Acquire Timing
tPOWERUP
20799-004
VCC
CS
Figure 4. Power-Up Time to Conversion
tREGWRITE
VCC
SDI
REG WRITE
20799-005
CS
Figure 5. Power-Up Time to Register Read Write Access
CS
INTERNAL
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
tCONVERT2
tCONVERT3
tCONVERT4
1t
20799-007
tCONVERTx 1
CONVERTx STANDS FOR tCONVERT2 , tCONVERT3 , OR tCONVERT4 .
Figure 6. Conversion Timing During Normal Averaging Oversampling Mode
Rev. A | Page 10 of 37
Data Sheet
AD7386/AD7387/AD7388
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
Parameter
VCC to GND
VLOGIC to GND
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
REFIO Input to GND
Input Current to Any Pin Except
Supplies
Temperature
Operating Range
Storage Range
Junction
Pb-Free Soldering Reflow
Electrostatic Discharge (ESD)
Ratings
Human Body Model (HBM)
Field Induced Charge Device
Model (FICDM)
Rating
−0.3 V to +4 V
−0.3 V to +4 V
−0.3 V to VREF + 0.3 V,
VCC + 0.3 V or 4 V
−0.3 V to VLOGIC + 0.3 V or 4 V
−0.3 V to VLOGIC + 0.3 V or 4 V
−0.3 V to VCC + 0.3 V or 4 V
±10 mA
Thermal performance is directly linked to printed circuit
board (PCB) design and operating environment. Careful
attention to PCB thermal design is required.
θJA is the natural convection junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure. θJC is the junction
to case thermal resistance.
Table 7. Thermal Resistance
Package Type
CP-16-451
1
−40°C to +125°C
−65°C to +150°C
150°C
260°C
θJA
55.4
θJC
12.7
Unit
°C/W
Test Condition 1: thermal impedance simulated values are based on
JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESDS1.
ESD CAUTION
4 kV
1.25 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 11 of 37
AD7386/AD7387/AD7388
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13 SDOA
14 SDOB/ALERT
16 SCLK
15 SDI
AD7386/AD7387/AD7388
GND 1
REGCAP 3
12 CS
TOP VIEW
(Not to Scale)
11 REFIO
10 GND
9
REFCAP
AINA0 8
AINA1 7
AINB0 6
AINB1 5
VCC 4
NOTES
1. EXPOSED PAD. FOR CORRECT OPERATION OF THE DEVICE,
THE EXPOSED PAD MUST BE CONNECTED TO GND.
20799-009
VLOGIC 2
Figure 7. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1, 10
2
3
Mnemonic
GND
VLOGIC
REGCAP
4
5, 6
7, 8
9
VCC
AINB1, AINB0
AINA1, AINA0
REFCAP
11
REFIO
12
CS
13
SDOA
14
SDOB/ALERT
15
16
Not Applicable
SDI
SCLK
EPAD
Description
Ground Reference Point. These pins are the ground reference points for all circuitry on the device.
Logic Interface Supply Voltage, 1.65 V to 3.6 V. Decouple this pin to GND with a 1 µF capacitor.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this pin to GND with a
1 µF capacitor. The voltage at this pin is 1.9 V typical.
Power Supply Input Voltage, 3.0 V to 3.6 V. Decouple this pin to GND using a 1 µF capacitor.
Analog Inputs of ADC B.
Analog Inputs of ADC A.
Decoupling Capacitor Pin for Band Gap Reference. Decouple this pin to GND with a 0.1 µF capacitor. The
voltage at this pin is 2.5 V typical. If the device is configured for external reference operation, the 0.1 µF
capacitor is not required.
Reference Input/Output. The on-chip reference of 2.5 V is available as an output on this pin for external
use if the device is configured accordingly. Alternatively, an external reference of 2.5 V to 3.3 V can be
input to this pin. The REFSEL bit in the CONFIGURATION1 register must be set correctly when choosing
the reference voltage source. Decoupling is required on this pin for both the internal and external
reference options. A 1 μF capacitor must be applied from this pin to GND.
Chip Select Input. Active low, logic input. This input provides the dual function of initiating conversions
and framing the serial data transfer.
Serial Data Output A. This pin functions as a serial data output pin to access the ADC A or ADC B
conversion results or data from any of the on-chip registers.
Serial Data Output B (SDOB). This pin functions as a serial data output pin to access the ADC B conversion
results.
Alert Indication Output (ALERT). This pin operates as an alert pin going low to indicate that a conversion
result has exceeded a configured threshold.
Serial Data Input. This input provides the data written to the on-chip control registers.
Serial Clock Input. This serial clock input is for data transfers to and from the ADC.
Exposed Pad. For correct operation of the device, the exposed pad must to connected to GND.
Rev. A | Page 12 of 37
Data Sheet
AD7386/AD7387/AD7388
TYPICAL PERFORMANCE CHARACTERISTICS
VREF = 2.5 V internal, VCC = 3.6 V, VLOGIC = 3.3 V, fSAMPLE = 4 MSPS, fIN = 1 kHz, and TA = 25°C, unless otherwise noted.
2.0
0
SNR = 85.32dB
THD = –100.29dB
SINAD = 85.18dB
1.5
–40
1.0
–60
0.5
INL ERROR (LSB)
–80
–100
–120
0
–0.5
–1.0
–140
–1.5
–160
60000
1000
20799-013
800
50000
600
40000
400
FREQUENCY (kHz)
30000
200
20000
0
20799-010
0
–2.0
–180
10000
MAGNITUDE (dB)
–20
CODE
Figure 11. AD7386 Integral Nonlinearity (INL) Error
Figure 8. AD7386 Fast Fourier Transform (FFT), VREF = 2.5 V Internal
1.5
0
SNR = 87.14dB
THD = –99.03dB
SINAD = 86.88dB
–20
1.0
–60
DNL ERROR (LSB)
–80
–100
–120
0.5
0
–0.5
–1.0
–140
–160
CODE
Figure 12. AD7386 Differential Nonlinearity (DNL) Error
Figure 9. AD7386 FFT, VREF = 3.3 V External
35
0
SNR = 94.28dB
THD = –98.5dB
SINAD = 92.82dB
OSR = 8, ROLLING AVERAGE, RES = 1
VREF = 3.3V EXTERNAL
–40
30
DYNAMIC CURRENT (mA)
–20
–60
–80
–100
–120
IVCC
IVLOGIC
25
20
15
10
–140
–180
0
50
100
150
FREQUENCY (kHz)
200
0
0
1
2
3
THROUGHPUT RATE (MSPS)
Figure 13. Dynamic Current vs. Throughput Rate
Figure 10. AD7386 FFT with Oversampling
Rev. A | Page 13 of 37
4
20799-015
5
–160
20799-012
MAGNITUDE (dB)
60000
1000
20799-014
800
50000
600
40000
400
FREQUENCY (kHz)
30000
200
20000
0
20799-011
0
–1.5
–180
10000
MAGNITUDE (dB)
–40
AD7386/AD7387/AD7388
Data Sheet
0.5
30
IVCC , INTERNAL REFERENCE = 2.5V
IVCC , EXTERNAL REFERENCE = 3.3V
OFFSET ERROR, INTERNAL REFERENCE = 2.5V
OFFSET ERROR, EXTERNAL REFERENCE = 3.3V
SUPPLY CURRENT DYNAMIC (mA)
0.4
0.3
OFFSET ERROR (mV)
0.2
0.1
0
–0.1
–0.2
–0.3
25
20
15
10
5
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
0
–40
20799-016
–0.5
–40
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 14. AD7386 Offset Error vs. Temperature
20799-019
–0.4
Figure 17. Supply Current Dynamic vs. Temperature
15
95
GAIN ERROR, INTERNAL REFERENCE = 2.5V
GAIN ERROR, EXTERNAL REFERENCE = 3.3V
90
10
AD7386
AD7387
AD7388
85
SNR (dB)
0
80
75
–5
70
–10
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
60
–40
–25
5
20
35
50
65
80
95
110
125
95
110
125
TEMPERATURE (°C)
Figure 18. SNR vs. Temperature
Figure 15. AD7386 Gain Error vs. Temperature
500
–60
450
–70
400
AD7386
AD7387
AD7388
–80
350
–90
THD (dB)
300
250
200
–100
–110
150
–120
100
–130
50
0
–40
–25
–10
5
20
35
50
65
80
95
TEMPERATURE (°C)
110
125
20799-018
SHUTDOWN CURRENT (µA)
–10
20799-118
–25
20799-017
–15
–40
65
Figure 16. Shutdown Current vs. Temperature
Rev. A | Page 14 of 37
–140
–40
–25
–10
5
20
35
50
65
80
TEMPERATURE (°C)
Figure 19. THD vs. Temperature
20799-119
GAIN ERROR (LSB)
5
Data Sheet
AD7386/AD7387/AD7388
95
94
VREF = 3.3V
VREF = 2.5V
92
90
85
88
SNR (dB)
SINAD (dB)
AD7386
AD7387
AD7388
90
86
80
75
84
70
82
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
60
20799-022
78
–40
0
40
80
120
160
200
INPUT FREQUENCY (kHz)
Figure 20. AD7386 SINAD vs. Temperature
20799-123
65
80
Figure 23. SNR vs. Input Frequency
102
–60
100
AD7386
AD7387
AD7388
–70
98
96
–80
–90
92
THD (dB)
90
88
–100
–110
VREF
VREF
VREF
VREF
86
84
= 3.3V,
= 3.3V,
= 2.5V,
= 2.6V,
RES = 1
RES = 0
RES = 1
RES = 0
–120
–130
80
0
2
4
16
8
32
OVERSAMPLING RATIO
20799-023
82
–140
0
40
80
120
160
200
INPUT FREQUENCY (kHz)
Figure 21. AD7386 SNR at Normal Oversampling
20799-124
SNR (dB)
94
Figure 24. THD vs. Input Frequency
96
110
94
100
92
90
PSRR (dB)
88
86
VREF
VREF
VREF
VREF
84
= 3.3V,
= 3.3V,
= 2.5V,
= 2.6V,
RES = 1
RES = 0
RES = 1
RES = 0
80
70
60
82
80
0
2
4
OVERSAMPLING RATIO
8
Figure 22. AD7386 SNR at Rolling Average Oversampling
40
1
10
100
1000
RIPPLE FREQUENCY (kHz)
Figure 25. PSRR vs. Ripple Frequency
Rev. A | Page 15 of 37
10000
20799-125
50
20799-024
SNR (dB)
90
AD7386/AD7387/AD7388
Data Sheet
TERMINOLOGY
Differential Nonlinearity (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Integral Nonlinearity (INL)
INL is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line.
Gain Error
The first transition (from 000…000 to 000…001) must occur
at a level ½ LSB above nominal negative full scale. The last
transition (from 111…110 to 111…111) occurs for an analog
voltage 1½ LSB below the nominal full scale. The gain error is
the deviation of the difference between the actual level of the
last transition and the actual level of the first transition from the
difference between the ideal levels.
Gain Error Temperature Drift
The gain error change due to a temperature change of 1°C.
Gain Error Match
Gain error match is the difference in negative full-scale error
between the input channels and the difference in positive fullscale error between the input channels.
Offset Error
The first transition must occur at a level ½ LSB above analog
ground. The offset error is the deviation of the actual transition
from that point.
Offset Error Temperature Drift
The zero error change due to a temperature change of 1°C.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Signal-to-Noise-and-Distortion (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value for SINAD is expressed in decibels.
Channel to Channel Memory
Channel to channel memory is a measure of the level of crosstalk
between channels in sequencer mode. It is measured by applying a
full-scale signal of a specific frequency in one analog input channel
of the ADC and determining how much that signal is attenuated in
the alternate ADC channel, when a full-scale signal of different
frequency is applied. The figure given is the typical value in
decibels and is measured for both ADC A and ADC B.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affects the full-scale transition but not
the linearity of the converter. Power supply rejection is the
maximum change in the full-scale transition point due to the
change in the power supply voltage from the nominal value. PSRR
is the ratio of power in the ADC output at full-scale frequency, f, to
the power of a 100 mV p-p sine wave applied to the VCC supply of
the ADC of the fs frequency.
PSRR (dB) = 10log(Pf/Pfs)
where:
Pf is equal to the power at f in the ADC output.
Pfs is equal to the power at fs coupled onto the VCC supply.
Aperture Delay
Aperture delay is the measure of the acquisition performance
and is the time between the falling edge of the CS input and
when the input signal is held for a conversion.
Aperture Jitter
Aperture jitter is the variation in aperture delay.
Rev. A | Page 16 of 37
Data Sheet
AD7386/AD7387/AD7388
The AD7386/AD7387/AD7388 are high speed, 4-channel, dual,
simultaneous sampling, single-ended, 16-bit/14-bit/12-bit SAR
ADCs. The devices operate from a 3.3 V power supply and
features throughput rates of up to 4 MSPS.
The AD7386/AD7387/AD7388 contain two SAR ADCs, a
multiplexer, a sequencer, and a serial interface with two separate
data output pins. The devices are housed in a 16-lead LFCSP
package, offering the user considerable space-saving advantages
over alternative solutions.
Data is accessed from the device via the serial interface. The
interface can operate with two or one serial output(s). The
AD7386/AD7387/AD7388 have an on-chip, 2.5 V internal
reference, VREF. If an external reference is desired, the internal
reference buffer can be disabled and a reference value ranging
from 2.5 V to 3.3 V can be supplied. If the internal reference is
used elsewhere in the system, the reference output must be
buffered. The analog input range for the AD7386/AD7387/
AD7388 is 0 V to VREF.
The AD7386/AD7387/AD7388 feature an on-chip oversampling
block to improve performance. Normal averaging and rolling
average oversampling modes are available. Power-down options
to allow power saving between conversions are available.
Configuration of the device is implemented via the standard
serial interface. See the Interface section for more information.
CONVERTER OPERATION
The AD7386/AD7387/AD7388 have two SAR ADCs, each
based around two capacitive DACs. Figure 26 and Figure 27
show simplified schematics of one of these ADCs in acquisition
and conversion phases, respectively. The ADC comprises
control logic, an SAR, and two capacitive DACs. In Figure 26
(the acquisition phase), SW2 is closed and SW1 is in Position A,
the comparator is held in a balanced condition, and the
sampling capacitor array acquires the signal on the input.
When the ADC starts a conversion (see Figure 27), SW2 opens
and SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution DAC
are used to add and subtract fixed amounts of charge from the
capacitive DAC to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
CAPACITIVE
DAC
ANALOG INPUT STRUCTURE
Figure 28 shows the equivalent circuit of the analog input
structure of the AD7386/AD7387/AD7388. The two diodes
provide ESD protection for the analog inputs. Care must be
taken to ensure that the analog input signals never exceed the
supply rails by more than 300 mV. Exceeding the limit causes
these diodes to become forward-biased and start conducting
into the substrate. These diodes can conduct up to 10 mA
without causing irreversible damage to the device.
The C1 capacitor in Figure 28 is typically 3 pF and can primarily
be attributed to pin capacitance. The R1 resistor is a lumped
component made up of the on resistance of the switches. The
value of these resistors is typically about 200 Ω. The C2 capacitor
is the sampling capacitor of the ADC with a capacitance of
15 pF, typically.
A SW1
SW2
GND
CONTROL
LOGIC
VCC
D
AINAx OR AINBx
C1
R1 C2
D
Figure 28. Equivalent Analog Input Circuit,
Conversion Phase = Switch Open, Track Phase = Switch Closed
COMPARATOR
CS
CONTROL
LOGIC
SW2
GND
20799-028
B
A SW1
Figure 27. ADC Conversion Phase
CAPACITIVE
DAC
AINAx OR AINBx
COMPARATOR
CS
B
AINAx OR AINBx
20799-029
CIRCUIT INFORMATION
20799-030
THEORY OF OPERATION
Figure 26. ADC Acquisition Phase
Rev. A | Page 17 of 37
AD7386/AD7387/AD7388
Data Sheet
ADC TRANSFER FUNCTION
The AD7386/AD7387/AD7388 use a 2.5 V to 3.3 V reference.
The AD7386/AD7387/AD7388 convert the voltage of the
analog inputs (AINA0 and AINA1, AINB0 and AINB1) into a digital
output.
ADC CODE (STRAIGHT BINARY)
111 ... 111
The conversion result is MSB first, straight binary. The LSB size
is (VREF)/2N, where N is the ADC resolution. The ADC resolution is
determined by the resolution of the device chosen and if
resolution boost mode is enabled. Table 9 outlines the LSB size
expressed in microvolts for different resolutions and reference
voltages options.
111 ... 110
111 ... 101
000 ... 010
000 ... 001
The ideal transfer characteristic of the AD7386/AD7387/
AD7388 is shown in Figure 29.
0V
0 + 1LSB
VREF – 1LSB
VREF – 1.5LSB
0 + 0.5LSB
20799-031
000 ... 000
ANALOG INPUT
Figure 29. ADC Ideal Transfer Function
Table 9. LSB Size
Resolution
12 Bits
14 Bits
16 Bits
18 Bits
2.5 V Reference (µV)
610.3
152.6
38.1
9.55
3.3 V Reference (µV)
805.7
201.4
50.4
12.6
V+ = 5V
V+
REF
V+
VCM = REF ÷ 2
LDO
VREF =
2.5V TO 3.3V
3.0V
TO
3.6V
LDO
INVERTER
1.65V
TO
3.6V
10kΩ
5V
TO
–5V
LDO
10kΩ
V– = –2.5V
1µF
1µF
V+ = 5V
VREF
REFIO
R
0V
C
VCC
AINA0
VLOGIC
V–
V+ = 5V
1µF
AD7386/AD7387/AD7388
VREF
R
0V
C
SDI
AINA1
SDOA
V–
V+ = 5V
EXPOSED
PAD
VREF
SDOB/ALERT
100Ω
100Ω
SCLK
R
0V
C
AINB0
CS
AINB1
REGCAP
DIGITAL HOST
(MICROPROCESSOR/
FPGA)
V–
V+ = 5V
VREF
C
V–
REFCAP
1µF
GND
0.1µF
Figure 30. Typical Application Circuit (See the Power Supply Section for Additional Information on V+ and V−)
Rev. A | Page 18 of 37
20799-032
R
0V
Data Sheet
AD7386/AD7387/AD7388
APPLICATIONS INFORMATION
Figure 30 shows an example of a complete signal chain connection
diagram for the AD7386/AD7387/AD7388. Decouple the VCC,
VLOGIC, REGCAP, and REFIO pins with suitable decoupling
capacitors, as shown in Figure 30.
The exposed pad is a ground reference point for circuitry on the
device and must be connected to the board ground.
A differential RC filter must be placed on the analog inputs to
ensure performance is achieved. For a typical application, the
recommended resistor is R = 33 Ω, and C = 330 pF.
The performance of the AD7386/AD7387/AD7388 can be
impacted by noise on the digital interface. This impact is
dependent on board layout and design. Keep a minimal
distance of the digital line to the digital interface or place
a 100 Ω resistor in series and close to the SDOA pin and
SDOB/ALERT pin to reduce noise from digital interface
coupling of the AD7386/AD7387/AD7388.
Each of the single-ended analog inputs of the AD7386/AD7387/
AD7388 can accept a voltage from 0 V to VREF and can easily
be driven by an amplifier for optimum performance. Table 10
shows the recommended components for the complete signal
chain solution that can best fit the application for the
AD7386/AD7387/AD7388.
The AD7386/AD7387/AD7388 have an internal 2.5 V reference
and can use an ultralow noise, high accuracy voltage reference
ranging from 2.5 V to 3.3 V, such as the ADR4525 or ADR4533,
as an external voltage source.
POWER SUPPLY
The typical application circuit in Figure 30 can be powered by
a single 5 V (V+) voltage source that supplies the whole signal
chain. The 5 V supply can come from a low noise, complementary
metal-oxide semiconductor (CMOS) low dropout (LDO) regulator
(for example, the ADP7105). The driver amplifier supply is
provided by +5 V (V+) and −2.5 V (V−), which is derived from
the inverter (for example, the ADM660). The inverter then
converts +5 V to −5 V and supplies this voltage to the ADP7182
low noise voltage regulator to output −2.5 V.
The two independent supplies of the AD7386/AD7387/
AD7388, VCC and VLOGIC, that supply the analog circuitry and
digital interface, respectively, can be supplied by a low quiescent
current LDO regulator like the ADP166. The ADP166 is a
suitable supply with a fixed output voltage range from 1.2 V to
3.3 V for typical VCC and VLOGIC levels. Decouple both the VCC
supply and the VLOGIC supply separately with a 1 µF capacitor.
Additionally, there is an internal LDO regulator to supply the
AD7386/AD7387/AD7388. The on-chip regulator provides a
1.9 V supply for internal use on the device only. Decouple the
REGCAP pin with a 1 µF capacitor to GND.
Power-Up
The AD7386/AD7387/AD7388 are robust to power supply
sequencing. VCC and VLOGIC can be applied in any sequence.
An external reference must be applied after VCC and VLOGIC are
applied. Analog and digital signals must be applied after the
external reference is applied.
The AD7386/AD7387/AD7388 require a tPOWERUP time from
applying VCC and VLOGIC until the ADC conversion results are
stable. Applying CS pulses or interfacing with the AD7386/
AD7387/AD7388 prior to the setup time elapsing does not have
a negative impact on ADC operation.
Table 10. Signal Chain Components
Companion Devices
ADC Driver
External Reference
LDO
Device Name
ADA4896-2
ADA4807-2
ADR4525
ADR4533
ADP166
ADP7104
ADP7182
Description
1 nV/√Hz, rail-to-rail output amplifier
1 mA, rail-to-rail output amplifier
Ultralow noise, high accuracy 2.5 V voltage reference
Ultralow noise, high accuracy 3.3 V voltage reference
Very low quiescent, 150 mA, LDO regulator
Low noise, CMOS LDO regulator
Low noise line regulator
Rev. A | Page 19 of 37
Typical Application
Precision, low noise, high frequency
Precision, low power, high frequency
2.5 V reference voltage
3.3 V reference voltage
3.0 V to 3.6 V supply for VCC and VLOGIC
5 V supply for driver amplifier
−2.5 V supply for driver amplifier
AD7386/AD7387/AD7388
Data Sheet
MODES OF OPERATION
SEQUENCER
The AD7386/AD7387/AD7388 have several on-chip
configuration registers for controlling the operational mode
of the device.
The AD7386/AD7387/AD7388 can be configured to automatically
cycle through the AINx0 and AINx1 channels using the on-chip
sequencer.
CHANNEL SELECTION
The sequencer is controlled via the SEQ bit in the
CONFIGURATION1 register. If the SEQ bit is set to 0, the
sequencer is disabled. If SEQ is set to 1, the sequencer is enabled.
The CH bit is not queried for the sequencer mode. The sequencer
always starts at the AINx0 channels and then moves to the AINx1
channels. After converting the AINx1 channel, the sequencer
loops back to the AINx0 channels and the sequence restarts.
The ADC channel pairs for conversion (AINA0/AINB0 and
AINA1/AINB1) are selected by setting the CH bit in the
CONFIGURATION1 register. If the CH bit is set to 0, the
AINA0 and AINB0 channels simultaneously convert.
Alternatively, if the CH bit is set to 1, the AINA1 and AINB1
channels are selected for simultaneous conversion.
If the channel to convert is changing, the ADC requires
additional settling time. The maximum throughput rate when
changing between the AINx0 and AINx1 channels is 2 MSPS.
If the channel to convert is changing, the ADC requires
additional settling time. The maximum throughput rate when
changing between AINx0 and AINx1 channels is 2 MSPS.
CS
INTERNAL ACQ 0
NOP
CH1
ACQ 0
CONV0
CH0
ACQ 0
CONV0
NOP
ACQ 1
CONV0
NOP
ACQ 0
CONV1
ACQ 0
CONV0
SDOA
DON'T CARE
A0
A0
A0
A1
SDOB/ALERT
DON'T CARE
B0
B0
B0
B1
CONVERT AINA0 AND AINB0
CONVERT AINA0 AND AINB0
CONVERT AINA1 AND AINB1
CONV0
20799-033
SDI
CONVERT AINA0 AND AINB0 CONVERT AINA0 AND AINB0
Figure 31. Manual Channel Selection Setup
CS
INTERNAL ACQ
SEQ = 1
CONVx
NOP
ACQx
CONVx
NOP
ACQ0
SDOA
DON'T CARE
Ax
SDOB/ALERT
DON'T CARE
Bx
CONV0
NOP
ACQ1
CONV1
NOP
ACQ0
CONV0
ACQ1
Ax
A0
A1
A0
Bx
B0
B1
B0
Figure 32. Channel Sequencer Setup
Rev. A | Page 20 of 37
20799-034
SDI
Data Sheet
AD7386/AD7387/AD7388
OVERSAMPLING
Oversampling is a common method used in analog electronics
to improve the accuracy of the ADC result. Multiple samples of
the analog input are captured and averaged to reduce the noise
component from quantization noise and thermal noise (kTC) of
the ADC. The AD7386/AD7387/AD7388 offer an oversampling
function on chip and has two user configurable oversampling
modes, normal averaging and rolling average.
The oversampling functionality is configured by programming
the OS_MODE bit and the OSR bits in the CONFIGURATION1
register.
Normal Average Oversampling
Normal average oversampling mode can be used in applications
where slower output data rates are allowable and where higher
SNR or dynamic range is desirable. Normal average oversampling
involves taking a number of samples, adding them together, and
dividing the result by the number of samples taken. This result
is then output from the device. The sample data is cleared when
the process is completed.
Normal average oversampling mode is configured by setting the
OS_MODE bit to Logic 0 and having a valid nonzero value in the
OSR bits. Writing to the OSR bits has a two-cycle latency before
the register updates. The oversampling ratio of the digital filter is
controlled using the oversampling bits, OSR.
Table 11 and Table 12 provide the oversampling bit decoding to
select the different oversampling rates. The output result is
decimated to a 16-bit resolution for the AD7386, 14-bit resolution
for the AD7387, and 12-bit resolution for the AD7388. If
additional resolution is required, configure the RES bit in
the CONFIGURATION1 register. See the Resolution Boost
section for further details.
The number of samples, n, defined by the OSR bits are taken,
added together, and the result is divided by n. The initial ADC
conversion is initiated by the falling edge of CS and the AD7386/
AD7387/AD7388 control all subsequent samples in the
oversampling sequence internally. The sampling rate of the
additional n samples is at the device maximum sampling rate,
3 MSPS for the AD7386 and 4 MSPS for the AD7387 and the
AD7388 in normal average oversampling mode. The data
is ready for readback on the next serial interface access. After the
technique is applied, the sample data used in the calculation is
discarded. This process is repeated every time the application
needs a new conversion result and is initiated by the next falling
edge of CS.
As the output data rate is reduced by the oversampling ratio, the
serial peripheral interface (SPI) SCLK frequency required to
transmit the data is also reduced accordingly.
Table 11. Normal Average Oversampling Overview for the AD7386
Oversampling Ratio
Disabled
2
4
8
16
32
Throughput Rate (kSPS Maximum)
4000
1500
750
375
187.5
93.75
SNR (dB Typical)
VREF = 2.5 V
VREF = 3.3 V
RES = 0
RES = 1
RES = 0
RES = 1
85
85
87
87
88
88.7
90
90.6
90.7
91.7
92.3
93.5
93
94.6
94
96.3
94.4
97
95
98.2
94.7
98.5
96
99.1
Table 12. Normal Average Oversampling Overview for the AD7387 and for the AD7388
AD7387
SNR (dB Typical), VREF = 2.5 V
Oversampling Ratio
Disabled
2
4
8
16
32
RES = 0
83
83.5
84.4
85.1
85.5
85.7
RES =1
83
86
88.8
91.1
93.1
94.1
Throughput Rate
(kSPS Maximum)
4000
2000
1000
500
250
125
Rev. A | Page 21 of 37
AD7388
SNR (dB Typical), VREF = 2.5V
RES = 0
73.6
73.25
73.4
73.5
73.7
73.8
RES = 1
73.6
76.5
79.5
81.3
83.0
84.2
Throughput Rate
(kSPS Maximum)
4000
2000
1000
500
250
125
AD7386/AD7387/AD7388
Data Sheet
CS
S1
ACQ
S2
Sn
ACQ
S1
ACQ
SDOA
DON’T CARE
t0 RESULT
SDOB/ALERT
DON’T CARE
t0 RESULT
CONVERT START AT t0
S2
CONVERT START AT t1
Figure 33. Normal Averaging Oversampling Operation
Rev. A | Page 22 of 37
Sn
ACQ
20799-035
INTERNAL
Data Sheet
AD7386/AD7387/AD7388
configuring the RES bit in the CONFIGURATION1 register.
See the Resolution Boost section for further details.
Rolling Average Oversampling
Rolling average oversampling mode can be used in applications
where higher output data rates are required and where higher SNR
or dynamic range is desirable. Rolling average oversampling
involves taking a number of samples, adding the samples together,
and dividing the result by the number of samples taken. This result
is then output from the device. The sample data is not cleared
when the process is completed. The rolling oversampling mode
uses a first in, first out (FIFO) buffer of the most recent samples in
the averaging calculation, allowing the ADC throughput rate and
output data rate to stay the same. Rolling average oversampling
mode is configured by setting the OS_MODE bit to Logic 1 and
having a valid nonzero value in the OSR bits. The over-sampling
ratio of the digital filter is controlled using the OSR bits. Table 13
and Table 14 provide the oversampling bit decoding to select
the different oversample rates. The output result is decimated to
16-bit resolution for the AD7386, 14-bit resolution for the
AD7387, and 12-bit resolution for the AD7388. If additional
resolution is required, this resolution can be achieved by
In rolling average oversampling mode, all ADC conversions are
controlled and initiated by the falling edge of CS. When a
conversion is complete, the result is loaded into the FIFO. The
FIFO length is 8 regardless of the oversampling ratio set. The
FIFO is filled on the first conversion after a power-on reset (POR),
the first conversion after a software controlled hard or soft reset,
or the first conversion after the REFSEL bit is toggled. A new
conversion result is shifted into the FIFO on completion of every
ADC conversion, regardless of the status of the OSR bits and the
OS_MODE bit. This shift allows a seamless transition from no
oversampling to rolling average oversampling, or different
rolling average oversampling ratios without waiting for the
FIFO to fill.
The number of samples, n, defined by the OSR bits, are taken from
the FIFO, added together, and the result is divided by n. The
time between CS falling edges is the cycle time that can be
controlled by the user, depending on the desired data output rate.
Table 13. Rolling Average Oversampling Overview for the AD7386
Oversampling Ratio
Disabled
2
4
8
SNR (dB Typical)
VREF = 2.5 V
VREF = 3.3 V
RES = 0
RES = 1
RES = 0
RES = 1
85.7
85.7
87
87
87.5
87.9
89.1
89.4
90
90.8
91.5
92.2
92.3
93.6
93.5
94.6
Throughput Rate (kSPS Maximum)
4000
4000
4000
4000
Table 14. Rolling Average Oversampling Overview for the AD7387 and for the AD7388
Oversampling Ratio
Disabled
2
4
8
AD7387
SNR (dB Typical)
RES = 0
RES = 1
83
83
83.3
85.5
84.2
88.4
85
90.7
Throughput Rate (kSPS Maximum)
4000
4000
4000
4000
VCC
AD7388
SNR (dB Typical)
RES = 0
RES = 1
73.6
73.6
73.1
76.3
73.3
79.5
73.5
81.6
tCYC
CS
S1
ACQ
SDI
SDOA
SDOB/ALERT
S2
ACQ
S3
ACQ
S4
ACQ
(FIFO1 +
FIFO2)/2
1
2
3
4
5
6
7
8
FIFO
S1
S1
S1
S1
S1
S1
S1
S1
S1
1
2
3
4
5
6
7
8
ACQ
S6
ACQ
S7
ACQ
...
ENABLE OS = 4
ENABLE OS = 2
DON’T CARE
S5
(FIFO1 +
FIFO2)/2
(FIFO1 +
FIFO2)/2
(FIFO1 + FIFO2 +
FIFO3 + FIFO4)/4
S2
FIFO
S2
S1
S1
S1
S1
S1
S1
S1
1
2
3
4
5
6
7
8
FIFO
S3
S2
S1
S1
S1
S1
S1
S1
1
2
3
4
5
6
7
8
FIFO
S4
S3
S2
S1
S1
S1
S1
S1
1
2
3
4
5
6
7
8
FIFO
S5
S4
S3
S2
S1
S1
S1
S1
Figure 34. Rolling Average Oversampling Mode Configuration
Rev. A | Page 23 of 37
1
2
3
4
5
6
7
8
FIFO
S6
S5
S4
S3
S2
S1
S1
S1
1
2
3
4
5
6
7
8
FIFO
S7
S6
S5
S4
S3
S2
S1
S1
20799-036
INTERNAL
AD7386/AD7387/AD7388
Data Sheet
To perform oversampling in sequencer mode, write a nonzero
value to enable the OSR bits in the CONFIGURATION1
register to select the number of samples to average. In addition,
select the oversampling mode, either normal oversampling or
rolling average, in the OS_MODE bit, while simultaneously setting
the SEQ bit in the CONFIGURATION1 register to 1.
Oversampling in Sequencer Mode
While in sequencer mode, oversampling on the AINx0 and AINx1
channels can be performed in the AD7386/AD7387/AD7388.
There is a two-cycle latency before the register update and start
conversion in oversampling mode, and AD7386/AD7387/AD7388
automatically cycle through AINx0 and AINx1. Figure 35 and
Figure 36 show the timing diagrams of the normal average
oversampling and rolling average oversampling in sequencer
mode, respectively.
CS
ACQ ACQ CONVx
ACQx
NOP
NOP
SEQ 1, OS = NORM, OSR = 2
ACQ0
CONVx
CONV0
ACQ0
NOP
CONV0
ACQ1
CONV1
ACQ1
NOP
CONV1
ACQ0
CONV0
ACQ0
CONV0
ACQ1
SDOA
DON'T CARE
Ax
Ax
A0
A1
A0
SBOB/
ALERT
DON'T CARE
Bx
Bx
B0
B1
B0
Figure 35. Normal Average Oversampling in Sequencer Mode
CS
INTERNAL ACQ
SEQ 1, OS = ROLL, OSR = 2
CONVx
ACQx
NOP
CONVx
NOP
ACQ0
CONV0
NOP
ACQ1
CONV1
NOP
ACQ0
CONV0
ACQ1
CONV1
SDOA
DON'T CARE
Ax
Ax
A0(FIFOn, n – 1)/2
A1(FIFOn, n – 1)/2
A0(FIFOn, n – 1)/2
SBOB/
ALERT
DON'T CARE
Bx
Bx
B0(FIFOn, n – 1)/2
B1(FIFOn, n – 1)/2
B0(FIFOn, n – 1)/2
FIFO Ax, Bx
FIFO Ax, Bx
FIFO0 A0, B0
FIFO1 A1, B1
Figure 36. Rolling Average Oversampling Sequencer Mode
Rev. A | Page 24 of 37
FIFO0 A0, B0
20799-136
SDI
20799-135
SDI
Data Sheet
AD7386/AD7387/AD7388
RESOLUTION BOOST
Detailed alert information is accessible in the Alert Register
section. The register contains two status bits per ADC, one
corresponding to the high limit and the other to the low limit. A
logical OR of alert signals for all ADCs creates a common alert
value. This value can be configured to drive out on the ALERT
function of the SDOB/ALERT pin. The SDOB/ALERT pin is
configured as ALERT by configuring the following bits in the
CONFIGURATION1 register and the CONFIGURATION2
register:
The default conversion result output data size for the AD7386 is
16 bits, for the AD7387 is 14 bits, and for the AD7388 is 12 bits.
When the on-chip oversampling function is enabled, the
performance of the ADC can exceed the 16-bit level for the
AD7386, the 14-bit level for the AD7387, and the 12-bit level for
the AD7388. To accommodate the performance boost, it is
possible to enable an additional two bits of resolution. If the
RES bit in the CONFIGURATION1 register is set to Logic 1
and the AD7386/AD7387/AD7388 are in a valid oversampling
mode, the conversion result size is 18 bit for the AD7386, is 16
bit for the AD7387, and is 14-bit for the AD7388. In this mode,
18 SCLK cycles are required to propagate the data for the
AD7386, 16 SCLK cycles are required for the AD7387, and
14 SCLK cycles are required for the AD7388.
•
•
Set the SDO bit to 1.
Set the ALERT_EN bit to 1.
In addition, set a valid value to the ALERT_HIGH_THRESHOLD
register and the ALERT_LOW_THRESHOLD register.
The alert indication function is available in oversampling, both
rolling average and normal average, and in nonoversampling
modes.
ALERT
The alert functionality is an out of range indicator and can
be used as an early indicator of an out of bounds conversion
result. An alert event triggers when the conversion result
value register exceeds the alert high limit value in the
ALERT_HIGH_THRESHOLD register or falls below the alert
low limit value in the ALERT_LOW_THRESHOLD register.
The ALERT_HIGH_THRESHOLD register and the ALERT_
LOW_THRESHOLD register are common to all ADCs.
The ALERT function of the SDOB/ALERT pin is updated at the
end of conversion. The alert indication status bits in the alert
register update as well and must be read before the end of the next
conversion. The ALERT function of the SDOB/ALERT pin is
cleared with a falling edge of CS. Issuing a software reset also
clears the alert status in the alert register.
CS
SDOA
SDOB/ALERT
SDI
DB17
DB15
2
3
DB16
DB15
DB14
DB13
14
15
16
17
18
DB4
DB3
DB2
DB1
DB0
DB2
DB1
20799-037
1
SCLK
DB0
Figure 37. Resolution Boost
tALERTS
tALERTC
CS
NO OVERSAMPLING OR
ROLLING AVERAGE
OVERSAMPLING
SDOA
INTERNAL
CONV
CONV
ACQ
CONV
ACQ
CONV
ACQ
ACQ
ALERT
EXCEEDS THRESHOLD
CS
SDOA
INTERNAL
C A C A C A C
A
C A C A C A C
A
C A C A C A C
A
C A C A C A C
A
ALERT
EXCEEDS THRESHOLD
tALERTS_NOS
Figure 38. Alert Operation
Rev. A | Page 25 of 37
tALERTC
20799-038
NORMAL
AVERAGE
OVERSAMPLING
AD7386/AD7387/AD7388
Data Sheet
POWER MODES
INTERNAL AND EXTERNAL REFERENCES
The AD7386/AD7387/AD7388 have two power modes, normal
mode and power-down mode. These modes of operation provide
flexible power management options, allowing optimization of
the power dissipation and throughput rate ratio for different
application requirements.
The AD7386/AD7387/AD7388 have a 2.5 V internal reference.
Alternatively, if a more accurate reference or higher dynamic
range is required, an external reference can be supplied. An
externally supplied reference can be in the range of 2.5 V to 3.3 V.
The recommended external voltage reference is ADR4525 for
2.5 V and ADR4533 for a 3.3 V reference.
Normal Mode
Keep the AD7386/AD7387/AD7388 in normal mode to achieve
the fastest throughput rate. All blocks within the AD7386 remain
fully powered at all times, and an ADC conversion can be
initiated by a falling edge of CS when required. When the
AD7386/AD7387/AD7388 are not converting, the devices are
in static mode and power consumption automatically reduces.
Additional current is required to perform a conversion. Therefore,
power consumption of the AD7386/AD7387/AD7388 scales with
throughput.
Power-Down Mode
When slower throughput rates and lower power consumption
are required, use power-down mode by either powering down
the ADC between each conversion or by performing a series of
conversions at a high throughput rate and then powering down
the ADC for a relatively long duration, depending on the user
application, between these burst conversions. When the AD7386/
AD7387/AD7388 are in power-down mode, all analog circuitry
powers down including the internal reference if enabled. The
serial interface remains active during power-down mode to
allow the AD7386/AD7387/AD7388 to exit power-down mode.
Reference selection, internal and external, is configured by the
REFSEL bit in the CONFIGURATION1 register. If the REFSEL
bit is set to 0, the internal reference buffer is enabled. If an external
reference is preferred, the REFSEL bit must be set to 1, and an
external reference must be supplied to the REFIO pin.
SOFTWARE RESET
The AD7386/AD7387/AD7388 have two reset modes, a soft
reset and a hard reset. A reset is initiated by writing to the
RESET bits in the CONFIGURATION2 register.
A soft reset maintains the contents of the configurable registers
but refreshes the interface and the ADC blocks. Any internal
state machines are reinitialized, and the oversampling block and
FIFO are flushed. The alert register is cleared. The reference and
LDO regulator remain powered.
A hard reset, in addition to the blocks reset by a soft reset, resets
all user registers to the default status, resets the reference buffer,
and resets the internal oscillator block.
tRESET
CS
SDI
20799-139
Program the PMODE bit in the CONFIGURATION1 register
to configure the power modes in the AD7386/AD7387/
AD7388. Set PMODE to Logic 0 for normal mode and Logic 1
for power-down mode.
SOFTWARE RESET
Figure 39. Software Reset Operation
DIAGNOSTIC SELF TEST
The AD7386/AD7387/AD7388 run a diagnostic self test after a
POR or after a software hard reset to ensure correct
configuration is loaded into the device.
To exit power-down mode and return to normal mode, set the
PMODE bit in the CONFIGURATION1 register to Logic 0. All
register configuration settings remain unchanged entering or
leaving power-down mode. After exiting power-down mode,
allow sufficient time for the circuitry to turn on before starting
a conversion. If the internal reference is enabled, the reference
must be allowed to settle for accurate conversions to happen.
The result of the self test is displayed in the SETUP_F bit in the
alert register. If the SETUP_F bit is set to Logic 1, the diagnostic
self test has failed. If this occurs, perform a software hard reset
to reset the AD7386/AD7387/AD7388 to default status.
tSTARTUP
CS
SDI
SHUTDOWN
POWER-DOWN
MODE
NORMAL
NORMAL
MODE
Figure 40. Power-Down Mode Operation
Rev. A | Page 26 of 37
ACCURATE
CONVERSION
20799-039
To enter power-down mode, write to the power mode
configuration bit, PMODE, in the CONFIGURATION1
register to a Logic 1. The AD7386/AD7387/AD7388 shut
down and current consumption reduces.
Data Sheet
AD7386/AD7387/AD7388
INTERFACE
READING CONVERSION RESULTS
The interface to the AD7386/AD7387/AD7388 is via a SPI. The
interface consists of the CS, SCLK, SDOA, SDOB/ALERT, and
SDI pins.
The CS signal initiates the conversion process. A high to low
transition on the CS signal initiates a simultaneous conversion of
both ADCs, ADC A and ADC B. The AD7386/AD7387/AD7388
have a one-cycle readback latency. Therefore, the conversion
results are available on the next SPI access. Then, take the CS
signal low, and the conversion result clocks out on the SDOA
and SDOB/ALERT pin. The next conversion is also initiated at
this point. The conversion result is shifted out of the device as a
16-bit word for the AD7386, a 14-bit word for the AD7387, and a
12-bit word for the AD7388. The MSB of the conversion result is
shifted out on the CS falling edge. The remaining data is shifted
out of the device under the control of the serial clock (SCLK)
input. The data is shifted out on the rising edge of SCLK, and
the data bits are valid on both the falling edge and the rising
edge. After the final SCLK falling edge, take CS high again to return
the SDOA and SDOB/ALERT pins to a high impedance state.
The CS signal frames a serial data transfer and initiates an ADC
conversion process. The falling edge of CS puts the track-andhold into hold mode at which point the analog input is sampled
and the bus is taken out of three-state.
The SCLK signal synchronizes data in and out of the device via
the SDOA, SDOB, and SDI signals. A minimum of 16 SCLKs are
required for a write to or read from a register. The minimum
number of SCLK pulses for a conversion read is dependent on
the resolution of the device and the configuration settings.
The ADC conversion operation is driven internally by an
on-board oscillator and is independent of the SCLK signal.
The AD7386/AD7387/AD7388 have two serial output signals,
SDOA and SDOB. To achieve the highest throughput, use both
SDOA and SDOB, 2-wire mode, to read the conversion results.
If a reduced throughput is required or oversampling is used, it
is possible to use 1-wire mode, SDOA signal only, for reading
conversion results. Programming the SDO bit in the
CONFIGURATION2 register configures 2-wire or 1-wire mode.
The number of SCLK cycles to propagate the conversion results
on the SDOA and SDOB/ALERT pins is dependent on the serial
mode of operation configured and if resolution boost is enabled
(see Figure 41 and Table 15 for details). If CRC reading is
enabled, additional SCLK pulses are required to propagate the
CRC information (see the CRC section for more details). As the
CS signal initiates a conversion, as well as framing the data,
access must be completed within a single frame.
Configuring a cyclic redundancy check (CRC) operation for SPI
reads, SPI writes, and oversampling modes alters the operation
of the interface. The relevant CRC Read, CRC Write, and CRC
Polynomial sections of this data sheet must be consulted to
ensure correct operation.
CS
1
2
3
SDOA AND SDOB/ALERT
n–2
n–1
n1
CONVERSION RESULT
1CONSULT TABLE 15 FOR n, THE NUMBER OF SCLK PULSES REQUIRED
20799-040
SCLK
Figure 41. Reading Conversion Results
Table 15. Number of SCLKs, n, Required for Reading Conversion Results
Interface
Configuration
2-Wire
Number of SCLK Pulses
Resolution Boost Mode
Disabled
Enabled
1-Wire
Disabled
Enabled
CRC Read
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
AD7386
16
24
18
26
32
40
36
44
Rev. A | Page 27 of 37
AD7387
14
22
16
24
28
36
32
40
AD7388
12
20
14
22
24
32
28
36
AD7386/AD7387/AD7388
Data Sheet
the performance boost, it is possible to enable an additional two
bits of resolution in the conversion output data. If the RES bit in
the CONFIGURATION1 register is set to Logic 1 and the
AD7386/AD7387/AD7388 are in a valid oversampling mode,
the conversion result size is 18 bits for the AD7386, is 16 bits for
the AD7387, and is 14 bits for the AD7388.
Serial 2-Wire Mode
Configure 2-wire mode by setting the SDO bit in the
CONFIGURATION2 register to 0. In 2-wire mode, the
conversion result for ADC A is output on the SDOA pin, and the
conversion result for ADC B is output on the SDOB/ALERT pin.
See Figure 42 for more information.
When the resolution boost mode is enabled, 18 SCLK cycles for
the AD7386, 16 SCLK cycles for the AD7387, and 14 SCLK
cycles for the AD7388 are required to propagate the data.
Serial 1-Wire Mode
In applications where slower throughput rates are acceptable, or
normal averaging oversampling is used, the serial interface can
be configured to operate in 1-wire mode. In 1-wire mode, the
conversion results from ADC A and ADC B are output on the
serial output, SDOA. Additional SCLK cycles are required to
propagate all the data. ADC A data is output first, followed by
ADC B conversion results. See Figure 43 for more information.
LOW LATENCY READBACK
The interface on the AD7386/AD7387/AD7388 has a one-cycle
latency, as shown in Figure 44. For applications that operate at
lower throughput rates, the latency of reading the conversion
result can be reduced. After the conversion time elapses, a second
CS pulse after the initial CS pulse that initiated the conversion
can be used to read back the conversion result. This operation is
shown in Figure 44.
Resolution Boost Mode
The default resolution and output data size is 16 bits for the
AD7386, is 14 bits for the AD7387, and is 12 bits for the
AD7388. Enabling the on-chip oversampling function reduces
noise and improves the device performance. To accommodate
S1
S0
S3
S2
SDOA
SDOB/ALERT
DON’T CARE
ADC A S0
ADC A S1
DON’T CARE
ADC B S0
ADC B S1
NOP
NOP
NOP
SDI
20799-041
CS
Figure 42. Reading Conversion Results for 2-Wire Mode
S1
S0
S2
S3
SDOA
SDI
DON’T CARE
NOP
ADC A S0 ADC B S 0
ADC A S 1 ADC B S 1
NOP
NOP
20799-042
CS
Figure 43. Read Conversion Results for 1-Wire Mode
CS
SDOA
SDOB/ALERT
CNVn
DON’T CARE
ACQ
RESULTn
CNVn+1
DON’T CARE
ACQ
RESULTn+1
SCLK
TARGET SAMPLE PERIOD
Figure 44. Low Throughput Low Latency
Rev. A | Page 28 of 37
20799-043
INTERNAL
Data Sheet
AD7386/AD7387/AD7388
READING FROM DEVICE REGISTERS
WRITING TO DEVICE REGISTERS
All the registers in the devices can be read over the serial interface.
A register read is performed by issuing a register read command
followed by an additional SPI command that can be either a valid
command or a no operation (NOP) command. The format for a
read command is shown in Table 18. Bit D15 must be set to 0 to
select a read command. Bits[D14:D12] contain the register address.
The subsequent 12 bits, Bits[D11:D0] are ignored. Figure 45 shows
the timing details on reading the AD7386/AD7387/AD7388
registers.
All the read and write registers in the AD7386/AD7387/AD7388
can be written to over the SPI. The length of an SPI write access
is determined by the CRC write function. An SPI access is 16bit if the CRC write is disabled and 24-bit when the CRC write is
enabled. The format for a write command is shown in Table 18.
Bit D15 must be set to 1 to select a write command. Bits[D14:D12]
contain the register address. The subsequent 12 bits, Bits[D11:D0],
contain the data to be written to the selected register.
S2
S1
S0
S3
S4
NOP
READ REG1
READ REG2
NOP
NOP
SDOA
INVALID
RESULT S0
REG1 DATA
REG2 DATA
RESULT S3
SDOB/ALERT
INVALID
RESULT S0
SDI
RESULT S3
Figure 45. Register Read
S0
S2
S1
S3
SDI
SDOA
SDOB/ALERT
NOP
WRITE REG 1
WRITE REG 2
NOP
INVALID
RESULT S0
RESULT S1
RESULT S2
Figure 46. Register Write
Rev. A | Page 29 of 37
20799-045
CS
20799-044
CS
AD7386/AD7387/AD7388
Data Sheet
CRC
CRC Polynomial
The AD7386/AD7387/AD7388 have CRC checksum modes that
can be used to improve interface robustness by detecting errors
in data transmissions. The CRC feature is independently
selectable for SPI interface reads and SPI interface writes. For
example, enable the CRC function for SPI writes to prevent
unexpected changes to the device configuration but not enable
it on SPI reads, thus maintaining a higher throughput rate. The
CRC feature is controlled by programming the CRC_W bit and
CRC_R bit in the CONFIGURATION1 register.
For CRC checksum calculations, the following polynomial is
always used:
CRC Read
If enabled, a CRC is appended to the conversion result or
register read and consists of an 8-bit word. The CRC is calculated
in the conversion result for ADC A and ADC B and is output on
SDOA. A CRC is also calculated and appended to register read
outputs.
The CRC read function can be used in 2-wire SPI mode, 1-wire
SPI mode, and resolution boost mode.
CRC Write
To enable the CRC write function, the CRC_W bit in the
CONFIGURATION1 register must be set to 1. To set the CRC_W
bit to 1 to enable the CRC feature, the request frame must have
a valid CRC appended to the frame.
After the CRC feature is enabled, all register write requests are
ignored unless accompanied by a valid CRC command, requiring a
valid CRC to both enable and disable the CRC write feature.
x8 + x2 + x + 1
To generate the checksum, the 16-bit data conversion result of
the two channels are combined, which produces a 32-bit data.
The eight MSBs of the 32-bit data are inverted and then shift by
eight bits to create a number ending in eight Logic 0s. The
polynomial is aligned such that its MSB is adjacent to the
leftmost Logic 1 of the data. An exclusive OR (XOR) function is
applied to the data to produce a new, shorter number. The
polynomial is again aligned such that its MSB is adjacent to the
leftmost Logic 1 of the new result, and the procedure is repeated.
This process repeats until the original data is reduced to a value
less than the polynomial, the 8-bit checksum. For example, the
polynomial is 100000111.
Let the original data of two channels be 0xAAAA and 0x5555,
that is, 1010 1010 1010 1010 and 0101 0101 0101 0101. The data
of the two channels is then appended, including eight 0s on the
right. The data then becomes 1010 1010 1010 1010 0101 0101
0101 0101 0000 0000.
Table 16 shows the CRC calculation of 16-bit, 2-channel data. In
the final XOR operation, the reduced data is less than the
polynomial. Thus, the remainder is the CRC for the assumed data.
Rev. A | Page 30 of 37
Data Sheet
AD7386/AD7387/AD7388
Table 16. Example CRC Calculation for 2-Channel, 16-Bit Data
Data
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X 1 X1 X1 X1 X1 X1 X1 X1
Process Data
0 1 0 1
1 0 0
1
1
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1
1
0
0
0
1
1 1 0
1 1 1
1 1 0
1 0 0
1 0
1 0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
1
1
0
1
CRC
X = don’t care.
16 + 8 = 24 BITS
SDOA
RESULT A
SDOB/ALERT
RESULT B
CRCA, B
2-WIRE 16-BIT
16 + 16 + 8 = 40 BITS
SDOA
RESULT A
SDOA
RESULT A
SDOB/ALERT
RESULT B
1-WIRE 16-BIT
RESULT B
CRCA, B
18 + 8 = 26 BITS
CRCA, B
2-WIRE 18-BIT
18 + 18 + 8 = 44 BITS
1-WIRE 18-BIT
SDOA
RESULT A
REGISTER READ RESULT
SDOA
REGISTER X
RESULT B
CRCA, B
16 + 8 = 24 BITS
CRCREG X
16 + 8 = 24 BITS
REGISTER READ REQUEST
SDI
REGISTER X
CRCREG X
16 + 8 = 24 BITS
REGISTER WRITE
SDI
WRITE REGISTER X
CRCREG X
Figure 47. CRC Operation
Rev. A | Page 31 of 37
20799-046
1
0 0 0 0 0 0 0
0 0 0
0 0 1
0 0 1
0 0
1 1
1 1 0
0
AD7386/AD7387/AD7388
Data Sheet
REGISTERS
The AD7386/AD7387/AD7388 have user-programmable on-chip registers for configuring the device. Table 17 shows a complete
overview of the registers available on the AD7386/AD7387/AD7388. The registers are either read/write (R/W) or read only (R). Any read
request to a write only register is ignored. Any write to a read only register is ignored. Writes to any other register address are considered a
NOP and are ignored. Any read request to a register address, other than those listed in Table 17, are considered a NOP, and the data
transmitted in the next SPI frame are the conversion results.
Table 17. Register Description
Reg
0x1
Name
CONFIGURATION1
0x2
CONFIGURATION2
0x3
ALERT
0x4
ALERT_LOW_
THRESHOLD
0x5
ALERT_HIGH_
THRESHOLD
Bits
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 7
Bit 6
Bit 5
ADDRESSING
CRC_W
ADDRESSING
Bit 4
Bit 3
CH
ALERT_EN
OSR[1:0]
CRC_R
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
SEQ
OS_MODE
RES
REFSEL
RESERVED
Bit 0
OSR[2]
PMODE
SDO
Reset
0x0000
RW
R/W
0x0000
R/W
SETUP_F
AL_A_LOW
0x0000
R
0x0000
R/W
0x0FFF
R/W
RESET
RESERVED
[7:0]
[15:8]
ADDRESSING
AL_B_HIGH
ADDRESSING
RESERVED
RESERVED
AL_B_LOW
CRCW_F
AL_A_HIGH
ALERT_LOW[11:8]
ALERT_LOW[7:0]
ADDRESSING
ALERT_HIGH[11:8]
[7:0]
ALERT_HIGH[7:0]
ADDRESSING REGISTERS
A serial register transfer on the AD7386/AD7387/AD7388 consists of 16 SCLK cycles. The four MSBs written to the device are decoded to
determine which register is addressed. The four MSBs consist of the register address (REGADDR), Bits[2:0], and the read/write bit (WR).
The register address bits determine which on-chip register is selected. The read/write bit determines if the remaining 12 bits of data on
the SDI input are loaded into the addressed register if the addressed register is a valid write register. If the WR bit is 1, the bits load into
the register addressed by the register select bits. If the WR bit is 0, the command is seen as a read request. The addressed register data is
available to be read during the next read operation.
Table 18. Addressing Register Format
MSB
D15
WR
LSB
D14
D13
D12
REGADDR
D11
D10
D9
D8
D7
D6
D5
D[11:0]
D4
D3
D2
D1
D0
Table 19. Bit Descriptions for Addressing Registers
Bit
D15
Mnemonic
WR
D14 to D12
REGADDR
D11 to D0
D[11:0]
Description
If a 1 is written to this bit, Bits[D11:D0] of this register are written to the register specified by REGADDR if it is
a valid address. Alternatively, if a 0 is written, the next data sent out on the SDOA pin is a read from the
designated register if it is a valid address.
When WR = 1, the contents of REGADDR determine the register for selection as outlined in Table 17.
When WR = 0, and REGADDR contain a valid register address, the contents on the requested register are
output on the SDOA pin during the next interface access.
When WR = 0, and REGADDR contain 0x0, 0x6, or 0x7, the contents on the SDI line are ignored. The next
interface access results in the conversion results being read back.
These bits are written into the corresponding register specified by the REGADDR bits when the WR bit is
equal to 1 and the REGADDR bits contain a valid address.
Rev. A | Page 32 of 37
Data Sheet
AD7386/AD7387/AD7388
CONFIGURATION1 REGISTER
Address: 0x1, Reset: 0x0000, Name: CONFIGURATION1
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:12] ADDRESSING (R/W)
Addressing.
[0] PMODE (R/W)
Power-Down Mode.
[11] CH (R/W)
Channel Selection.
[1] REFSEL (R/W)
Reference Select.
[10] SEQ (R/W)
Sequencer.
[2] RES (R/W)
Resolution.
[9] OS_MODE (R/W)
Oversam pling Mode.
[3] ALERT_EN (R/W)
Enable Alert Indicator Function.
[8:6] OSR (R/W)
Oversam pling Ratio.
[4] CRC_R (R/W)
CRC Read.
[5] CRC_W (R/W)
CRC Write.
Table 20. Bit Descriptions for CONFIGURATION1
Bits
[15:12]
Bit Name
ADDRESSING
11
CH
10
SEQ
9
OS_MODE
[8:6]
OSR
5
CRC_W
4
CRC_R
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
Channel Selection. Selects the channels to be converted.
0: Channel 0s. Selects Channel 0s of the ADC, AINA0 and AINB0.
1: Channel 1s. Selects Channel 1s of the ADC, AINA1 and AINB1.
Sequencer. Cycles through the AINx0 and AINx1 channels of the ADC for conversion.
0: sequencer disabled.
1: sequencer enabled.
Oversampling Mode. Sets the oversampling mode of the ADC.
0: normal average.
1: rolling average.
Oversampling Ratio. Sets the oversampling ratio for all the ADCs in the relevant mode. Normal
averaging mode supports oversampling ratios of ×2, ×4, ×8, ×16, and ×32. Rolling average
mode supports oversampling ratios of ×2, ×4, and ×8.
000: disabled.
001: 2×.
010: 4×.
011: 8×.
100: 16×.
101: 32×.
110: disabled.
111: disabled.
CRC Write. Controls the CRC functionality for the SDI interface. When setting this bit from a 0
to a 1, the command must be followed by a valid CRC to set this configuration bit. If a valid
CRC is not received, the entire frame is ignored. If the bit is set to 1, it requires a CRC to clear it
to 0.
0: no CRC function.
1: CRC function.
CRC Read. Controls the CRC functionality for the SDOA and SDOB/ALERT interface.
0: no CRC function.
1: CRC function.
Rev. A | Page 33 of 37
Reset
0x0
Access
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
AD7386/AD7387/AD7388
Bits
3
Bit Name
ALERT_EN
2
RES
1
REFSEL
0
PMODE
Data Sheet
Description
Enable Alert Indicator Function. This register functions when the SDO bit = 1. Otherwise, the
ALERT_EN bit is ignored.
0: SDOB.
1: ALERT.
Resolution. Sets the size of the conversion result data. If OSR = 0, these bits are ignored and
the resolution is set to default resolution.
0: normal resolution.
1: 2-bit higher resolution.
Reference Select. Selects the ADC reference source.
0: selects internal reference.
1: selects external reference.
Power-Down Mode. Sets the power modes.
0: normal mode.
1: power-down mode.
Reset
0x0
Access
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Reset
0x0
Access
R/W
0x0
0x0
R
R/W
0x0
R/W
CONFIGURATION2 REGISTER
Address: 0x2, Reset: 0x0000, Name: CONFIGURATION2
15 14 13 12
0
0
0
0
11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
[15:12] ADDRESSING (R/W)
Addressing.
[7:0] RESET (R/W)
Reset.
[11:9] RESERVED
[8] SDO (R/W)
SDO.
Table 21. Bit Descriptions for CONFIGURATION2
Bits
[15:12]
Bit Name
ADDRESSING
[11:9]
8
RESERVED
SDO
[7:0]
RESET
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
Reserved.
SDO. Conversion results serial data output.
0: 2-wire—conversion data are output on both SDOA and SDOB/ALERT pins.
1: 1-wire—conversion data are output on SDOA pin only.
Reset. 0x3C—performs a soft reset. Refreshes some blocks. Register contents remain
unchanged. Clears the alert register and flushes any oversampling stored variables or active
state machine. 0xFF—performs a hard reset. Resets all possible blocks in the device. Register
contents are set to defaults. All other values are ignored.
Rev. A | Page 34 of 37
Data Sheet
AD7386/AD7387/AD7388
ALERT REGISTER
Address: 0x3, Reset: 0x0000, Name: Alert
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:12] ADDRESSING (R)
Addressing.
[0] AL_A_LOW (R)
Alert A Low.
[11:10] RESERVED
[1] AL_A_HIGH (R)
Alert A High.
[9] CRCW_F (R)
CRC Error.
[3:2] RESERVED
[8] SETUP_F (R)
Load Error.
[4] AL_B_LOW (R)
Alert B Low.
[7:6] RESERVED
[5] AL_B_HIGH (R)
Alert B High.
Table 22. Bit Descriptions for Alert
Bits
[15:12]
Bit Name
ADDRESSING
[11:10]
9
RESERVED
CRCW_F
8
SETUP_F
[7:6]
5
RESERVED
AL_B_HIGH
4
AL_B_LOW
[3:2]
1
RESERVED
AL_A_HIGH
0
AL_A_LOW
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
Reserved.
CRC Error. Indicates that a register write command failed due to a CRC error. This fault bit is
sticky and remains set until the register is read.
0: no CRC error.
1: CRC error.
Load Error. The SETUP_F bit indicates that the device configuration data did not load correctly
on startup. This bit does not clear on an alert register read. A hard reset via the
CONFIGURATION2 register is required to clear this bit and restart the device setup again.
0: no setup error.
1: setup error.
Reserved.
Alert B High. The alert indication high bits indicate if a conversion result for the respective
input channel exceeds the value set in the ALERT_HIGH_THRESHOLD register. This fault bit is
sticky and remains set until the register is read.
1: alert indication.
0: no alert indication.
Alert B Low. The alert indication low bits indicate if a conversion result for the respective input
channel exceeds the value set in the ALERT_LOW_THRESHOLD register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
Reserved.
Alert A High. The alert indication high bits indicate if a conversion result for the respective
input channel exceeds the value set in the ALERT_HIGH_THRESHOLD register. This fault bit is
sticky and remains set until the register is read.
0: no alert indication.
1: alert indication.
Alert A Low. The alert indication low bits indicate if a conversion result for the respective input
channel exceeds the value set in the ALERT_LOW_THRESHOLD register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
Rev. A | Page 35 of 37
Reset
0x0
Access
R
0x0
0x0
R
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
0x0
R
R
0x0
R
AD7386/AD7387/AD7388
Data Sheet
ALERT_LOW_THRESHOLD REGISTER
Address: 0x4, Reset: 0x0000, Name: ALERT_LOW_THRESHOLD
15 14 13 12
0
0
0
0
11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
[15:12] ADDRESSING (R/W)
Addressing.
[11:0] ALERT_LOW (R/W)
Alert Low.
Table 23. Bit Descriptions for ALERT_LOW_THRESHOLD
Bits
[15:12]
Bit Name
ADDRESSING
[11:0]
ALERT_LOW
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
Alert Low. Data Bits[D11:D0] are the MSBs of the 16-bit internal alert low register. The
remaining 4 bits are fixed at 0x0, which sets an alert when the conversion result is below the
ALERT_LOW_THRESHOLD and disables when the conversion result is above the
ALERT_LOW_THRESHOLD.
Reset
0x0
Access
R/W
0x0
R/W
Reset
0x0
Access
R/W
0xFFF
R/W
ALERT_HIGH_THRESHOLD REGISTER
Address: 0x5, Reset: 0x0FFF, Name: ALERT_HIGH_THRESHOLD
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
[15:12] ADDRESSING (R/W)
Addressing.
[11:0] ALERT_HIGH (R/W)
Alert High.
Table 24. Bit Descriptions for ALERT_HIGH_THRESHOLD
Bits
[15:12]
Bit Name
ADDRESSING
[11:0]
ALERT_HIGH
Description
Addressing. Bits [15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
Alert High. Data Bits[D11:D0] are the MSBs of the 16-bit internal alert high register. The
remaining 4 bits are fixed at 0xF, which sets an alert when the conversion result is above the
ALERT_HIGH_THRESHOLD and disables when the conversion result is below the
ALERT_HIGH_THRESHOLD.
Rev. A | Page 36 of 37
Data Sheet
AD7386/AD7387/AD7388
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10
3.00 SQ
2.90
0.30
0.25
0.18
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
16
13
12
1
0.50
BSC
0.45
*1.20
ED
EXPOSED
PAD
1.10 SQ
1.00
9
0.45
0.40
0.35
TOP VIEW
0.80
0.75
0.70
0.55 REF
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.15 REF
SEATING
PLANE
PKG-005000
4
5
8
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WEED-4
WITH EXCEPTION TO THE EXPOSED PAD
08-29-2018-A
PIN 1
INDICATOR
AREA
Figure 48. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-45)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2, 3
AD7386BCPZ-RL
AD7386BCPZ-RL7
AD7387BCPZ-RL
AD7387BCPZ-RL7
AD7388BCPZ-RL
AD7388BCPZ-RL7
EVAL-AD7386FMCZ
EVAL-SDP-CH1Z
Resolution (Bit)
16
16
14
14
12
12
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
AD7386 Evaluation Board
Controller Board
Z = RoHS Compliant Part.
The EVAL-AD7386FMCZ is compatible with the EVAL-SDP-CH1Z high speed controller board.
3
The AD7387 and the AD7388 use the EVAL-AD7386FMCZ evaluation board.
1
2
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D20799-0-10/19(A)
Rev. A | Page 37 of 37
Package Option
CP-16-45
CP-16-45
CP-16-45
CP-16-45
CP-16-45
CP-16-45
Marking Code
C8Z
C8Z
DMW
DMW
C9T
C9T
