a
3 V Serial-Input
Micropower 10-Bit and 12-Bit DACs
AD7390/AD7391
FEATURES
Micropower—100 A
Single-Supply—2.7 V to 5.5 V Operation
Compact 1.75 mm Height SO-8 Package
and 1.1 mm Height TSSOP-8 Package
AD7390—12-Bit Resolution
AD7391—10-Bit Resolution
SPI and QSPI Serial Interface Compatible with Schmitt
Trigger Inputs
FUNCTIONAL BLOCK DIAGRAM
VDD
AD7390
REF
VOUT
12-BIT DAC
12
CLR
LD
EN
CLK
APPLICATIONS
Automotive 0.5 V to 4.5 V Output Span Voltage
Portable Communications
Digitally Controlled Calibration
GND
DAC REGISTER
12
SERIAL REGISTER
SDI
GENERAL DESCRIPTION
The AD7390/AD7391 family of 10-bit and 12-bit voltageoutput digital-to-analog converters is designed to operate
from a single 3 V supply. Built using a CBCMOS process,
these monolithic DACs offer the user low cost, and ease-of-use
in single-supply 3 V systems. Operation is guaranteed over the
supply voltage range of 2.7 V to 5.5 V consuming less than 100 µA
making this device ideal for battery operated applications.
The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail REFIN to
DACOUT allows for a full-scale voltage set equal to the positive
supply VDD or any value in between.
A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI and microcontroller compatible inputs using data
in (SDI), clock (CLK) and load strobe (LD) pins. Additionally, a CLR input sets the output to zero scale at power on or
upon user demand.
Both parts are offered in the same pinout to allow users to select
the amount of resolution appropriate for their application without
circuit card redesign.
The AD7390/AD7391 are specified over the extended industrial
(40°C to 85°C) temperature range. The AD7391AR is
specified for the 40°C to 125°C automotive temperature
range. The AD7390/AD7391s are available in plastic DIP, and
low profile 1.75 mm height SO-8 surface mount packages. The
AD7391ARU is available for ultracompact applications in a thin
1.1 mm TSSOP-8 package.
2.0
1.00
AD7390
AD7390
0.75
1.5
0.50
1.0
0.25
0.5
INL – LSB
DNL – LSB
+25C, +85C
0.00
0.25
0.5
55C
1.0
0.50
VDD = 3.0V
TA = 55C, +25C, +85C
SUPERIMPOSED
0.75
1.00
0.0
0
512
1024
1536
VDD = 3.0V
VREF = 2.5V
1.5
2048
2560
3072
3584
4096
CODE – Decimal
Figure 1. Differential Nonlinearity Error vs. Code
2.0
0
512
1024
1536
2048
2560
3072
2584
4096
CODE – Decimal
Figure 2. INL Error vs. Code and Temperature
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD7390/AD7391–SPECIFICATIONS
AD7390 ELECTRICAL CHARACTERISTICS (@ V
Parameter
STATIC PERFORMANCE
Resolution1
Relative Accuracy2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Tempco3
REF IN
= 2.5 V, –40C < TA < +85C unless otherwise noted.)
Symbol
Conditions
3 V 10%
5 V 10%
Unit
N
INL
INL
DNL
DNL
VZSE
VFSE
VFSE
TCVFS
TA = 25°C
TA = 40°C, 85°C
TA = 25°C, Monotonic
Monotonic
Data = 000H
TA = 25°C, 85°C, Data = FFFH
TA = 40°C, Data = FFFH
12
± 1.6
± 2.0
± 0.9
±1
4.0
±8
± 20
16
12
± 1.6
±2
± 0.9
±1
4.0
±8
± 20
16
Bits
LSB max
LSB max
LSB max
LSB max
mV max
mV max
mV max
ppm/°C typ
0/VDD
2.5
5
0/VDD
2.5
5
V min/max
MΩ typ4
pF typ
1
3
100
1
3
100
mA typ
mA typ
pF typ
REFERENCE INPUT
VREF IN Range
Input Resistance
Input Capacitance3
VREF
RREF
CREF
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Capacitive Load3
IOUT
IOUT
CL
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
VIL
VIH
IIL
CIL
0.5
VDD 0.6
10
10
0.8
VDD 0.6
10
10
V max
V min
µA max
pF max
INTERFACE TIMING3, 5
Clock Width High
Clock Width Low
Load Pulsewidth
Data Setup
Data Hold
Clear Pulsewidth
Load Setup
Load Hold
tCH
tCL
tLDW
tDS
tDH
tCLRW
tLD1
tLD2
50
50
30
10
30
15
30
40
30
30
20
10
15
15
15
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
AC CHARACTERISTICS6
Output Slew Rate
Settling Time
DAC Glitch
Digital Feedthrough
Feedthrough
SR
tS
Q
Q
VOUT/VREF
Data = 000H to FFFH to 000H
To 0.1% of Full Scale
Code 7FFH to 800H to 7FFH
0.05
70
65
15
63
0.05
60
65
15
63
V/µs typ
µs typ
nVs typ
nVs typ
dB typ
VDD RANGE
IDD
IDD
PDISS
PSS
DNL < ± 1 LSB
VIL = 0 V, No Load, TA = 25°C
VIL = 0 V, No Load
VIL = 0 V, No Load
∆VDD = ± 5%
2.7/5.5
55
100
300
0.006
2.7/5.5
55
100
500
0.006
V min/max
µA typ
µA max
µW max
%/% max
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
Data = 800H, ∆VOUT = 5 LSB
Data = 800H, ∆VOUT = 5 LSB
No Oscillation
VREF = 1.5 VDC 1 V p-p,
Data = 000H, f = 100 kHz
NOTES
1
One LSB = VREF/4096 V for the 12-bit AD7390.
2
The first two codes (000 H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at 25°C.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
–2–
REV. A
AD7390/AD7391
AD7391 ELECTRICAL CHARACTERISTICS
Parameter
STATIC PERFORMANCE
Resolution1
Relative Accuracy2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Error
Full-Scale Tempco3
Symbol
N
INL
INL
INL
DNL
DNL
VZSE
VZSE
VFSE
VFSE
TCVFS
TCVFS
(@ VREF IN = 2.5 V, 40C < TA < 85C unless otherwise noted.)
Conditions
TA = 25°C
TA = 40°C, 85°C, 125°C
TA = 55°C, S Grade
Monotonic
TA = 55°C, S Grade
Data = 000H
TA = 55°C, S Grade
TA = 25°C, 85°C, 125°C,
Data = 3FFH
TA = 55°C, S Grade
TA = 55°C, S Grade
3 V 10%
5 V 10%
Unit
10
± 1.75
± 2.0
10
± 1.75
± 2.0
±3
± 0.9
±2
9.0
20
± 32
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
mV max
mV max
mV max
16
± 55
16
32
mV max
ppm/°C typ
ppm/°C typ
0/VDD
2.5
5
0/VDD
2.5
5
V min/max
MΩ typ4
pF typ
1
3
100
1
3
100
mA typ
mA typ
pF typ
± 0.9
9.0
± 32
REFERENCE INPUT
VREF IN Range
Input Resistance
Input Capacitance3
VREF
RREF
CREF
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Capacitive Load3
IOUT
IOUT
CL
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
VIL
VIH
IIL
CIL
0.5
VDD 0.6
10
10
0.8
VDD 0.6
10
10
V max
V min
µA max
pF max
INTERFACE TIMING3, 5
Clock Width High
Clock Width Low
Load Pulsewidth
Data Setup
Data Hold
Clear Pulsewidth
Load Setup
Load Hold
tCH
tCL
tLDW
tDS
tDH
tCLRW
tLD1
tLD2
50
50
30
10
30
15
30
40
30
30
20
10
15
15
15
20
ns
ns
ns
ns
ns
ns
ns
ns
0.05
70
65
15
63
0.05
60
100
65
15
63
V/µs typ
µs typ
µs typ
nVs typ
nVs typ
dB typ
2.7/5.5
55
100
300
0.006
2.7/5.5
55
100
500
0.006
V min/max
µA typ
µA max
µW max
%/% max
AC CHARACTERISTICS6
Output Slew Rate
Settling Time
DAC Glitch
Digital Feedthrough
Feedthrough
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
Data = 800H, ∆VOUT = 5 LSB
Data = 800H, ∆VOUT = 5 LSB
No Oscillation
SR
tS
tS
Q
Q
VOUT/VREF
Data = 000H to 3FFH to 000H
To 0.1% of Full Scale
TA = –55°C, S Grade
Code 7FFH to 800H to 7FFH
VDD RANGE
IDD
IDD
PDISS
PSS
DNL < ± 1 LSB
VIL = 0 V, No Load, TA = 25°C
VIL = 0 V, No Load
VIL = 0 V, No Load
∆VDD = ± 5%
VREF = 1.5 VDC 1 V p-p,
Data = 000H, f = 100 kHz
NOTES
1
One LSB = VREF/1024 V for the 10-bit AD7391.
2
The first two codes (000 H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at 25°C.
5
All input control signals are specified with t R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
REV. A
–3–
AD7390/AD7391
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATIONS
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, 8 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD 0.3 V
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . .0.3 V, 8 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . 0.3 V, VDD 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . (TJ MAX TA)/θJA
Thermal Resistance θJA
8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . . 158°C/W
TSSOP-8 Package (RU-8) . . . . . . . . . . . . . . . . . . . 240°C/W
Maximum Junction Temperature (TJ MAX) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . 40°C to 85°C
AD7391AR . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 125°C
Storage Temperature Range . . . . . . . . . . . 65°C to 150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
specification is not implied. Exposure to the above maximum rating conditions for
extended periods may affect device reliability.
TSSOP-8
8
1
2
3
TOP VIEW
(Not to
Scale)
LOAD
CLK
12-BIT AD7390*
SHIFT REGISTER
SDI
8
2
7
TOP VIEW
(Not to Scale)
6
3
6
5
4
P-DIP-8
LD 1
8
VREF
7 VDD
TOP VIEW
(Not to Scale) 6
SDI 3
VOUT
CLK 2
CLR 4
5
GND
Pin No.
Name
Function
1
LD
2
CLK
3
SDI
4
CLR
5
6
GND
VOUT
7
VDD
8
VREF
Load Strobe. Transfers shift register
data to DAC register while active low.
See truth table for operation.
Clock Input. Positive edge clocks data
into shift register.
Serial Data Input. Data loads directly
into the shift register.
Resets DAC register to zero condition.
Active low input.
Analog and Digital Ground.
DAC Voltage Output. Full-scale output
1 LSB less than reference input voltage REF.
Positive Power Supply Input. Specified
range of operation 2.7 V to 5.5 V.
DAC Reference Input Pin. Establishes
DAC full-scale voltage.
12
CLK
1
PIN DESCRIPTIONS
DAC
REGISTER
LD
7
5
4
RESET
CLR
SO-8
D
*AD7391 HAS A 10-BIT SHIFT REGISTER
Figure 3. Digital Control Logic
ORDERING GUIDE1
Model
Resolution
Temperature
Range
Package
Description
Package
Option
Top
Mark2
Number of Devices
Per Container
AD7390AN
AD7390AR
AD7390AR-REEL7
AD7391AN
AD7391AR
AD7391SR
AD7391ARU-REEL
12
12
12
10
10
10
10
40°C to 85°C
40°C to 85°C
40°C to 85°C
40°C to 85°C
40°C to 125°C
55°C to 125°C
40°C to 85°C
8-Lead P-DIP
8-Lead SOIC
8-Lead SOIC
8-Lead P-DIP
8-Lead SOIC
8-Lead SOIC
TSSOP-8
N-8
SO-8
SO-8
N-8
SO-8
SO-8
RU-8
AD73902
AD73903
AD73903
AD73912
AD73913
AD73913
AD7391A4
50
196
1000
50
196
39
2500
NOTES
1
The AD7390 contains 588 transistors. The die size measures 70 mm 68 mm.
2
Line 1 contains ADI logo symbol and part number. Line 2 contains grade and date code YWW. Line 3 contains the letter G plus the 4-digit lot number.
3
Line 1 contains part number. Line 2 contains grade and date code YWW. Line 3 contains the letter G plus the 4-digit lot number and the ADI logo symbol.
4
Line 1 contains the date code YWW. Line 2 contains the 4-digit part number plus grade.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7390/AD7391 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. A
AD7390/AD7391
SDI
D11
D10
D9
AD7390
D7
D5
D4
D3
D2
D1
D0
AD7391
CLK
tLD2
tLD1
tLD1
LD
DAC REGISTER LOAD
SDI
tDS
tDH
tCL
CLK
tCH
LD
tLDW
CLR
tCLRW
tS
FS
0.1% FS
ERROR BAND
VOUT
ZS
tS
Figure 4. Timing Diagram
Table I. Control-Logic Truth Table
CLK
CLR
LD
Serial Shift Register Function
DAC Register Function
↑
X
X
X
X
H
H
L
↑
↑
H
L
X
H
L
Shift-Register-Data Advanced One-Bit
Disables
No Effect
No Effect
Disabled
Latched
Updated with Current Shift Register Contents
Loaded with all Zeros
Latched with all Zeros
Previous SR Contents Loaded (Avoid usage of CLR
when LD is logic low, since SR data could be corrupted
if a clock edge takes place, while CLR returns high.)
↑ = Positive logic transition.
X = Don’t care.
Table II. AD7390 Serial Input Register Data Format, Data is Loaded in the MSB-First Format
MSB
AD7390
LSB
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table III. AD7391 Serial Input Register Data Format, Data is Loaded in the MSB-First Format
MSB
AD7391
REV. A
LSB
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
–5–
AD7390/AD7391–Typical Performance Characteristics
30
100
25
SS = 100 UNITS
TA = 25C
20 VDD = 2.7V
VREF = 2.5V
SS = 100 UNITS
TA = 40C TO +85C
VDD = 2.7V
24
VREF = 2.5V
SS = 300 UNITS
TA = 25C
VDD = 2.7V
VREF = 2.5V
90
80
15
10
FREQUENCY
FREQUENCY
FREQUENCY
70
60
50
40
18
12
30
6
20
5
10
16
TPC 2. AD7391 Total Unadjusted
Error Histogram
5.0
95
4.5
SUPPLY CURRENT – A
12
10
8
6
4
85
80
TA = 25C
VDD = 3.0V
75
70
65
2
55
0
1
50
0.0
10
100
1k
FREQUENCY – Hz
10k
100k
100
1000
VDD = 5.0V, VLOGIC = 0V
80
VDD = 3.6V, VLOGIC = 2.4V
60
50
40
VDD = 3.0V, VLOGIC = 0V
SUPPLY CURRENT – A
90
800
0.5
1.0
1.5
VIN – V
2.0
2.5
TPC 7. AD7390 Supply Current
vs. Temperature
3.5
3.0
VLOGIC FROM
HIGH TO LOW
2.5
2.0
VLOGIC FROM
LOW TO HIGH
1.5
1.0
a. V DD = 5.5V,
b. V DD = 5.5V,
600 c. V DD = 2.7V,
d. V DD = 2.7V,
CODE = 155H
CODE = 3FFH
CODE = 155H
CODE = 355H
1
2
7
3
4
5
6
SUPPLY VOLTAGE – V
TPC 6. AD7390 Logic Threshold
vs. Supply Voltage
60
VLOGIC = 0V TO V DD TO 0V
VREF = 2.5V
TA = 25C
TA = 25C
50
VDD = 5V 5%
40
a b
400
VDD = 3V 5%
30
20
200
5
25 45 65 85 105 125
TEMPERATURE – C
CODE = FFFH
VREF = 2V
RS LOGIC VOLTAGE
VARIED
4.0
0.0
3.0
10
30
20
55 35 15
0
0.5
TPC 5. AD7390 Supply Current vs.
Logic Input Voltage
SAMPLE SIZE = 300 UNITS
70
VLOGIC FROM
0V TO 3.0V
60
TPC 4. AD7390 Voltage Noise
Density vs. Frequency
SUPPLY CURRENT – A
VLOGIC FROM
3.0V TO 0V
90
–33 –30 –26 –23 –20 –16 –13 –10 –6 –3
FULL-SCALE TEMPCO – ppm/ C
TPC 3. AD7391 Full-Scale Output
Tempco Histogram
100
VDD = 5V
VREF = 2.5V
TA = 25C
14
0
–10 –3.3 3.3 10 16 23 30 36 43 50
TOTAL UNADJUSTED ERROR – LSB
THRESHOLD VOLTAGE – V
TPC 1. AD7390 Total Unadjusted
Error Histogram
OUTPUT VOLTAGE NOISE – V Hz
0
5.0 5.8 6.6 7.3 8.1 8.9 9.7 10.5 11.2 12.0
TOTAL UNADJUSTED ERROR – LSB
PSRR – dB
0
0
1k
d c
10k
100k
1M
CLOCK FREQUENCY – Hz
10M
TPC 8. AD7391 Supply Current
vs. Clock Frequency
–6–
0
10
100
1k
FREQUENCY – Hz
10k
TPC 9. Power Supply Rejection
vs. Frequency
REV. A
AD7390/AD7391
40
VDD = 5V
VREF = 3V
CODE = ØØØH
2s
VOUT
(5mV/DIV)
VOUT
(5mV/DIV)
LD = HIGH
20
10
VDD = 5V
VREF = 2.5V
fCLK = 50kHz
CODE: 7FH to 80H
LD
(5V/DIV)
20mV
0
0
2
3
VOUT – V
1
4
5
TIME – 2s/DIV
TPC 10. IOUT at Zero Scale vs. VOUT
TIME – 5s/DIV
TPC 11. AD7390 Midscale Transition Performance
100s
2.0
5
1.8
–5
GAIN – dB
VDD = 5V
VREF = 2.5V
LD
(5V/DIV)
–10
–15
–20
–25
fCLK = 50kHz
–30
–35
1V
–40
100
TIME – 100s/DIV
TPC 13. AD7390 Large Signal
Settling Time
VDD = 5V
VREF = 50mV 2V dc
DATA = FFFH
1k
10k
FREQUENCY – Hz
TPC 14. AD7390 Gain vs.
Frequency
1.2
SAMPLE SIZE = 50
1.0
0.8
CODE = FFFH
0.6
0.4
CODE = 000H
0.2
0.0
0
100
200
300
400
500
600
HOURS OF OPERATION AT 150C
TPC 16. AD7390 Long-Term Drift
Accelerated by Burn-In
REV. A
TPC 12. Digital Feedthrough
10
0
VOUT
(1V/DIV)
–7–
CLK
(5V/DIV)
5mV
INTEGRAL NONLINEARITY – LSB
IOUT – mA
30
NOMINAL CHANGE IN VOLTAGE – mV
VDD = 5V
VREF = 2.5V
fCLK = 50kHz
5s
1.6
1.4
1.2
1.0
0.8
0.6
VDD = 5V
CODE = 768H
TA = 25C
0.4
0.2
100k
0.0
0
1
2
3
4
REFERENCE VOLTAGE – V
TPC 15. AD7390 INL Error vs.
Reference Voltage
5
AD7390/AD7391
OPERATION
VDD
The AD7390 and AD7391 are a set of pin compatible, 12-bit/
10-bit digital-to-analog converters. These single-supply operation devices consume less than 100 microamps of current while
operating from power supplies in the 2.7 V to 5.5 V range making them ideal for battery operated applications. They contain a
voltage-switched, 12-bit/10-bit, laser-trimmed digital-to-analog
converter, rail-to-rail output op amps, serial-input register, and
a DAC register. The external reference input has constant input
resistance independent of the digital code setting of the DAC.
In addition, the reference input can be tied to the same supply
voltage as VDD resulting in a maximum output voltage span of
0 to VDD. The SPI compatible, serial-data interface consists of
a serial data input (SDI), clock (CLK), and load (LD) pins.
A CLR pin is available to reset the DAC register to zero-scale.
This function is useful for power-on reset or system failure
recovery to a known state.
The rail-to-rail output stage provides ± 1 mA of output current.
The N-channel output pull-down MOSFET shown in Figure 5
has a 35 Ω ON resistance, which sets the sink current capability
near ground. In addition to resistive load driving capability, the
amplifier has also been carefully designed and characterized for
up to 100 pF capacitive load driving capability.
D/A CONVERTER SECTION
REFERENCE INPUT
P-CH
N-CH
VOUT
AGND
Figure 5. Equivalent Analog Output Circuit
The reference input terminal has a constant input-resistance
independent of digital code which results in reduced glitches on
the external reference voltage source. The high 2 MΩ inputresistance minimizes power dissipation within the AD7390/
AD7391 D/A converters. The VREF input accepts input voltages
ranging from ground to the positive-supply voltage VDD. One of
the simplest applications which saves an external reference
voltage source is connection of the VREF terminal to the positive
VDD supply. This connection results in a rail-to-rail voltage
output span maximizing the programmed range. The reference
input will accept ac signals as long as they are kept within the
supply voltage range, 0 < VREF IN < VDD. The reference bandwidth and integral nonlinearity error performance are plotted in
the typical performance section (see TPCs 14 and 15). The
ratiometric reference feature makes the AD7390/AD7391 an
ideal companion to ratiometric analog-to-digital converters such
as the AD7896.
The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the
VREF pin according to the following equation:
D
(1)
2N
where D is the decimal data word loaded into the DAC register,
and N is the number of bits of DAC resolution. In the case of the
10-bit AD7391 using a 2.5 V reference, Equation 1 simplifies to:
VOUT = VREF ×
D
(2)
1024
Using Equation 2 the nominal midscale voltage at VOUT is
1.25 V for D = 512; full-scale voltage is 2.497 V. The LSB step
size is = 2.5 1/1024 = 0.0024 V.
VOUT = 2.5 ×
For the 12-bit AD7390 operating from a 5.0 V reference
Equation 1 becomes:
POWER SUPPLY
VOUT
D
= 5.0 ×
4096
The very low power consumption of the AD7390/AD7391 is a
direct result of a circuit design optimizing the use of a CBCMOS
process. By using the low power characteristics of CMOS for the
logic, and the low noise, tight-matching of the complementary
bipolar transistors, excellent analog accuracy is achieved. One
advantage of the rail-to-rail output amplifiers used in the AD7390/
AD7391 is the wide range of usable supply voltage. The part is
fully specified and tested for operation from 2.7 V to 5.5 V.
(3)
Using Equation 3 the AD7390 provides a nominal midscale
voltage of 2.5 V for D = 2048, and a full-scale output of 4.998 V.
The LSB step size is = 5.0 1/4096 = 0.0012 V.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power consumption precision amplifier. The op amp has a 60 µs typical
settling time to 0.1% of full scale. There are slight differences in
settling time for negative slewing signals versus positive. Also,
negative transition settling time to within the last 6 LSBs of zero
volts has an extended settling time. The rail-to-rail output stage
of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 5
shows an equivalent output schematic of the rail-to-rail amplifier with its N-channel pull-down FETs that will pull an output
load directly to GND. The output sourcing current is provided
by a P-channel pull-up device that can source current to GND
terminated loads.
POWER SUPPLY BYPASSING AND GROUNDING
Precision analog products, such as the AD7390/AD7391, require
a well filtered power source. Since the AD7390/AD7391 operates
from a single 3 V to 5 V supply, it seems convenient to simply tap
into the digital logic power supply. Unfortunately, the logic supply is often a switch-mode design, which generates noise in the
20 kHz to 1 MHz range. In addition, fast logic gates can generate
glitches hundred of millivolts in amplitude due to wiring resistance and inductance. The power supply noise generated thereby
means that special care must be taken to assure that the inherent
precision of the DAC is maintained. Good engineering judgment
should be exercised when addressing the power supply grounding and bypassing of the AD7390.
–8–
REV. A
AD7390/AD7391
The AD7390 should be powered directly from the system
power supply. This arrangement, shown in Figure 6, employs an
LC filter and separate power and ground connections to isolate
the analog section from the logic switching transients.
TTL/CMOS
LOGIC
CIRCUITS
FERRITE BEAD:
TWO TURNS, FAIR-RITE
#2677006301
5V
100F
ELECT.
10F–22F
TANTALUM
0.1F
CERAMIC
CAPACITOR
5V
RETURN
5V
POWER SUPPLY
Figure 6. Use Separate Traces to Reduce Power
Supply Noise
Whether or not a separate power supply trace is available, however, generous supply bypassing will reduce supply-line induced
errors. Local supply bypassing consisting of a 10 µF tantalum
electrolytic in parallel with a 0.1 µF ceramic capacitor is recommended in all applications (Figure 7).
2.7V TO 5.5V
*
LD
CLK
SDI
CLR
8
7
REF
VDD
C
1
2
3
4
AD7390
0.1F
6
OR
10F
VOUT
AD7391
GND
supply current showing that negligible current consumption
takes place when logic levels are in their quiescent state. The
normal crossover current still occurs during logic transitions. A
secondary advantage of this Schmitt trigger is the prevention of
false triggers that would occur with slow moving logic transitions when a standard CMOS logic interface or opto isolators
are used. The logic inputs SDI, CLK, LD, CLR all contain the
Schmitt trigger circuits.
DIGITAL INTERFACE
The AD7390/AD7391 have a double-buffered serial data input.
The serial-input register is separate from the DAC register,
which allows preloading of a new data value into the serial register without disturbing the present DAC values. A functional
block diagram of the digital section is shown in Figure 4, while
Table I contains the truth table for the control logic inputs.
Three pins control the serial data input. Data at the Serial Data
Input (SDI) is clocked into the shift register on the rising edge
of CLK. Data is entered in MSB-first format. Twelve clock
pulses are required to load the 12-bit AD7390 DAC value. If
additional bits are clocked into the shift register, for example
when a microcontroller sends two 8-bit bytes, the MSBs are
ignored (Figure 9). The CLK pin is only enabled when Load
(LD) is high. The lower resolution 10-bit AD7391 contains a
10-bit shift register. The AD7391 is also loaded MSB first with
10 bits of data. Again if additional bits are clocked into the shift
register, only the last 10 bits clocked in are used.
The Load pin (LD) controls the flow of data from the shift
register to the DAC register. After a new value is clocked into
the serial-input register, it will be transferred to the DAC register
by the negative transition of the Load pin (LD).
5
BYTE 1
BYTE 0
LSB MSB
MSB
*OPTIONAL EXTERNAL
REFERENCE BYPASS
B15 B14 B13 B12 B11 B10 B9
Figure 7. Recommended Supply Bypassing
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protection
structure (Figure 8) that allows logic input voltages to exceed the
VDD supply voltage. This feature can be useful if the user is driving
one or more of the digital inputs with a 5 V CMOS logic inputvoltage level while operating the AD7390/AD7391 on a 3 V power
supply. If this mode of interface is used, make sure that the VOL
of the 5 V CMOS meets the VIL input requirement of the AD7390/
AD7391 operating at 3 V. See TPC 6 for a graph for digital
logic input threshold versus operating VDD supply voltage.
VDD
LOGIC
IN
GND
Figure 8. Equivalent Digital Input ESD Protection
In order to minimize power dissipation from input-logic levels that
are near the VIH and VIL logic input voltage specifications, a
Schmitt trigger design was used that minimizes the input-buffer
current consumption compared to traditional CMOS input
stages. TPC 5 shows a plot of incremental input voltage versus
REV. A
X
X
X
X
X
X
X
X
D11 D10 D9
X
X
D9
LSB
B8
B7
B6
B5
B4
B3
B2
B1
B0
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
D11–D0: 12-BIT AD7390 DAC VALUE; D9–D0: 10-BIT AD7391 DAC VALUE
X = DON’T CARE
THE MSB OF BYTE 1 IS THE FIRST BIT THAT IS LOADED INTO THE DAC
Figure 9. Typical AD7390-Microprocessor Serial Data
Input Forms
RESET (CLR) PIN
Forcing the CLR pin low will set the DAC register to all zeros
and the DAC output voltage will be zero volts. The reset function
is useful for setting the DAC outputs to zero at power-up or
after a power supply interruption. Test systems and motor
controllers are two of many applications which benefit from
powering up to a known state. The external reset pulse can be
generated by the microprocessor’s power-on RESET signal, by
an output from the microprocessor, or by an external resistor
and capacitor. CLR has a Schmitt trigger input which results in
a clean reset function when using external resistor/capacitor
generated pulses. The CLR input overrides other logic inputs,
specifically LD. However, LD should be set high before CLR
goes high. If CLR is kept low, then the contents of the shift
register will be transferred to the DAC register as soon as CLR
returns high. See the Control-Logic Truth Table I.
–9–
AD7390/AD7391
gain setting resistors, which should have low temperature coefficients to maintain accuracy and matching (preferably the same
material, such as metal film). If better stability is required, the power
supply could be substituted with a precision reference voltage such
as the low dropout REF195, which can easily supply the circuit’s
162 µA of current, and still provide additional power for the
load connected to VO. The micropower REF195 is guaranteed
to source 10 mA output drive current, but only consumes 50 µA
internally. If higher resolution is required, the AD7390 can be
used with the addition of two more bits of data inserted into the
software coding, which would result in a 2.5 mV LSB step size.
Table V shows examples of nominal output voltages VO provided
by the Bipolar Operation circuit application.
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7390. As shown
in Figure 10, the AD7390 has been designed to drive loads as
low as 5 kΩ in parallel with 100 pF. The code table for this
operation is shown in Table IV.
2.7V TO 5.5V
R
0.01F
0.1F
10F
RL
5k
CL
100pF
7
EXT
REF
C
RS
REF
LD
3
CLK
2
AD7390
VOUT
SDI 1
CLR
4
VDD
GND
6
ISY < 162A
5
+5V
470k
Figure 10. AD7390 Unipolar Output Operation
470k
< 50A
< 100A
+5V
Table IV. AD7390 Unipolar Code Table
REF
Hexadecimal
Number
in DAC Register
Decimal
Number
in DAC Register
Output
Voltage (V)
VREF = 2.5 V
FFF
801
800
7FF
000
4095
2049
2048
2047
0
2.4994
1.2506
1.2500
1.2494
0
C
AD7391
OP196
VOUT
VO
BIPOLAR
OUTPUT
SWING
–5V
GND
–5V
DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY
Figure 11. Bipolar Output Operation
Table V. Bipolar Code Table
The circuit can be configured with an external reference plus
power supply, or powered from a single dedicated regulator or
reference, depending on the application performance requirements.
BIPOLAR OUTPUT OPERATION
Although the AD7391 has been designed for single-supply operation, the output can be easily configured for bipolar operation.
A typical circuit is shown in Figure 11. This circuit uses a clean
regulated 5 V supply for power, which also provides the circuit’s
reference voltage. Since the AD7391 output span swings from
ground to very near 5 V, it is necessary to choose an external
amplifier with a common-mode input voltage range that extends
to its positive supply rail. The micropower consumption OP196 has
been designed just for this purpose and results in only 50 microamps of maximum current consumption. Connection of the equally
valued 470 kΩ resistors results in a differential amplifier mode
of operation with a voltage gain of two, which results in a circuit
output span of ten volts, that is, 25 V to 15 V. As the DAC is
programmed with zero-code 000H to midscale 200H to full-scale
3FFH, the circuit output voltage VO is set at 25 V, 0 V and 15 V
(minus 1 LSB). The output voltage VO is coded in offset binary
according to Equation 4.
D
VO =
– 1 × 5
512
VDD
(4)
where D is the decimal code loaded in the AD7391 DAC register.
Note that the LSB step size is 10/1024 = 10 mV. This circuit has
been optimized for micropower consumption including the 470 kΩ
Hexadecimal
Number
in DAC Register
Decimal
Number
in DAC Register
Analog
Output
Voltage (V)
3FF
201
200
1FF
000
1023
513
512
511
0
4.9902
0.0097
0.0000
–0.0097
–5.0000
MICROCOMPUTER INTERFACES
The AD7390 serial data input provides an easy interface to a
variety of single-chip microcomputers (µCs). Many µCs have a
built-in serial data capability which can be used for communicating with the DAC. In cases where no serial port is provided,
or it is being used for some other purpose (such as an RS-232
communications interface), the AD7390/AD7391 can easily be
addressed in software.
Twelve data bits are required to load a value into the AD7390.
If more than 12 bits are transmitted before the load LD input
goes high, the extra (i.e., the most-significant) bits are ignored.
This feature is valuable because most µCs only transmit data
in 8-bit increments. Thus, the µC sends 16 bits to the DAC
instead of 12 bits. The AD7390 will only respond to the last
12 bits clocked into the SDI input, however, so the serial-data
interface is not affected.
Ten data bits are required to load a value into the AD7391. If
more than 10 bits are transmitted before load LD returns high,
the extra bits are ignored.
–10–
REV. A
AD7390/AD7391
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(R-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0196 (0.50)
45
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
8
0.0500 (1.27)
0.0098 (0.25) 0
0.0160 (0.41)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
8-Lead Plastic DIP
(N-8)
0.430 (10.92)
0.348 (8.84)
8
5
PIN 1
0.280 (7.11)
0.240 (6.10)
4
1
0.325 (8.25)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15) PLANE
8-Lead TSSOP
(RU-8)
0.122 (3.10)
0.114 (2.90)
8
5
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
4
PIN 1
0.0256 (0.65)
BSC
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
REV. A
0.0118 (0.30)
0.0075 (0.19)
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
–11–
8
0
0.028 (0.70)
0.020 (0.50)
AD7390/AD7391
Revision History
Location
Page
Data Sheet changed from REV. 0 to REV. A.
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edit to Figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
PRINTED IN U.S.A.
Edit to TPC 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
C01120–0–2/02(A)
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
–12–
REV. A
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