AD7395

a FEATURES Micropower: 100 A/DAC 0.1 A Typical Power Shutdown Single-Supply +2.7 V to +5.5 V Operation Compact 1.1 mm Height TSSOP-14 Package AD7394/12-Bit Resolution AD7395/10-Bit Resolution Serial Interface with Schmitt Trigger Inputs APPLICATIONS Automotive Output Span Voltage Portable Communications Digitally Controlled Calibration PC Peripherals CS CLK EN +3 V, Dual, Serial Input 12-/10-Bit DACs AD7394/AD7395 FUNCTIONAL BLOCK DIAGRAM VDD VREF OP AMP A DAC A VOUTA R E DG AI CS T AE R D S H I F T R E G I S T E R PR 12 SDI (DATA) AD7394/AD7395 D R E DG AI CS T BE R PR OP AMP B DAC B VOUTB LDA GENERAL DESCRIPTION LDB The AD7394/AD7395 family of dual, 12-/10-bit, voltage output digital-to-analog converters is designed to operate from a single +3 V supply. Built using a CBCMOS process, this monolithic DAC offers the user low cost and ease of use in single-supply +3 V systems. Operation is guaranteed over the supply voltage range of +2.7 V to +5.5 V making this device ideal for battery operated applications. The full-scale output voltage is determined by the applied external reference input voltage, VREF. The rail-to-rail VREF input to VOUT outputs allows for a full-scale voltage set equal to the positive supply VDD or any value in between. A doubled-buffered serial data interface offers high speed, microcontroller compatible inputs using serial-data-in (SDI), clock (CLK) and load strobe (LDA + LDB) pins. A chip-select (CS) pin simplifies connection of multiple DAC packages by enabling the clock input when active low. Additionally, an RS input sets the output to zero scale or to 1/2 scale based on the logic level applied to the MSB pin. The power shutdown pin, SHDN, reduces power dissipation to nanoamp current levels. All digital inputs contain Schmitt-triggered logic levels to minimize power dissipation and prevent false triggering on the clock input. Both parts are offered in the same pinout to allow users to select the amount of resolution appropriate for their application without circuit card redesign. DGND MSB RS AGND SHDN The AD7394/AD7395 is specified over the extended industrial (–40°C to +85°C) temperature range. Packages available include plastic DIP and low profile 1.75 mm height SO-14 surface mount packages. The AD7395ARU is available for ultracompact applications in a thin 1.1 mm TSSOP-14 package. For automotive applications the AD7395AR is specified for operation over the (–40°C to +125°C) temperature range. 1 0.8 0.6 0.4 DNL – LSB VDD = 3V VREF = 2.5V 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 TA = –55 C, +25 C, +85 C SUPERIMPOSED 500 1000 1500 2000 2500 CODE – Decimal 3000 3500 4000 Figure 1. Differential Nonlinearity Error vs. Code R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD7394/AD7395–SPECIFICATIONS AD7394 12-BIT RAIL-TO-RAIL VOLTAGE OUT DAC ELECTRICAL CHARACTERISTICS (@ V = 2.5 V, –40 C < T < +85 C, unless otherwise noted) REF IN A Parameter STATIC PERFORMANCE Resolution1 Relative Accuracy2 Relative Accuracy2 Differential Nonlinearity2 Differential Nonlinearity2 Zero-Scale Error Full-Scale Voltage Error Full-Scale Voltage Error Full-Scale Tempco3 REFERENCE INPUT VREF IN Range Input Resistance Input Capacitance3 ANALOG OUTPUT Output Current (Source) Output Current (Sink) Capacitive Load3 LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance3 INTERFACE TIMING3, 5 Clock Width High Clock Width Low Load Pulsewidth Data Setup Data Hold Clear Pulsewidth Load Setup Load Hold AC CHARACTERISTICS Output Slew Rate Settling Time6 DAC Glitch Digital Feedthrough Feedthrough SUPPLY CHARACTERISTICS Power Supply Range Shutdown Supply Current Positive Supply Current Power Dissipation Power Supply Sensitivity Symbol N INL INL DNL DNL VZSE VFSE VFSE TCVFS VREF RREF CREF IOUT IOUT CL VIL VIH IIL CIL tCH tCL tLDW tDS tDH tCLRW tLD1 tLD2 SR tS Q Q VOUT/VREF Conditions 3V 12 ± 1.5 ± 2.0 ± 0.9 ±1 4.0 ±8 ± 20 –30 0/VDD 2.5 5 10% 5V 12 ± 1.5 ± 2.0 ± 0.9 ±1 4.0 ±8 ± 20 –30 0/VDD 2.5 5 1 3 100 0.8 4.0 10 10 30 30 20 10 15 15 15 20 0.05 60 65 15 –63 10% Units Bits LSB max LSB max LSB max LSB max mV max mV max mV max ppm/°C typ V min/max MΩ typ4 pF typ mA typ mA typ pF typ V max V min µA max pF max ns min ns min ns min ns min ns min ns min ns min ns min V/µs typ µs typ nV/s typ nV/s typ dB typ V min/max µA typ/max µA typ/max µW max %/% max TA = +25°C TA = –40°C, +85°C TA = +25°C, Monotonic Monotonic Data = 000H TA = +25°C, +85°C, Data = FFFH TA = –40°C, Data = FFFH Data = 800H, ∆VOUT = 5 LSB Data = 800H, ∆VOUT = 5 LSB No Oscillation 1 3 100 0.5 VDD–0.6 10 10 50 50 30 10 30 15 30 40 Data = 000H to FFFH to 000H To ± 0.1% of Full Scale Code 7FFH to 800H to 7FFH VREF = 1.5 VDC +1 V p-p, Data = 000H, f = 100 kHz DNL < ± 1 LSB SHDN = 0, VIL = 0 V, No Load VIL = 0 V, No Load VIL = 0 V, No Load ∆VDD = ± 5% 0.05 70 65 15 –63 2.7/5.5 0.1/1.5 125/200 600 0.006 VDD RANGE IDD_SD IDD PDISS PSS 2.7/5.5 0.1/1.5 125/200 1000 0.006 NOTES 1 One LSB = V REF/4096 V for the 12-bit AD7394. 2 The first two codes (000 H, 001H) are excluded from the linearity error measurement. 3 These parameters are guaranteed by design and not subject to production testing. 4 Typicals represent average readings measured at +25 °C. 5 All input control signals are specified with t R = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V. 6 The settling time specification does not apply for negative going transitions within the last three LSBs of ground. Specifications subject to change without notice. – 2– REV. 0 AD7394/AD7395 AD7395 10-BIT RAIL-TO-RAIL VOLTAGE OUT DAC ELECTRICAL CHARACTERISTICS (@ V = 2.5 V, –40 C < T < +85 C/+125 C, unless otherwise noted) REF IN A Parameter STATIC PERFORMANCE Resolution1 Relative Accuracy2 Relative Accuracy2 Differential Nonlinearity2 Zero-Scale Error Full-Scale Voltage Error Full-Scale Voltage Error Full-Scale Tempco3 REFERENCE INPUT VREF IN Range Input Resistance Input Capacitance3 ANALOG OUTPUT Output Current (Source) Output Current (Sink) Capacitive Load3 LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance3 INTERFACE TIMING3, 5 Clock Width High Clock Width Low Load Pulsewidth Data Setup Data Hold Clear Pulsewidth Load Setup Load Hold AC CHARACTERISTICS Output Slew Rate Settling Time6 DAC Glitch Digital Feedthrough Feedthrough SUPPLY CHARACTERISTICS Power Supply Range Shutdown Supply Current Positive Supply Current Power Dissipation Power Supply Sensitivity Symbol N INL INL DNL VZSE VFSE VFSE TCVFS VREF RREF CREF IOUT IOUT CL VIL VIH IIL CIL tCH tCL tLDW tDS tDH tCLRW tLD1 tLD2 SR tS Q Q VOUT/VREF Conditions 3V 10 ± 1.5 ± 2.0 ±1 9.0 ± 42 ± 48 –35 0/VDD 2.5 5 10% 5V 10 ± 1.5 ± 2.0 ±1 9.0 ± 42 ± 48 –35 0/VDD 2.5 5 1 3 100 0.8 4.0 10 10 30 30 20 10 15 15 15 20 0.05 60 65 15 –63 10% Units Bits LSB max LSB max LSB max mV max mV max mV max ppm/°C typ V min/max MΩ typ4 pF typ mA typ mA typ pF typ V max V min µA max pF max ns min ns min ns min ns min ns min ns min ns min ns min V/µs typ µs typ nV/s typ nV/s typ dB typ V min/max µA typ/max µA typ/max µW max %/% max TA = +25°C TA = –40°C, +85°C, +125°C Monotonic Data = 000H TA = +25°C, +85°C, +125°C Data = FFFH TA = –40°C, Data = FFFH Data = 200H, ∆VOUT = 5 LSB Data = 200H, ∆VOUT = 5 LSB No Oscillation 1 3 100 0.5 VDD–0.6 10 10 50 50 30 10 30 15 30 40 Data = 000H to 3FFH to 000H To ± 0.1% of Full Scale Code 7FFH to 800H to 7FFH VREF = 1.5 VDC +1 V p-p, Data = 000H, f = 100 kHz DNL < ± 1 LSB SHDN = 0, VIL = 0 V, No Load VIL = 0 V, No Load VIL = 0 V, No Load ∆VDD = ± 5% 0.05 70 65 15 –63 2.7/5.5 0.1/1.5 125/200 600 0.006 VDD RANGE IDD_SD IDD PDISS PSS 2.7/5.5 0.1/1.5 125/200 1000 0.006 NOTES 1 One LSB = VREF/4096 V for the 10-bit AD7395. 2 The first two codes (000 H, 001H) are excluded from the linearity error measurement. 3 These parameters are guaranteed by design and not subject to production testing. 4 Typicals represent average readings measured at +25 °C. 5 All input control signals are specified with t R = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V. 6 The settling time specification does not apply for negative going transitions within the last three LSBs of ground. Specifications subject to change without notice. REV. 0 – 3– AD7394/AD7395 SDI D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK CS LDA,B tCSS tLD1 tDS tDH tCSH tLD2 SDI CLK LDA,B RS VOUT FS ZS tCL tCH tLDW tCLRW tS tS 1 LSB ERROR BAND Figure 2. Timing Diagram SHDN tSDR IDD Figure 3. Timing Diagram Table I. Control Logic Truth Table CS CLK H L L L L L ↑+ H H X X X X X X L H ↑+ ↑+ H L X X X X X X X RS H H H H H H H H H L ↑+ L ↑+ X MSB X X X X X X X X X H H L L X SHDN H H H H H H H H H H H H H L LDA/B H H H H L L H ↓– L X H X H X Serial Shift Register Function No Effect No Effect No Effect Shift-Register-Data Advanced One Bit Shift-Register-Data Advanced One Bit No Effect No Effect No Effect No Effect No Effect No Effect No Effect No Effect No Effect DAC Register Function Latched Latched Latched Latched Transparent Transparent Latched Updated with Current Shift Register Contents Transparent Loaded with 800H Latched with 800H Loaded with All Zeros Latched All Zeros No Affect NOTES 1. ↑+ positive logic transition; ↓– negative logic transition; X Don’t Care 2. Do not clock in serial data while level sensitive inputs LDA or LDB are logic LOW. –4– REV. 0 AD7394/AD7395 Table II. AD7394 Serial Input Register Data Format, Data Is Loaded in MSB-First Format MSB B11 AD7394 D11 B10 D10 B9 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 LSB B0 D0 Table III. AD7395 Serial Input Register Data Format, Data Is Loaded in MSB-First Format MSB B9 AD7395 D9 B8 D8 B7 D7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 LSB B0 D0 ABSOLUTE MAXIMUM RATINGS* VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V VOUT to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/θJA Thermal Resistance θJA 14-Lead Plastic DIP Package (N-14) . . . . . . . . . . 103°C/W 14-Lead SOIC Package (R-14) . . . . . . . . . . . . . . . 158°C/W 14-Lead Thin Shrink Surface Mount (RU-14) . . . 180°C/W Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C Operating Temperature Range . . . . . . . . . . . –40°C to +85°C AD7395AR and AD7395AN Only . . . . . . –40°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature N-14 (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . . +300°C R-14 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . . . . . . . +215°C RU-14 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . . . +224°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model AD7394AN AD7394AR AD7395AN AD7395AR AD7395ARU Res (LSB) 12 12 10 10 10 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +125°C –40°C to +125°C –40°C to +85°C Package Description 14-Lead P-DIP 14-Lead SOIC 14-Lead P-DIP 14-Lead SOIC 14-Lead Thin Shrink Small Outline Package (TSSOP) Package Options N-14 R-14 N-14 R-14 RU-14 The AD7394/AD7395 contains 709 transistors. The die size measures 70 mil × 99 mil. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7394/AD7395 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –5– AD7394/AD7395 PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Name AGND VOUTA VREF DGND CS CLK SDI LDA RS LDB MSB SHDN Function Analog Ground. DAC A Voltage Output. DAC Reference voltage input terminal. Establishes DAC full-scale output voltage. Pin can be tied to VDD pin. Digital Ground. Should be tied to analog GND. Chip Select, active low input. Disables shift register loading when high. Does not effect LDA or LDB operation. Clock input, positive edge clocks data into shift register, MSB data bit first. Serial Data Input, input data loads directly into the shift register. Load DAC register strobe, level sensitive active low. Transfers shift register data to DAC A register. Asynchronous active low input. See Control Logic Truth Table for operation. Resets DAC register to zero condition or half-scale, depending on MSB pin logic level. Asynchronous active low input. Load DAC register strobe, level-sensitive active low. Transfers shift register data to DAC B register. Asynchronous active low input. See Control Logic Truth Table for operation. Digital Input: Logic High presets DAC registers to half-scale 800H (sets MSB bit to one) when the RS pin is strobed; Logic Low clears all DAC registers to zero (000H) when the RS pin is strobed. Active low shutdown control input. Does not affect register contents as long as power is present on VDD. New data can be loaded into the shift register and DAC register during shutdown. When device is powered up the most recent data loaded into the DAC register will control the DAC output. Positive power supply input. Specified range of operation +2.7 V to +5.5 V DAC B Voltage Output. 13 14 VDD VOUTB PIN CONFIGURATIONS AGND 1 VOUTA 2 VREF 3 DGND 4 14 VOUTB 13 VDD AD7394 AD7395 12 SHDN TOP VIEW 11 MSB CS 5 (Not to Scale) 10 LDB 9 8 CLK 6 SDI 7 RS LDA –6– REV. 0 Typical Performance Characteristics– AD7394/AD7395 1.5 TA = –55 C 1 VDD = 3V VREF = 2.5V 25 SS = 200 UNITS TA = +25 C VDD = 2.7V VREF = 2.5V 50 AD7394 40 FREQEUENCY 20 FREQUENCY SS = 200 UNITS TA = +25 C VDD = 2.7V VREF = 2.5V AD7395 0.5 INL – LSB 15 30 0 10 20 –0.5 TA = +25 C, +85 C –1 5 10 –1.5 0 500 1000 1500 2000 2500 3000 3500 4000 CODE – Decimal 0 0 1 3 2 1 TOTAL UNADJUSTED ERROR – LSB 0 –5 5 10 15 0 TOTAL UNAJUSTED ERROR – LSB Figure 4. AD7394 Integral Nonlinearity Error vs. Code Figure 5. Total Unadjusted Error Histogram Figure 6. Total Unadjusted Error Histogram 35 AD7395 30 25 FREQUENCY SS = 200, VDD = 2.7V VREF = 2.5V TA = +85 C TO –40 C 0.6 30 AD7394 25 0.5 AD7394 TA = +25 C 20 VDD = 5.0V TA = +25 C CODE = 768H 0.4 15 20 15 10 5 0 FSE – LSB INL – LSB 10 5 0 5 0.3 TOTAL UNADJUSTED FULL SCALE ERROR 0.2 0.1 10 FULL SCALE ERROR 26 28 30 32 34 36 TEMPCO – ppm/ C 38 40 0 0 0.5 1 1.5 2 2.5 3 3.5 VREF – Volts 4 4.5 5 15 0 0.5 1 1.5 2 2.5 3 3.5 VREF – Volts 4 4.5 5 Figure 7. Full-Scale Output Tempco Histogram Figure 8. Integral Nonlinearity Error vs. VREF Figure 9. Full-Scale Error vs. VREF 10 OUTPUT NOISE DENSITY – V/ Hz LOGIC THRESHOLD – V 8 VDD = 5V VREF = 2.5V TA = +25 C 140 VDD = 3V 135 130 5 AD7394 4.5 4 3.5 3 2.5 2 1.5 1 VLOGIC FROM LOW TO HIGH AD7394 IDD – A 6 125 120 115 110 VIN 3V TO 0V VIN 0V TO 3V 4 2 105 0 VLOGIC FROM HIGH TO LOW 2 3 4 5 VDD – Volts 6 7 1 10 100 1k 10k FREQUENCY – Hz 100k 100 0 0.5 1 1.5 2 VIN – Volts 2.5 3 Figure 10. AD7394 Output Noise Density vs. Frequency Figure 11. Supply Current vs. Logic Input Voltage Figure 12. Logic Threshold vs. Supply Voltage REV. 0 –7– AD7394/AD7395 1800 80 20 AD7394 1600 1400 1200 IDD – A 1000 800 600 400 200 0 1k 10k 100k 1M CLOCK FREQUENCY – Hz 10M A B C A: IDD = 2.7V, CODE = 555H B: IDD = 2.7V, CODE = 3FFH C: VDD = 5.5V, CODE = 155H D: VDD = 5.5V, CODE = 3FFH TA = +25 C CURRENT SINKING – mA 70 60 VDD = 5.0V, D PSRR – dB 18 16 14 12 10 8 6 4 2 0 VDD = 5V VREF = 2.5V CODE = 800H 5% 50 40 30 20 10 0 1 10 100 1k FREQUENCY – Hz 10k VDD = 3.0V, 5% VDD = 3V 0 1 2 3 4 56 7 VOUT – LSB 8 9 10 Figure 13. Supply Current vs. Clock Frequency Figure 14. AD7394 Power Supply Rejection vs. Frequency Figure 15. AD7394 IOUT Sink Current vs. ∆VOUT 10 9 VREF = 2.5V CODE = 800H VDD = 5V 1.262 VDD = +5V VREF = 2.5V TA = +25 C CODE = 800H TO 7FFH 5mV/DIV 0 5 10 15 VDD = 5V CODE = FFFH CURRENT SOURCING – mA 8 7 6 5 4 3 2 1 0 10 9 8 7 6 5 43 VOUT – LSB 2 1 0 VDD = 3V 1.257 VOUT – Volts 1.252 GAIN – dB 20 25 30 35 1.247 1.242 40 45 1.237 TIME – 2 s/DIV 50 100 10k 1k FREQUENCY – Hz 100k Figure 16. AD7394 IOUT Source Current vs. ∆VOUT Figure 17. Midscale Transition Performance Figure 18. AD7395 Reference Multiplying Bandwidth 1.4 AD7394 NOMINAL CHANGE IN VOUT – mV 1.2 1 CODE = FFFH 0.8 0.6 CODE = 000H 0.4 0.2 0 0 200 300 400 500 100 HOURS OF OPERATION – 150 C 600 Figure 19. Long-Term Drift Accelerated by Burn-In –8– REV. 0 AD7394/AD7395 OPERATION AMPLIFIER SECTION The AD7394 and AD7395 are a set of pin compatible, dual, 12-bit/10-bit digital-to-analog converters. These single-supply operation devices consume less than 200 microamps of current while operating from power supplies in the +2.7 V to +5.5 V range, making them ideal for battery operated applications. They contain a voltage-switched, 12-bit/10-bit, laser trimmed digital-to-analog converter, rail-to-rail output op amps, two DAC registers and a serial input shift register. The external reference input has constant input resistance independent of the digital code setting of the DAC. In addition, the reference input can be tied to the same supply voltage as VDD, resulting in a maximum output voltage span of 0 to VDD. The serial interface consists of a serial data input (SDI), clock (CLK) and chip select pin (CS) and two load DAC Register pins (LDA and LDB). A reset (RS) pin is available to reset the DAC register to zero scale or midscale, depending on the digital level applied to the MSB pin. This function is useful for power-on reset or system failure recovery to a known state. Additional power savings are accomplished by activating the SHDN pin resulting in a 1.5 µA maximum consumption sleep mode. D/A CONVERTER SECTION The internal DAC’s output is buffered by a low power consumption precision amplifier. The op amp has a 60 µs typical settling time to 0.1% of full scale. There are slight differences in settling time for negative slewing signals versus positive. Also, negative transition settling time to within the last 6 LSBs of zero volts has an extended settling time. The rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 20 shows an equivalent output schematic of the rail-to-rail-amplifier with its N-channel pull-down FETs that will pull an output load directly to GND. The output sourcing current is provided by a P-channel pull-up device that can source current to GND terminated loads. VDD P-CH VOUT N-CH The voltage switched R-2R DAC generates an output voltage dependent on the external reference voltage connected to the REF pin according to the following equation: V OUT V REF × D = 2N AGND Figure 20. Equivalent Analog Output Circuit (1) where D is the decimal data word loaded into the DAC register and N is the number of bits of DAC resolution. In the case of the 10-bit AD7395 using a 2.5 V reference, Equation 1 simplifies to: The rail-to-rail output stage provides more than ± 1 mA of output current. The N-channel output pull-down MOSFET shown in Figure 20 has a 35 Ω ON resistance, which sets the sink current capability near ground. In addition to resistive load driving capability, the amplifier has also been carefully designed and characterized for up to 100 pF capacitive load driving capability. REFERENCE INPUT V OUT = 2.5 × D 1024 (2) Using Equation 2 the nominal midscale voltage at VOUT is 1.25 V for D = 512; full-scale voltage is 2.497 V. The LSB step size is = 2.5 × 1/1024 = 0.0024 V. For the 12-bit AD7394 operating from a 5.0 V reference Equation 1 becomes: V OUT = 5.0 × D 4096 (3) Using Equation 3 the AD7394 provides a nominal midscale voltage of 2.50 V for D = 2048, and a full-scale output of 4.998 V. The LSB step size is = 5.0 × 1/4096 = 0.0012 V. The reference input terminal has a constant input resistance independent of digital code which results in reduced glitches on the external reference voltage source. The high 2.5 MΩ input resistance minimizes power dissipation within the AD7394/ AD7395 D/A converters. The VREF input accepts input voltages ranging from ground to the positive supply voltage VDD. One of the simplest applications, which saves an external reference voltage source, is connection of the VREF terminal to the positive VDD supply. This connection results in a rail-to-rail voltage output span maximizing the programmed range. The reference input will accept ac signals as long as they are kept within the supply voltage range, 0 < VREF < VDD. The reference bandwidth and integral nonlinearity error performance are plotted in the Typical Performance Characteristics section (see Figures 8 and 18). The ratiometric reference feature makes the AD7394/AD7395 an ideal companion to ratiometric analog-to-digital converters such as the AD7896. REV. 0 –9– AD7394/AD7395 POWER SUPPLY The very low power consumption of the AD7394/AD7395 is a direct result of a circuit design optimizing the use of a CBCMOS process. By using the low power characteristics of CMOS for the logic, and the low noise, tight matching of the complementary bipolar transistors, excellent analog accuracy is achieved. One advantage of the rail-to-rail output amplifiers used in the AD7394/AD7395 is the wide range of usable supply voltage. The part is fully specified and tested for operation from +2.7 V to +5.5 V. Local supply bypassing consisting of a 10 µF tantalum electrolytic in parallel with a 0.1 µF ceramic capacitor is recommended in all applications (Figure 21). +2.7V TO +5.5V C REF CS LDA, B CLK SDI RS *OPTIONAL EXTERNAL REFERENCE BYPASS DGND AGND VDD logic transitions when a standard CMOS logic interface or opto isolators are used. The logic inputs SDI, CLK, CS, LDA, LDB, RS, SHDN all contain the Schmitt trigger circuits. CS CLK DAC A REGISTER SDI D P R EN POWER SUPPLY BYPASSING AND GROUNDING SHIFT REGISTER DAC B REGISTER Q D P R * 0.1 F 10 F LDA LDB RS MSB Figure 23. Equivalent Digital Interface Logic VOUTA VOUTB AD7394 OR AD7395 DIGITAL INTERFACE Figure 21. Recommended Supply Bypassing for the AD7394/AD7395 INPUT LOGIC LEVELS All digital inputs are protected with a Zener-type ESD protection structure (Figure 22) that allows logic input voltages to exceed the VDD supply voltage. This feature can be useful if the user is driving one or more of the digital inputs with a 5 V CMOS logic input-voltage level while operating the AD7394/AD7395 on a +3 V power supply. If this mode of interface is used, make sure that the VOL of the 5 V CMOS meets the VIL input requirement of the AD7394/AD7395 operating at 3 V. See Figure 12 for a graph of digital logic input threshold versus operating VDD supply voltage. VDD LOGIC IN GND Figure 22. Equivalent Digital Input ESD Protection The AD7394/AD7395 has a serial data input. A functional block diagram of the digital section is shown in Figure 23, while Table I contains the truth table for the logic control inputs. Three pins control the serial data input register loading. Two additional pins determine which DAC will receive the data loaded into the input shift register. Data at the SDI is clocked into the shift register on the rising edge of the CLK. Data is entered in the MSB-first format. The active low chip select (CS) pin enables loading of data into the shift register from the SDI pin. Twelve clock pulses are required to load the 12-bit AD7390 DAC shift register. If additional bits are clocked into the shift register, for example, when a microcontroller sends two 8-bit bytes, the MSBs are ignored (Table IV). The lowest resolution AD7395 is also loaded MSB-first with 10 bits of data. Again, if additional bits are clocked into the shift register only the last 10 bits clocked in are used. When CS returns to logic high, shiftregister loading is disabled. The load pins LDA and LDB control the flow of data from the shift register to the DAC register. After a new value is clocked into the serial-input register, it will be transferred to the DAC register associated with its LDA or LDB logic control line. Note, if the user wants to load both DAC registers with the current contents of the shift register, both control lines LDA and LDB should be strobed together. The LDA and LDB pins are level-sensitive and should be returned to logic high prior to any new data being sent to the input shift register to avoid changing the DAC register values. See Truth Table for complete set of conditions. RESET (RS) PIN In order to minimize power dissipation from input logic levels that are near the VIH and VIL logic input voltage specifications, a Schmitt trigger design was used that minimizes the inputbuffer current consumption compared to traditional CMOS input stages. Figure 11 is a plot of incremental input voltage versus supply current showing that negligible current consumption takes place when logic levels are in their quiescent state. The normal crossover current still occurs during logic transitions. A secondary advantage of this Schmitt trigger is the prevention of false triggers that would occur with slow moving Forcing the asynchronous RS pin low will set the DAC register to all zeros, or midscale, depending on the logic level applied to the MSB pin. When the MSB pin is set to logic high, both DAC registers will be reset to midscale (i.e., the DAC Register’s MSB bit will be set to Logic 1 followed by all zeros). The reset function is useful for setting the DAC outputs to zero at power-up or after a power supply interruption. Test systems and motor controllers are two of many applications that benefit from powering up to a known state. The external reset pulse can be –10– REV. 0 AD7394/AD7395 Table IV. Typical Microcontroller Interface Formats MSB B15 X X B14 X X B13 X X BYTE 1 B12 X X B11 D11 X B10 D10 X B9 D9 D9 LSB B8 D8 D8 MSB B7 D7 D7 B6 D6 D6 B5 D5 D5 BYTE 0 B4 D4 D4 B3 D3 D3 B2 D2 D2 B1 D1 D1 LSB B0 D0 D0 D11–D0: 12-bit AD7394 DAC data; D9–D0: 10-bit AD7395 DAC data; X = Don’t Care; The MSB of byte 1 is the first bit that is loaded into the SDI input. generated by the microprocessor’s power-on RESET signal, by an output from the microprocessor, or by an external resistor and capacitor. RESET has a Schmitt trigger input which results in a clean reset function when using external resistor/capacitor generated pulses. See the Control-Logic Truth Table I. POWER SHUTDOWN ( SHDN) Table V. Unipolar Code Table Hexadecimal Number in DAC Register FFF 801 800 7FF 000 Decimal Number in DAC Register 4095 2049 2048 2047 0 Output Voltage (V) [VREF = 2.5 V] 2.4994 1.2506 1.2500 1.2494 0 Maximum power savings can be achieved by using the power shutdown control function. This hardware activated feature is controlled by the active low input SHDN pin. This pin has a Schmitt trigger input which helps to desensitize it to slowly changing inputs. By placing a logic low on this pin the internal consumption of the device is reduced to nano amp levels, guaranteed to 1.5 µA maximum over the operating temperature range. When the AD7394/AD7395 has been programmed into the power shutdown state, the present DAC register data is maintained as long as VDD remains greater than 2.7 V. Once a wake-up command SHDN = 1 is given, the DAC voltage outputs will return to their previous values. It typically takes 80 microseconds for the output voltage to fully stabilize. In the shutdown state the DAC output amplifier exhibits an opencircuit with a nominal output resistance of 500 kΩ to ground. If the power shutdown feature is not needed, then the user should tie the SHDN pin to the VDD voltage thereby disabling this function. UNIPOLAR OUTPUT OPERATION The circuit can be configured with an external reference plus power supply, or powered from a single dedicated regulator or reference depending on the application performance requirements. BIPOLAR OUTPUT OPERATION This is the basic mode of operation for the AD7394. As shown in Figure 24, the AD7394 has been designed to drive loads as low as 5 kΩ in parallel with 100 pF. The code table for this operation is shown in Table V. +2.7V TO +5.5V R 0.01 F VDD VREF DAC A 75k EXT REF 5 DAC B DIGITAL DGND AGND DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY. 75k 100pF VOUTB 100pF VOUTA 0.1 F 10 F Although the AD7395 has been designed for single-supply operation, the output can easily be configured for bipolar operation. A typical circuit is shown in Figure 25. This circuit uses a clean regulated +5 V supply for power, which also provides the circuit’s reference voltage. Since the AD7395 output span swings from ground to very near +5 V, it is necessary to choose an external amplifier with a common-mode input voltage range that extends to its positive supply rail. The micropower consumption OP196 has been designed just for this purpose and results in only 50 microamps of maximum current consumption. Connection of the equally valued 470 kΩ resistors results in a differential amplifier mode of operation with a voltage gain of two, which produces a circuit output span of ten volts, that is, –5 V to +5 V. As the DAC is programmed from zero code 000H to midscale 200H to full-scale 3FFH, the circuit output voltage VO is set at –5 V, 0 V and +5 V (–1 LSB). The output voltage VO is coded in offset binary according to Equation 4.  D   V OUT =   –1 × 5  512     (4) C Figure 24. AD7394 Unipolar Output Operation where D is the decimal code loaded in the AD7395 DAC register. Note that the LSB step size is 10/1024 = 10 mV. This circuit has been optimized for micropower consumption including the 470 kΩ gain setting resistors, which should have low temperature coefficients to maintain accuracy and matching (preferably the same resistor material, such as metal film). If better stability is required, the power supply could be substituted with a precision reference voltage such as the low dropout REF195, which can easily supply the circuit’s 262 microamps of current, and still provide additional power for the load connected to VOUT. The micropower REF195 is guaranteed to source 10 mA REV. 0 –11– AD7394/AD7395 output drive current, but consumes only 50 microamps internally. If higher resolution is required, the AD7394 can be used with the addition of two more bits of data inserted into the software coding, which would result in a 2.5 mV LSB step size. Table VI shows examples of nominal output voltages, VO, provided by the Bipolar Operation circuit application. ISY < 262 A +5V 470k 200 A REF VDD 470k < 50 A VO Table VI. Bipolar Code Table Hexadecimal Number Decimal Number Analog Output in DAC Register in DAC Register Voltage (V) 3FF 201 200 1FF 000 1023 513 512 511 0 4.9902 0.0097 0.0000 –0.0097 –5.0000 +5V BIPOLAR OUTPUT SWING –5V OP196 C AD7395 GND VOUTA 5V ONLY ONE CHANNEL SHOWN. DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY. Figure 25. Bipolar Output Operation OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP Package (N-14) 0.795 (20.19) 0.725 (18.42) 14 1 8 7 Thin Surface Mount TSSOP Package (RU-14) 0.201 (5.10) 0.193 (4.90) 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 14 8 PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.177 (4.50) 0.169 (4.30) 1 7 0.256 (6.50) 0.246 (6.25) 0.100 0.070 (1.77) SEATING (2.54) 0.045 (1.15) PLANE BSC 0.015 (0.381) 0.008 (0.204) 0.006 (0.15) 0.002 (0.05) PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) SOIC Package (R-14) 0.3444 (8.75) 0.3367 (8.55) 14 1 8 7 SEATING PLANE 8 0 0.028 (0.70) 0.020 (0.50) 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 SEATING (1.27) PLANE BSC 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) 8 0 0.0500 (1.27) 0.0160 (0.41) –12– REV. 0 PRINTED IN U.S.A. C3323–8–4/98