AD7400AYRWZ-RL

Isolated Sigma-Delta Modulator AD7400A Data Sheet FEATURES GENERAL DESCRIPTION 10 MHz clock rate Second-order modulator 16 bits, no missing codes ±2 LSB INL typical at 16 bits 1.5 μV/°C typical offset drift On-board digital isolator On-board reference ±250 mV analog input range Low power operation: 15.5 mA typical at 5.5 V −40°C to +125°C operating range 16-lead SOIC package AD7401A, external clock version in 16-lead SOIC Safety and regulatory approvals UL recognition 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 891 V peak The AD7400A1 is a second-order, Σ-Δ modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7400A operates from a 5 V power supply and accepts a differential input signal of ±250 mV (±320 mV full-scale). The analog input is sampled continuously by the analog modulator, eliminating the need for external sampleand-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of 10 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). APPLICATIONS 1 The serial interface is digitally isolated. High speed CMOS, combined with monolithic air core transformer technology, means the on-chip isolation provides outstanding performance characteristics superior to alternatives such as optocoupler devices. The part contains an on-chip reference and has an operating temperature range of −40°C to +125°C. The AD7400A is offered in a 16-lead SOIC package. Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. AC motor controls Shunt current monitoring Data acquisition systems Analog-to-digital and opto-isolator replacements FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 AD7400A VIN+ T/H Σ-∆ ADC UPDATE ENCODE BUF REF CONTROL LOGIC UPDATE ENCODE GND1 WATCHDOG DECODE MDAT WATCHDOG MCLKOUT DECODE GND2 07077-001 VIN– Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7400A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .................................................................................... 12 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 13 General Description ......................................................................... 1 Circuit Information.................................................................... 13 Functional Block Diagram .............................................................. 1 Analog Input ............................................................................... 13 Revision History ............................................................................... 2 Differential Inputs ...................................................................... 14 Specifications..................................................................................... 3 Current Sensing Applications ................................................... 14 Timing Specifications .................................................................. 4 Voltage Sensing Applications .................................................... 14 Insulation and Safety-Related Specifications ............................ 5 Digital Filter ................................................................................ 15 Regulatory Information ............................................................... 5 Applications Information .............................................................. 17 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 6 Grounding and Layout .............................................................. 17 Absolute Maximum Ratings............................................................ 7 Insulation Lifetime ..................................................................... 17 ESD Caution .................................................................................. 7 Outline Dimensions ....................................................................... 18 Pin Configuration and Function Descriptions ............................. 8 Ordering Guide .......................................................................... 18 Evaluating the AD7400A Performance ................................... 17 Typical Performance Characteristics ............................................. 9 REVISION HISTORY 4/2018—Rev. D to Rev. E Changes to Table 3 and Table 4 ....................................................... 5 11/2012—Rev. C to Rev. D Deleted 8-Lead PDIP ......................................................... Universal Change to Note 1 .............................................................................. 1 Deleted Figure 5 and Renumbered Sequentially .......................... 8 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 7/2011—Rev. B to Rev. C Changes to Minimum External Air Gap (Clearance) Parameter, Table 3 and Minimum External Tracking (Creepage) Parameter, Table 3 ................................................................................................ 5 Changes to Figure 6; Pin 1 Description, Table 8; and Pin 7 Description, Table 8.......................................................................... 8 9/2008—Rev. 0 to Rev. A Added 16-Lead SOIC ......................................................... Universal Changes to General Description Section .......................................1 Changes to Table 1, Test Conditions/Comments Column ..........3 Changes to Timing Specifications Table Summary ......................4 Changes to Table 4, Note 2 ...............................................................5 Added Figure 6; Renumbered Sequentially ...................................8 Changes to Terminology Section ................................................. 12 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 5/2008—Revision 0: Initial Version 1/2011—Rev. A to Rev. B Changed UL Recognition from 3750 V rms to 5000 V rms ....... 1 Changes to Input-to-Output Momentary Withstand Voltage Value (Table 3) .................................................................................. 5 Changed UL Recognition from 3750 V rms to 5000 V rms (Table 4) ............................................................................................. 5 Changes to Note 1 (Table 4) ............................................................ 5 Rev. E | Page 2 of 18 Data Sheet AD7400A SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, except where specified, and VIN− = 0 V (single-ended); TA = −40°C to +125°C, except where specified; fMCLK = 10 MHz, tested with Sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity 2 Min Y Version 1 Typ Max 16 ±2 ±4 ±4 Differential Nonlinearity2 Offset Error2 Offset Drift vs. Temperature Offset Drift vs. VDD1 Gain Error2 Gain Error Drift vs. Temperature Gain Error Drift vs. VDD1 ANALOG INPUT Input Voltage Range Dynamic Input Current Input Capacitance DYNAMIC SPECIFICATIONS Signal-to-Noise and Distortion (SINAD) Ratio2 Signal-to-Noise Ratio (SNR) ±50 1.5 120 ±1.5 ±2 23 110 −250 ±7 ±9 ±0.5 10 70 68 73 72 Peak Harmonic or Spurious Noise (SFDR)2 Isolation Transient Immunity2 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL POWER REQUIREMENTS VDD1 VDD2 IDD1 3 IDD2 4 +250 ±8 ±10 78 78 80 80 −84 −82 −86 −84 12.5 12.5 30 Total Harmonic Distortion (THD)2 Effective Number of Bits (ENOB)2 ±12 ±16 ±22 ±0.9 ±500 4 11.5 11 25 11 4.5 3 Test Conditions/Comments Bits LSB LSB LSB LSB μV µV/°C µV/V mV mV µV/°C µV/V Filter output truncated to 16 bits VIN+ = ±200 mV, TA = −40°C to +125°C VIN+ = ±250 mV, TA = −40°C to +85°C VIN+ = ±250 mV, TA = −40°C to +125°C Guaranteed no missing codes to 16 bits mV µA µA µA pF For specified performance, full range = ±320 mV VIN+ = 400 mV, VIN− = 0 V VIN+ = 500 mV, VIN− = 0 V VIN+ = VIN− = 0 V dB dB dB dB dB dB dB dB Bits Bits kV/µs VDD2 − 0.1 4.5 3 Unit −40°C to +125°C −40°C to +85°C −40°C to +125°C −40°C to +125°C VIN+ = 35 Hz VIN+ = ±200 mV VIN+ = ±250 mV VIN+ = ±200 mV VIN+ = ±250 mV VIN+ = ±200 mV VIN+ = ±250 mV VIN+ = ±200 mV VIN+ = ±250 mV VIN+ = ±200 mV VIN+ = ±250 mV 0.4 V V IO = −200 µA IO = +200 µA 5.5 5.5 13 6 3.5 V V mA mA mA VDD1 = 5.5 V VDD2 = 5.5 V VDD2 = 3.3 V All voltages are relative to their respective ground. See the Terminology section. 3 See Figure 14. 4 See Figure 15. 1 2 Rev. E | Page 3 of 18 AD7400A Data Sheet TIMING SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +125°C, except where specified.1 Table 2. Parameter fMCLKOUT2 t13 t23 t3 t4 Limit at tMIN, tMAX 10 9/11 40 10 0.4 × tMCLKOUT 0.4 × tMCLKOUT Unit MHz typ MHz min/MHz max ns max ns min ns min ns min Description Master clock output frequency Master clock output frequency Data access time after MCLK rising edge Data hold time after MCLK rising edge Master clock low time Master clock high time 1 Sample tested during initial release to ensure compliance. Mark space ratio for clock output is 40/60 to 60/40. 3 Measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 2 200µA +1.6V CL 25pF 200µA 07077-002 TO OUTPUT PIN IOL IOH Figure 2. Load Circuit for Digital Output Timing Specifications t4 t1 t2 MDAT Figure 3. Data Timing Rev. E | Page 4 of 18 t3 07077-003 MCLKOUT Data Sheet AD7400A INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 3. Parameter Input-to-Output Momentary Withstand Voltage Minimum External Air Gap (Clearance) Symbol VISO L(I01) Value 5000 min 7.81,2 min Unit V rms mm Minimum External Tracking (Creepage) L(I02) 7.81,2 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >400 II mm V 1 2 Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material group (DIN VDE 0110, 1/89, Table 1) In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 m. Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained. REGULATORY INFORMATION Table 4. UL1 Recognized Under 1577 Component Recognition Program1 5000 V rms isolation voltage File E214100 1 2 CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-07 and IEC 60950-1, 780 V rms maximum working voltage. Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 390 V rms maximum working voltage. File 205078 VDE2 Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, 891 V peak File 2471900-4880-0001 In accordance with UL 1577, each AD7400A is proof tested by applying an insulation test voltage ≥6000 V rms for 1 sec (current leakage detection limit = 15 μA). In accordance with DIN V VDE V 0884-10, each AD7400A is proof tested by applying an insulation test voltage ≥1671 V peak for 1 sec (partial discharge detection limit = 5 pC). Rev. E | Page 5 of 18 AD7400A Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 5. Parameter INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 450 V rms For Rated Mains Voltage ≤ 600 V rms CLIMATIC CLASSIFICATION POLLUTION DEGREE (DIN VDE 0110, Table 1) MAXIMUM WORKING INSULATION VOLTAGE INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1 VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A After Environmental Test Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC After Input and/or Safety Test Subgroup 2/Safety Test Subgroup 3 VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, ALSO SEE Figure 4) Case Temperature Side 1 Current Side 2 Current INSULATION RESISTANCE AT TS, VIO = 500 V 250 SIDE 2 200 150 SIDE 1 100 50 50 100 150 CASE TEMPERATURE (°C) 200 07077-026 SAFETY-LIMITING CURRENT (mA) 300 0 Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. E | Page 6 of 18 Characteristic Unit VIORM I to IV I to II I to II 40/105/21 2 891 V peak 1671 V peak 1426 V peak 1069 V peak VTR 6000 V peak TS IS1 IS2 RS 150 265 335 >109 °C mA mA Ω VPR VPR 350 0 Symbol Data Sheet AD7400A ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground. Table 6. Parameter VDD1 to GND1 VDD2 to GND2 Analog Input Voltage to GND1 Output Voltage to GND2 Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature SOIC Package θJA Thermal Impedance 2 θJC Thermal Impedance2 Resistance (Input-to-Output), RI-O Capacitance (Input-to-Output), CI-O 3 RoHS-Compliant Temperature, Soldering Reflow ESD Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to VDD1 + 0.3 V −0.3 V to VDD2 + 0.3 V ±10 mA −40°C to +125°C −65°C to +150°C 150°C 89.2°C/W 55.6°C/W 1012 Ω 1.7 pF typ Table 7. Maximum Continuous Working Voltage1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform DC Voltage 1 260 (+0)°C 2.5 kV Transient currents of up to 100 mA do not cause SCR to latch-up. JEDEC 2S2P standard board. 3 f = 1 MHz. 1 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Max 565 Unit V peak 891 V peak 891 V Constraint 50-year minimum lifetime Maximum CSA/VDE approved working voltage Maximum CSA/VDE approved working voltage Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. ESD CAUTION 2 Rev. E | Page 7 of 18 AD7400A Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 16 GND2 VIN+ 2 15 NC NC 5 12 NC NC 6 11 MDAT VDD1/NC 7 10 NC GND1 8 9 GND2 NC 4 AD7400A 14 V DD2 TOP VIEW (Not to Scale) 13 MCLKOUT NC = NO CONNECT 07077-104 VIN– 3 Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD1 2 3 4 to 6, 10, 12, 15 7 VIN+ VIN− NC VDD1/NC 8 9, 16 11 GND1 GND2 MDAT 13 MCLKOUT 14 VDD2 Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7400A and is relative to GND1. Positive Analog Input. Specified range of ±250 mV. Negative Analog Input. Normally connected to GND1. No Connect. Supply Voltage. 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7400A and is relative to GND1. No Connect (NC). If desired, Pin 7 of the SOIC device may be allowed to float. It should not be tied to ground. The AD7400A will operate normally provided that the supply voltage is applied to Pin 1. Ground 1. This is the ground reference point for all circuitry on the isolated side. Ground 2. This is the ground reference point for all circuitry on the nonisolated side. Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are clocked out on the rising edge of the MCLKOUT output and are valid on the following MCLKOUT rising edge. Master Clock Logic Output (10 MHz Typical). The bit stream from the modulator is valid on the rising edge of MCLKOUT. Supply Voltage, 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2. Rev. E | Page 8 of 18 Data Sheet AD7400A TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, using 20 kHz brickwall filter, unless otherwise noted. 110 –85 100 90 –80 80 SINAD (dB) PSRR (dB) 70 60 50 40 –75 –70 30 –65 VDD1 = VDD2 = 5V NO DECOUPLING CAPACITOR VRIPPLE = 200mV SINE WAVE ON VDD1 0 100 1k 10k 100k 1M 10M SUPPLY RIPPLE FREQUENCY (Hz) –60 50 07077-005 10 VDD1 = VDD2 = 5V TA = 25°C 100 150 200 250 300 350 50,000 60,000 INPUT AMPLITUDE (mV) 07077-008 20 Figure 9. SINAD vs. VIN Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling (1 MHz Filter Used) –90 0.5 –80 0.4 –70 VIN+ = –200mV TO +200mV VIN– = 0V 0.3 VDD1 = VDD2 = 4.5V –40 VDD1 = VDD2 = 5.5V VDD1 = VDD2 = 5V –30 0.2 0.1 0 –0.1 –20 –0.2 –10 –0.3 0 0 500 1000 1500 2000 2500 3000 3500 4000 INPUT FREQUENCY (Hz) –0.4 0 0.8 8192 POINT FFT fIN = 35Hz SINAD = 79.6991dB THD = –92.6722dB DECIMATION BY 256 40,000 VIN+ = –200mV TO +200mV VIN– = 0V 0.6 0.4 INL ERROR (LSB) –60 –80 –100 –120 0.2 0 –0.2 –140 –180 0 2 4 6 8 10 12 14 FREQUENCY (kHz) 16 18 20 Figure 8. Typical FFT, ±200 mV Range (Using Sinc3 Filter, 256 Decimation Rate) –0.6 0 10,000 20,000 30,000 CODE 40,000 50,000 Figure 11. Typical INL, ±200 mV Range (Using Sinc3 Filter, 256 Decimation Rate) Rev. E | Page 9 of 18 60,000 07077-010 –0.4 –160 07077-007 (dB) 30,000 Figure 10. Typical DNL, ±200 mV Range (Using Sinc3 Filter, 256 Decimation Rate) 0 –40 20,000 CODE Figure 7. SINAD vs. Analog Input Frequency for Various Supply Voltages –20 10,000 07077-009 DNL ERROR (LSB) –50 07077-006 SINAD (dB) –60 AD7400A Data Sheet 3.9 500 +125°C 450 +85°C 3.7 400 3.5 300 IDD2 (mA) OFFSET (µV) 350 250 200 150 +25°C 3.3 –40°C 3.1 2.9 100 2.7 VDD1 = VDD2 = 5V TA = 25°C –40 –20 VDD2 = VDD1 = 5V 0 20 40 60 80 100 120 TEMPERATURE (°C) 2.5 –0.4 –0.3 –0.2 –0.1 0.2 0.1 0 0.3 0.4 VIN DC INPUT VOLTAGE (V) Figure 12. Offset Drift vs. Temperature 07077-014 0 –60 07077-012 50 Figure 15. IDD2 vs. VIN at Various Temperatures 0.20 –30 0.15 –40 0.10 –50 VDD1 = VDD2 = 4.5V VDD1 = VDD2 = 5V CMRR (dB) 0 –0.05 –60 –70 –80 –0.10 VDD1 = VDD2 = 5.5V –0.20 –45 –35 –25 –15 –5 5 –90 15 25 35 45 55 65 75 85 95 105 TEMPERATURE (°C) –100 100 07077-032 –0.15 1k 10k 100k 1M 10M COMMON-MODE RIPPLE FREQUENCY (Hz) Figure 13 . Gain Error Drift vs. Temperature for Various Supply Voltages 07077-015 GAIN (%) 0.05 Figure 16. CMRR vs. Common-Mode Ripple Frequency 11.0 1.0 +125°C BANDWIDTH = 100kHz +85°C 0.8 NOISE (mV) +25°C 10.0 –40°C 9.5 9.0 0.6 0.4 0.2 Figure 17. RMS Noise Voltage vs. VIN DC Input Figure 14. IDD1 vs. VIN at Various Temperatures Rev. E | Page 10 of 18 0.30 07077-017 VIN DC INPUT (V) 0.25 0.20 0.15 0.10 0 0 0.05 VIN DC INPUT VOLTAGE (V) 0.39 –0.05 0.27 –0.10 0.15 –0.15 0.03 –0.20 –0.09 –0.25 –0.21 –0.30 VDD2 = VDD1 = 5V 8.5 –0.33 07077-013 IDD1 (mA) 10.5 Data Sheet AD7400A 11.0 10.8 10.6 VDD1 = VDD2 = 4.5V 10.2 10.0 9.8 VDD1 = VDD2 = 5.25V 9.6 9.4 VDD1 = VDD2 = 5V TEMPERATURE (°C) 07077-024 95 105 85 75 65 45 55 25 35 5 15 –5 –15 –25 9.0 –35 9.2 –45 MCLKOUT (MHz) 10.4 Figure 18. MCLKOUT vs. Temperature for Various Supplies Rev. E | Page 11 of 18 AD7400A Data Sheet TERMINOLOGY Differential Nonlinearity Differential nonlinearity is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are specified negative full scale, −250 mV (VIN+ − VIN−), Code 7169, and specified positive full scale, +250 mV (VIN+ − VIN−), Code 58,366 for the 16-bit level. Offset Error Offset is the deviation of the midscale code (Code 32,768 for the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V). Gain Error Gain error includes both positive full-scale gain error and negative full-scale gain error. Positive full-scale gain error is the deviation of the specified positive full-scale code (58,366 for the 16-bit level) from the ideal VIN+ − VIN− (+250 mV) after the offset error is adjusted out. Negative full-scale gain error is the deviation of the specified negative full-scale code (7169 for the 16-bit level) from the ideal VIN+ − VIN− (−250 mV) after the offset error is adjusted out. Gain error includes reference error. Signal-to-Noise and Distortion (SINAD) Ratio This ratio is the measured ratio of signal-to-noise and distortion at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical signal-to-noise and distortion ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-Noise and Distortion = (6.02N + 1.76) dB Therefore, for a 12-bit converter, SINAD is 74 dB. Effective Number of Bits (ENOB) The ENOB is defined by ENOB = (SINAD − 1.76)/6.02 Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7400A, it is defined as THD(dB) = 20 log V 2 2 + V 3 2 + V 4 2 + V 5 2 + V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at ±250 mV frequency, f, to the power of a 250 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− of frequency fS as CMRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency f in the ADC output. PfS is the power at frequency fS in the ADC output. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the converter linearity. PSRR is the maximum change in the specified full-scale (±250 mV) transition point due to a change in power supply voltage from the nominal value (see Figure 6). Isolation Transient Immunity The isolation transient immunity specifies the rate of rise/fall of a transient pulse applied across the isolation boundary beyond which clock or data is corrupted. (The AD7400A was tested using a transient pulse frequency of 100 kHz.) Rev. E | Page 12 of 18 Data Sheet AD7400A THEORY OF OPERATION CIRCUIT INFORMATION The AD7400A isolated Σ-Δ modulator converts an analog input signal into a high speed (10 MHz typical), single-bit data stream; the time average of the single-bit data from the modulator is directly proportional to the input signal. Figure 21 shows a typical application circuit where the AD7400A is used to provide isolation between the analog input, a current sensing resistor, and the digital output, which is then processed by a digital filter to provide an N-bit word. ANALOG INPUT The differential analog input of the AD7400A is implemented with a switched capacitor circuit. This circuit implements a second-order modulator stage that digitizes the input signal into a 1-bit output stream. The sample clock (MCLKOUT) provides the clock signal for the conversion process as well as the output data-framing clock. This clock source is internal on the AD7400A. The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. A digital stream that accurately represents the analog input over time appears at the output of the converter (see Figure 19). MODULATOR OUTPUT A differential input of 320 mV ideally results in a stream of all 1s. This is the absolute full-scale range of the AD7400A, while 250 mV is the specified full-scale range, as shown in Table 9. Table 9. Analog Input Range Analog Input Full-Scale Range Positive Full Scale Positive Typical Input Range Positive Specified Input Range Zero Negative Specified Input Range Negative Typical Input Range Negative Full Scale Voltage Input +640 mV +320 mV +250 mV +200 mV 0 mV −200 mV −250 mV −320 mV To reconstruct the original information, this output needs to be digitally filtered and decimated. A Sinc3 filter is recommended because this is one order higher than that of the AD7400A modulator. If a 256 decimation rate is used, the resulting 16-bit word rate is 39 kHz, assuming a 10 MHz internal clock frequency. Figure 20 shows the transfer function of the AD7400A relative to the 16-bit output. +FS ANALOG INPUT 65535 53248 07077-019 SPECIFIED RANGE ADC CODE Figure 19. Analog Input vs. Modulator Output A differential signal of 0 V ideally results in a stream of 1s and 0s at the MDAT output pin. This output is high 50% of the time and low 50% of the time. A differential input of 200 mV produces a stream of 1s and 0s that are high 81.25% of the time (for a +250 mV input, the output stream is high 89.06% of the time). A differential input of −200 mV produces a stream of 1s and 0s that are high 18.75% of the time (for a −250 mV input, the output stream is high 10.94% of the time). 12288 0 –320mV –200mV +200mV +320mV ANALOG INPUT 07077-020 –FS ANALOG INPUT ANALOG INPUT Figure 20. Filtered and Decimated 16-Bit Transfer Characteristic ISOLATED 5V INPUT CURRENT VDD1 AD7400A VIN+ Σ-∆ MOD/ ENCODER VDD2 VDD SINC3 FILTER* DECODER VIN– MDAT MDAT MCLKOUT MCLK CS SCLK SDAT RSHUNT DECODER GND1 ENCODER GND2 GND * THIS FILTER IS IMPLEMENTED WITH AN FPGA OR DSP. Figure 21. Typical Application Circuit Rev. E | Page 13 of 18 07077-018 + NONISOLATED 5V/3V AD7400A Data Sheet DIFFERENTIAL INPUTS The analog input to the modulator is a switched capacitor design. The analog signal is converted into charge by highly linear sampling capacitors. A simplified equivalent circuit diagram of the analog input is shown in Figure 22. A signal source driving the analog input must be able to provide the charge onto the sampling capacitors every half MCLKOUT cycle and settle to the required accuracy within the next half cycle. φA VIN– 1kΩ MCLKOUT 2pF φA 2pF φB φA φB φA φB Figure 22. Analog Input Equivalent Circuit Because the AD7400A samples the differential voltage across its analog inputs, low noise performance is attained with an input circuit that provides low common-mode noise at each input. The amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the AD7400A. When a capacitive load is switched onto the output of an op amp, the amplitude drops momentarily. The op amp tries to correct the situation and, in the process, hits its slew rate limit. This nonlinear response, which can cause excessive ringing, can lead to distortion. To remedy the situation, a low-pass RC filter can be connected between the amplifier and the input to the AD7400A. The external capacitor at each input aids in supplying the current spikes created during the sampling process, and the resistor isolates the op amp from the transient nature of the load. The recommended circuit configuration for driving the differential inputs to achieve best performance is shown in Figure 23. A capacitor between the two input pins sources or sinks charge to allow most of the charge that is needed by one input to be effectively supplied by the other input. The series resistor again isolates any op amp from the current spikes created during the sampling process. Recommended values for the resistors and capacitor are 22 Ω and 47 pF, respectively. R VIN+ VIN– The shunt resistor values used in conjunction with the AD7400A are determined by the specific application requirements in terms of voltage, current, and power. Small resistors minimize power dissipation, while low inductance resistors prevent any induced voltage spikes, and good tolerance devices reduce current variations. The final values chosen are a compromise between low power dissipation and good accuracy. Low value resistors have less power dissipated in them, but higher value resistors may be required to use the full input range of the ADC, thus achieving maximum SNR performance. When the peak sense current is known, the voltage range of the AD7400A (±200 mV) is divided by the maximum sense current to yield a suitable shunt value. If the power dissipation in the shunt resistor is too large, the shunt resistor can be reduced, in which case, less of the ADC input range is used. Using less of the ADC input range results in performance that is more susceptible to noise and offset errors because offset errors are fixed and are thus more significant when smaller input ranges are used. RSENSE must be able to dissipate the I2R power losses. If the power dissipation rating of the resistor is exceeded, its value may drift or the resistor may be damaged, resulting in an open circuit. This can result in a differential voltage across the terminals of the AD400A in excess of the absolute maximum ratings (see Table 6.). If ISENSE has a large high frequency component, take care to choose a resistor with low inductance. VOLTAGE SENSING APPLICATIONS The AD7400A can also be used for isolated voltage monitoring. For example, in motor control applications, it can be used to sense bus voltage. In applications where the voltage being monitored exceeds the specified analog input range of the AD7400A, a voltage divider network can be used to reduce the voltage being monitored to the required range. AD7400A 07077-028 C R The AD7400A is ideally suited for current sensing applications where the voltage across a shunt resistor is monitored. The load current flowing through an external shunt resistor produces a voltage at the input terminals of the AD7400A. The AD7400A provides isolation between the analog input from the current sensing resistor and the digital outputs. By selecting the appropriate shunt resistor value, a variety of current ranges can be monitored. Choosing RSENSE φB 07077-027 VIN+ 1kΩ CURRENT SENSING APPLICATIONS Figure 23. Differential Input RC Network Rev. E | Page 14 of 18 Data Sheet AD7400A DIGITAL FILTER reg [23:0] diff2; The overall system resolution and throughput rate is determined by the filter selected and the decimation rate used. The higher the decimation rate, the greater the system accuracy, as illustrated in Figure 24. However, there is a tradeoff between accuracy and throughput rate and, therefore, higher decimaltion rates result in lower throughput solutions. reg [23:0] diff3; reg [23:0] diff1_d; reg [23:0] diff2_d; reg [15:0] DATA; reg [7:0] word_count; A Sinc3 filter is recommended for use with the AD7400A. This filter can be implemented on an FPGA or a DSP.  1  Z DR    H (z )  1   1  Z   3 /*Perform the Sinc ACTION*/ always @ (mdata1) if(mdata1==0) ip_data1