16-Bit, Isolated Sigma-Delta Modulator
AD7402
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VDD1
VDD2
AD7402
REF
VIN+
BUF
CLOCK
Σ-Δ ADC
VIN–
CLK
ENCODER
CLK
DECODER
MCLKOUT
(10MHz)
DATA
ENCODER
CLK
DECODER
MDAT
GND1
GND2
12898-001
10 MHz internal clock rate
16 bits, no missing codes
Signal-to-noise ratio (SNR): 87 dB typical
Effective number of bits (ENOB): 13.5 bits typical
Typical offset drift vs. temperature: 1.7 µV/°C
On-board digital isolator
On-board reference
Full-scale analog input range: ±320 mV
−40°C to +105°C operating range
High common-mode transient immunity: >25 kV/µs
8-lead, wide-body SOIC, with increased creepage package
Slew rate limited output for low electromagnetic
interference (EMI)
Safety and regulatory approvals
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 1250 VPEAK
Figure 1.
APPLICATIONS
Shunt current monitoring
AC motor controls
Power and solar inverters
Wind turbine inverters
Data acquisition systems
Analog-to-digital and opto-isolator replacements
GENERAL DESCRIPTION
The AD74021 is a high performance, second-order, Σ-Δ modulator
that converts an analog input signal into a high speed, single-bit
data stream, with on-chip digital isolation based on Analog
Devices, Inc., iCoupler® technology. The AD7402 operates from
a 4.5 V to 5.5 V (VDD1) power supply and accepts a differential
input signal of ±250 mV (±320 mV full scale). The differential
input is ideally suited to shunt voltage monitoring in high
voltage applications where galvanic isolation is required.
The analog input is continuously sampled by a high performance
analog modulator, and converted to a ones density, digital
output stream with a data rate of 10 MHz. The original
1
information can be reconstructed with an appropriate digital
filter to achieve 87 dB signal to noise ratio (SNR) at 39 kSPS. The
serial input/output can use a 3 V to 5.5 V or a 3.3 V supply (VDD2).
The serial interface is digitally isolated. High speed complementary
metal oxide semiconductor (CMOS) technology, combined with
monolithic transformer technology, means the on-chip isolation
provides outstanding performance characteristics, superior to
alternatives such as optocoupler devices. The AD7402 device is
offered in an 8-lead, wide body SOIC package and has an
operating temperature range of −40°C to +105°C.
Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
Rev. A
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AD7402
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 13
Applications ....................................................................................... 1
Circuit Information.................................................................... 13
Functional Block Diagram .............................................................. 1
Analog Input ............................................................................... 13
General Description ......................................................................... 1
Differential Inputs ...................................................................... 14
Revision History ............................................................................... 2
Digital Output ............................................................................. 14
Specifications..................................................................................... 3
Applications Information .............................................................. 15
Timing Specifications .................................................................. 4
Current Sensing Applications ................................................... 15
Package Characteristics ............................................................... 5
Voltage Sensing Applications .................................................... 15
Insulation and Safety-Related Specifications ............................ 5
Input Filter .................................................................................. 15
Regulatory Information ............................................................... 5
Digital Filter ................................................................................ 16
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation
Characteristics .............................................................................. 6
Power Supply Considerations ................................................... 19
Absolute Maximum Ratings............................................................ 7
Insulation Lifetime ..................................................................... 19
ESD Caution .................................................................................. 7
Outline Dimensions ....................................................................... 20
Pin Configuration and Function Descriptions ............................. 8
Ordering Guide .......................................................................... 20
Grounding and Layout .............................................................. 19
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
REVISION HISTORY
6/15—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Ordering Guide .......................................................... 20
2/15—Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet
AD7402
SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, TA = −40°C to +105°C, tested with sinc3 filter, 256
decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Offset Error1
Offset Drift vs. Temperature
Offset Drift vs. VDD1
Gain Error1
Gain Error Drift vs. Temperature
Gain Error Drift vs. VDD1
ANALOG INPUT
Input Voltage Range
Input Common-Mode Voltage Range
Dynamic Input Current
Input Capacitance
DYNAMIC SPECIFICATIONS
Signal-to-(Noise + Distortion) Ratio (SINAD)1
Signal-to-Noise Ratio (SNR)1
Total Harmonic Distortion (THD)1
Peak Harmonic or Spurious Noise (SFDR)1
Effective Number of Bits (ENOB)1
Noise Free Code Resolution1
ISOLATION TRANSIENT IMMUNITY1
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
POWER REQUIREMENTS
VDD1
VDD2
IDD1
IDD2
Min
Typ
Max
±1
±5
±0.99
±0.75
5
16
±0.2
1.7
85
0.2
18
11
0.2
−320
−200 to +300
±19
0.05
14
Test Conditions/Comments
Bits
LSB
LSB
mV
µV/°C
µV/V
% FSR
ppm/°C
µV/°C
mV/V
Filter output truncated to 16 bits
+320
mV
±28
µA
µA
pF
Guaranteed no missed codes to 16 bits
VIN+ = ±250 mV, VIN− = 0 V
VIN+ = 0 V, VIN− = 0 V
VIN+ = 35 Hz
74
86
82
87
−84
−84
13.5
12
14
25
dB
dB
dB
dB
Bits
Bits
kV/µs
30
VDD2 − 0.1
4.5
3
26
6
4.5
POWER DISSIPATION
1
±0.5
32
20
Unit
See the Terminology section.
Rev. A | Page 3 of 20
0.4
V
V
IO = −200 µA
IO = +200 µA
5.5
5.5
31
7
5.5
209
V
V
mA
mA
mA
mW
VDD1 = 5.5 V
VDD2 = 5.5 V
VDD2 = 3.3 V
VDD1 = VDD2 = 5.5 V
AD7402
Data Sheet
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +105°C, unless otherwise noted.
Table 2.
Parameter1
fMCLKOUT2
t13
t23
t3
t4
Min
9.4
Typ
10
Max
10.6
±10
Unit
MHz
ns
ns
ns
ns
44
33
33
Description
Master clock output frequency
Data access time after MCLKOUT rising edge
Data hold time after MCLKOUT falling edge
Master clock low time
Master clock high time
1
Sample tested during initial release to ensure compliance.
Mark space ratio for clock output is 45/55 to 55/45.
3
Defined as the time required for the output to cross 0.8 V or 2.0 V for VDD2 = 3 V to 3.6 V, or when the output crosses 0.8 V or 0.7 × VDD2 for VDD2 = 4.5 V to 5.5 V, as
outlined in Figure 2. Measured with a ±200 μA load and a 25 pF load capacitance.
2
t4
2.0V OR 0.7V × VDD2 1
MCLKOUT
0.8V
t2
t3
MDAT
2.0V OR 0.7V × VDD2 1
0.8V
1 SEE NOTE 3 OF TABLE 2 FOR FURTHER DETAILS.
Figure 2. Data Timing
Rev. A | Page 4 of 20
12898-002
t1
Data Sheet
AD7402
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
IC Junction to Ambient Thermal Resistance
1
Symbol
RI-O
CI-O
θJA
Min
Typ
1012
2.2
105
Max
Unit
Ω
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces
The device is considered a 2-terminal device: Pin 1 to Pin 4 are shorted together, and Pin 5 to Pin 8 are shorted together.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter
Input-to-Output Momentary Withstand Voltage
Minimum External Air Gap (Clearance)
Symbol
VISO
L(I01)
Value
5000 min
8.1 min1, 2
Unit
V
mm
Minimum External Tracking (Creepage)
L(I02)
8.1 min1
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.034 min
>400
II
mm
V
1
2
Test Conditions/Comments
1-minute duration
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table I)
In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 meters.
Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.
REGULATORY INFORMATION
Table 5.
UL1
Recognized under 1577
Component Recognition
Program1
5000 V rms Isolation Voltage
Single Protection
File E214100
1
2
3
CSA
Approved under CSA Component Acceptance Notice 5A
VDE2
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
810 V rms (1145 VPEAK) maximum working voltage3
Reinforced insulation per CSA 60950-1-07 and
IEC 60950-1, 405 V rms (583 VPEAK) maximum working
voltage3
Reinforced insulation per IEC 60601-1, 250 V rms
(353 VPEAK) maximum working voltage
File 205078
Reinforced insulation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12, 1250 VPEAK
File 2471900-4880-0001
In accordance with UL 1577, each AD7402-8 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA).
In accordance with DIN V VDE V 0884-10, each AD7402-8 is proof tested by applying an insulation test voltage ≥ 2344 VPEAK for 1 second (partial discharge detection limit = 5 pC).
Rating is calculated for a pollution degree of 2 and a Material Group III. The AD7402 RI-8-1 package material is rated by CSA to a CTI of >400 V and therefore
Material Group II.
Rev. A | Page 5 of 20
AD7402
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 6.
Description
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 450 V rms
For Rated Mains Voltage ≤ 600 V rms
For Rated Mains Voltage ≤ 1000V rms
CLIMATIC CLASSIFICATION
POLLUTION DEGREE (DIN VDE 0110, TABLE 1)
MAXIMUM WORKING INSULATION VOLTAGE
INPUT TO OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 Second, Partial Discharge < 5 pC
INPUT TO-OUTPUT TEST VOLTAGE, METHOD A
After Environmental Test Subgroup 1
VIORM × 1.6 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/Safety Test Subgroup 3
VIORM × 1.2 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 Seconds)
SURGE ISOLATION VOLTAGE
1.2 μs Rise Time, 50 μs, 50% Fall Time
SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, SEE Figure 3)
Case Temperature
Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation
INSULATION RESISTANCE AT TS, VIO = 500 V
Symbol
Characteristic
Unit
VIORM
VPD(M)
I to IV
I to IV
I to IV
I to IV
40/105/21
2
1250
2344
VPEAK
VPEAK
2000
VPEAK
1500
VPEAK
VIOTM
8000
VPEAK
VIOSM
12000
VPEAK
TS
PSO
RIO
150
1.19
>109
°C
W
Ω
VPR(M)
1
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
12898-003
SAFE OPERATING POWER (W)
2
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. A | Page 6 of 20
Data Sheet
AD7402
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.
Table 7.
Parameter
VDD1 to GND1
VDD2 to GND2
Analog Input Voltage to GND1
Output Voltage to GND2
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Pb-Free Temperature, Soldering
Reflow
ESD
FICDM2
HBM3
Rating
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−1 V to VDD1 + 0.3 V
−0.3 V to VDD2 + 0.3 V
±10 mA
−40°C to +105°C
−65°C to +150°C
150°C
Table 8. Maximum Continuous Working Voltage1
Parameter
AC Voltage
Bipolar Waveform
Unipolar Waveform
DC Voltage
1
Unit
Constraint
1250
VPEAK
1250
VPEAK
1250
VPEAK
20-year minimum
lifetime (VDE
approved working
voltage)
20-year minimum
lifetime
20-year minimum
lifetime
Refers to continuous voltage magnitude imposed across the isolation barrier.
ESD CAUTION
260°C
2 kV
±1250 V
± 4000 V
Max
Transient currents of up to 100 mA do not cause silicon controlled rectifier
(SCR) to latch up.
2
JESD22-C101; RC network: 1 Ω, package capacitance (CPKG); Class: IV.
3
ESDA/JEDEC JS-001-2011; RC network: 1.5 kΩ, 100 pF; Class: 3A.
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 7 of 20
AD7402
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1
1
VIN+
2
AD7402-8
7 MCLKOUT
VIN–
3
TOP VIEW
(Not to Scale)
6 MDAT
GND1
4
5 GND2
12898-004
8 VDD2
Figure 4. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
VDD1
VIN+
VIN−
GND1
GND2
MDAT
7
MCLKOUT
8
VDD2
Description
Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7402 and is relative to GND1.
Positive Analog Input.
Negative Analog Input. Normally connected to GND1.
Ground 1. This is the ground reference point for all circuitry on the isolated side.
Ground 2. This is the ground reference point for all circuitry on the nonisolated side.
Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are
clocked out on the rising edge of the MCLKOUT input and are valid on the following MCLKOUT falling edge.
Master Clock Logic Output, 10 MHz (Typical). The bit stream from the modulator is valid on the falling edge of
MCLKOUT.
Supply Voltage, 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2.
Rev. A | Page 8 of 20
Data Sheet
AD7402
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD1 = 5 V, VDD2 = 5 V, using sinc3 filter with a 256 oversampling ratio (OSR), unless otherwise noted.
0
0
fIN = 35.8Hz
SNR = 87.4dB
SINAD = 86dB
THD = –92dB
–20
200mV p-p SINE WAVE ON VDD1
1nF DECOUPLING
–20
–40
MAGNITUDE (dB)
PSRR (dB)
–40
–60
–80
–60
–80
–100
–120
–100
–140
–120
100k
SUPPLY RIPPLE FREQUENCY (Hz)
1M
–180
12898-005
–140
10k
0
15
Figure 8. Fast Fourier Transform (FFT)
2.0
0
SINC3 OSR = 256 FILTER
UNFILTERED
–20
1.5
1.0
DNL ERROR (LSB)
–40
–60
–80
–100
0.5
0
–0.5
–1.0
–120
COMMON-MODE RIPPLE FREQUENCY (Hz)
60
70
12898-009
1M
60
70
–2.0
12898-006
100k
12898-010
–1.5
–140
10k
0
10
20
30
40
50
CODE (k)
Figure 6. CMRR vs. Common-Mode Ripple Frequency
Figure 9. Typical DNL Error
90
2.5
5.5V
5V
4.5V
80
2.0
1.5
60
1.0
INL ERROR (LSB)
70
50
40
30
0.5
0
–0.5
20
–1.0
10
–1.5
0
10
100
1k
ANALOG INPUT FREQUENCY (Hz)
12898-007
SINAD (dB)
10
FREQUENCY (kHz)
Figure 5. PSRR vs. Supply Ripple Frequency
CMRR (dB)
5
12898-008
–160
–2.0
0
10
20
30
40
50
CODE (k)
Figure 7. SINAD vs. Analog Input Frequency
Figure 10. Typical INL Error
Rev. A | Page 9 of 20
AD7402
Data Sheet
0.3
800
VIN+ = VIN– = 0V
1M SAMPLES
676225
700
0.2
0.1
500
OFFSET (mV)
400
300
0
–0.1
200
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
161448
159024
–0.2
100
1902
32769
32768
32767
32766
32770
CODE
–0.3
–40
12898-011
1401
0
–25
5
20
35
50
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
65
= 5.5V
= 5.0V
= 5.5V
= 3.0V
= 5.0V
= 3.3V
80
95
80
95
TEMPERATURE (°C)
Figure 11. Histogram of Codes at Code Center
Figure 14. Offset vs. Temperature
100
1.5
fIN = 35Hz
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
1.0
GAIN ERROR (mV)
90
SNR AND SINAD (dB)
–10
= 5.5V,
= 5.5V,
= 4.5V,
= 4.5V,
= 5.0V,
= 5.0V,
12898-014
HITS PER CODE (k)
600
80
0.5
= 5.5V,
= 5.5V,
= 4.5V,
= 4.5V,
= 5.0V,
= 5.0V,
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
= 5.5V
= 5.0V
= 5.5V
= 3.0V
= 5.0V
= 3.3V
0
–0.5
70
–25
–10
5
20
35
50
65
80
95
TEMPERATURE (°C)
12898-012
60
–40
–1.5
–40
Figure 12. SNR and SINAD vs. Temperature
–10
5
20
35
50
TEMPERATURE (°C)
65
Figure 15. Gain Error vs. Temperature
–60
35
fIN = 35Hz
30
–70
TA = –40°C
TA = +25°C
TA = +105°C
25
IDD1 (mA)
–80
–90
20
15
–100
10
THD
SFDR
–120
–40
–25
–10
5
20
35
50
65
80
TEMPERATURE (°C)
5
95
Figure 13. THD and SFDR vs. Temperature
0
4.50
4.75
5.00
5.25
VDD1 (V)
Figure 16. IDD1 vs. VDD1 at Various Temperatures
Rev. A | Page 10 of 20
5.50
12898-016
–110
12898-013
THD AND SFDR (dB)
–25
12898-015
–1.0
SNR
SINAD
Data Sheet
AD7402
6
27.0
26.5
TA = –40°C
TA = +85°C
TA = –40°C
TA = +25°C
TA = +85°C
TA = +105°C
TA = +25°C
TA = +105°C
26.0
IDD2 (mA)
IDD1 (mA)
25.5
25.0
5
24.5
24.0
–125
0
VIN+ DC INPUT (mV)
125
250
4
–250
125
250
Figure 19. IDD2 vs. VIN+ DC Input at Various Temperatures
10
8
0
VIN+ DC INPUT (mV)
Figure 17. IDD1 vs. VIN+ DC Input at Various Temperatures
9
–125
12898-019
23.0
–250
12898-017
23.5
30
TA = –40°C
TA = +25°C
TA = +105°C
20
7
IIN+ (µA)
5
4
0
–10
3
2
–20
4.0
4.5
5.0
VDD2 (V)
5.5
–30
–320
–240
–160
–80
0
80
160
240
320
VIN+ DC INPUT (mV)
Figure 20. IIN+ vs. VIN+ DC Input
Figure 18. IDD2 vs. VDD2 at Various Temperatures
10.5
VDD1 = 4.5V
VDD1 = 5.0V
VDD1 = 5.5V
10.4
10.3
10.2
10.1
10
9.9
9.8
9.7
9.6
–40
–25
–10
5
20
35
50
TEMPERATURE (°C)
65
80
95
12898-021
3.5
CLOCK FREQUENCY (MHz)
0
3.0
12898-020
1
12898-018
IDD2 (mA)
10
6
Figure 21. Clock Frequency vs. Temperature for Various Supply Voltages
Rev. A | Page 11 of 20
AD7402
Data Sheet
TERMINOLOGY
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7402, it is defined as
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are specified negative full
scale, −250 mV (VIN+ − VIN−), Code 7168 for the 16-bit level,
and specified positive full scale, +250 mV (VIN+ − VIN−),
Code 58,368 for the 16-bit level.
THD(dB) = 20 log
V2 2 + V3 2 + V4 2 + V5 2 + V6 2
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Offset Error
Offset error is the deviation of the midscale code (32,768 for the
16-bit level) from the ideal VIN+ − VIN− (that is, 0 V).
Gain Error
The gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (58,368 for the
16-bit level) from the ideal VIN+ − VIN− (250 mV) after the offset
error is adjusted out. Negative full-scale gain error is the
deviation of the specified negative full-scale code (7168 for the
16-bit level) from the ideal VIN+ − VIN− (−250 mV) after the
offset error is adjusted out.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
a noise peak.
Effective Number of Bits (ENOB)
ENOB is defined by
ENOB = (SINAD − 1.76)/6.02 bits
Noise Free Code Resolution
Noise free code resolution represents the resolution in bits for
which there is no code flicker. The noise free code resolution for
an N-bit converter is defined as
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the measured ratio of signal to noise and distortion at
the output of the ADC. The signal is the rms value of the sine
wave, and noise is the rms sum of all nonfundamental signals
up to half the sampling frequency (fS/2), including harmonics,
but excluding dc.
The peak-to-peak noise in LSBs is measured with VIN+ = VIN− = 0 V.
Signal-to-Noise Ratio (SNR)
SNR is the measured ratio of signal to noise at the output of the
ADC. The signal is the rms amplitude of the fundamental. Noise
is the sum of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
±250 mV frequency, f, to the power of a +250 mV peak-to-peak
sine wave applied to the common-mode voltage of VIN+ and VIN−
of frequency, fS, as
The ratio is dependent on the number of quantization levels in the
digitization process: the greater the number of levels, the smaller
the quantization noise. The theoretical signal-to-noise ratio for
an ideal N-bit converter with a sine wave input is given by
Signal-to-Noise Ratio = (6.02N + 1.76) dB
Therefore, for a 12-bit converter, the SNR is 74 dB.
Isolation Transient Immunity
The isolation transient immunity specifies the rate of rise and
fall of a transient pulse applied across the isolation boundary,
beyond which clock or data is corrupted. The AD7402 was
tested using a transient pulse frequency of 100 kHz.
Noise Free Code Resolution (Bits) = log2(2N/Peak-to-Peak Noise)
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. PSRR is the maximum change
in the specified full-scale (±250 mV) transition point due to a
change in power supply voltage from the nominal value.
Rev. A | Page 12 of 20
Data Sheet
AD7402
THEORY OF OPERATION
A differential signal of 0 V ideally results in a stream of alternating 1s and 0s at the MDAT output pin. This output is high
50% of the time and low 50% of the time. A differential input of
250 mV produces a stream of 1s and 0s that are high 89.06% of
the time. A differential input of −250 mV produces a stream of
1s and 0s that are high 10.94% of the time.
CIRCUIT INFORMATION
The AD7402 isolated Σ-Δ modulator converts an analog input
signal into a high speed (10 MHz maximum), single-bit data
stream; the time average single-bit data from the modulator is
directly proportional to the input signal. Figure 22 shows a
typical application circuit where the AD7402 is used to provide
isolation between the analog input, a current sensing resistor or
shunt, and the digital output, which is then processed by a
digital filter to provide an N-bit word.
A differential input of 320 mV ideally results in a stream of all
1s. A differential input of −320 mV ideally results in a stream of
all 0s. The absolute full-scale range is ±320 mV and the specified
full-scale performance range is ±250 mV, as shown in Table 10.
ANALOG INPUT
Table 10. Analog Input Range
The differential analog input of the AD7402 is implemented
with a switched capacitor circuit. This circuit implements a
second-order modulator stage that digitizes the input signal
into a single-bit output stream. The sample clock (MCLKOUT)
provides the clock signal for the conversion process as well as
the output data framing clock. This clock source is internal on
the AD7402. The analog input signal is continuously sampled
by the modulator and compared to an internal voltage
reference. A digital stream that accurately represents the
analog input over time appears at the output of the converter
(see Figure 23).
Analog Input
Positive Full-Scale Value
Positive Specified Performance Input
Zero
Negative Specified Performance Input
Negative Full-Scale Value
Voltage Input (mV)
+320
+250
0
−250
−320
FLOATING
POWER SUPPLY
+400V
NONISOLATED
5V/3.3V
GATED
DRIVE
CIRCUIT
VDD1
AD7402
VDD2
VDD
SINC3 FILTER*
5.1V
220pF
10Ω
10Ω
RSHUNT
FLOATING
POWER SUPPLY
220pF
VIN–
Σ-Δ
MOD/
ENCODER
MDAT
MDAT
DECODER MCLKOUT
MCLK
SCLK
SDAT
100nF
10µF 1nF
GND1
GND
GND2
*THIS FILTER IS IMPLEMENTED
WITH AN FPGA OR DSP
–400V
Figure 22. Typical Application Circuit
MODULATOR OUTPUT
+FS ANALOG INPUT
–FS ANALOG INPUT
ANALOG INPUT
Figure 23. Analog Input vs. Modulator Output
Rev. A | Page 13 of 20
12898-022
GATED
DRIVE
CIRCUIT
12898-023
MOTOR
CS
VIN+
AD7402
Data Sheet
To reconstruct the original information, this output must be
digitally filtered and decimated. A sinc3 filter is recommended
because it is one order higher than that of the AD7402 modulator,
which is a second-order modulator. If a 256 decimation rate is
used, the resulting 16-bit word rate is 39 kSPS. See the Digital
Filter section for more detailed information on the sinc filter
implementation. Figure 24 shows the transfer function of the
AD7402 relative to the 16-bit output.
DIFFERENTIAL INPUTS
The analog input to the modulator is a switched capacitor
design. The analog signal is converted into charge by highly
linear sampling capacitors. A simplified equivalent circuit
diagram of the analog input is shown in Figure 25. A signal
source driving the analog input must provide the charge onto the
sampling capacitors every half MCLKOUT cycle and settle to the
required accuracy within the next half cycle.
φA
65535
VIN+
300Ω
φB
1.9pF
φA
1.9pF
58368
VIN–
MCLKIN
7168
φB
φA φB φA φB
12898-025
ADC CODE
SPECIFIED RANGE
300Ω
Figure 25. Analog Input Equivalent Circuit
Because the AD7402 samples the differential voltage across its
analog inputs, low noise performance is attained with an input
circuit that provides low common-mode noise at each input.
–320mV
–250mV
+250mV +320mV
ANALOG INPUT
Figure 24. Filtered and Decimated 16-Bit Transfer Function
12898-024
0
DIGITAL OUTPUT
The AD7402 MDAT output driver is a slew rate limited driver.
This driver lowers electromagnetic emissions, thus minimizing
electromagnetic interference, both conducted and radiated.
Rev. A | Page 14 of 20
Data Sheet
AD7402
APPLICATIONS INFORMATION
90
CURRENT SENSING APPLICATIONS
85
80
SINAD (dB)
The AD7402 is ideally suited for current sensing applications
where the voltage across a shunt resistor (RSHUNT) is monitored.
The load current flowing through an external shunt resistor
produces a voltage at the input terminals of the AD7402. The
AD7402 provides isolation between the analog input from the
current sensing resistor and the digital outputs. By selecting the
appropriate shunt resistor value, a variety of current ranges can
be monitored.
fIN = 35Hz
VDD1 = 5V
VDD2 = 5V
TA = 25°C
75
11-BIT
ENOB
70
13-BIT
ENOB
12-BIT
ENOB
Choosing RSHUNT
14-BIT
ENOB
60
0
50
100
150
200
VIN+ AC INPUT SIGNAL AMPLITUDE (mV)
250
Figure 26. SINAD vs. VIN+ AC Input Signal Amplitude
2.0
DC INPUT
100k SAMPLES PER DATA POINT
1.8
1.6
RMS NOISE (LSB)
1.4
1.2
1.0
0.8
0.6
0.4
To choose a suitable shunt resistor, first determine the current
through the shunt. The shunt current for a 3-phase induction
motor can be expressed as
0.2
0
–250
PW
IRMS =
1.73 V EF PF
–170
–90
–10
70
150
RMS NOISE (LSB)
230
12898-027
The shunt resistor (RSHUNT) values used in conjunction with the
AD7402 are determined by the specific application
requirements in terms of voltage, current, and power. Small
resistors minimize power dissipation, whereas low inductance
resistors prevent any induced voltage spikes, and good tolerance
devices reduce current variations. The final values chosen are a
compromise between low power dissipation and accuracy.
Higher value resistors use the full performance input range of
the ADC, thus achieving maximum SNR performance. Low
value resistors dissipate less power but do not use the full
performance input range. The AD7402, however, delivers
excellent performance, even with lower input signal levels,
allowing low value shunt resistors to be used while maintaining
system performance.
12898-026
65
Figure 27. RMS Noise vs. VIN+ DC Input Signal Amplitude
where:
IRMS is the motor phase current (A rms)
PW is the motor power (Watts)
V is the motor supply voltage (V ac)
EF is the motor efficiency (%)
PF is the power efficiency (%)
To determine the shunt peak sense current, ISENSE, consider the
motor phase current and any overload that may be possible in
the system. When the peak sense current is known, divide the
voltage range of the AD7402 (±250 mV) by the peak sense
current to yield a maximum shunt value.
If the power dissipation in the shunt resistor is too large, the
shunt resistor can be reduced and less of the ADC input range can
be used. Figure 26 shows the SINAD performance characteristics
and the ENOB of resolution for the AD7402 for different input
signal amplitudes. Figure 27 shows the rms noise performance
for dc input signal amplitudes. The AD7402 performance at
lower input signal ranges allows smaller shunt values to be used
while still maintaining a high level of performance and overall
system efficiency.
RSHUNT must be able to dissipate the I2R power losses. If the
power dissipation rating of the resistor is exceeded, its value
may drift or the resistor may be damaged, resulting in an open
circuit. This open circuit can result in a differential voltage
across the terminals of the AD7402, in excess of the absolute
maximum ratings. If ISENSE has a large high frequency
component, choose a resistor with low inductance.
VOLTAGE SENSING APPLICATIONS
The AD7402 can also be used for isolated voltage monitoring.
For example, in motor control applications, it can be used to
sense the bus voltage. In applications where the voltage being
monitored exceeds the specified analog input range of the
AD7402, a voltage divider network can be used to reduce the
voltage being monitored to the required range.
INPUT FILTER
In a typical use case for directly measuring the voltage across a
shunt resistor, the AD7402 can be connected directly across the
shunt resistor with a simple RC low-pass filter on each input.
Rev. A | Page 15 of 20
AD7402
Data Sheet
The recommended circuit configuration for driving the
differential inputs to achieve best performance is shown in
Figure 28. An RC low-pass filter is placed on both the analog
input pins. Recommended values for the resistors and capacitors
are 10 Ω and 220 pF, respectively. If possible, equalize the
source impedance on each analog input to minimize offset.
higher the decimation rate, the greater the system accuracy, as
illustrated in Figure 31. However, there is a trade-off between
accuracy and throughput rate and, therefore, higher decimation
rates result in lower throughput solutions.
100
fIN = 35Hz
90
80
C
R
70
VIN+
SNR (dB)
AD7402
R
12898-028
VIN–
30
Figure 28. RC Low-Pass Filter Input Network
12898-029
AD7402
VIN–
10
0
10
100
DECIMATION RATE
Figure 31. SNR vs. Decimation Rate for Different Sincx Filter Orders
A sinc3 filter is recommended for use with the AD7402. This
filter can be implemented on a field programmable gate array
(FPGA) or a digital signal processor (DSP).
R
VIN+
C
SINC1
SINC2
SINC3
SINC4
20
The input filter configuration for the AD7402 is not limited to
the low-pass structure shown in Figure 28. The differential RC
filter configuration shown in Figure 29 also achieves excellent
performance. Recommended values for the resistors and
capacitor are 22 Ω and 47 pF, respectively.
R
50
40
Equation 1 describes the transfer function of a sinc filter.
1 (1 − Z − DR )
H (z ) =
−1
DR (1 − Z )
Figure 29. Differential RC Filter Network
Figure 30 compares the typical performance for the input filter
structures outlined in Figure 28 and Figure 29 for different
resistor and capacitor values.
N
(1)
where DR is the decimation rate and N is the sinc filter order.
The throughput rate of the sinc filter is determined by the
modulator clock and the decimation rate selected.
95
90
fIN = 35Hz
Throughput =
85
80
SNR (dB)
12898-031
C
60
(2)
where MCLK is the modulator clock frequency
75
As the decimation rate increases, the data output size from the
sinc filter increases. The output data size is expressed in
Equation 3. The 16 most significant bits are used to return a
16-bit result.
70
65
60
50
10Ω, 220pF
DIFFERENTIAL 22Ω, 47pF
DIFFERENTIAL 22Ω, 10nF
45
10
100
DECIMATION RATE
Data size = N × log2 DR
(3)
For a sinc filter, the −3 dB filter response point can be derived
from the filter transfer function, Equation 1, and is 0.262 times
the throughput rate. The filter characteristics for a third-order
sinc filter are summarized in Table 11.
3
12898-030
55
MCLK
DR
Figure 30. SNR vs. Decimation Rate for Different Filter Structures for Different
Resistor and Capacitor Values
Table 11. Sinc3 Filter Characteristics for 10 MHz
DIGITAL FILTER
The output of the AD7402 is a continuous digital bit stream. To
reconstruct the original input signal information, this output bit
stream needs to be digitally filtered and decimated. A sinc filter
is recommended due to its simplicity. A sinc3 filter is
recommended because it is one order higher than that of the
AD7402 modulator, which is a second-order modulator. The type
of filter selected, the decimation rate, and the modulator clock used
determines the overall system resolution and throughput rate. The
Decimation
Ratio (DR)
32
64
128
256
512
Rev. A | Page 16 of 20
Throughput
Rate (kHz)
312.5
156.2
78.1
39.1
19.55
Output Data
Size (Bits)
15
18
21
24
27
Filter Response
(kHz)
81.8
40.9
20.4
10.2
5.1
Data Sheet
AD7402
The following Verilog code provides an example of a sinc3 filter
implementation on a Xilinx® Spartan®-6 FPGA. Note that the
data is read on the negative clock edge. It is recommended to
read in the data on the negative clock edge. The code is
configurable to accommodate decimation rates from 32 to 4096.
module dec256sinc24b
(
input mclk1, /* used to clk filter */
input reset, /* used to reset filter */
input mdata1, /* input data to be filtered
*/
output reg [15:0] DATA, /* filtered output
*/
output reg data_en,
input [15:0] dec_rate
);
acc3
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