AD74111YRUZ

Low Cost, Low Power Mono Audio Codec AD74111 FEATURES 2.5 V Mono Audio Codec with 3.3 V Tolerant Digital Interface Supports 8 kHz to 48 kHz Sample Rates Supports 16-/20-/24-Bit Word Lengths Multibit
- Modulators with “Perfect Differential Linearity Restoration” for Reduced Idle Tones and Noise Floor Data Directed Scrambling DAC – Least Sensitive to Jitter Performance (20 Hz to 20 kHz) 85 dB ADC Dynamic Range 93 dB DAC Dynamic Range Programmable ADC Gain On-Chip Volume Control for DAC Channel Software Controllable Clickless Mute Supports 256  f S, 512  fS, and 768  fS Master Mode Clocks Master Clock Prescaler for Use with DSP Master Clocks On-Chip Reference 16-Lead TSSOP Package APPLICATIONS Digital Video Camcorders (DVC) Portable Audio Devices (Walkman®, PDAs, and so on) Audio Processing Voice Processing Telematic Systems General-Purpose Analog I/O GENERAL DESCRIPTION The AD74111 is a front-end processor for general-purpose audio and voice applications. It features a multibit ⌺-⌬ A/D conversion channel and a multibit ⌺-⌬ D/A conversion channel. The ADC channel provides >67 dB THD+N and the DAC channel provides >88 dB THD+N, both over an audio signal bandwidth. The AD74111 is particularly suitable for a variety of applications where mono input and output channels are required, including audio sections of digital video camcorders, portable personal audio devices, and telematic applications. Its high quality performance also makes it suitable for speech and telephony applications such as speech recognition and synthesis, and modern feature phones. An on-chip reference voltage is included but can be powered down and bypassed by an external reference source if required. The AD74111 offers sampling rates that, depending on MCLK selection and MCLK divider ratio, range from 8 kHz in the voiceband range to 48 kHz in the audio range. The AD74111 is available in a 16-lead TSSOP package option and is specified for the automotive temperature range of –40°C to +105°C. FUNCTIONAL BLOCK DIAGRAM RESET MCLK DVDD1 DVDD2 AVDD ADC DIGITAL FILTER DIN DOUT DFS
- MODULATOR CAPP GAIN STAGE SERIAL DATA PORT VIN CAPN DCLK DAC CHANNEL DIGITAL FILTER REFERENCE REFCAP DGND VOLUME CONTROL
- DAC MODULATOR VOUT AGND REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. = 2.5 V ± 5%, DVDD2 = 2.5 V ± 5%, DVDD1 = 2.5 V ± 5%, f f = 48 kHz, T = T to T , unless otherwise noted.) AD74111–SPECIFICATIONS (AVDD = 12.288 MHz, Parameter Unit MCLK S ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Signal to Noise Ratio (SNR) Dynamic Range (20 Hz to 20 kHz, –60 dB Input) No Filter With A-Weighted Filter Total Harmonic Distortion + Noise Programmable Input Gain Gain Step Size Offset Error Full-Scale Input Voltage Input Resistance Input Capacitance Common-Mode Input Volts Crosstalk DIGITAL-TO-ANALOG CONVERTERS DAC Resolution Signal to Noise Ratio (SNR) Dynamic Range (20 Hz to 20 kHz, –60 dB Input) No Filter With A-Weighted Filter Total Harmonic Distortion + Noise DC Accuracy Offset Error Gain Error Volume Control Step Size (1024 Linear Steps) Volume Control Range (Max Attenuation) Mute Attenuation De-emphasis Gain Error Full-Scale Output Voltage Output Resistance Common Mode Output Volts Crosstalk A MIN MAX Conditions Min Typ fS = 16 kHz 70 24 77 Bits dB 85 85 87 –67 –75 12 3 +30 0.5 4 1.125 100 dB dB dB dB dB dB dB mV V rms kΩ pF V dB 24 89 Bits dB 93 93 95 –88 –88 –81 dB dB dB dB dB dB –10 +0.175 +50 +0.8 fS = 48 kHz fS = 16 kHz fS = 48 kHz fS = 48 kHz, PGA = 0 dB fS = 16 kHz 78 –55 Max +80 15 ADC Input Signal = 1.0 kHz, 0 dB; DAC Output = DC fS = 16 kHz 80 fS = 48 kHz fS = 16 kHz fS = 48 kHz fS = 48 kHz fS = 16 kHz 84 –75 –0.9 Signal Input ADC = AGND; DAC Output Level = 1.0 kHz, 0 dB REFERENCE (Internal) Absolute Voltage, VREF VREF TC –2– mV dB 0.098 –60 –100 ± 0.1 0.5 145 1.125 95 % dB dB dB V rms Ω V dB 1.125 50 V ppm/°C REV. 0 AD74111 Parameter Conditions ADC DECIMATION FILTER* Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Low Group Delay Mode fS = 48 kHz DAC INTERPOLATION FILTER* Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Low Group Delay Mode fS = 48 kHz Min Typ Max Unit 21.5 0.2 kHz mdB kHz kHz dB µs µs 21.5 10 kHz mdB kHz kHz dB µs µs DVDD1 – 0.8 0 –10 DVDD1 0.8 +10 10 V V µA pF DVDD1 – 0.4 0 –10 DVDD1 V 0.4 V +10 µA 2.375 2.375 2.375 2.625 2.625 3.6 5 26.5 120 910 87 5 26.5 75 505 55 LOGIC INPUT VINH, Input High Voltage VINL, Input Low Voltage Input Current Input Capacitance LOGIC OUTPUT VOH, Output High Voltage VOL, Output Low Voltage Three-State Leakage Current POWER SUPPLIES AVDD DVDD2 DVDD1 Power Supply Rejection Ratio 1 kHz, 300 mV p-p Signal at Analog Supply Pins 50/60 Hz, 300 mV p-p Signal at Analog Supply Pins 72 dB 73 dB *Guaranteed by design. Specifications subject to change without notice. Table I. Current Summary (AVDD = 2.5 V, DVDD1 = 2.5 V, DVDD2 = 2.5 V) 1, 2, 3 Conditions AVDD Current (mA) DVDD1 Current (mA) DVDD2 Total Current Current (mA) (Max)(mA) ADC, Reference, Ref-Amp On DAC, Reference, Ref-Amp On Reference, Ref-Amp On All Sections On Power-Down Mode 6.11 (6.11) 3.80 (4.0) 0.60 (0.60) 8.60 0.035 0.15 (0.43) 0.15 (0.43) 0.15 (0.43) 0.15 (0.43) 0.15 (0.43) 0.72 (2.10) 0.85 (2.23) 0.27 (0.50) 1.72 (4.80) 0.49 (0.49) NOTES 1 All values are typical, unless otherwise noted. 2 Max values are quoted with DVDD1 = 3.6 V. 3 Sample rates quoted are for 16 kHz and (48 kHz). REV. 0 –3– V V V 15.35 2.6 AD74111 TIMING CHARACTERISTICS (AVDD = 2.5 V ± 5%, DVDD2 = 2.5 V ± 5%, DVDD1 = 3.3 V ± 10%, fMCLK = 12.288 MHz, fS = 48 kHz, TA = TMIN to TMAX, unless otherwise noted.) Parameter Min MASTER CLOCK AND RESET tMH MCLK High MCLK Low tML RESET Low tRES DIN Setup Time tRS tRH DIN Setup Time SERIAL PORT tCH DCLK High2 DCLK Low2 tCL DFS Delay tFD tFS DFS Setup Time DFS Hold Time tFH DOUT Delay tDD tDS DIN Setup Time DIN Hold Time tDH tDT DOUT Three-State Max Unit Comments 25 25 10 5 5 ns ns ns MCLKS MCLKS To RESET Rising Edge1 To RESET Rising Edge1 20 20 ns ns ns ns ns ns ns ns ns From DCLK Rising Edge3 To DCLK Falling Edge From DCLK Falling Edge From DCLK Rising Edge To DCLK Falling Edge From DCLK Falling Edge From DCLK Rising Edge4 5 5 15 30 5 15 40 NOTES 1 Determines Master/Slave mode operation. 2 Applies in Slave mode only. 3 Applies in Master mode only. 4 Applies in Multiframe-Sync mode only. tMH MCLK tML RESET tRES DIN tRS tRH Figure 1. MCLK and RESET Timing tFS DFS tFH tCH DCLK tCL tFD MSB DIN MSB–1 MSB–2 tDS tDH MSB–1 MSB DOUT MSB–2 tDD Figure 2. Serial Port Timing 100A TO OUTPUT PIN IOL DVDD1 2 CL 50pF 100A IOH Figure 3. Load Circuit for Digital Output Timing Specifications –4– REV. 0 AD74111 16-Lead TSSOP, θJA Thermal Impedance . . . . . . . . 150.4°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C ABSOLUTE MAXIMUM RATINGS* (TA = 25°C, unless otherwise noted.) AVDD, DVDD2 to AGND, DGND . . . . . . . –0.3 V to +3.0 V DVDD1 to AGND, DGND . . . . . . . . . . . . . –0.3 V to +4.5 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . . –0.3 V to DVDD1 + 0.3 V Operating Temperature Range Automotive (Y Version) . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TEMPERATURE RANGE ORDERING GUIDE Parameter Min Max Unit Model Range Package Specifications Guaranteed Storage –40 –65 +105 +150 ºC ºC AD74111YRU –40ºC to +105ºC RU-16 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD74111 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– AD74111 PIN CONFIGURATION DCLK 1 16 MCLK DIN 2 15 DVDD1 14 DVDD2 DFS 3 AD74111 13 DGND TOP VIEW (NOT TO SCALE) 12 AGND 5 DOUT 4 RESET AVDD 6 11 REFCAP CAPN 7 10 CAPP 9 VOUT 8 VIN PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic I/O Description DCLK DIN I/O I DFS DOUT RESET AVDD CAPN VOUT VIN CAPP REFCAP AGND DGND DVDD2 DVDD1 MCLK I/O O I Serial Clock Serial Data Input. The state of DIN on the rising edge of RESET determines the operating mode of the interface. See the Selecting Master or Slave Mode section for more information. Frame Synchronization Signal Serial Data Output Power-Down/Reset Input Analog 2.5 V Power Supply Connection ADC Filter Capacitor (Negative) DAC Analog Output ADC Analog Input ADC Filter Capacitor (Positive) Internal Reference Decoupling Capacitor. Can also be used for connection of an external reference. Analog Ground Connection Digital Ground Connection Digital 2.5 V Power Supply Connection (Core) Digital Power Supply Connection (Interface) External Master Clock Input O I I/O I –6– REV. 0 0 0 –50 –40 MAGNITUDE – dB MAGNITUDE – dB Typical Performance Characteristics–AD74111 –100 –80 –120 –150 0 0.25 0.5 0.75 0 1.0 0.25 FREQUENCY – NORMALIZED TO fS 0 0 –50 –40 –100 –150 0.25 0.5 0.75 –120 1.0 0 0.25 0.5 0.75 1.0 FREQUENCY – NORMALIZED TO fs TPC 2. ADC Composite Filter Response Low Group Delay Enabled TPC 5. DAC Composite Filter Response Low Group Delay Enabled 1.0 10 0.5 5 MAGNITUDE – mdB MAGNITUDE – mdB 1.0 –80 FREQUENCY – NORMALIZED TO fS 0 –0.5 0 –5 –1.0 –10 0 0.1 0.2 0.3 0.4 0.5 0 FREQUENCY – NORMALIZED TO fs TPC 3. ADC Composite Filter Response (Pass-Band Section) REV. 0 0.75 TPC 4. DAC Composite Filter Response MAGNITUDE – dB MAGNITUDE – dB TPC 1. ADC Composite Filter Response 0 0.5 FREQUENCY – NORMALIZED TO fs 0.1 0.2 0.3 0.4 FREQUENCY – NORMALIZED TO fS TPC 6. DAC Composite Filter Response (Pass-Band Section) –7– 0.5 78 90 74 88 70 86 THD+N – dB THD+N – dB AD74111 66 84 62 82 58 80 78 54 84 16 32 24 SAMPLE RATE – kHz 8 48 40 TPC 7. ADC THD+N vs. Sample Rate 32 24 SAMPLE RATE – kHz 40 48 TPC 8. DAC THD+N vs. Sample Rate FUNCTIONAL DESCRIPTION General Description ADC Section The AD74111 contains a multibit sigma-delta ADC. The ADC has a single input pin with additional pins for decoupling/filter capacitors. The ADC channel has an independent input amplifier gain stage that can be programmed in steps of 3 dB, from 0 dB to 12 dB. The input amplifier gain settings are set by programming the appropriate bits in Control Register E. The ADC can also be muted under software control. The AD74111 input channel employs a multibit sigma-delta conversion technique that provides a high resolution output with system filtering implemented on-chip. Sigma-delta converters employ a technique known as oversampling, where the sampling rate is many times the highest frequency of interest. In the case of the AD74111, the oversampling ratio is 64 and a decimation filter is used to reduce the output to standard sample rates. The maximum sample rate is 48 kHz. The AD74111 is a 2.5 V mono codec. It comprises an ADC and DAC channel with single-ended input and output. The ADC has a programmable gain stage and the DAC has programmable volume control. Each of these sections is described in further detail below. The AD74111 is controlled by means of a flexible serial port (SPORT) that can be programmed to accommodate many industry standard DSPs and microcontrollers. The AD74111 can be set to operate as a master or slave device. The AD74111 can be set to operate with sample rates of 8 kHz to 48 kHz, depending on the values of MCLK and the MCLK prescalers. On-chip digital filtering is provided as part of the DAC and ADC channels with a low group delay option to reduce the delays through the filters when operating at lower sample rates. Figure 4 shows a block diagram of the DAC and ADC channel in the AD74111. Figures 5a and 5b show block diagrams of the filter arrangements of the ADC and DAC filters. MCLK PRESCALERS (/1 to /12) 16 ADC INPUT
- ADC MODULATOR /4 DECIMATOR (/8) SINC FILTER (/8) ADC MODULATOR CLOCK DAC O/P
- DAC MODULATOR ADC DATA 16-/20-/24BITS /2 DAC MODULATOR CLOCK 5 BITS INTERPOLATOR ( 16) INTERPOLATOR ( 8) DAC DATA 16-/20-/24BITS Figure 4. ADC and DAC Engine –8– REV. 0 AD74111 ADC MODULATOR 64  fS 5th ORDER COMB FILTER 4  fS 8  fS 2  fS COMB COMPENSATION HALF-BAND fS HALF-BAND ADC RESULT LOW GROUP DELAY OUTPUT Figure 5a. ADC Filter Section DAC MODULATOR 128  fS 16  ZERO ORDER HOLD 8  fS HALF-BAND FILTER 4  fS ZERO ORDER HOLD 2  fS SINC COMPENSATION FILTER HALF-BAND– FILTER fS DAC INPUT LOW GROUP DELAY INPUT Figure 5b. DAC Filter Section ADC, CAPP, and CAPN Pins Output Signal Swing The ADC channel requires two external capacitors to act as charge reservoirs for the switched capacitor inputs of the sigmadelta modulator. These capacitors isolate the outputs of the PGA stage from glitches generated by the sigma-delta modulator. The capacitor also forms a low-pass filter with the output impedance of the PGA (approximately 124 Ω), which helps to isolate noise from the modulator engine. The capacitors should be of good quality, such as NPO or polypropylene film, with values from 100 pF to 1 nF and should be connected to AGND. The DAC has an output range of 0.5 V rms/1.414 V p-p about a bias point equal to VREFCAP (see Figure 7). VREFCAP VOUT 820 1.414V p-p 2n2F NPO Figure 7. Typical Output Circuit Peak Readback Low Group Delay The AD74111 can store the highest ADC value to facilitate level adjustment of the input signal. Programming the Peak Enable bit in Control Register E with a 1 will enable ADC Peak Level Reading. The peak value is stored as a 6-bit number from 0 dB to –63 dB in 1 dB steps. Reading Control Register F will give the highest ADC value since the bit was set. The ADC peak register is automatically cleared after reading. It is possible to bypass much of the digital filtering by enabling the Low Group Delay function in Control Register C. By reducing the amount of filtering the AD74111 applies to input and output samples, the time delay between the sampling interval and when the sample is available is greatly reduced. This can be of benefit in applications such as telematics, where minimal time delays are important. When the Low Group Delay function is enabled, the sample rate becomes IMCLK/128. Decimator Section The digital decimation filter has a pass-band ripple of 0.2 mdB and a stop-band attenuation of 120 dB. The filter is an FIR type with a linear phase response. The group delay at 48 kHz is 910 µs. Output sample rates up to 48 kHz are supported. Reference The AD74111 features an on-chip reference whose nominal value is 1.125 V. A 100 nF ceramic and 10 µF tantalum capacitor applied at the REFCAP pin are necessary to stabilize the reference. (See Figure 8.) Input Signal Swing The ADC input has an input range of 0.5 V rms/1.414 V p-p about a bias point equal to VREFCAP. Figure 6 shows a typical input filter circuit for use with the AD74111. REFCAP 10F 1.414V p-p VAGND  51 47F VIN 10nF NPO Figure 8. Reference Decoupling If required, an external reference can be used as the reference source of the ADC and DAC sections. This may be desirable in situations where multiple devices are required to use the same value of reference or because of a better temperature coefficient specification. The internal reference can be disabled via Control Register A and the external reference applied at the REFCAP pin (see Figure 9). External references should be of a suitable value such that the voltage swing of the inputs or outputs is not affected by being too close to the power supply rails and should be adequately decoupled. Figure 6. Typical Input Circuit DAC Section The AD74111 DAC channel has a single-ended, analog output. The DAC has independent software controllable Mute and Volume Control functions. Control Register G controls the attenuation factor for the DAC. This register is 10 bits wide, giving 1024 steps of attenuation. The AD74111 output channel employs a multibit sigma-delta conversion technique that provides a high quality output with system filtering implemented on-chip. REV. 0 0.1F –9– AD74111 Example 2: fSAMP = 44.1 kHz and 11.025 kHz Required 1.125V MCLK = 44.1 kHz ⫻ 256 = 11.2896 MHz to provide 44.1 kHz fSAMP. REFCAP For fSAMP = 11.025 kHz, it is necessary to use the ⫼1 setting in Prescaler 1 and the ⫼4 setting in Prescaler 2, and pass through in Prescaler 3. This results in an IMCLK = 11.025 kHz ⫻ 256 = 2.8224 MHz (= 11.2896 MHz/4). EXTERNAL REFERENCE Figure 9. External Reference Resetting the AD74111 Master Clocking Scheme The update rate of the AD74111’s ADC and DAC channels requires an internal master clock (IMCLK) that is 256 times the sample update rate (IMCLK = 256 ⫻ fS). To provide some flexibility in selecting sample rates, the device has a series of three master clock prescalers that are programmable and allow the user to choose a range of convenient sample rates from a single external master clock. The master clock signal to the AD74111 is applied at the MCLK pin. The MCLK signal is passed through a series of three programmable MCLK prescaler (divider) circuits that can be selected to reduce the resulting Internal MCLK (IMCLK) frequency if required. The first and second MCLK prescalers provide divider ratios of ⫼1 (pass through), ⫼2, ⫼3; while the third prescaler provides divider ratios of ⫼1 (pass through), ⫼2, ⫼4. MCLK PRESCALER 2 PRESCALER 3 /1 /1 /1 /2 /2 /2 /3 /3 /4 Power Supplies and Grounds The AD74111 features three separate supplies: AVDD, DVDD1, and DVDD2. AVDD is the supply to the analog section of the device and must be of sufficient quality to preserve the AD74111’s performance characteristics. It is nominally a 2.5 V supply. DVDD1 is the supply for the digital interface section of the device. It is fed from the digital supply voltage of the DSP or controller to which the device is interfaced and allows the AD74111 to interface with devices operating at supplies of between 2.5 V – 5% to 3.3 V + 10%. PROGRAMMABLE MCLK DIVIDER PRESCALER 1 The AD74111 can be reset by bringing the RESET pin low. Following a reset, the internal circuitry of the AD74111 ensures that the internal registers are reset to their default settings and the on-chip RAM is purged of previous data samples. The DIN pin is sampled to determine if the AD74111 is required to operate in Master or Slave mode. The reset process takes 3072 MCLK periods, and the user should not attempt to program the AD74111 during this time. IMCLK DVDD2 is the supply for the digital core of the AD74111. It is nominally a 2.5 V supply. CONTROL REGISTER Accessing the Internal Registers Figure 10. MCLK Divider The divider ratios allow a more convenient sample rate selection from a common MCLK, which may be required in many voice related applications. Control Register B should be programmed to achieve the desired divider ratios. Selecting Sample Rates The sample rate at which the converter runs is always 256 times the IMCLK rate. IMCLK is the Internal Master Clock and is the output from the Master Clock Prescaler. The default sample rate is 48 kHz (based on an external MCLK of 12.288 MHz). In this mode, the ADC modulator is clocked at 3.072 MHz and the DAC modulator is clocked at 6.144 MHz. Sample rates that are lower than MCLK/256 can be achieved by using the MCLK prescaler. Example 1: fSAMP = 48 kHz and 8 kHz Required MCLK = 48 kHz ⫻ 256 = 12.288 MHz to provide 48 kHz fSAMP. For fSAMP = 8 kHz, it is necessary to use the ⫼3 setting in Prescaler 1, the ⫼2 setting in Prescaler 2, and pass through in Prescaler 3. This results in an IMCLK = 8 kHz ⫻ 256 = 2.048 MHz (= 12.288 MHz/6). The AD74111 has seven registers that can be programmed to control the functions of the AD74111. Each register is 10 bits wide and is written to or read from using a 16-bit write or read operation, with the exception of Control Register F, which is read-only. Table V shows the format of the data transfer operation. The Control Word is made up of a Read/Write bit, the register address, and the data to be written to the device. Note that in a read operation the data field is ignored by the device. Access to the control registers is via the serial port through one of the operating modes described below. Serial Port The AD74111 contains a flexible serial interface port that is used to program and read the control registers and to send and receive DAC and ADC audio data. The serial port is compatible with many popular DSPs and can be programmed to operate in a variety of modes, depending on which one best suits the DSP being used. The serial port can be set to operate as a Master or Slave device, as discussed below. Figure 11 shows a timing diagram of the serial port. –10– REV. 0 AD74111 tFS DFS tFH tCH DCLK tCL tFD MSB DIN MSB–1 MSB–2 tDS tDH MSB–1 MSB DOUT MSB–2 tDD Figure 11. Serial Port (SPORT) Timing Serial Port Operating Modes Master Mode Operation The serial port of the AD74111 can be programmed to operate in a variety of modes depending on the requirements and flexibility of the DSP to which it is connected. The two principal modes of operation are Mixed mode and Data mode. In Master mode, the DFS and DCLK pins are outputs from the AD74111. This is the easiest mode in which to use the AD74111 because the correct timing relationship between sample rate, DCLK, and DFS is controlled by the AD74111. Mixed Mode Slave Mode Operation Mixed mode allows the control registers of the AD74111 to be programmed and read back. It also allows data to be sent to the DACs and data to be read from the ADCs. In Mixed mode, there are separate data slots, each with its own frame synchronization signal (DFS) for control and DAC or ADC information. The AD74111 powers up in Mixed mode by default to allow the control registers to be programmed. Figure 13 shows the default setting for Mixed mode. In Slave mode, the DFS and DCLK pins are inputs to the AD74111. Care needs to be exercised when designing a system to operate the AD74111 in this mode as the relationship between the sample rate, DCLK, and DFS needs to be controlled by the DSP or other controller and must be compatible with the internal DAC/ADC engine of the AD74111. Figure 12 shows a block diagram of the DAC engine and the AD74111’s serial port. The sample rate for the DAC engine is determined by the MCLK and MCLK prescalers. The DAC engine will read data from the DAC Data register at this rate. It is therefore important that the serial port is updated at the same rate, as any error between the two will accumulate and eventually cause the DAC engine to have to resynchronize with the serial port, which will cause erroneous values on the DAC output pins. Data Mode Data mode can be used when programming or reading the control registers is no longer required. Data mode provides a frame synchronization (DFS) pulse for each sample of data. Once the part has been programmed into Data mode, the only way to change the control registers is to perform a hardware reset to put the AD74111 back into Mixed mode. Figure 15 shows the default setting for Data mode. RESYNC* DAC ENGINE Data-Word Length The AD74111 can be programmed to send DAC audio data and receive ADC audio data in different word length formats of 16, 20, or 24 bits. The default mode is 16 bits, but this can be changed by programming Control Register C for the appropriate word length. DAC DATA REGISTER DFS DIN Selecting Master or Slave Mode The initial operating mode of the AD74111 is determined by the state of the DIN pin following a reset. If the DIN pin is high during this time, Slave mode is selected. In Slave mode, the DFS and DCLK pins are inputs and the control signals for these pins must be provided by the DSP or other controller. If the DIN pin is low immediately following a reset, the AD74111 will operate in Master mode. REV. 0 VOUT LOAD DAT SERIAL PORT *RESYNC IS ONLY USED WHEN THE DAC BECOMES UNSYNCHRONIZED WITH THE SERIAL PORT Figure 12. DAC Engine In most cases, it is easy to keep a DSP in synchronization with the AD74111 if they are both run from the same clock or the DSP clock is a multiple of the AD74111’s MCLK. In this case, –11– AD74111 there will be a fixed relationship between the instruction cycle time of the DSP program and the AD74111, so a timer could be used to accurately control the DAC updates. If a timer is not available, the Multiframe-Sync (MFS) mode could be used to generate a DFS pulse every 16 or 32 DCLKs, allowing the DSP to accurately control the number of DCLKs between updates using an autobuffering or DMA type technique. In all cases for Slave mode operation, there should be 128 DCLKs (Normal mode) or 256 DCLKs (Fast mode) between DAC updates. The ADC operates in a similar manner; however, if the DSP does not read an ADC result, this will appear only as a missed sample and will not be audible. Slave mode is most suited to state-machine type applications where the number of DCLKs and their relationships to the other interface signals can be controlled. Table II. Serial Mode Selection CRD:3 DM/MM CRD:2 CRC:5, 4 DSP Word Operating Mode Width Mode Figure 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 15 19 13 17 16 20 14 18 16 16 16 16 >16 >16 >16 >16 16-Bit Data Mode 32-Bit Data Mode 16-Bit Mixed Mode 32-Bit Mixed Mode 16-Bit Data Mode 32-Bit Data Mode 16-Bit Mixed Mode 32-Bit Mixed Mode 1/fS DIN CONTROL (16 BITS) DAC (16 BITS) CONTROL (16 BITS) DAC (16 BITS) DOUT STATUS STATUS (16 BITS) ADC (16 BITS) STATUS STATUS (16 (16 BITS) BITS) ADC (16 BITS) DFS (MM16) 128 DCLKs (NORMAL MODE) 256 DCLKs (FAST MODE) Figure 13. 16-Bit Mixed Mode, Word Length = 16 Bits 1/fS DIN CONTROL (16 BITS) DAC DATA (24 BITS) CONTROL (16 BITS) DOUT STATUS (16 BITS) ADC DATA (24 BITS) STATUS (16 BITS) DFS (MM16) 16 DCLKS 128 DCLKs (NORMAL MODE) 256 DCLKs (FAST MODE) Figure 14. 16-Bit Mixed Mode, Word Length = 24 Bits 1/fS DIN DAC (16 BITS) DAC (16 BITS) DOUT ADC STATUS (16 BITS) ADC STATUS (16 BITS) BITS) (16 DFS (MM16) 128 DCLKs (NORMAL MODE) 256 DCLKs (FAST MODE) Figure 15. 16-Bit Data Mode, Word Length = 16 Bits –12– REV. 0 AD74111 1/fS DIN DAC DATA (24 BITS) DAC DATA (24 BITS) DOUT ADC DATA (24 BITS) ADC DATA (24 BITS) DFS (MM16) 16 DCLKs 128 DCLKs (NORMAL MODE) 256 DCLKs (FAST MODE) Figure 16. 16-Bit Data Mode, Word Length = 24 Bits 1/fS DIN CONTROL (16 BITS) DAC DATA (16 BITS) CONTROL (16 BITS) DOUT STATUS (16 BITS) ADC DATA (16 BITS) STATUS (16 BITS) DFS 32 DCLKs 128 DCLKs (NORMAL MODE) 256 DCLKs (FAST MODE) Figure 17. 32-Bit Mixed Mode, Word Length = 16 Bits 1/fS DIN CONTROL (16 BITS) DAC DATA (24 BITS) CONTROL (16 BITS) DOUT STATUS (16 BITS) ADC DATA (24 BITS) STATUS (16 BITS) DFS 32 DCLKS 128 DCLKs (NORMAL MODE) 256 DCLKs (FAST MODE) Figure 18. 32-Bit Mixed Mode, Word Length = 24 Bits 1/fS DIN DAC DATA (16 BITS) DAC DATA (24 BITS) DOUT ADC DATA (16 BITS) ADC DATA (24 BITS) DFS 128 DCLKs (NORMAL MODE) 256 DCLKs (FAST MODE) Figure 19. 32-Bit Data Mode, Word Length = 16 Bits REV. 0 –13– AD74111 1/fS DIN DAC DATA (24 BITS) DAC DATA (24 BITS) DOUT ADC DATA (24 BITS) ADC DATA (24 BITS) DFS 128 DCLKs (NORMAL MODE) 256 DCLKs (FAST MODE) Figure 20. 32-Bit Data Mode, Word Length = 24 Bits 1/fS 32 DCLKs DFS DIN DOUT C DAC C DAC S ADC S ADC Figure 21. Multiframe Sync 32-Bit Mixed Mode 1/fS 32 DCLKs DFS DIN DOUT DAC DAC ADC ADC Figure 22. Multiframe Sync 32-Bit Data Mode 1/fS 16 DCLKS DFS DIN C DAC C DAC DOUT S ADC S ADC Figure 23. Multiframe Sync 16-Bit Mixed Mode –14– REV. 0 AD74111 1/fS 16 DCLKs DFS DIN DAC DAC DOUT ADC ADC Figure 24. Multiframe Sync 16-Bit Data Mode Table III. Multiframe Sync Selection CRD:9 MFS CRD:3 DM/MM CRC:2 DSP Mode Operating Mode Figure 1 1 1 1 0 0 1 1 0 1 0 1 16-Bit Data Mode 32-Bit Data Mode 16-Bit Mixed Mode 32-Bit Mixed Mode 24 22 23 21 Table IV. Control Register Map Address (Binary) Name Description Type Width Reset Setting 0000 0001 0010 0011 0100 0101 0110 CRA CRB CRC CRD CRE CRF CRG Control Register A Control Register B Control Register C Control Register D Control Register E Control Register F Control Register G R/W R/W R/W R/W R/W R R/W 10 10 10 10 10 10 10 00h 00h 00h 08h or 09h* 00h 00h 00h *09h if DIN is low and 08h if DIN is high. Table V. Control Word Descriptions Bit Field Description 15 R/W When this bit is high, the contents of the data field will be written to the register specified by the Address Field. When this bit is low, a read of the register specified by the Address Field will occur at the next sample interval; the contents of the Data Field are ignored. This 4-bit field is used to select one of the seven control registers of the AD74111. This bit is reserved and should always be programmed with zero. This 10-bit field holds the data that is to be written to or read from the register specified in the Address Field. 14–11 Register Address 10 Reserved 9–0 Data Field REV. 0 –15– AD74111 Table VI. Control Register A Function R/W ADDRESS RES Reserved ADC Input Amplifier ADC DAC Reference Reference Amplifier Reserved 15 14, 13, 12, 11 10 9, 8, 7 6 5 4 3 2 1, 0 1 0000 0 0 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 Table VII. Control Register B Function R/W ADDRESS RES Reserved Third MCLK Divider Second MCLK Divider First MCLK Divider 15 14, 13, 12, 11 10 9, 8, 7, 6 5, 4 3, 2 1, 0 1 0001 0 0 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 1 00 = Divide by 1 01 = Divide by 2 10 = Divide by 3 11 = Divide by 1 00 = Divide by 1 01 = Divide by 2 10 = Divide by 3 11 = Divide by 1 Table VIII. Control Register C Function R/W ADDRESS RES Reserved DAC and ADC Word Width Low Group Delay DAC De-emphasis ADC HighPass Filter 15 14, 13, 12, 11 10 9, 8, 7, 6 5, 4 3 2, 1 0 1 0010 0 0 00 = 16 Bits 01 = 20 Bits 10 = 24 Bits 11 = 24 Bits 0 = Disabled 1 = Enabled 00 = None 01 = 44.1 kHz 10 = 32 kHz 11 = 48 kHz 0 = Disabled 1 = Enabled Table IX. Control Register D Function R/W ADDRESS RES Multiframe Sync Reserved DM/MM DSP Mode Fast DCLK Master/ Slave 15 14, 13, 12, 11 10 9 8, 7, 6, 5, 4 3 2 1 0 1 0011 0 0 = Normal Mode 1 = MFS Mode 0 0 = Data Mode 0 = 16 Bits 1 = Mixed Mode 1 = 32 Bits 0 = 128 ⫻ fS 1 = 256 ⫻ fS 0 = Slave 1 = Master –16– REV. 0 AD74111 Table X. Control Register E Function R/W ADDRESS RES Reserved ADCL Peak Enable ADC Gain ADC Mute DAC Mute 15 14, 13, 12, 11 10 9, 8, 7, 6 5 4, 3, 2 1 0 1 0100 0 0 0 = Disabled 1 = Peak Enable 000 = 0 dB 001 = 3 dB 010 = 6 dB 011 = 9 dB 1XX = 12 dB 0 = Normal 1 = Mute 0 = Normal 1 = Mute Table XI. Control Register F Function R/W ADDRESS RES Reserved ADC Input Peak Level 15 14, 13, 12, 11 10 9, 8, 7, 6 5, 4, 3, 2, 1, 0 0 000000 = 0 dBFS 000001 = –1 dBFS 000010 = –2 dBFS 111110 = –62 dBFS 111111 = –63 dBFS 0 0101 0 Table XII. Control Register G Function R/W ADDRESS RES DAC Volume 15 14, 13, 12, 11 10 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 0 0000000000 = 0 dBFS 0000000001 = (1023/1024) dBFS 0000000010 = (1022/1024) dBFS 1111111110 = (2/1024) dBFS 1111111111 = Mute 1 REV. 0 0110 –17– AD74111 OUTLINE DIMENSIONS 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AB –18– REV. 0 –19– –20– PRINTED IN U.S.A. C03069–0–2/03(0)