Quad-Channel,
Software Configurable Input/Output
AD74412R
Data Sheet
FEATURES
GENERAL DESCRIPTION
Quad-channel software configurable input/output circuit
Screw terminals protected to ±40 V
Line protectors to block power from the screw terminals to
supplies
Six configurable modes
Voltage input
Current input
Voltage output
Current output
Digital input
RTD measurement
Internal 16-bit, Σ-∆ ADC with optional 50 Hz and 60 Hz
rejection
13-bit monotonic DACs
Charge pump for true zero voltage output
Internal temperature sensor, 5°C accuracy
On-chip diagnostics including open circuit and short-circuit
detection
Robust architecture
SPI
Temperature range: −40°C to +85°C
64-lead LFCSP
The AD74412R is a quad-channel software configurable
input/output solution for building and process control
applications. The AD74412R contains functionality for analog
output, analog input, digital input, and resistance temperature
detector (RTD) measurements integrated into a single chip
solution with an interface compatible with the serial port
interface (SPI).
APPLICATIONS
PRODUCT HIGHLIGHTS
Building control systems
Process control
Industrial automation
1.
2.
3.
Rev. A
The device features a 16-bit, Σ-∆ analog-to-digital converter
(ADC) and four configurable, 13-bit digital-to-analog converters
(DACs) to provide four configurable input/output channels and a
suite of diagnostic functions.
There are several modes related to the AD74412R. These modes
are voltage output, current output, voltage input, externally
powered current input, loop powered current input, external RTD
measurement, digital input logic, and loop powered digital input.
The AD74412R contains a high accuracy 2.5 V internal
reference to drive the DACs and the ADC.
COMPANION PRODUCTS
External Reference: ADR4525
Power: ADP1720
Quad-Channel, Software Configurable Channels.
Built In Diagnostics and Alert Features.
Robust Architecture. Surge tested to ±1 kV, per the
IEC61000-4-5 standard, on the input/output terminals
with unshielded cables.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD74412R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ADC Functionality ..................................................................... 40
Applications ....................................................................................... 1
Diagnostics .................................................................................. 44
General Description ......................................................................... 1
DACs ............................................................................................ 45
Companion Products ....................................................................... 1
Driving Inductive Loads............................................................ 46
Product Highlights ........................................................................... 1
Reset Function ............................................................................ 46
Revision History ............................................................................... 3
Thermal Alert and Thermal Reset ........................................... 46
Functional Block Diagram .............................................................. 4
Faults and Alerts ......................................................................... 46
Specifications..................................................................................... 5
Power Supply Monitors ............................................................. 46
Voltage Output .............................................................................. 5
GPO_x Pins ................................................................................. 47
Current Output ............................................................................. 6
SPI Interface and Diagnostics ................................................... 47
Voltage Input ................................................................................. 7
Board Design and Layout Considerations .................................. 50
Current Input Externally Powered ............................................. 8
Applications Information .............................................................. 51
Current Input Loop Powered ...................................................... 9
Register Map ................................................................................... 52
RTD Measurement ....................................................................... 9
NOP Register .............................................................................. 53
Digital Input Logic ..................................................................... 10
Function Setup Register per Channel...................................... 53
Digital Input Loop Powered ...................................................... 10
ADC Configuration Register per Channel ............................. 53
ADC Specifications .................................................................... 11
Digital Input Configuration Register per Channel................ 54
General Specifications ............................................................... 12
GPO Parallel Data Register ....................................................... 55
Timing Characteristics .............................................................. 14
GPO Configuration Register per Channel ............................. 55
Absolute Maximum Ratings .......................................................... 16
Output Configuration Register per Channel.......................... 56
Thermal Resistance .................................................................... 16
DAC Code Register per Channel ............................................. 56
ESD Caution ................................................................................ 16
DAC Clear Code Register per Channel................................... 56
Pin Configuration and Function Descriptions ........................... 17
DAC Active Code Register per Channel ................................. 57
Typical Performance Characteristics ........................................... 20
Digital Input Threshold Register.............................................. 57
Voltage Output ............................................................................ 20
ADC Conversion Control Register .......................................... 57
Current Output ........................................................................... 22
Diagnostics Select Register ....................................................... 58
Reference ..................................................................................... 24
Digital Output Level Register ................................................... 59
ADC ............................................................................................. 25
ADC Conversion Results Register per Channel .................... 60
Supplies ........................................................................................ 26
Diagnostic Results Registers per Diagnostic Channel .......... 60
Theory of Operation ...................................................................... 27
Alert Status Register ................................................................... 60
Robust Architecture ................................................................... 27
Live Status Register .................................................................... 62
Serial Interface ............................................................................ 27
Alert Mask Register.................................................................... 63
DAC Architecture ....................................................................... 27
Readback Select Register ........................................................... 63
ADC Overview ........................................................................... 28
80 SPS ADC Conversion Control Register ............................. 64
Reference ..................................................................................... 28
Thermal Reset Enable Register................................................. 64
Power-On State of the AD74412R............................................ 28
Command Register .................................................................... 65
Device Functions ........................................................................ 28
Scratch or Spare Register ........................................................... 65
Digital Input, Loop Powered Mode ......................................... 38
Silicon Revision Register ........................................................... 65
Getting Started ............................................................................ 39
Outline Dimensions ....................................................................... 66
Using Channel Functions .......................................................... 39
Ordering Guide .......................................................................... 66
Rev. A | Page 2 of 66
Data Sheet
AD74412R
REVISION HISTORY
9/2019—Rev. 0 to Rev. A
Change to Figure 6 and Figure 8 ...................................................20
Changes to Figure 18 ......................................................................22
Changes to Table 19 and Table 20 .................................................43
9/2019—Revision 0: Initial Version
Rev. A | Page 3 of 66
AD74412R
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
REFOUT
ALDO5V
ALDO1V8
REFIN
AVDD
AD74412R
5V
LDO
1.8V
ALDO
2.5V
VREF
IOVDD
DVCC
DLDO1V8
CCOMP_x 1
1.8V
DLDO
INTERNAL
OSCILLATOR
VIOUTP_x1
DAC
CASCODE_x 1
DGND
OUTPUT/
INPUT
CONFIGURE
SCLK
SYNC
16-BIT
ADC
SDI
ADC_RDY
LDAC
GPO_A
SENSEL_x1
INPUT
SHIFT
REGISTER
AND
DIGITAL
LOGIC
SENSELF_x1
DIAGNOSTICS
CHANNELS
GPO_B
GPO_C
THRESHOLD
GPO_D
RESET
CHANNEL A
POWER-ON
RESET
CHANNEL B
AVSS = –DVCC
CHANNEL C
CHARGE PUMP
CHANNEL D
AGND1
AVSS
CPUMP_N CPUMP_P
AGND2
AGND3
AGND_SENSE
1x
Figure 1.
Rev. A | Page 4 of 66
= A, B, C, AND D
21274-001
ALERT
SENSEHF_x 1
MUX
SDO
VIOUTN_x1
SENSEH_x 1
Data Sheet
AD74412R
SPECIFICATIONS
VOLTAGE OUTPUT
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V (REFOUT tied to REFIN), DVCC = 2.7 V to 5.5 V, IOVDD = 1.7 V to 5.5
V, and all specifications at TA = −40°C to +85°C, unless otherwise noted. Resistor load (RLOAD) = 100 kΩ and capacitor load (CLOAD) =
68 nF per recommended configuration.
Table 1.
Parameter
VOLTAGE OUTPUT
Resolution
Output Range
ACCURACY
Total Unadjusted Error (TUE)
TUE at 25°C
Min
Max
Unit
13
0
11
Bits
V
−0.4
−0.35
−0.2
−15
+0.4
+0.35
+0.2
+0.15
TUE Drift vs. Time 1
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Gain Error
OUTPUT CHARACTERISTICS
Load
Headroom (500 Ω Load)
Short-Circuit Current (Sourcing)
Typ
±400
±100
−4
−1
−8
−0.4
−0.25
+4
+1
+8
+0.4
+0.25
500
4
100k
25
5.5
3.0
29
7
3.8
%FSR
%FSR
%FSR
%FSR
ppm FSR
ppm FSR
LSB
LSB
mV
%FSR
%FSR
Ω
V
0.12
80
mA
mA
mA
µF
Ω
dB
90
µs
Output Noise
Output Noise Spectral Density
Noise (External Reference)
0.1
2
LSB p-p
μV/√Hz
Output Noise
Output Noise Spectral Density
AC PSRR
0.07
320
65
LSB p-p
nV/√Hz
dB
Short-Circuit Current (Sinking)
Maximum Capacitive Load
DC Output Impedance
DC Power Supply Rejection Ratio (PSRR)
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
32
9
4.5
2
Noise (Internal Reference)
1
Guaranteed by design and characterization.
Rev. A | Page 5 of 66
Test Conditions/Comments
Internal reference
External reference
Internal reference
External reference
Internal reference, drift after 1000 hours at TA = 85°C
External reference, drift after 1000 hours at TA = 85°C
Guaranteed monotonic
Internal reference
External reference
Minimum voltage difference required between
AVDD and the input/output positive (I/OP_x
where x is the channel number) screw terminal to
provide 11 V across a 500 Ω load
Per channel, lower limit bit = 0 (default)
Per channel, lower limit bit = 1
10 V step (0.5 V to 10.5 V or 10.5 V to 0.5 V) to
±0.05%FSR
Measured at the I/OP_x screw terminal, 2.5 V
output
0.1 Hz to 10 Hz bandwidth
Measured at 1 kHz
Measured at the I/OP_x screw terminal, 2.5 V
output
0.1 Hz to 10 Hz bandwidth
Measured at 1 kHz
200 mV at 1 kHz sine wave superimposed on the
AVDD supply
AD74412R
Data Sheet
CURRENT OUTPUT
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V (REFOUT tied to REFIN), DVCC = 2.7 V to 5.5 V, IOVDD= 1.7 V to
5.5 V, and all specifications at TA=−40°C to +85°C, unless otherwise noted. RLOAD = 250 Ω, CLOAD = 68 nF per recommended configuration,
and the sense resistor (RSENSE) = 100 Ω, 0.1%, 10 ppm/°C.
Table 2.
Parameter
CURRENT OUTPUT
Resolution
Output Range
ACCURACY
TUE 1
TUE at 25°C
Min
Max
Unit
13
0
25
Bits
mA
−0.55
−0.45
−0.35
−0.2
+0.55
+0.45
+0.35
+0.2
TUE Drift vs. Time 2
INL
DNL
Offset Error
Gain Error1
OUTPUT CHARACTERISTICS
Headroom
Open Circuit Voltage
Output Impedance
DC PSRR
DYNAMIC PERFORMANCE2
Output Current Settling Time
Typ
500
300
−4
−1
−37.5
−0.4
−0.3
+5.0
5
+4
+1
+37.5
+0.4
+0.3
%FSR
%FSR
%FSR
%FSR
ppm FSR
ppm FSR
LSB
LSB
µA
%FSR
%FSR
Internal reference
External reference
Internal reference
External reference
Internal reference, drift after 1000 hours at TA = 85°C
External reference, drift after 1000 hours at TA = 85°C
From zero-scale to full-scale
Guaranteed monotonic
V
Minimum voltage difference required between AVDD
and the I/OP_x screw terminal to source 25 mA
AVDD
4
200
V
MΩ
nA/V
230
µs
Output Noise
Output Noise Spectral Density
Noise (External Reference)
0.2
12
LSB p-p
nA/√Hz
Output Noise
Output Noise Spectral Density
AC PSRR
0.15
2
80
LSB p-p
nA/√Hz
dB
1.5
Noise (Internal Reference)
1
2
Test Conditions/Comments
RSENSE accuracy directly impacts the TUE and gain error.
Guaranteed by design and characterization.
Rev. A | Page 6 of 66
Internal reference
External reference
PSRR measured with a change in AVDD
25 mA step up or down, time to settle within a
window of ±100 µA of final current
Measured at the I/OP_x screw terminal with 250 Ω
load, 12.5 mA output
0.1 Hz to 10 Hz bandwidth
Measured at 1 kHz
Measured at the I/OP_x screw terminal with 250 Ω
load, 12.5 mA output
0.1 Hz to 10 Hz bandwidth
Measured at 1 kHz, 12.5 mA output
Voltage on the supply at 1 kHz to the voltage across
the 250 Ω.
Data Sheet
AD74412R
VOLTAGE INPUT
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V (REFOUT tied to REFIN), DVCC = 2.7 V to 5.5 V, IOVDD = 1.7 V to
5.5 V, and all specifications at TA=−40°C to +85°C, unless otherwise noted. CLOAD = 68 nF per recommended configuration.
Table 3.
Parameter
VOLTAGE INPUT
Input Resolution
Input Range
ACCURACY
TUE
TUE at 25°C
Min
Max
Unit
16
0
10
Bits
V
−0.4
−0.2
−0.3
−0.1
+0.4
+0.2
+0.3
+0.1
TUE Drift vs. Time 1
INL
Gain Error
Offset Error
OTHER INPUT SPECIFICATIONS
DC PSRR1
Normal Mode Rejection1
Input Bias Current at 25°C
Input Resistance
1
−5
Typ
500
500
±2
2000
±2
+5
10
75
−100
175
195
%FSR
%FSR
%FSR
%FSR
ppm FSR
ppm FSR
LSB
ppm FSR
LSB
+100
µV/V
dB
nA
215
kΩ
Guaranteed by design and characterization.
Rev. A | Page 7 of 66
Test Conditions/Comments
Internal reference
External reference
Internal reference
External reference
Internal reference, drift after 1000 hours, TA = 85°C
External reference, drift after 1000 hours, TA = 85°C
Internal reference
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
As seen from the I/OP_x screw terminal, ADC is
either idle or converting; 200 kΩ to GND is
disabled (CH_200K_TO_GND bit = 0), does not
include transient voltage suppressor (TVS)
leakage
200 kΩ to GND enabled
AD74412R
Data Sheet
CURRENT INPUT EXTERNALLY POWERED
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V (REFOUT tied to REFIN), DVCC = 2.7 V to 5.5 V, IOVDD = 1.7 V to
5.5 V, and all specifications at TA=−40°C to +85°C, unless otherwise noted. CLOAD = 68 nF per recommended configuration. AGND −
0.5 V < I/OP_x screw terminal voltage < AVDD − 0.2 V, and RSENSE = 100 Ω, 0.1%, 10 ppm/°C.
Table 4.
Parameter
CURRENT INPUT
Input Resolution
Input Range
Short-Circuit Current Limit
ACCURACY
TUE 1
TUE at 25°C
Min
Max
Unit
Test Conditions/Comments
16
0
25
25
35
Bits
mA
mA
Sensed across the external 100 Ω resistor
Nonprogrammable
−0.5
−0.36
−0.34
−0.2
+0.5
+0.36
+0.34
+0.2
TUE Drift vs. Time1, 2
INL
Gain Error
Offset Error
OTHER INPUT SPECIFICATIONS
DC PSRR2
Input Impedance
Compliance
1
2
−5
Typ
700
600
+2
2000
±2
150
200
6.3
+5
%FSR
%FSR
%FSR
%FSR
ppm FSR
ppm FSR
LSB
ppm FSR
LSB
nA/V
Ω
V
RSENSE accuracy directly impacts the TUE and gain error.
Guaranteed by design and characterization; not production tested.
Rev. A | Page 8 of 66
Internal reference, 0.16% contribution from RSENSE
External reference, 0.16% contribution from RSENSE
Internal reference
External reference
Internal reference, drift after 1000 hours, TA = 85°C
External reference, drift after 1000 hours, TA = 85°C
Including 100 Ω RSENSE
Minimum voltage required at the I/OP_x screw
terminal to sink 25 mA
Data Sheet
AD74412R
CURRENT INPUT LOOP POWERED
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V (REFOUT tied to REFIN), DVCC = 2.7 V to 5.5 V, IOVDD = 1.7 V to
5.5 V, and all specifications at TA=−40°C to +85°C, unless otherwise noted. CLOAD = 68 nF per recommended configuration, AGND − 0.5 V <
I/OP_x screw terminals voltage < AVDD − 0.2 V, and RSENSE = 100 Ω, 0.1%, 10 ppm/°C.
Table 5.
Parameter
CURRENT INPUTS
Input Resolution
Input Range
Programmable Current Limit
ACCURACY
TUE 1
TUE at 25°C
Min
Typ
Max
Unit
16
0
0.5
25
24.5
Bits
mA
mA
−0.5
−0.36
−0.34
−0.2
+0.5
+0.36
+0.34
+0.2
TUE Drift vs. Time1, 2
INL
Gain Error
Offset Error
OTHER INPUT SPECIFICATIONS
DC PSRR2
Input Impedance
Headroom
1
2
700
600
+2
2000
±2
−5
+5
150
175
Test Conditions/Comments
Sensed across external 100 Ω resistor
Typical programmable current limit, current input loop
powered enabled, 13-bit resolution
%FSR
%FSR
%FSR
%FSR
ppm FSR
ppm FSR
LSB
ppm FSR
LSB
nA/V
Ω
V
5.0
Internal reference, 0.16% contribution from RSENSE
External reference, 0.16% contribution from RSENSE
Internal reference
External reference
Internal reference, drift after 1000 hours, TA = 85°C
External reference, drift after 1000 hours, TA = 85°C
Linearity specified in 0.1 mA – 25 mA range
Including 100 Ω RSENSE
Minimum required difference between AVDD and the I/OP_x
screw terminal voltage to source 25 mA
RSENSE accuracy directly impacts the TUE and gain error.
Guaranteed by design and characterization.
RTD MEASUREMENT
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V (REFOUT pin tied to REFIN pin), DVCC = 2.7 V to 5.5 V, IOVDD =
1.7 V to 5.5 V, and all specifications at TA= −40°C to +85°C, unless otherwise noted. External current limiting resistor of 2 kΩ, 0.1%
accuracy, and 10 ppm/°C connected to the SENSEH_x pin. RSENSE = 100 Ω, 0.1%, 10 ppm/°C.
Table 6.
Parameter
RESISTANCE MEASUREMENT
Input Range
Bias Voltage
Pull-Up Resistor (RPULL-UP)
ACCURACY
Measurement Range
0 Ω to 80 Ω
80 Ω to 200 Ω
200 Ω to 1 kΩ
1 kΩ to 10 kΩ
10 kΩ to 20 kΩ
20 kΩ to 100 kΩ
100 kΩ to 200 kΩ
200 kΩ to 1 MΩ
Min
Typ
Max
Unit
Test Conditions/Comments
1
MΩ
V
kΩ
2-wire RTD measurements supported
2.5
2.1
0.5% ± 0.5
0.3
0.2
0.2
0.3
0.8
1.0
8
Ω
%
%
%
%
%
%
%
0
Rev. A | Page 9 of 66
RPULL-UP is comprised of the external 2 kΩ resistor
and the external 100 Ω RSENSE with an accuracy of
0.1%, 10 ppm/°C
±% of measured value ± Ω offset
±% of measured value
±% of measured value
±% of measured value
±% of measured value
±% of measured value
±% of measured value
±% of measured value
AD74412R
Data Sheet
DIGITAL INPUT LOGIC
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V (REFOUT pin tied to REFIN pin), DVCC = 2.7 V to 5.5 V, IOVDD =
1.7 V to 5.5 V, and all specifications at TA=−40°C to +85°C, unless otherwise noted.
Table 7.
Parameter
DIGITAL INPUTS
Input Data Rate 1
Maximum Input Voltage1
Minimum Input Voltage1
CURRENT SINK
Series Resistor Value
Current Sink Range
Current Sink Resolution
Current Sink Accuracy
VOLTAGE THRESHOLDS MODES
AVDD Threshold Mode
Threshold Range
Threshold Resolution
Hysteresis
Fixed Threshold Mode
Threshold Range
Threshold Resolution
Hysteresis
Threshold Accuracy
1
Min
Typ
Max
Unit
Test Conditions/Comments
5
kHz
40
V
Unfiltered input, SENSEL pin driven by a low
impedance source, 0 V to 10 V signal, duty cycle: 60:40
Limited by the TVS clamping voltage
−40
2.3
0
1.8
120
2
AVDD/60
Typical programmable current sink to AGND
AVDD × 59/60
V
V
V
Programmable trip level shared between all channels
16
V
V
V
%FSR
Programmable trip level shared between all channels
AVDD/30
AVDD/60
0.5
kΩ
mA
µA
%FSR
0.5
0.5
2
Guaranteed by design and characterization.
DIGITAL INPUT LOOP POWERED
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V (REFOUT pin tied to REFIN pin), DVCC = 2.7 V to 5.5 V, IOVDD =
1.7 V to 5.5 V, and all specifications at TA=−40°C to +85°C, unless otherwise noted.
Table 8.
Parameter
DIGITAL INPUTS
Input Data Rate 1
Dry Contact Wetting Current
Range
Headroom
THRESHOLD MODES
AVDD Threshold Mode
Threshold Range
Threshold Resolution
Hysteresis
Fixed Threshold Mode
Threshold Range
Threshold Resolution
Hysteresis
Threshold Accuracy
1
Min
Typ
Max
Unit
Test Conditions/Comments
15
5
kHz
24.5
mA
Unfiltered input, typically dominated by wetting
current, load capacitance, and threshold voltage
Loop powered—typical programmable
current per channel
Minimum required voltage difference between
AVDD and the I/OP_x screw terminal to source 25 mA
0.5
5.0
V
AVDD/60
AVDD × 59/60
V
V
V
Programmable trip level shared between all channels
16
V
V
V
%FSR
Programmable trip level shared between all channels
AVDD/30
AVDD/60
0.5
0.5
0.5
2
Guaranteed by design and characterization.
Rev. A | Page 10 of 66
Data Sheet
AD74412R
ADC SPECIFICATIONS
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V (REFOUT tied to REFIN), DVCC = 2.7 V to 5.5 V, IOVDD = 1.7 V to 5.5
V, and all specifications at TA=−40°C to +85°C, unless otherwise noted. AGND − 0.5 V < I/OP_x screw terminal voltage < AVDD − 0.2 V
when measuring current by sensing voltage across RSENSE.
Table 9.
Parameter
ADC SPECIFICATIONS
Resolution
No Missing Codes 1
Conversion Rates1
Min
Max
16
16
20 SPS
80 SPS
4.8 kSPS
Noise1
ADC INPUT RANGES
0 V to 10 V
Unit
Test Conditions/Comments
Bits
Bits
20
80
4.8
SPS
SPS
kSPS
Sample rates vary depending on the number of channels selected
and the use of single or continuous conversion modes.
50 Hz and 60 Hz rejection enabled.
50 Hz and 60 Hz rejection enabled.
50 Hz and 60 Hz rejection disabled.
Refer to Table 19.
Typically used to measure voltage across I/OP_x to I/ON_x screw
terminals (I/ON_x is the input/output negative, where x is the
channel number).
Range
TUE
INL
Gain Error
Offset Error
0 V to 2.5 V
0
Range
TUE
INL
Gain Error
Offset Error
−2.5 V to 0 V
0
Range
TUE
INL
Gain Error
Offset Error
−2.5 V to +2.5 V
−2.5
Range
TUE
INL
Gain Error
Offset Error
DIAGNOSTICS SPECIFICATIONS
Accuracy
Typ
10
±0.4
±2
2000
±2
V
%FSR
LSB
ppm FSR
LSB
Typically used to measure the current flowing out of the
AD74412R through the 100 Ω RSENSE or RTD voltage
measurements at the I/OP_x screw terminal.
2.5
±0.25
±2
2000
±2
V
%FSR
LSB
ppm FSR
LSB
TUE does not include RSENSE.
Typically used to measure the current flowing into the AD74412R
across the 100 Ω RSENSE.
0
±0.2
±2
2000
±2
V
%FSR
LSB
ppm FSR
LSB
Typically used to measure bidirectional current across 100 Ω sense
resistor in voltage output mode.
−2.5
±0.2
±2
2000
±2
+2.5
V
%FSR
LSB
ppm FSR
ppm FSR
Measured at the 0 V input voltage.
2
%
% of measured value.
Rev. A | Page 11 of 66
AD74412R
Parameter
INTERNAL TEMPERATURE SENSOR1
Junction Operating
Temperature Range
Data Sheet
Min
−40
Accuracy
Resolution
1
Typ
Max
Unit
Test Conditions/Comments
+125
°C
The 85°C maximum specified in the Ordering Guide is the ambient
temperature. However, the temperature sensor is specified to a die
temperature of 125°C.
5
0.2
°C
°C
Guaranteed by design and characterization; not production tested.
GENERAL SPECIFICATIONS
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V (REFOUT tied to REFIN), DVCC = 2.7 V to 5.5 V, IOVDD = 1.7 V to
5.5 V, and all specifications at TA=−40°C to +85°C, unless otherwise noted.
Table 10.
Parameter
REFERENCE SPECIFICATIONS
Reference Input
Reference Input Voltage
DC Input Current
Reference Output
Output Voltage
Reference Temperature Coefficient 1
Output Voltage Drift vs. Time1
Output Noise1
Output Noise Spectral Density
Capacitive Load
Output Impedance
Short Circuit
CHARGE PUMP
Voltage
Accuracy
Output Impedance
CASCODE PINS
Cascode Voltage
Min
Typ
Max
Unit
2.495
−1
2.5
2.505
+1
V
µA
2.495
2.5
2.505
20
TA = 25°C
0.6
25
V
ppm/°C
ppm FSR
µV p-p
µV/√Hz
nF
Ω
mA
−DVCC
V
The charge pump generates a voltage
that is equal to the negative of DVCC
±10
12.5
%
Ω
400
59
2.3
100
AVDD − 8
AVDD – 7
AVDD − 6
V
TEMPERATURE ALERT AND RESET1
Temperature Alert
115
°C
Temperature Alert Accuracy
Temperature Reset
5
140
°C
°C
Temperature Reset Accuracy
5
°C
Rev. A | Page 12 of 66
Test Conditions/Comments
Drift after 1000 hours, TA = 85°C
0.1 Hz to 10 Hz bandwidth.
Frequency = 1 kHz
On REFOUT pin
Sourcing or sinking up to 5 mA
Channel output stage enabled, with
decimal Code 0x000 loaded to the DAC
Junction temperature
Junction temperature, high temperature
event flags the alert status and the ALERT
pin (if unmasked)
Junction temperature, resets the device if
over temperature event when
EN_THERM_RST =1
Data Sheet
Parameter
LOGIC INPUTS
Input Voltage
High (VIH)
AD74412R
Min
Typ
High Impedance Leakage Current
GPO_x Pin
Output Voltage
Low VOL
Pull-Down Resistance
High Impedance Leakage Current
OPEN-DRAIN LOGIC OUTPUTS
VOL
High Impedance Leakage Current
POWER SUPPLY MONITORS
AVDD Threshold
ALDO5V Threshold
DVCC Threshold
ALDO1V8 Threshold
AVSS Threshold
POWER REQUIREMENTS
Supply Voltages1
AVDD
DVCC
IOVDD
Supply Quiescent Currents
AVDD Current
Test Conditions/Comments
SCLK, SDI, RESET, SYNC, LDAC
V
IOVDD ≤ 2.7 V
V
IOVDD > 2.7 V
V
IOVDD ≤ 2.7 V
V
IOVDD > 2.7 V
µA
pF
Per pin
Per pin
0.4
V
V
Sink current (ISINK) = 200 µA
Source current (ISOURCE) = 200 µA
+1
µA
0.4
0.4
V
V
V
ISINK = 200 µA
ISINK = 3 mA for IOVDD > 2.7 V
ISINK = 200 µA
V
ISINK = 3 mA for IOVDD > 2.7 V
0.2 ×
IOVDD
0.3 ×
IOVDD
+1
−1
3
IOVDD −
0.4
−1
0.15
High VOH
Unit
0.8 ×
IOVDD
0.7 ×
IOVDD
Low (VIL)
Input Current
Input Capacitance1
LOGIC OUTPUTS
SDO Pin
Output Voltage
Low (VOL)
High (VOH)
Max
IOVDD −
0.4
IOVDD −
0.4
−1
101
+1
kΩ
µA
−1
0.4
0.4
+1
V
V
V
9.5
4.1
2.0
1.4
−1.9
ADC_RDY, ALERT
10 kΩ pull-up resistor to IOVDD
At 2.5 mA
V
V
V
V
V
14
2.7
1.7
24
3.3
DVCC
26.4
5.5
5.5
V
V
V
10
10
13.5
12.5
18
14
mA
mA
10
15
18.5
mA
Rev. A | Page 13 of 66
AD74412R powered up and in high-Z mode
Four channels configured in any output
mode, no load current
Four channels configured in any input
mode, no load current
AD74412R
Data Sheet
Parameter
DVCC Current
Min
5.5
8.5
Typ
9.0
10.5
Max
13.5
12.5
Unit
mA
mA
15
100
µA
IOVDD Current
CONFIGURATION TIMING
Device Power-Up Time1
Device Reset Time1
10
1
ms
ms
Use Case Switch Time1
130
µs
Time in Use Case Before Loading DAC
Codes1
150
µs
1
Test Conditions/Comments
AD74412R powered up and in high-Z mode
Four channels configured in any output
mode, no load current
AD74412R powered up and in high-Z mode
After AVDD and DVCC power up
Time taken for device reset and
calibration memory upload to complete
hardware or software reset events after
the device is powered up (see Table 11
for RESET pulse width specifications)
Time in use case before changing to
another use case
Guaranteed by design and characterization.
TIMING CHARACTERISTICS
SPI Timing Specifications
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V internal or external, DVCC = 2.7 V to 5.5 V, IOVDD = 1.7 V to 5.5 V, and
all specifications at TA=−40°C to +85°C, unless otherwise noted.
Table 11.
Parameter 1, 2
t1
t2
t3
t4
t5
t6
t7
t8
t9
Description
SCLK pin cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Last SCLK falling edge to SYNC rising edge
SYNC high time
Data setup time
Data hold time
RESET pulse width
t10
t11
t12
t13
SCLK rising edge to SDO valid
SYNC falling edge to SDO valid (for readback MSB only)
SYNC rising edge to SDO tristate
LDAC pulse width
(LDAC must not be pulsed low until after SYNC is
returned high)
SYNC rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
SYNC rising edge to DAC output response time
(when LDAC is 0)
ADC_RDY pulse
t14
t15
t16
t17 3
1
2
3
IOVDD = 1.7 V to 2.7 V
50
20
20
25
25
650
5
5
50
1
39.5
34
15
350
IOVDD = 2.7 V to 5.5 V
42
17
17
21
21
650
5
5
50
1
23
15
14
350
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs min
ms max
ns max
ns max
ns min
ns min
1
3
3.5
1
3
3
µs min
µs typ
µs typ
30
30
µs typ
All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of the voltage on the IOVDD pin (VIOVDD)) and timed from a voltage level of VIOVDD/2.
Guaranteed by design and characterization; not production tested.
t17 is not shown in Figure 2 because it is not an SPI timing specification. See Figure 47 for a diagram with the t17.
Rev. A | Page 14 of 66
Data Sheet
AD74412R
Timing Diagrams
t1
SCLK
1
t6
2
32
t2
t3
t4
t6
t5
SYNC
t8
t7
SDI
MSB
LSB
t9
RESET
t11
SDO
t12
t10
MSB
MSB
LSB
t13
LDAC
t14
t15
VIOUTP_x
LDAC = 0
21274-002
t16
VIOUTP_x
Figure 2. SPI Timing Diagram
200µA
IOL
TO OUTPUT
PIN
200µA
IOL
21274-003
VOH (MIN) OR
VOL (MAX)
CL
30pF
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. A | Page 15 of 66
AD74412R
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
THERMAL RESISTANCE
With the recommended configuration, the I/OP_x screw terminal
tolerates overvoltages to dc ± 40 V (limited by external TVS).
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 12.
Parameter
AVDD to AGND
REFIN, REFOUT to AGND
SENSEH_x1, SENSEHF_x1 SENSEL_x1,
SENSELF_x1 to AGND
VIOUTP_x1 to AGND
VIOUTN_x1 to AGND
Digital Inputs to DGND (RESET, SYNC,
SCLK, SDI, LDAC)
Digital Outputs to DGND (GPO_x1,
SDO, ALERT, ADC_RDY)
DVCC, IOVDD to DGND
AGND_SENSE to AGND
DGND to AGND
Operating Temperature Range
Storage Temperature Range
Reflow Profile
Junction Temperature (TJ Maximum)2
Power Dissipation
θJA is the junction to ambient thermal resistance. θJC is the
junction to case thermal resistance.
Rating
−0.3 V to +30 V
−0.3 V to +5 V
−50 V to +50 V
Table 13. Thermal Resistance
−50 V to AVDD + 0.3 V
AVSS − 0.3 V to +50 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to +6.0 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−40°C to +85°C
−65°C to +150°C
JEDEC industry standard
J-STD-020
125°C
(TJ maximum – TA)/θJA
1
x = A, B, C, and D.
2
It is important to manage the power dissipation of the AD74412R to ensure
that the maximum junction temperature is not violated by using the
recommended external field-effect transistor (FET). It is also recommended
to enable the thermal shutdown function to avoid damage to the
AD74412R.
Package Type
CP-64-15
θJA1
22.81
θJC
1.32
Unit
°C/W
Based on simulated data using a JEDEC 2s2p thermal test board with a 7 mm ×
7 mm array of thermal vias in a JEDEC natural convection environment. See
JEDEC specification JESD-51 for details.
2
Measured at exposed paddle surface with the cold plate in direct contact
with the package top surface.
1
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 16 of 66
Data Sheet
AD74412R
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CASCODE_A
CCOMP_A
RESET
SYNC
SDI
SCLK
LDAC
DLDO1V8
DVCC
IOVDD
DGND
ALERT
ADC_RDY
SDO
CCOMP_D
CASCODE_D
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AD74412R
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SENSEH_D
SENSEHF_D
SENSEL_D
SENSELF_D
VIOUTP_D
VIOUTN_D
AVDD
AGND_SENSE
AGND2
RESERVED
VIOUTN_C
VIOUTP_C
SENSELF_C
SENSEL_C
SENSEHF_C
SENSEH_C
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AVSS.
21274-004
CASCODE_B
CCOMP_B
GPO_A
GPO_B
GPO_C
GPO_D
DVCC
CPUMP_P
DGND
CPUMP_N
AVSS
AGND3
REFIN
REFOUT
CCOMP_C
CASCODE_C
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SENSEH_A
SENSEHF_A
SENSEL_A
SENSELF_A
VIOUTP_A
VIOUTN_A
AVDD
AGND1
ALDO5V
ALDO1V8
VIOUTN_B
VIOUTP_B
SENSELF_B
SENSEL_B
SENSEHF_B
SENSEH_B
Figure 4. Pin Configuration
Table 14. Pin Function Description
Pin No.
1
Mnemonic
SENSEH_A
2
SENSEHF_A
3
SENSEL_A
4
SENSELF_A
5
VIOUTP_A
6
VIOUTN_A
7
8
9
AVDD
AGND1
ALDO5V
10
ALDO1V8
11
VIOUTN_B
12
VIOUTP_B
13
SENSELF_B
14
SENSEL_B
Description
High-Side Sense Pin on Channel A Closes Loop in Current Output Mode. This pin is routed to the AD74412R
side of RSENSE.
Filtered High-Side Sense Pin on Channel A Can Be Switched to ADC Inputs. This pin is routed to the
AD74412R side of RSENSE through the off chip filter.
Low-Side Sense Pin on Channel A Closes Loop in Voltage and Current Output Modes. This pin is routed to
the I/OP_x screw terminal side of RSENSE.
Filtered Low-Side Sense Pin on Channel A Can Be Switched to ADC Inputs. This pin is routed to the I/OP_x
screw terminal side of RSENSE through the off chip filter.
Voltage or Current High-Side Force Pin on Channel A. This pin operates in conjunction with the VIOUTN_A
pin to provide a voltage or a current to the I/OP_x screw terminal.
Voltage or Current Low-Side Force Pin on Channel A. This pin operates in conjunction with the VIOUTP_A pin
to provide a voltage or a current to the I/OP_x screw terminal.
Positive Analog Supply, 14 V to 26.4 V.
Analog Ground.
5 V Analog LDO Output. Decouple this pin with the recommended capacitor shown in Table 27. Do not use
this pin externally.
1.8 V Analog LDO Output. Decouple this pin with the recommended capacitor shown in Table 27. Do not use
this pin externally.
Voltage or Current Low-Side Force Pin on Channel B. This pin operates in conjunction with the VIOUTP_B pin
to provide a voltage or a current to the I/OP_x screw terminal.
Voltage or Current High-Side Force Pin on Channel B. This pin operates in conjunction with the VIOUTN_B
pin to provide a voltage or a current to the I/OP_x screw terminal.
Filtered Low-Side Sense Pin on Channel B Can Be Switched to ADC Inputs. This pin is routed to the I/OP_x
screw terminal side of RSENSE through the off chip filter.
Low-Side Sense Pin on Channel B Closes Loop in Voltage and Current Output Modes. This pin is routed to
the I/OP_x screw terminal side of RSENSE.
Rev. A | Page 17 of 66
AD74412R
Pin No.
15
Mnemonic
SENSEHF_B
16
SENSEH_B
17
CASCODE_B
18
CCOMP_B
19
20
21
22
23
24
GPO_A
GPO_B
GPO_C
GPO_D
DVCC
CPUMP_P
25
26
DGND
CPUMP_N
27
28
29
30
31
AVSS
AGND3
REFIN
REFOUT
CCOMP_C
32
CASCODE_C
33
SENSEH_C
34
SENSEHF_C
35
SENSEL_C
36
SENSELF_C
37
VIOUTP_C
38
VIOUTN_C
39
40
41
42
43
RESERVED
AGND2
AGND_SENSE
AVDD
VIOUTN_D
44
VIOUTP_D
45
SENSELF_D
46
SENSEL_D
Data Sheet
Description
Filtered High-Side Sense Pin on Channel B Can Be Switched to ADC Inputs. This pin is routed to the
AD74412R side of RSENSE through the off chip filter.
High-Side Sense Pin on Channel B Closes Loop in Current Output Mode. This pin is routed to the AD74412R
side of RSENSE.
Gate Drive Pin for Optional External Power Dissipating FET on Channel B. Leave this pin disconnected if not
using this FET.
Compensation Capacitor Pin for Channel B. This pin allows the AD74412R to drive high capacitive loads in
the voltage output use case. Connect the capacitor between the CCOMP_B pin and the AD74412R side of
RSENSE.
General-Purpose Digital Output Pin A. This pin can monitor the digital input comparator output.
General-Purpose Digital Output Pin B. This pin can monitor the digital input comparator output.
General-Purpose Digital Output Pin C. This pin can monitor the digital input comparator output.
General-Purpose Digital Output Pin D. This pin can monitor the digital input comparator output.
Digital Supply, 2.7 V to 5.5 V. Decouple this pin with the recommended capacitor shown in Table 27.
Charge Pump Fly Capacitor Terminal. Connect the recommended fly capacitor between the CPUMP_P pin
and the CPUMP_N pin.
Digital Ground.
Charge Pump Fly Capacitor Terminal. Connect the recommended fly capacitor between the CPUMP_P pin
and the CPUMP_N pin.
Charge Pump Output Voltage (Equal to Negative DVCC). Do not use this pin externally.
Analog Ground.
2.5 V Reference Input.
Internal 2.5 V Reference Output. This pin must be connected to the REFIN pin to use the internal reference.
Compensation Capacitor Pin for Channel C. This pin allows the AD74412R to drive high capacitive loads in
the voltage output use case. Connect the capacitor between the CCOMP_C pin and the AD74412R side of
RSENSE.
Gate Drive Pin for Optional External Power Dissipating FET on Channel C. Leave this pin disconnected if not
using this FET.
High-Side Sense Pin on Channel C Closes Loop in Current Output Mode. This pin is routed to the AD74412R
side of RSENSE.
Filtered High-Side Sense Pin on Channel C Can Be Switched to ADC Inputs. This pin is routed to the
AD74412R side of RSENSE through the off chip filter.
Low-Side Sense Pin on Channel C Closes Loop in Voltage and Current Output Modes. This pin is routed to
the I/OP_x screw terminal side of RSENSE.
Filtered Low-Side Sense Pin on Channel C Can Be Switched to ADC Inputs. This pin is routed to the I/OP_x
screw terminal side of RSENSE through the off chip filter.
Voltage or Current High-Side Force Pin on Channel C. This pin operates in conjunction with the VIOUTN_C
pin to provide a voltage or a current to the I/OP_x screw terminal.
Voltage or Current Low-Side Force Pin on Channel C. This pin operates in conjunction with the VIOUTP_C pin
to provide a voltage or a current to the I/OP_x screw terminal.
Reserved Pin. Tie to ground.
Analog Ground.
Analog Ground Sense. Tie this pin to the I/ON_x screw terminal.
Positive Analog Supply, 14 V to 26.4 V.
Voltage or Current Low-Side Force Pin on Channel D. This pin operates in conjunction with the VIOUTP_D
pin to provide a voltage or a current to the I/OP_x screw terminal.
Voltage or Current High-Side Force Pin on Channel D. This pin operates in conjunction with the VIOUTN_D
pin to provide a voltage or a current to the I/OP_x screw terminal.
Filtered Low-Side Sense Pin on Channel D Can Be Switched to ADC Inputs. This pin is routed to the I/OP_x
screw terminal side of RSENSE through the off chip filter.
Low-Side Sense Pin on Channel D Closes Loop in Voltage and Current Output Modes. This pin is routed to
the I/OP_x screw terminal side of RSENSE.
Rev. A | Page 18 of 66
Data Sheet
Pin No.
47
Mnemonic
SENSEHF_D
48
SENSEH_D
49
CASCODE_D
50
CCOMP_D
51
52
SDO
ADC_RDY
53
ALERT
54
55
56
57
DGND
IOVDD
DVCC
DLDO1V8
58
LDAC
59
60
61
62
63
SCLK
SDI
SYNC
RESET
CCOMP_A
64
CASCODE_A
Exposed Pad
AD74412R
Description
Filtered High-Side Sense Pin on Channel D Can Be Switched to ADC Inputs. This pin is routed to the
AD74412R side of RSENSE through the off chip filter.
High-Side Sense Pin on Channel D Closes Loop in Current Output Mode. This pin is routed from the
AD74412R side of RSENSE.
Gate Drive Pin for Optional External Power Dissipating FET on Channel D. Leave this pin disconnected if not
using this FET.
Compensation Capacitor Pin for Channel D. This pin allows the AD74412R to drive high capacitive loads in
the voltage output use case. Connect the capacitor between the CCOMP_D and the AD74412R side of RSENSE.
Serial Interface Data Out.
Active Low, Open-Drain Output. This pin asserts when a new sequence of ADC conversion results is ready to
be read. Connect this pin to a pull-up resistor to the IOVDD pin.
Active Low, Open-Drain Output. This pin asserts low when an alert condition occurs. Read the ALERT_STATUS
register when this pin is asserted. Connect this pin to the IOVDD pin via a pull-up resistor.
Digital Ground.
Input/Output Supply, 1.7 V to 5.5 V
Digital Supply, 2.7 V to 5.5 V.
1.8 V Digital LDO Output. Decouple with the recommended capacitor shown in Table 27. Do not use this pin
externally.
Load DAC Pin. Active low input. Drive this pin low to update all four DACs in parallel. This pin can be tied
permanently low if simultaneous updates are not required.
Serial Interface Clock.
Serial Interface Data In.
Serial Interface Frame Synchronization Pin. Active low input.
Hardware Reset Pin. Active low input. This pin resets the AD74412R to the power-on state.
Compensation Capacitor Pin for Channel A. This pin allows the AD74412R to drive high capacitive loads in
the voltage output use case. Connect the capacitor between the CCOMP_A pin and the AD74412R side of
RSENSE.
Gate Drive Pin for Optional External Power Dissipating FET on Channel A. Leave this pin disconnected if not
using this FET.
Exposed Pad. Connect the exposed pad to the AVSS pin.
Rev. A | Page 19 of 66
AD74412R
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE OUTPUT
0.6
0.08
0.5
0.3
0.2
0.1
AVDD = 24V
DVCC = IOVDD = 3.3V
RLOAD = 100kΩ
REFIN = 2.5V (IDEAL)
TA = 25°C
2000
3000
4000
5000
6000
7000
8000
DAC CODE
–4
–0.02
–0.04
–6
VSCREW
VSYNC
–0.06
–0.10
0
–10
40
0.06
10
SCREW TERMINAL VOLTAGE (V)
12
0.04
0.02
0
–0.02
–0.04
AVDD = 24V
DVCC = IOVDD = 3.3V
RLOAD = 100kΩ
2000
3000
4000
5000
6000
7000
8000
DAC CODE
200
6
4
2
10
30
50
70
90
TIME (µs)
Figure 6. DNL vs. DAC Code
Figure 9. Full-Scale Positive Step
12
0.006
AVDD = 24V
DVCC = IOVDD = 3.3V
RLOAD = 100kΩ
REFIN = 2.5V (IDEAL)
TA = 25°C
0.002
0
10
SCREW TERMINAL VOLTAGE (V)
0.004
–0.002
–0.004
–0.006
–0.008
–0.010
–0.012
8
6
4
2
0
–0.014
–0.016
0
1000
2000
3000
4000
5000
DAC CODE
6000
7000
8000
21274-101
TUE (%FSR)
160
8
–2
–10
21274-103
1000
120
0
REFIN = 2.5V (IDEAL)
TA = 25°C
–0.08
0
80
Figure 8. Screw Terminal Voltage (VSCREW) vs. Time on Voltage Output Enable
0.08
–0.06
–8
TIME (µs)
Figure 5. INL vs. DAC Code
DNL (LSB)
–2
0
21274-104
1000
0.02
–0.08
–0.2
0
0
0.04
21274-105
–0.1
21274-102
0
2
0.06
–2
–0.5
1.5
3.5
5.5
TIME (µs)
7.5
Figure 10. Full-Scale Negative Step
Figure 7. TUE vs. DAC Code
Rev. A | Page 20 of 66
9.5
21274-206
INL (LSB)
0.4
4
SYNC PIN VOLTAGE (VSYNC )
0.10
SCREW TERMINAL VOLTAGE (V)
0.7
Data Sheet
AD74412R
0
REFIN = 2.5V (IDEAL)
–20
A
B
C
D
200
OUTPUT VOLTAGE (µV)
CHANNEL
CHANNEL
CHANNEL
CHANNEL
–10
–40
–50
–60
100
0
–100
–200
–70
–80
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
21274-106
–300
–90
0
5.0
2.5
7.5
10.0
12.5
15.0
17.5
20.0
TIME (ms)
Figure 11. AC PSRR vs. Frequency
21274-108
AC PSRR (dB)
–30
Figure 13. Peak-to-Peak Noise (100 kHz Bandwidth)
60
0.020
REFIN = 2.5V (IDEAL)
0.015
OUTPUT VOLTAGE DELTA (V)
40
0
–20
0.010
0.005
0
–0.005
–0.010
–40
–60
0
2
4
6
8
10
TIME (seconds)
Figure 12. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)
–0.020
–5
0
5
10
15
20
25
SOURCE AND SINK CURRENT (mA)
Figure 14. Output Voltage (VOUT) Source and Sink Capability
Rev. A | Page 21 of 66
30
21274-128
–0.015
21274-107
VOUT (µV)
20
AD74412R
Data Sheet
CURRENT OUTPUT
1.2
6
400
1.0
0.6
0.4
AVDD = 24V
DVCC = IOVDD = 3.3V
RLOAD = 100kΩ
REFIN = 2.5V (IDEAL)
TA = 25°C
0
1000
2000
3000
4000
2
IOUT
VSYNC
0
0
–2
–4
–200
–6
–0.2
0
200
5000
6000
7000
8000
DAC CODE
–8
–400
0
50
100
150
21274-112
0.2
21274-109
INL ERROR (LSB)
0.8
VSYNC PIN VOLTAGE (V)
CURRENT OUTPUT (µA)
4
200
TIME (µs)
Figure 15. INL Error vs. DAC Code
Figure 18. Current Output (IOUT) vs. Time on Output Enable
0.15
0.10
DNL (LSB)
0.05
0
–0.05
1
REFIN = 2.5V (IDEAL)
TA = 25°C
21274-132
AVDD = 24V
DVCC = IOVDD = 3.3V
RLOAD = 100kΩ
–0.15
0
1000
2000
3000
4000
5000
6000
7000
8000
DAC CODE
21274-110
–0.10
CH1 1.00V
M20.0µs
A CH1
T
72.6000ms
920mV
Figure 19. Current Output Settling Time
Figure 16. DNL vs. DAC Code
9
0.05
8
VOLTAGE ACROSS 250Ω (V)
–0.05
–0.10
AVDD = 24V
DVCC = IOVDD = 3.3V
RLOAD = 100kΩ
REFIN = 2.5V (IDEAL)
TA = 25°C
1000
2000
3000
6
5
4
3
NO INDUCTIVE LOAD
22mH NO SLEW
22mH, 280µs SLEW
22mH, 520µs SLEW
22mH, 858µs SLEW
2
1
0
–0.20
0
7
4000
5000
6000
DAC CODE
Figure 17. TUE vs. DAC Code
7000
8000
–1
0
200
400
600
TIME (µs)
800
1000
21274-129
–0.15
21274-111
TUE (%FSR)
0
Figure 20. Current Output Settling Time with Inductive Load With and
Without Slew Rate Enabled
Rev. A | Page 22 of 66
Data Sheet
AD74412R
0
REFIN = 2.5V (IDEAL)
200
–20
100
IOUT (nA)
AC PSRR (dB)
–40
–60
–80
–100
0
–100
–120
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0
Figure 21. AC PSRR vs. Frequency
4
6
TIME (Seconds)
8
10
Figure 23. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)
23.5
3
REFIN = 2.5V (IDEAL)
AVDD = 24V
DVCC = IOVDD = 3.3V
23.0
2
22.5
22.0
1
IOUT (µA)
21.5
21.0
20.5
20.0
0
–1
19.5
19.0
–2
18.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
IOUT (mA)
22.5
25.0
–3
0
2.5
5.0
7.5
12.5
10.0
TIME (ms)
15.0
17.5
Figure 24. Peak-to-Peak Noise (100 kHz Bandwidth)
Figure 22. Compliance Voltage vs. IOUT
Rev. A | Page 23 of 66
20.0
21274-131
18.5
21274-114
COMPLIANCE VOLTAGE (V)
2
21274-130
100
21274-113
–200
–40
10
AD74412R
Data Sheet
30
5.5
20
4.5
REFOUT VOLTAGE (V)
10
0
–10
–20
3.5
2.5
1.5
0.5
2
0
4
6
8
10
TIME (seconds)
–0.5
–0.03
21274-115
–30
–0.02
–0.01
0
0.01
0.02
0.03
LOAD CURRENT (A)
Figure 25. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)
21274-124
REFERENCE VOLTAGE (µV)
REFERENCE
Figure 27. REFOUT Voltage vs. Load Current
800
2.501
600
REFERENCE VOLTAGE (V)
200
0
–200
–400
2.499
2.498
30 DEVICES SHOWN
AVDD = 24V
2.497
–800
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
TIME (ms)
20.0
2.496
–40
25
85
TEMPERATURE (°C)
Figure 26. Peak-to-Peak Noise (100 kHz Bandwidth)
Figure 28. Reference Voltage vs. Temperature
Rev. A | Page 24 of 66
105
21274-117
–600
21274-116
REFERENCE NOISE (µV)
2.500
400
Data Sheet
AD74412R
ADC
1000
1000
ADC RANGE: 0V TO 10V, VIN = 2V
ADC RANGE: 0V TO 10V, VOLTAGE INPUT (VIN) = 2V
800
SAMPLE COUNT
600
400
400
200
13102
13103
13104
ADC CODE
13105
13106
13107
21274-120
200
0
13101
600
Figure 29. ADC Noise Histogram with Output Data Rate (ODR) = 20 SPS
Rev. A | Page 25 of 66
0
13101
13102
13103
13104
13105
13106
ADC CODE
Figure 30. ADC Noise Histogram with ODR = 4 kSPS
13107
21274-123
SAMPLE COUNT
800
AD74412R
Data Sheet
14.5
14.5
14.0
14.0
AVDD CURRENT (mA)
13.5
13.0
13.0
12.5
12.0
13
15
17
19
21
23
AVDD VOLTAGE (V)
21274-127
12.5
30
AVDD
IOVDD/DVCC
REFOUT
AVSS
25
20
15
10
5
0
–10
0.02
0.04
0.06
0.08
0.10
TIME (Seconds)
0.12
0.14
0.16
21274-125
–5
0
12.0
–50
–30
–10
10
30
50
70
TEMPERATURE (°C)
Figure 33. AVDD Current vs. Temperature
Figure 31. AVDD Current vs. AVDD Voltage
SUPPLY VOLTAGE AND REFERENCE VOLTAGE (V)
13.5
Figure 32. Supply Voltage and Reference Voltage vs. Time on Power-Up
Rev. A | Page 26 of 66
90
21274-126
AVDD CURRENT (mA)
SUPPLIES
Data Sheet
AD74412R
THEORY OF OPERATION
REFOUT
REFIN ALDO1V8
ALDO5V
AVDD
AD74412R
1.8V
ALDO
IOVDD
5V
LDO
DVCC
1.8V
INTERNAL
DLDO OSCILLATOR
1nF
VIOUTP_x
OUTPUT
CONFIGURE
DAC
CASCODE_x
RSENSE
100, 0.1%
10ppm/°C
DGND
SCLK
SYNC
ADC
SDO
ALERT
ADC_RDY
LDAC
GPO_A
INPUT
SHIFT
REGISTER
AND
DIGITAL
LOGIC
SENSEH_x
2kΩ, 0.1%
SENSEHF_x
CFILTER
DIAGNOSTICS
BLOCK
SENSELF_x
SENSEL_x
SENSEL_x
CFILTER
CLOAD
68nF
RFILTER
2kΩ
SENSELF_x
THRESHOLD
GPO_D
RESET
VIOUTN_x
AGND_SENSE
GPO_B
GPO_C
I/OP_x
BAV99
SENSELF_x
MUX
SDI
MUX
CHANNEL
MUX
SENSEHF_x
TVS
RFILTER
LOAD
CHANNEL A
POWER-ON
RESET
AVSS = NEGATIVE DVCC
CHANNEL B
CHANNEL C
CHARGE PUMP
CHANNEL D
AGND1 AVSS CPUMP_N
CPUMP_P
AGND3
AGND2
AGND_SENSE
CPUMP FLY
CAPACITOR
I/ON_x
AGND
21274-005
DLDO1V8
CCOMP_x
2.5V
VREF
Figure 34. Detailed Functional Block Diagram
The AD74412R is a quad-channel software configurable
input/output application specific standard part (ASSP) designed to
meet the requirements of building control, process control, and
industrial automation applications. The device provides a fully
integrated single chip solution for input and output operation. The
AD74412R features a 16-bit, Σ-Δ ADC and multiple DACs, and
the device is packaged in a 9 mm × 9 mm, 64-lead LFCSP. The four
channels are configured by writing to the configuration
registers. Users can refine the default configurations of each
operation mode via the AD74412R register map (see Table 28).
Refer to Figure 34 for a detailed functional block diagram of the
AD74412R.
ROBUST ARCHITECTURE
The AD74412R system is robust in noisy environments and can
withstand overvoltage scenarios such as miswire and surge events.
On-chip line protectors ensure that the I/OP_x and I/ON_x
screw terminals do not provide power to the IC when brought
to a higher potential than the AVDD pin.
The recommended external components shown in Figure 34
and Table 27, including the TVS, are selected to withstand 1 kV
surge on the input/output terminals and have been tested by the
IEC61000-4-5 standard.
With the recommended components, the I/OP_x and I/ON_x
screw terminals tolerate overvoltages up to dc ± 40 V (limited
by the external TVS).
A cyclic redundancy check (CRC) function is built into the SPI
interface to ensure error free communications in noisy
environments.
SERIAL INTERFACE
The AD74412R is controlled over a versatile 4-wire serial
interface that operates at clock speeds of up to 24 MHz (refer
the t1 parameter in Table 11) and is compatible with SPI, QSPI™,
MICROWIRE™, and DSP standards. Data coding is always
straight binary.
DAC ARCHITECTURE
The AD74412R contains four 13-bit DACs, one per channel.
Each DAC core is a 13-bit string DAC. The architecture structure
consists of a string of resistors, each with a value of R. The
digital input code that is loaded to the DAC_CODEx registers
determines which node on the string the voltage is tapped off
from and fed into the output amplifier. This architecture is
inherently monotonic and linear.
Rev. A | Page 27 of 66
AD74412R
Data Sheet
ADC OVERVIEW
DEVICE FUNCTIONS
The AD74412R provides the user with a single multichannel
multiplexer and a single, 16-bit Σ-∆ ADC. The channel multiplexer
selects which of the four channels the ADC measures. The ADC
can measure either the voltage across the 100 Ω RSENSE or the voltage
at the I/OP_x screw terminal of each channel. The ADC also
provides diagnostic information on user-selectable inputs such
as supplies, internal die temperature, reference, and regulators.
The ADC contains a 50 Hz and 60 Hz rejection filter, that the
user can enable.
The following sections describe the various programmable
device functions of the AD74412R with block diagrams and
guidelines on how to interpret the ADC results if converting
with the default settings. These functions are programmed
within the CH_FUNC_SETUPx registers.
REFERENCE
The AD74412R can operate with either an external or an internal
reference. The reference input requires 2.5 V for the AD74412R
to function correctly. The reference voltage is internally buffered
before being applied to the DAC and the ADC. If using the internal
reference, the REFIN pin must be tied to the REFOUT pin.
Reference Noise
High Impedance
High impedance is the default function upon power-up or after
a device reset. All channels are high impedance.
The CASCODE_x pins are pulled to ground via a 100 µA current
sink to ground.
The CCOMP_x pins have a 40 kΩ resistor and a Zener diode in
parallel to ground.
If a channel is held in high impedance for an extended time,
such as when the channel is not in use, it is recommended to
enable the 200 kΩ resistor to ground. Enable the 200 kΩ resistor
by setting the CH_200K_TO_GND bit in the ADC_ CONFIGx
registers.
It is recommended to decouple the reference voltage with a
100 nF capacitor. The reference specifications are generated
assuming this 100 nF configuration.
Users can reduce the reference noise with the following
additional external components:
•
•
•
Each device function is configured with default measurement
settings. However, users can adjust these settings as required
within the register map (see Table 28).
Interpreting ADC Data
No resistor, 100 nF capacitor (default)
10 kΩ, 100 nF capacitor
10 kΩ, 1 μF capacitor
In high impedance mode, the ADC, by default, measures the
voltage across the screw terminals (I/OP_x to I/ON_x) in a 0 V
to 10 V range. Use the following equation to calculate the ADC
measurement result:
The reference power-on time is affected by the selection of
additional external components.
VADC = (ADC_CODE/65,535) × Voltage Range
Charge Pump
The AD74412R has an internal charge pump that provides a
negative voltage that enables the AD74412R to force out 0 V
while sinking current in voltage output mode. For correct
operation, the charge pump requires an external capacitor
(CPUMP fly capacitor in Figure 35) between the CPUMP_N
pin and the CPUMP_P pin. Note that the AVSS pin cannot
drive external circuitry.
where:
VADC is the measured voltage in volts.
ADC_CODE is the value of the ADC_RESULTx registers.
Voltage Range is the measurement range of the ADC and is 10 V.
POWER-ON STATE OF THE AD74412R
Upon initial power-up or a device reset of the AD74412R, the
output channels are disabled and placed in a high impedance
state by default.
Rev. A | Page 28 of 66
Data Sheet
AD74412R
Voltage Output Mode
Interpreting ADC Data
The voltage output amplifier can generate unipolar voltages up
to 11 V. An internal low voltage charge pump allows the amplifier
to generate a true zero output voltage. The voltage on the lowside of the RSENSE is sensed on the SENSEL_x pin via a 2 kΩ
resistor, which closes the feedback loop and maintains stability.
In voltage output mode, the ADC, by default, measures the
current through the RSENSE in a −25 mA to +25 mA range. Use
the ADC measurement result to calculate the current through
the RSENSE with the following equation:
The short-circuit limit in voltage output mode is programmable
per channel. The circuit minimizes glitching on the I/OP_x
screw terminal when the AVDD supply (VAVDD) is ramping or
when the use case configuration is changed.
I RSENSE
where:
I RSENSE is the measured current in amps. A negative current
Figure 35 shows the current, voltage, and measurement paths of
the voltage output mode.
indicates the current is sourced from the AD74412R. A positive
current indicates that the AD74412R is sinking the current.
VMIN is the minimum voltage of the selected ADC range, which
is −2.5 V by default.
ADC_CODE is the value of the ADC_RESULTx registers.
Voltage Range is the full span of the ADC range, which is 5 V.
RSENSE is the RSENSE resistor, which is 100 Ω.
Voltage Output Short-Circuit Protection
The short-circuit limit for the voltage output mode of the
AD74412R is typically 29 mA per channel when sourcing
current. To provide flexibility for the user, a lower short-circuit
limit of typically 7 mA can be selected per channel by setting
the I_LIMIT bit in the OUTPUT_CONFIGx registers. The current
limit for when the AD74412R is sinking current is typically
3.8 mA. If the selected short-circuit limit is reached on a channel, a
voltage output short-circuit error is flagged for that channel and
the ALERT pin asserts.
REFOUT
REFIN
ALDO1V8
ADC _ CODE
× Voltage Range
VMIN +
65,535
=
RSENSE
ALDO5V
MEASUREMENT PATH
VOLTAGE PATH
CURRENT PATH
AVDD
AD74412R
1.8V
LDO
IOVDD
5V
LDO
DVCC
VIOUTP_x
1.8V
INTERNAL
DLDO OSCILLATOR
2.5V
VREF
DAC
RSENSE
100, 0.1%
10ppm/°C
AVSS
DGND
SCLK
LDAC
GPO_A
SENSELF_x
SENSEH_x
2kΩ, 0.1%
SENSEHF_x
CFILTER
DIAGNOSTICS
BLOCK
SENSELF_x
GPO_B
GPO_C
SENSEL_x
SENSEL_x
CFILTER
CLOAD
68nF
RFILTER
2kΩ
SENSELF_x
THRESHOLD
GPO_D
RESET
VIOUTN_x
AGND_SENSE
MUX
ADC_RDY
INPUT
SHIFT
REGISTER
AND
DIGITAL
LOGIC
MUX
ADC
CHANNEL
MUX
SENSEHF_x
SDI
SDO
I/OP_x
BAV99
SYNC
ALERT
1nF
CASCODE_x
RFILTER
VALVE
TVS
CHANNEL A
POWER-ON
RESET
AVSS = NEGATIVE DVCC
CHANNEL B
CHANNEL C
CHARGE PUMP
AGND1 AVSS CPUMP_N
I/ON_x
AGND
CHANNEL D
CPUMP_P
AGND3
AGND2
AGND_SENSE
CPUMP FLY
CAPACITOR
Figure 35. Voltage Output Mode Configuration
Rev. A | Page 29 of 66
21274-006
DLDO1V8
CCOMP_x
VOUT
SCALING
AD74412R
Data Sheet
Current Output Mode
Interpreting ADC Data
In current output mode, the DAC provides a current output on
the VIOUTP_x pin, that is regulated by sensing the differential
voltage across RSENSE by using the SENSEL_x and SENSEH_x
pins. In addition, an optional, external P channel FET can pass
the 0 mA to 25 mA current output to lower power dissipation on
the die in cases where a low resistive load is present.
In current output mode, the ADC, by default, is configured to
measures the voltage across the screw terminals (I/OP_x to
I/ON_x) in a 0 V to 10 V range. Use the ADC measurement
result to calculate the voltage across these screw terminals by
using the following equation:
VADC = (ADC_CODE/65,535) × Voltage Range
The circuit minimizes glitching on the I/OP_x screw terminal
when the VAVDD is ramping or when the use case configuration
is changed.
where:
VADC is the measured voltage in volts.
ADC_CODE is the value of the ADC_RESULTx registers.
Voltage Range is the measurement range of the ADC and is 10 V.
Figure 36 shows the current, voltage, and measurement paths of
the current output mode.
Current Output Open Circuit Detection
In current output mode, if the headroom voltage falls below the
compliance voltage (specified in Table 2), due to an open-loop
circuit on any channel, a current output open circuit error is
flagged for that channel and the ALERT pin asserts. If the VAVDD
is insufficient to drive the programmed current output, the
open circuit error is flagged.
REFOUT
REFIN
ALDO1V8
ALDO5V
MEASUREMENT PATH
VOLTAGE PATH
CURRENT PATH
AVDD
AD74412R
1.8V
LDO
IOVDD
5V
LDO
CCOMP_x
DVCC
1.8V
INTERNAL
DLDO OSCILLATOR
2.5V
VREF
MUX
SENSELF_x
SENSEH_x
2kΩ, 0.1%
SENSEHF_x
CFILTER
DIAGNOSTICS
BLOCK
SENSELF_x
GPO_B
SENSEL_x
SENSEL_x
CLOAD
68nF
RFILTER
VALVE
2kΩ
SENSELF_x
CFILTER
GPO_C
RFILTER
TVS
THRESHOLD
GPO_D
RESET
VIOUTN_x
AGND_SENSE
MUX
GPO_A
INPUT
SHIFT
REGISTER
AND
DIGITAL
LOGIC
CHANNEL
MUX
ADC
SDI
LDAC
I/OP_x
BAV99
SENSEHF_x
SYNC
ADC_RDY
RSENSE
100, 0.1%
10ppm/°C
G=1
SCLK
SDO
OPTIONAL P CHANNEL FET
FOR LOW RLOAD
DAC
DGND
ALERT
1nF
CASCODE_x
CHANNEL A
POWER-ON
RESET
AVSS = NEGATIVE DVCC
AGND1 AVSS
CHANNEL B
I/ON_x
CHANNEL C
AGND
CHARGE PUMP
CPUMP_N
CHANNEL D
CPUMP_P
AGND3
AGND2
AGND_SENSE
CPUMP FLY
CAPACITOR
Figure 36. Current Output Mode Configuration
Rev. A | Page 30 of 66
21274-007
DLDO1V8
VIOUTP_x
Data Sheet
AD74412R
Voltage Input Mode
Interpreting ADC Data
In voltage input mode, the voltage across the screw terminals
(I/OP_x to I/ON_x) is measured by the ADC via the SENSELF_x
and the AGND_SENSE pins. It is essential to connect the AGND_
SENSE pin as close as possible to the I/ON_x screw terminal to
ensure an accurate voltage measurement. Figure 37 shows the
current and measurement paths of the voltage input mode.
In voltage input mode, the ADC, by default, is configured to
measure the voltage across the screw terminals (I/OP_x to
I/ON_x) in a 0 V to 10 V range. Use the ADC measurement
result to calculate the voltage across these screw terminals by
using the following equation:
VADC = VMIN + (ADC_CODE/65,535) × Voltage Range
Selectable 200 kΩ to GND
where:
VMIN is the minimum input voltage of the selected ADC range
and is 0 V by default.
VADC is the measured voltage in volts.
ADC_CODE is value of the ADC_RESULTx registers.
Voltage Range is the measurement range of the ADC and is 10 V.
In voltage input mode, there is an option to connect the
VIOUTN_x pins to ground via a 200 kΩ resistor, which is
enabled via the ADC_CONFIGx registers (disabled by default).
This option is useful if there is a discrepancy in the ADC
measurement of the I/OP_x screw terminals, such as floating
voltages. By enabling the 200 kΩ resistor, a small current is
drawn through the 200 kΩ resistor, which pulls the voltage to
ground.
REFOUT
REFIN
ALDO1V8
AD74412R
ALDO5V
AVDD
1.8V
ALDO
IOVDD
MEASUREMENT PATH
CURRENT PATH
5V
ALDO
CCOMP_x
DVCC
1.8V
INTERNAL
DLDO OSCILLATOR
CASCODE_x
2.5V
VREF
RSENSE
100, 0.1%
10ppm/°C
200kΩ
DAC
DGND
ADC_RDY
LDAC
GPO_A
INPUT
SHIFT
REGISTER
AND
DIGITAL
LOGIC
VIOUTN_x
AGND_SENSE
SENSEH_x
2kΩ, 0.1%
SENSEHF_x
CFILTER
DIAGNOSTICS
BLOCK
SENSELF_x
GPO_B
GPO_C
SENSEL_x
SENSEL_x
CFILTER
CLOAD
68nF
RFILTER
2kΩ
SENSELF_x
THRESHOLD
GPO_D
RESET
SENSELF_x
MUX
ALERT
MUX
ADC
SDI
CHANNEL
MUX
SENSEHF_x
SYNC
SDO
I/OP_x
BAV99
SCLK
VOLTAGE
SOURCE
0V
TO
10V
TVS
RFILTER
CHANNEL A
POWER-ON
RESET
CHANNEL B
CHANNEL C
AVSS = NEGATIVE DVCC
AGND1 AVSS
AGND
CHARGE PUMP
CPUMP_N
I/ON_x
CHANNEL D
CPUMP_P
AGND3
AGND2
AGND_SENSE
CPUMP FLY
CAPACITOR
Figure 37. Voltage Input Mode Configuration
Rev. A | Page 31 of 66
21274-008
DLDO1V8
1nF
VIOUTP_x
AD74412R
Data Sheet
Current Input, Externally Powered Mode
Interpreting ADC Data
In current input, externally powered mode, the AD74412R
provides a current limited path to ground via the VIOUTN_x pin
for an external current source. The 16-bit, Σ-∆ ADC automatically
measures the current through RSENSE. The current is measured by
digitizing the voltage across RSENSE via the SENSEHF_x and the
SENSELF_x pins. Figure 38 shows the current and measurement
paths of the current input, externally powered mode.
In current input mode, the ADC, by default, measures the
current flowing from the I/OP_x screw terminal into the
AD74412R through the RSENSE in a 25 mA range. Use the ADC
measurement current to calculate the current through the RSENSE
with the following equation:
I RSENSE
Short-Circuit Protection
The maximum short-circuit limit is 35 mA in the current input,
externally powered mode to both protect the external circuitry and
to limit the power dissipated on the AD74412R device.
where:
I RSENSE is the measured current in amps.
ADC_CODE is the value of the ADC_RESULTx registers.
Voltage Range is the full span of the ADC range and is 2.5 V.
RSENSE is the sense resistor, which is set to 100 Ω.
If the digital input comparator is enabled, the ALERT_STATUS
register can detect a short circuit.
Enable the digital input comparator with a threshold voltage of
AVDD/2. In normal operation, the voltage on I/OP_x is typically
within 5 V of ground. If the current source attempts to sink more
than 35 mA into the AD74412R, the voltage on the SENSEL_x pin
instantly ramps. When the voltage on the I/OP_x screw terminal is
above the programmed threshold voltage, the comparator trips,
setting the relevant VI_ERR_x bit in the ALERT_STATUS register.
REFOUT
REFIN
ALDO1V8
ADC _ CODE
× Voltage Range
65,535
=
RSENSE
ALDO5V
AVDD
MEASUREMENT PATH
CURRENT PATH
AD74412R
1.8V
ALDO
IOVDD
5V
LDO
CCOMP_x
DVCC
CASCODE_x
2.5V
VREF
1.8V
INTERNAL
DLDO OSCILLATOR
CURRENT
SOURCE
DAC
DGND
SCLK
ADC
ALERT
ADC_RDY
LDAC
GPO_A
INPUT
SHIFT
REGISTER
AND
DIGITAL
LOGIC
SENSEH_x
CFILTER
DIAGNOSTICS
BLOCK
SENSELF_x
SENSEL_x
SENSEL_x
2kΩ, 0.1%
CFILTER
CLOAD
68nF
RFILTER
2kΩ
SENSELF_x
THRESHOLD
GPO_D
RESET
VIOUTN_x
AGND_SENSE
SENSEHF_x
GPO_B
GPO_C
I/OP_x
BAV99
SENSELF_x
MUX
SDI
MUX
CHANNEL
MUX
SENSEHF_x
SYNC
SDO
RSENSE
100, 0.1%
10ppm/°C
AGND
TVS
RFILTER
CHANNEL A
POWER-ON
RESET
CHANNEL B
CHANNEL C
AVSS = NEGATIVE DVCC
AGND1 AVSS
CPUMP_N
CPUMP_P
I/ON_x
AGND
CHARGE PUMP
CHANNEL D
AGND3
AGND2
AGND_SENSE
CPUMP FLY
CAPACITOR
Figure 38. Current Input, Externally Powered Mode Configuration
Rev. A | Page 32 of 66
21274-009
DLDO1V8
1nF
VIOUTP_x
Data Sheet
AD74412R
Current Input, Loop Powered Mode
Interpreting ADC Data
In current input loop powered mode, the AD74412R provides
a current limited voltage to the I/OP_x screw terminal. The
current is measured by digitizing the voltage across RSENSE via the
SENSEHF_x and the SENSELF_x pins. When selecting the current
input loop powered function, tie the VIOUTN_x pin to ground
via the on-chip 200 kΩ resistor by enabling the CH_200K_TO_
GND bit in the ADC_CONFIGx registers. Figure 39 shows the
current, voltage, and measurement paths of the current input,
loop powered mode.
In current input loop, powered mode, the ADC, by default,
measures the current flowing from the AD74412R into the I/OP_x
screw terminal through the RSENSE in a 25 mA range. Use the ADC
measurement result to calculate the current with the following
equation:
Short-Circuit Protection
where:
I RSENSE is the measured current in amps.
I RSENSE
The current from the AD74412R is limited by the programmable
DAC code (maximum 24.5 mA).
ADC _ CODE
× Voltage Range
65,535
=
RSENSE
ADC_CODE is the value of the ADC_RESULTx registers.
Voltage Range is the full ADC span of the ADC range and is 2.5 V.
RSENSE is the sense resistor, which has a value of 100 Ω.
If the digital input comparator is enabled, the ALERT_STATUS
register detects short circuits.
Enable the digital input comparator with a threshold voltage of
AVDD/2 and with the output inverted. During normal operation,
the voltage on I/OP_x is typically within 5 V of the VAVDD. If the
load is short circuited to ground, the voltage on the I/OP_x is
pulled to ground. When the voltage on the I/OP_x screw
terminal falls below the programmed threshold level, the
comparator trips low, setting the relevant VI_ERR_x bit in the
ALERT_STATUS register.
REFIN
REFOUT
ALDO1V8
ALDO5V
MEASUREMENT PATH
VOLTAGE PATH
CURRENT PATH
AVDD
AD74412R
1.8V
ALDO
IOVDD
5V
LDO
CCOMP_x
DVCC
DLDO1V8
1nF
VIOUTP_x
CASCODE_x
2.5V
VREF
1.8V
INTERNAL
DLDO OSCILLATOR
DAC
RSENSE
100, 0.1%
10ppm/°C
G=1
200kΩ
DGND
I/OP_x
BAV99
SCLK
SDI
ADC_RDY
LDAC
GPO_A
INPUT
SHIFT
REGISTER
AND
DIGITAL
LOGIC
SENSEHF_x
VIOUTN_x
SENSELF_x
SENSEH_x
AGND_SENSE
CFILTER
DIAGNOSTICS
BLOCK
SENSELF_x
GPO_B
GPO_C
RESET
SENSEL_x
SENSEL_x
CLOAD
68nF
RFILTER
LOAD
2kΩ
SENSELF_x
CFILTER
THRESHOLD
GPO_D
2kΩ, 0.1%
SENSEHF_x
RFILTER
TVS
CHANNEL A
POWER-ON
RESET
CHANNEL B
CHANNEL C
AVSS = NEGATIVE DVCC
AGND1 AVSS
CHARGE PUMP
CPUMP_N
CPUMP_P
I/ON_x
AGND
CHANNEL D
AGND3
AGND2
AGND_SENSE
CPUMP FLY
CAPACITOR
Figure 39. Current Input, Loop Powered Mode Configuration
Rev. A | Page 33 of 66
21274-010
ALERT
ADC
MUX
SDO
MUX
CHANNEL
MUX
SYNC
AD74412R
Data Sheet
Resistance Measurement (External 2-Wire RTD)
Interpreting ADC Data
The resistance measurement configuration biases an external
2-wire RTD with a voltage derived from a 2.5 V bias. The
resultant excitation current flows through the 2 kΩ and 100 Ω
resistors (shown as RPULL-UP in Figure 40). This configuration
ensures an accurate ratiometric measurement. The 16-bit, Σ-∆
ADC automatically digitizes the voltage across the RTD. The
low excitation current ensures that the power dissipated by the
RTD is minimized, reducing self heating. See Figure 40 for an
example of the RTD bias circuit.
In resistance measurement mode, the 16-bit, Σ-∆ ADC
automatically digitizes the voltage across the RTD in a
2.5 V range.
When a conversion is carried out, the ADC code reflects the
ratio between the RTD and the RPULL-UP. Use the ADC code to
calculate the RTD resistance with the following equation:
ResistanceRTD =
It is essential that the AGND_SENSE pin connects to the low-side
of the measured RTD. Figure 41 shows the current, voltage, and
measurement paths of the resistance measurement configuration.
where:
ResistanceRTD is the calculated RTD resistance in Ωs.
ADC_CODE is the code of the ADC_RESULTx registers.
RPULL-UP has a value of 2100 Ω.
RPULL UP
Do not change the ADC_MUX bits in the settings of the
ADC_CONFIGx registers if in RTD mode. Changing from the
default ADC mux configuration results in a void ADC result.
21274-011
16-BIT
ADC
2.5V
RTD
( ADC _ CODE × RPULL −UP )
( 65,535 − ADC_CODE )
Figure 40. RTD Bias Circuit
ALDO1V8
REFIN
REFOUT
ALDO5V
MEASUREMENT PATH
VOLTAGE PATH
CURRENT PATH
AVDD
AD74412R
5V
LDO
1.8V
ALDO
IOVDD
CCOMP_x
DVCC
DLDO1V8
VIOUTP_x
2.5V
VREF
1.8V
INTERNAL
DLDO OSCILLATOR
RSENSE
100, 0.1%
10ppm/°C
DAC
DGND
I/OP_x
BAV99
SCLK
INPUT
SHIFT
REGISTER
AND
DIGITAL
LOGIC
ADC_RDY
LDAC
GPO_A
SENSELF_x
VIOUTN_x
AGND_SENSE
SENSEH_x 2kΩ 0.1%
SENSEHF_x
CFILTER
DIAGNOSTICS
BLOCK
GPO_B
GPO_C
CLOAD
68nF
RFILTER
SENSELF_x
MUX
SDO
ALERT
MUX
ADC
SDI
CHANNEL
MUX
SENSEHF_x
SYNC
SENSEL_x
SENSEL_x
CFILTER
RTD
2kΩ
SENSELF_x
THRESHOLD
GPO_D
RFILTER
TVS
CHANNEL A
POWER-ON
RESET
AVSS = NEGATIVE DVCC
CHANNEL B
CHANNEL C
CHANNEL D
AGND1
I/ON_x
CHARGE PUMP
AVSS CPUMP_N
CPUMP_P
AGND3
AGND2
AGND
AGND_SENSE
21274-012
RESET
1nF
CASCODE_x
CPUMP FLY
CAPACITOR
Figure 41. Resistance Measurement Configuration
Rev. A | Page 34 of 66
Data Sheet
AD74412R
Digital Input Logic
Interpreting ADC Data
The digital input circuit can convert high voltage digital inputs
from the I/OP_x screw terminal to low voltage logic signals on
the GPO_x pins or on the SPI.
The ADC is not required for digital input operation. However,
the ADC is available for voltage and current measurements
while the digital input logic mode is enabled. In digital input
logic mode, the ADC, by default, measures the voltage across
the I/OP_x to I/ON_x screw terminals in a 0 V to 10 V range
when in digital input logic mode. Use the ADC result to
calculate the voltage across the I/OP_x to I/ON_x screw
terminals by using the following equation:
An externally powered sensor provides a high voltage digital
input on the I/OP_x screw terminal. Either the unfiltered screw
voltage on the SENSEL_x pin or a filtered version of the screw
voltage on the SENSELF_x pin can be routed to the on-chip
comparator. The comparator compares the voltage of the
selected pin to a programmable threshold (see the Digital Input
Threshold Setting section for additional information). To
debounce the comparator output see the Debounce Function
section.
VADC = (ADC_CODE/65,535) × Voltage Range
where:
VADC is the measured voltage in volts.
ADC_CODE is the value of the ADC_RESULTx registers.
Voltage Range is the ADC measurement range and is 10 V.
Monitor the digital input comparator outputs by reading from
the DIN_COMP_OUT register. Alternatively, each channel has
a corresponding GPO_x pin associated with the channel. These
GPO_x pins are configured via the GPO_CONFIGx registers to
drive out the debounced digital input signal.
Digital Input Current Sink
The AD74412R includes a programmable current sink. The
current sink is programmed via the DIN_SINK bits within the
DIN_CONFIGx registers from 0 mA to 1.8 mA in 120 µA steps.
Figure 42 shows the current, voltage, and output paths of the
digital input logic mode.
REFIN
REFOUT
ALDO1V8
ALDO5V
OUTPUT PATH
VOLTAGE PATH
CURRENT PATH
AVDD
EXAMPLE DRY
CONTACT INPUT
EXT POWER SUPPLY
AD74412R
5V
LDO
1.8V
ALDO
IOVDD
CCOMP_x
DVCC
DLDO1V8
1.8V
INTERNAL
DLDO OSCILLATOR
24V
1nF
VIOUTP_x
CASCODE_x
2.5V
VREF
AGND
CURRENT
SINK
DAC
RSENSE
100, 0.1%
10ppm/°C
DGND
SCLK
BAV99
SDI
SDO
ALERT
ADC_RDY
I/OP_x
SENSEHF_x
ADC
MUX
INPUT
SHIFT
REGISTER
AND
DIGITAL
LOGIC
CHANNEL
MUX
SYNC
VIOUTN_x
SENSELF_x
SENSEH_x
AGND_SENSE
SENSEHF_x
CFILTER
DEGLITCH
AND GPO
CONFIGURATION
CIRCUITRY
GPO_B
GPO_C
GPO_D
DIAGNOSTICS
BLOCK
SENSELF_x
MUX
LDAC
GPO_A
2kΩ 0.1%
SENSEL_x
SENSEL_x
2kΩ
SENSELF_x
CFILTER
THRESHOLD
CLOAD
68nF
RFILTER
RFILTER
TVS
CHANNEL A
POWER-ON
RESET
RESET
CHANNEL B
CHANNEL C
AGND1
AVSS
CHARGE PUMP
CPUMP_N
I/ON_x
AGND
CHANNEL D
CPUMP_P
AGND3
AGND2
AGND_SENSE
21274-013
AVSS = NEGATIVE DVCC
CPUMP FLY
CAPACITOR
Figure 42. Digital Input Logic Mode Configuration
Rev. A | Page 35 of 66
AD74412R
Data Sheet
Digital Input Threshold Setting
The digital input thresholds are set by an internal DAC. The
reference to this DAC is driven by either the VAVDD or the reference
voltage, VREFIN. This reference is configured by writing to the
DIN_THRESH_MODE bit within the DIN_THRESH register.
The specific threshold levels are programmed using the
COMP_THRESH bits in the DIN_THRESH register. There
are five bits available to configure the threshold.
The following equation shows the relationship between the
programmed code in the COMP_THRESH bits and the
corresponding threshold voltage when the DAC reference is
set to AVDD.
VTHRESH ( AVDD ) =
2 ×VAVDD
VAVDD
+ Code ×
60
60
where:
VTHRESH(AVDD) is the comparator threshold expressed in volts.
VAVDD is the AVDD supply value in volts.
Code is the decimal code loaded to the COMP_THRESH bits.
The maximum programmable code in this mode is Decimal 29.
The following equation shows the relationship between the
programmed code in the COMP_THRESH bits and the
corresponding threshold voltage when the DAC reference is
set to VREFIN.
VTHRESH(FIXED VOLTAGE) = 0.5 + (Code × 0.5)
DEBOUNCE_TIME Code (Hex)
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Debounce Time (ms)
0.0756
0.1008
0.1301
0.1805
0.2406
0.3203
0.4203
0.5602
0.7504
1.0008
1.3008
1.8008
2.4008
3.2008
4.2008
5.6008
7.5007
10.0007
13.0007
18.0006
24.0006
32.0005
42.0004
56.0003
75.0000
where:
VTHRESH(FIXED VOLTAGE) is the comparator threshold expressed in volts.
Code is the decimal code loaded to the COMP_THRESH bits.
The debounce circuit has the following two modes of operation:
Debounce Mode 0 and Debounce Mode 1. Both modes are
programmed via the DEBOUNCE_MODE bit in the DIN_
CONFIGx registers.
The maximum programmable code in this mode is Decimal 31.
Debounce Mode 0 (Default)
Debounce Function
In this mode, the sampled comparator outputs are counted. A
high sample occurrence is counted in one direction (either up
or down), whereas a low sample occurrence is counted in the
opposite direction. The DIN_COMP_OUT register changes
state when the programmed counter target is reached.
The digital input comparator outputs are sampled at regular
intervals and passed to a user-programmable debounce operation.
The comparator outputs can be debounced for a userprogrammable amount of time via the 5-bit DEBOUNCE_
TIME bits within the DIN_CONFIGx registers. Set these bits to
0x00 to bypass the debouncer. Table 15 shows the available
programmable debounce times.
Table 15. Digital Input Programmable Debounce Times
DEBOUNCE_TIME Code (Hex)
00
01
02
03
04
05
06
Debounce Time (ms)
Bypass
0.0130
0.0187
0.0244
0.0325
0.0423
0.0561
Figure 43 shows an example of Debounce Mode 0 in operation.
The debounce time is set to 100 μs in the DIN_CONFIGx registers.
A clock with an approximate frequency of 800 ns samples counts
the comparator signal. After the comparator signal changes state
from the current debounced signal, the debounce function counter
begins to count the duration of the signal at the new state. The
count direction changes if the comparator signal reverts back to the
original state. After the counter reaches the target count, the DIN_
COMP_OUT is updated with the state of the comparator signal.
Rev. A | Page 36 of 66
Data Sheet
AD74412R
COUNTING CLOCK (800ns)
COUNTER
0
1
2
1
2
3
4
3
4
5
124
125
124
125
21274-014
COMPARATOR OUTPUT SIGNAL
GPO_x/SPI SIGNAL
Figure 43. Digital Input Debounce Mode 0 Timing Example
COUNTING CLOCK (800ns)
COUNTER
0
1
2
0
1
2
3
0
1
2
21274-015
COMPARATOR OUTPUT SIGNAL
GPO_x/SPI SIGNAL
Figure 44. Digital Input Debounce Mode 1 Timing Example
AD74412R
DIGITAL LOGIC
AND
SERIAL INTERFACE
GPO_CONFIGx
REGISTER
COMP_INPUT_FILTERED
GPO_x
MUX
MUX
INV_DIN_COMP_OUT
COMPARATOR_EN
DEBOUNCER
MUX
SCLK
SYNC
SDI
SDO
SENSELF_x
SENSEL_x
COMP_THRESHOLD
DAC
PROGRAMMABLE
THRESHOLD
(SHARED ACROSS 4 CHANNELS)
21274-016
DEBOUNCE_MODE
DEBOUNCE_TIME
Figure 45. Digital Input Configuration
Debounce Mode 1
Digital Input Inverter
In this mode, a counter counts the sampled comparator outputs.
After a change of state occurs on the sampled comparator
output, the counter increments until the programmed debounce
time is reached, at which point the DIN_COMP_OUT register
changes state, and the counter resets. If the sampled comparator
output returns to the current DIN_COMP_OUT register value,
the counter resets.
The debounced comparator signal can pass directly to the
DIN_COMP_OUT register. Alternatively, the signal can be
inverted before being sent to the DIN_COMP_OUT register.
To enable this inverter, set the INV_DIN_COMP_OUT bit in
the DIN_CONFIGx registers.
Figure 44 shows an example of Debounce Mode 1 in operation.
Like Debounce Mode 0, the debounce time is set to 100 µs. In
Debounce Mode 1, the counter value is reset each time the
comparator signal returns to the original state. The comparator
output must be at the new state for the full duration of the
debounce time to update the DIN_COMP_OUT signal.
Figure 45 shows a detailed view of the digital input configuration
including the comparator, debouncer, inverter, and GPO_x
hook up.
Rev. A | Page 37 of 66
AD74412R
Data Sheet
DIGITAL INPUT, LOOP POWERED MODE
Figure 46 shows the current, voltage, and output paths of the
digital input, loop powered mode configuration.
Like the current output mode function (see the Current Output
Mode section), the digital input, loop powered function
configures the output state to provide a high-side current output
that can power an external sensor. Program the DAC_CODEx
registers to provide the required current source limit.
Interpreting ADC Data
The ADC is not required for digital input operation. However,
the ADC is available for voltage and current measurements
when the digital input loop powered mode is enabled. In digital
input loop powered mode, the ADC, by default, measures the
voltage across the I/OP_x to I/ON_x screw terminals in a 0 V
to 10 V range. Use the ADC measurement result to calculate
this voltage by using the following equation:
Either the unfiltered voltage on the SENSEL_x pin or the filtered
input on the SENSELF_x pin can be routed to the on-chip
comparators. These comparators compare the voltage on the
selected pin to a programmable threshold that can either be a
fixed voltage or a voltage proportional to the VAVDD. See the
Digital Input Threshold Setting section for more information
on the programmable threshold voltages.
VADC = (ADC_CODE/65,535) × Voltage Range
where:
VADC is the measured voltage in volts.
ADC_CODE is the value of the ADC_RESULTx registers.
Voltage Range is 10 V, the measurement range of the ADC.
The output of the comparators can be debounced (see the
Debounce Function section) or passed directly or inverted
to the serial interface and/or to the parallel output pins.
If the default measurement configuration is changed to measure
the current, tie the VIOUTN_x pin to ground via the on-chip
200 kΩ resistor by enabling the CH_200K_TO_GND bit in the
ADC_CONFIGx registers.
The digital input comparator outputs are monitored by reading
from the DIN_COMP_OUT register. The comparator outputs can
also be monitored with the GPO_x pins. Each channel has a
corresponding GPO_x pin that is configured via the GPO_
CONFIGx registers to drive out the debounced comparator
output signal.
REFIN
REFOUT
ALDO1V8
ALDO5V
OUTPUT PATH
VOLTAGE PATH
CURRENT PATH
AVDD
AD74412R
1.8V
ALDO
IOVDD
5V
LDO
CCOMP_x
DVCC
1.8V
INTERNAL
DLDO OSCILLATOR
2.5V
VREF
DAC
1nF
CASCODE_x
OPTIONAL P CHANNEL FET
FOR HIGH RLOAD IOUT
RSENSE
100, 0.1%
10ppm/°C
G=1
DGND
ADC_RDY
GPO_B
GPO_C
DEGLITCH
AND GPO
CONFIGURATION
CIRCUITRY
SENSEH_x
DIAGNOSTICS
BLOCK
SENSELF_x
SENSEL_x
CFILTER
2kΩ
RFILTER
TVS
CHANNEL A
CHANNEL B
CHANNEL C
AVSS = NEGATIVE DVCC
AVSS
OUT A
CAP
68nF
RFILTER
SENSELF_x
SENSEL_x
POWER-ON
RESET
AGND1
2kΩ 0.1%
SENSEHF_x
THRESHOLD
GPO_D
RESET
VIOUTN_x
AGND_SENSE
CFILTER
LDAC
GPO_A
SENSELF_x
MUX
SDO
ALERT
ADC
MUX
SDI
SENSEHF_x
INPUT
SHIFT
REGISTER
AND
DIGITAL
LOGIC
CHANNEL
MUX
SYNC
I/OP_x
BAV99
SCLK
AGND
CHARGE PUMP
CPUMP_N
CPUMP_P
I/ON_x
CHANNEL D
AGND3
AGND2
AGND_SENSE
CPUMP FLY
CAPACITOR
Figure 46. Digital Input, Loop Powered Configuration Mode
Rev. A | Page 38 of 66
21274-017
DLDO1V8
VIOUTP_x
Data Sheet
AD74412R
GETTING STARTED
USING CHANNEL FUNCTIONS
The following three external supplies are required to power up
the AD74412R: VAVDD, which is the positive analog supply, the
voltage on the DVCC pin (VDVCC), which is the digital and
charge pump supply, and the VIOVDD, which is the input/
output pads supply. The IOVDD pin and the DVCC pin can be
connected to the same external supply. VIOVDD can also be driven as
low as 1.8 V separately to allow SPI communications at 1.8 V. See
Table 10 for the voltage range of the three external supplies and
the associated conditions.
The channel function is selected using the CH_FUNC_
SETUPx registers. After a channel function is selected, the
contents of the ADC_CONFIGx registers and the DIN_CONFIGx
registers are updated with predefined values, which allows the
user to configure the device with a minimal set of commands.
Table 16 outlines the default settings of the bits for any given
channel function.
A charge pump generates a negative supply, VAVSS, that is equal
to negative VDVCC. VAVSS cannot be used to drive the external
circuitry.
When powering up the AD74412R, apply ground connections
first. After power-up, the user must wait approximately 10 ms
(see Table 10) before any transaction to the device can take place.
After initial power-up, the ALERT pin is pulled low as a result
of various bits, such as the RESET_OCCURRED bit and the
CHARGE_PUMP_ERR bit, being set in the ALERT_STATUS
register. It is recommended to clear the alert status before
continuing to use the AD74412R. Write 1 to clear each bit in the
ALERT_STATUS register.
Upon initial power-up or after device reset, the output channels
are disabled and default to a high impedance state.
After configuring the channel function, users can configure the
DAC_CODEx registers, if required. If the LDAC pin is not tied
low, a load DAC (LDAC) command is required to update the
channel outputs after the DAC codes are updated. See the
LDAC Function section more information.
Switching Channel Functions
Take care when switching from one channel function to
another. All functions must be selected for a minimum of
130 μs before changing to another function.
The DAC_CODEx registers are not reset by changing channel
functions. Prior to changing channel functions, it is recommended
to set the DAC code to 0x0000 via the DAC_CODEx registers.
Set the channel function to high impedance via the CH_FUNC_
SETUPx registers before transitioning to the new channel function.
After the new channel function is configured, it is recommended to
wait 150 μs before updating the DAC code.
Table 16. Register Edits based on Channel Function Selection
Channel Function (Programmed
via the CH_FUNC_SETUPx Registers)
High Impedance
Voltage Output
Current Output
Voltage Input
Current Input, Externally Powered
Current Input, Loop Powered
Resistance Measurement
Digital Input Logic
Digital Input, Loop Powered
Defaults of the ADC_CONFIGx Registers
ADC_MUX Bits
RANGE Bits
00: voltage across the I/OP_x to 000: 0 V to 10 V
I/ON_x screw terminals
01: voltage across RSENSE
011: −2.5 V to +2.5 V
00: voltage across the I/OP_x to 000: 0 V to 10 V
I/ON_x screw terminals
00: voltage across the I/OP_x to 000: 0 V to 10 V
I/ON_x screw terminals
01: voltage across RSENSE
010: −2.5 V to 0 V
01: voltage across RSENSE
001: 0 V to 2.5 V
00: voltage across the I/OP_x to 001: 0 V to 2.5 V
I/ON_x screw terminals
00: voltage across the I/OP_x to 000: 0 V to 10 V
I/ON_x screw terminals
00: voltage across the I/OP_x to 000: 0 V to 10 V
I/ON_x screw terminals
Rev. A | Page 39 of 66
Defaults of the DIN_CONFIGx Registers
COMPARATOR_EN Bit
DIN_SINK Bits
0: comparator disabled 0: ISINK off
0: comparator disabled
0: comparator disabled
0: ISINK off
0: ISINK off
0: comparator disabled
0: ISINK off
0: comparator disabled
0: comparator disabled
0: comparator disabled
0: ISINK off
0: ISINK off
0: ISINK off
1: comparator enabled
0: ISINK off
1: comparator enabled
0: ISINK off
AD74412R
Data Sheet
ADC FUNCTIONALITY
ADC Conversion Rates
The default measurement configurations for each mode are
described in the Using Channel Functions section. The ADC
can measure either current or voltage on one or more of the
four input/output channels and up to four diagnostic inputs
with one conversion request.
The available ADC conversion rates on the AD74412R are
4.8 kSPS with 50 Hz and 60 Hz rejection disabled, and 20 SPS,
with 50 Hz and 60 Hz rejection enabled.
The measurement settings of the channels and conversion rates
are configured via the ADC_CONFIGx registers. The diagnostics
settings are configured via the DIAG_ASSIGN register. The
diagnostics conversion rate is programmed in the ADC_
CONV_CTRL register.
After the measurements are configured, enable the relevant
ADC inputs via the ADC_CONV_CTRL register.
Select either single conversion or continuous conversion mode
by setting the appropriate value to the CONV_SEQ bits in the
ADC_CONV_CTRL register.
Each of the four input/output channels can be individually
configured to a conversion rate via the ADC_CONFIGx
registers. The conversion rate of the diagnostics inputs is set via
the ADC_CONV_CTRL register. One conversion rate selection
applies to all diagnostic inputs.
The time it takes for a sequence of conversions to complete is
dependent on several factors, such as the number of selected
channels, the selected conversion rates, and whether single or
continuous mode conversions are enabled. Conversions are
clocked by an on-chip oscillator, which has a typical accuracy
of ±1%. Figure 47 outlines the various components required to
estimate a complete conversion time for any given sequence.
For single channel conversions, consider the following time
components when calculating the overall sequence time:
In single conversion mode, the ADC sequencer starts conversions
at the lowest enabled channel before cycling through successively
higher enabled channel numbers, followed by the enabled
diagnostics. After each enabled channel is converted once, the
ADC enters idle mode, and conversions are stopped.
•
In continuous conversion mode, the ADC channel sequencer
continuously converts each enabled channel and diagnostic
until a command is written to stop the conversions. Set the stop
command by setting the CONV_SEQ bits in the ADC_CONV_
CTRL register bits to idle mode or power-down mode. The
command stops conversions at the end of the current sequence.
If the enabled channels or the measurement configuration on any
given channel require a function change, continuous conversions
must be stopped before making the changes. Restart the
continuous conversions after making the appropriate changes.
After a sequence is complete, either single conversion or
continuous conversion, all data results are transferred to the
relevant ADC_RESULTx and DIAG_RESULTx registers,
asserting the ADC_RDY pin.
•
•
The time taken for the SPI transaction to start the
conversions.
An initial pipeline delay prior to the first conversion.
The conversion time for each ADC conversion.
Figure 47 shows the timing breakdown of a single channel
conversion example. In this example, only Channel A is
enabled, and continuous conversions are initiated with a
4.8 kSPS conversion rate.
The time to the first complete conversion (the SYNC pin falling
edge to the ADC_RDY pin falling edge) is 284.32 µs and is
calculated by adding the SPI transfer time, the pipeline delay
time, and the conversion rate on Channel A at 4.8 kSPS (208.33 µs)
The time between conversions (the ADC_RDY pin falling edge
to the ADC_RDY pin falling edge) is 208.33 μs.
Table 17. Conversion Times Components
Conversion Rate
4.8 kSPS
20 SPS
SPI Transfer Time (μs),
42 ns SCLK
1.99
1.99
Start-Up Pipeline Delay (µs)
74
74
Single ADC
Conversion Time
208.33 μs
50 ms
Channel Switch Time,
Multiple Enabled Channels (μs)
24.4
24.4
SPI
TRANSFER
PIPELINE DELAY
CHANNEL A
CONVERSION 1
CHANNEL A
CONVERSION 2
CHANNEL A
CONVERSION 3
1.99µs
74µs
208.33µs
208.33µs
208.33µs
t17
ADC_RDY
Figure 47. Single Channel, Continuous Conversions Timing Diagram
Rev. A | Page 40 of 66
21274-018
SYNC
Data Sheet
AD74412R
For multichannel conversions, consider the following
components when calculating the overall sequence time:
•
•
•
•
The time it takes for the first complete conversion (SYNC falling
edge to ADC_RDY falling edge), is 200.149 ms and is calculated
by adding the SPI transfer time, the pipeline delay time, and the
conversion time on Channel A at 20 SPS, followed by adding the
channel switch time and conversion time for the remaining
three conversions.
The time taken for the SPI transaction to start the
conversions.
An initial pipeline delay prior to the first conversion.
The conversion time needed for each ADC conversion.
A channel switch time for each time the selected ADC
channel is switched.
The time between all subsequent conversion sequences
(the ADC_RDY pin falling edge to the ADC_RDY pin falling edge)
is 200.0976 ms and is calculated by adding the channel switch
time with the conversion time for the four selected ADC inputs.
Figure 48 shows an example of the timing breakdown for a
multichannel conversion. In this example, Channel A and
Channel B, with Diagnostic 0 and Diagnostic 1 enabled.
Continuous conversions are initiated with a 20 SPS
conversion rate.
CHANNEL SWITCH TIME
SPI
TRANSFER
PIPELINE
DELAY
CHANNEL A
CONVERSION 1
1.99µs
74µs
50ms
CHANNEL B
CONVERSION 1
24.4µs
50ms
DIAGNOSTIC0
CONVERSION 1
24.4µs
50ms
CHANNEL A
CONVERSION 2
DIAGNOSTIC1
CONVERSION 1
24.4µs
50ms
24.4µs
50ms
21274-019
SYNC
ADC_RDY
Figure 48. Multichannel, Continuous Conversions Timing Diagram
Rev. A | Page 41 of 66
AD74412R
Data Sheet
ADC_RDY Functionality
•
The ADC_RDY pin asserts low at the end of a sequence of
conversions for either single conversion or continuous
conversion mode.
See Figure 49 and Figure 50 for timing diagrams of
the ADC_RDY pin in single and continuous conversion modes.
After writing to either the ADC_CONV_CTRL register or
the ADC_CONV_CTRL_80SPS register.
The pin deasserts in any of the following scenarios:
ADC_RDY
ADC PROCESSING
ChA
IDLE
ChB
ChD
D3
IDLE
ChA
ChB
ChD
D3
ChA
IDLE
CONVERT ON ENABLED
CHANNELS
SPI INTERFACE
CNV
ChD
D3
IDLE
ENABLE
CONVERSION
CLEAR ADC_RDY
STATUS BIT, TOGGLE
ADC_DATA_RDY PIN
ENABLE
CONVERSION
ChB
ENABLE
CONVERSION
CLR
CNV
21274-020
•
A 1 is written to the ADC_DATA_RDY status bit in the
LIVE_STATUS register.
After 24 µs in continuous mode.
CNV
Figure 49. ADC_RDY Functionality in Single Conversion Mode
ADC_RDY PIN
NEW CONVERSION DATA AVAILABLE
ADC PROCESSING
IDLE
ChA
ChB
ChD
D3
ChA
ChB
ChD
D3
ChA
ChB
ChD
Figure 50. ADC_RDY Functionality in Continuous Conversion Mode
Rev. A | Page 42 of 66
D3
ChA
ChB
ChD
D3
21274-021
•
Data Sheet
AD74412R
ADC Output Data Format
Table 18 outlines the expected ADC results for inputs specified in the table for each voltage range.
Table 18. ADC Output Data Format 1
RANGE Bits
000: 0 V to 10 V
001: 0 V to 2.5 V 2
010: 0 V to 2.5 V 3
011: −2.5 V to +2.5 V
ADC_MUX Bits
0: voltage across the
I/OP_x to I/ON_x screw
terminals
1: voltage from SENSELF_x
pin to SENSEHF_x pin
across RSENSE
0: voltage across the
I/OP_x to I/ON_x screw
terminals
1: voltage from SENSELF_x
pin to SENSEHF_x pin
across RSENSE (SENSELF_x >
SENSEHF_x)
0: voltage across the
I/OP_x to I/ON_x screw
terminals
1: voltage from SENSELF_x
pin to SENSEHF_x pin
across RSENSE (SENSELF_x <
SENSEHF_x)
0: voltage across the
I/OP_x to I/ON_x screw
terminals
1: voltage from SENSELF_x
pin to SENSEHF_x pin
across RSENSE
ADC Data for Negative
Full-Scale Input
Not applicable
ADC Data for Zero Input
Code 0x0000 for 0 V
ADC Data for Positive
Full-Scale Input
Code 0xFFFF for 10 V
Code 0x0000 for 0 mA
flowing into the AD74412R
through RSENSE
Code 0x0000 for 0 V
Code 0x3FFF for 25 mA
flowing into the AD74412R
through RSENSE
Code 0xFFFF for 2.5 V
Not applicable
Code 0x0000 for 0 mA
flowing into the AD74412R
through RSENSE
Code 0xFFFF for 25 mA
flowing into the AD74412R
through RSENSE
Code 0xFFFF for −2.5 V 4
Code 0x0000 for 0 V
Not applicable
Code 0xFFFF for 25 mA
flowing out of the
AD74412R through RSENSE
Code 0x0000 for 0 mA
flowing out of the
AD74412R through RSENSE
Not applicable
Code 0x0000 for −2.5 V4
Code 0x8000 for 0 V
Code 0xFFFF for 2.5 V
Code 0x0000 for 25 mA
flowing out of the
AD74412R through RSENSE
Code 0x8000 for 0 mA
flowing through RSENSE
Code 0xFFFF for 25 mA
flowing into the AD74412R
through RSENSE
Not applicable
Not applicable
When measuring across the RSENSE, the I/OP_x screw terminal voltage must be between VAVDD − 0.2 and the voltage on the AGND pin (VAGND) − 500 mV for valid
measurements. A supplemental screw terminal diagnostic measurement is recommended.
Predominantly used to measure current sinking to AD74412R.
3
Predominantly used to measure current sourced by the AD74412R.
4
The lowest measurable negative voltage, with respect to ground, depends on the VAVSS. The full ADC range of 2.5 V is not available.
1
2
If the voltage measured by the ADC is either above full scale
or below zero scale, an ADC_CONV_ERR bit is set in the
ALERT_STATUSx registers, asserting the ALERT pin. In this
case, the ADC output reads 0xFFFF or 0x0000, respectively. The
ADC_CONV_ERR bit can be masked via the ALERT_ MASK
register (optional) if these alerts are not required.
ADC Noise
Table 19 shows the peak-to-peak noise of the AD74412R for
each of the output data rates and voltage ranges. These numbers are
typical and are generated with a differential input voltage of 0 V
when the ADC is continuously converting on a single channel.
Table 19. Peak-to-Peak Noise in LSBs per Voltage Range and
Output Data Rate (Inputs Shorted)
Output Data
Rate (SPS)
20
80
4.8k
+10 V Range
(LSBs)
0.18
0.61
2.96
+2.5 V Range
(LSBs)
0.21
0.75
3.57
±2.5 V Range
(LSBs)
0.22
0.86
3.52
Table 20 shows the peak-to-peak resolution for each voltage
range and output data rate.
Table 20. Peak-to-Peak Resolution in Bits per Voltage Range
and Output Data Rate
Output Data
Rate (SPS)
20
80
4800
Rev. A | Page 43 of 66
+10 V Range
(Bits)
16
16
14.7
+2.5 V Range
(Bits)
16
16
14.5
±2.5 V Range
(Bits)
16
16
14.5
AD74412R
Data Sheet
DIAGNOSTICS
The AD74412R has a diagnostic function that allows the ADC
to measure various on-chip voltages. These diagnostic voltages
are scaled to be measurable within the ADC range.
select the conversion rate via the ADC_CONV_CTRL register.
The following two conversion rates are available for selection
within the ADC_CONFIGx registers: 4.8 kSPS (50 Hz and 60 Hz
rejection disabled) or 20 SPS (50 Hz and 60 Hz reject enabled).
The diagnostics inputs are independent of the four, configurable
output channels of the AD74412R. The DIAG_ASSIGN register
assigns the voltage measurements to each diagnostic input.
Select a diagnostic input to be measured by the ADC by enabling
that input in the ADC_CONV_CTRL register. Users can also
In the equations listed in Table 21, DIAG_CODE is the ADC
result code read from the DIAG_RESULTx registers, and
voltage range is the ADC measurement range and is 2.5 V.
Table 21 shows a full list of available diagnostics, and the
equations required to calculate the diagnostic value.
Table 21. User Selectable Diagnostics
Diagnostic
VAGND
Formula to Interpret ADC Result
=
VAGND
DIAG_CODE
65,535
× Voltage Range
Temperature Sensor (Internal Die Temperature
DIAG_CODE − 2034
Measurement)/°C
=
Temperature
− 40
8.95
Voltage on AVDD Pin (VAVDD)
DIAG_CODE
16 ×
VAVDD =
× Voltage Range
65,535
Voltage on DLDO1V8 Pin (VDLDO1V8)
DIAG_CODE
VDLDO1V 8 =
3×
× Voltage Range
65,535
VAVSS
Voltage on REFOUT Pin (VREFOUT)
VAVSS = (0.0001776 × DIAG_CODE) – 5.98
Voltage on ALDO5V Pin (VALDO5V)
DIAG_CODE
VALDO 5V =
7×
× Voltage Range
65,535
Voltage on ALDO1V8 Pin (VALDO1V8)
DIAG_CODE
2.33 ×
VALDO1V 8 =
× Voltage Range
65,535
VDVCC
DIAG_CODE
VDVCC =
3.3 ×
× Voltage Range
65,535
VIOVDD
DIAG_CODE
VIOVDD =
3.3×
×Voltage Range
65,535
Measure of SENSEL_x Pin Voltage (VSENSEL_x)
DIAG _ CODE
VSENSEL _ x =
12 ×
× Voltage Range
65,535
DIAG_CODE
×Voltage Range
65,535
VREFOUT =
0.762
Rev. A | Page 44 of 66
Data Sheet
AD74412R
DACs
2.
There are three sources for the code loaded to the DAC. The
typical option is to load a code to the DAC from the DAC_
CODEx registers. The DAC can also be loaded from the
DAC_CLR_CODEx registers when the 0x73D1 code (DAC clear
key) is written to the CMD_KEY register (see Table 51). See the
Clear Code Function section for more information on the clear
functionality. The third option is to enable the digital linear
slew that controls the rate at which the DAC code is loaded to
the DAC.
The code loaded to the DAC from any of the three sources is
also loaded to the DAC_ACTIVEx registers. The DAC_ACTIVEx
registers contain the current code loaded to the DAC,
irrespective of the code source.
LDAC Function
The LDAC function controls when the DACs are updated. To
control the timing of the DAC updates, tie the LDAC pin high
while programming the DAC_CODEx registers. To update the
DAC code, pulse the LDAC pin low, or alternatively, program
the 0x953A code (LDAC key) to the CMD_KEY register (see
Table 51).
To ensure that the DAC is properly updated, only pulse
the LDAC pin low after the SPI write to the DAC_CODEx
registers is complete.
If simultaneous updates are not required on all four DACs, tie
the LDAC pin permanently low to allow the DACS to instantly
update after the DAC_CODEx registers are programmed.
When a DAC update takes place, the DAC_ACTIVEx registers
are updated at the same time as a new DAC code is passed to
the DAC.
Clear Code Function
The clear code function allows the user to clear the DACs to a
preprogrammed code at any given time.
When a DAC clear takes place, the DAC_ACTIVEx registers are
updated at the same time as a new DAC code is passed to the DAC.
If a channel is cleared by writing to the DAC clear key, and if
the LDAC pin is held low to update the DACs, the clear function
takes priority over the LDAC function.
If a DAC update is required after a clear has taken place, program
each individual DAC_CODEx register with the desired code.
Digital Linear Slew Rate Control
The digital linear slew rate control feature of the AD74412R
controls the rate at which the output transitions to the new value.
This slew rate control feature is available for both the current
and voltage outputs.
When the slew rate control feature is disabled, the output value
transitions at a rate limited by the output drive circuitry and the
attached load.
To reduce the slew rate, enable the digital slew rate control
feature via the OUTPUT_CONFIGx registers.
After the digital slew rate control feature is enabled, the output
steps digitally at a rate defined by the user in the OUTPUT_
CONFIGx registers. The SLEW_LIN_STEP bits dictate the
number of codes per increment, and the SLEW_LIN_RATE bits
dictate the rate at which the codes are updated. Table 22 shows
the typical programmable slew rates for a zero-scale to full-scale
(or full-scale to zero-scale) DAC update that are available on the
AD74412R.
The DAC_ACTIVEx registers can monitor the progress of slewing
to a target DAC code. These registers contain the code that is
currently loaded to the DAC.
Note that if the digital slew rate control feature is enabled and
the DAC clear key is written to the CMD_KEY register, the
output slews at the preprogrammed slew rate to the programmed
CLR_CODE bits in the DAC_CLR_CODEx registers.
To clear an output channel, take the following steps.
1.
3.
Program the desired 13-bit clear code to the DAC_CLR_
CODEx registers.
Write the DAC clear key to the CMD_KEY register to clear
the DAC to the preprogrammed 13-bit code. If the
CLR_EN bit is not set, the output remains in the current state.
Enable the clear option for the channel by setting the
CLR_EN bit in the OUTPUT_CONFIGx register. The
channel can now be cleared at any time.
Table 22. Programmable Slew Times for a Zero-Scale to Full-Scale Code Update
Update Slew Rate, Programmable via SLEW_LIN_RATE Bits (kHz)
4
64
150
240
1
Step Size (Codes), Programmable via SLEW_LIN_STEP Bits1
64
120
500
1820
31.7 ms
17 ms
4 ms
1 ms
2.0 ms
1.1 ms
259 μs
75.8 μs
858 μs
459 μs
113 μs
40.1 μs
520 μs
280 μs
73.6 μs
38.6 μs
These are theoretical values. The final slew rate is limited by CLOAD capacitor value.
Rev. A | Page 45 of 66
AD74412R
Data Sheet
DRIVING INDUCTIVE LOADS
FAULTS AND ALERTS
It is recommended to use the digital slew rate control when
driving inductive loads greater than approximately 4 mH.
Controlling the output slew rate minimizes ringing when
stepping the output current by minimizing the current rate
of change (dI/dt).
The AD74412R is equipped with several fault monitors to
detect an error condition.
If an open circuit is detected via the ALERT_STATUS register,
it is recommended to set the IOUT current to 0 mA before
reconnecting the load to avoid ringing on the I/OP_x screw
terminal.
RESET FUNCTION
After the AD74412R is reset, all registers are reset to the default
state, and the calibration memory is refreshed. The device is
configured in high impedance mode. A reset can be initiated in
several ways.
The hardware reset is initiated by pulsing the RESET pin low.
The RESET pulse width must comply with the specifications in
Table 11.
A software reset is initiated by writing the 0x15FA code
(Software Reset Key1) followed by the 0xAF51 code
(Software Reset Key2) to the CMD_KEY register (see Table 51).
A reset can also be initiated via the thermal reset function,
which is described in the Thermal Alert and Thermal Reset
section.
If an alert or fault condition occurs, the ALERT pin asserts. To
determine the source of the alert condition, read the ALERT_
STATUS register. This register contains a latched bit for each
alert condition. After the error condition is removed, clear the
activated flag by writing 1 to the location of the corresponding
bits. See Table 45 for a detailed description of each alert condition.
The LIVE_STATUS register is a live representation of the error
conditions. The bits in this register are not latched and are only
cleared after the error condition is no longer present. A full list
of the LIVE_STATUS bits is shown in Table 46.
The ALERT_MASK register prevents certain error conditions
from activating the ALERT pin.
Channel Faults
Each channel is equipped with a VOUT short-circuit error, an
IOUT open circuit error, and current input (IIN) short-circuit
error as described in the Device Functions section.
Note that the AD74412R is not designed to withstand more
than one fault condition at any point in time. Manage faults as
the faults appear and reset the channel, if necessary, to avoid
overheating the device.
POWER SUPPLY MONITORS
If the VDLDO1V8 drops below 1.62 V or if the VDVCC drops below
approximately 1.93 V, the internal power-on reset function
resets the AD74412R. The device does not come out of reset
until the VDLDO1V8 and the VDVCC rise above these voltage levels.
After a reset cycle completes, the RESET_OCCURRED bit is set
in the ALERT_STATUS register. If an SPI transfer is attempted
before the reset cycle is complete (see Table 11 for typical reset
time), the CAL_MEM_ERR bit in the ALERT_STATUS register is
also set to indicate that the calibration memory is not fully
refreshed. After the reset time elapses, clear these bits in the
ALERT_STATUS register before continuing to use the device.
THERMAL ALERT AND THERMAL RESET
The AD74412R includes four power supply monitors (PSMs) to
detect a supply failure. If any of the supplies falls below a defined
threshold (shown in Table 23), the corresponding bit is set in the
ALERT_STATUS register.
Table 23. PSM Trip Levels
Power Supply Monitor
ALDO1V8
DVCC
AVDD
ALDO5V
Charge Pump
If the AD74412R die temperature reaches 110°C, a high
temperature error bit (HI_TEMP_ERR) is set in the
ALERT_STATUS register to alert the user of increasing
die temperature.
The device can also be configured to reset at higher die
temperatures. To reset the device at higher temperatures, enable
the thermal reset function by setting the EN_THERM_RST bit in
the THERM_RST register. After this bit is set, the device goes
through a full reset after the die temperature reaches 140°C.
Rev. A | Page 46 of 66
Typical Trip Level (V)
+1.35
+1.93
+9.26
+4.05
−1.65
Data Sheet
AD74412R
GPO_x PINS
SPI CRC
The AD74412R has four GPO_x pins, one per channel. Each
channel GPO_x pin can be configured in the following ways:
To ensure that data is received correctly in noisy environments, the
AD74412R has a CRC implemented in the SPI interface. This
CRC is based on an 8-bit CRC. The device controlling the
AD74412R generates an 8-bit frame check sequence using the
following polynomial:
•
•
•
With a 100 kΩ pull-down resistor, the default state of the
GPO_x pins
As the logic outputs of the digital input functions
As a logic high or low output
In a high impedance state
The GPO_x configuration can be set via the GPO_SELECT bits
within the GPO_CONFIGx registers. When configuring the
GPO_x pins as logic outputs, the data of the pins can be written to
the GPO_DATA bit in the GPO_CONFIGx registers. If parallel
updates are required on all channels, the appropriate data can be
written to the GPO_PARALLEL register before being written to
the GPO_SELECT bits in the GPO_CONFIGx registers to
enable parallel updates.
SPI INTERFACE AND DIAGNOSTICS
The AD74412R is controlled over a 4-wire serial interface with
an 8-bit CRC. The input shift register is 32 bits wide, and data is
loaded into the device MSB first under the control of SCLK.
Data is clocked in on the falling edge of SCLK. Table 24 shows the
structure of an SPI write frame.
C(x) = x8 + x2 + x1 + 1
This frame check sequence is added to the end of the data-word,
and the 32-bit data-word is sent to the AD74412R before taking
the SYNC high pin.
The user must supply a frame 32 bits wide containing the
24 data bits and 8 CRC bits. If the CRC check is valid, the data
is written to the selected register. If the CRC check fails, the data
is ignored, the SPI_CRC_ERR status bit in the ALERT_STATUS
register is asserted, and the ALERT pin goes low.
Clear the SPI_CRC_ERR bit (ALERT_STATUS register) by writing
a 1, which returns the ALERT pin (assuming that there are no other
active alerts). The SPI CRC error can be masked by writing to the
relevant bit in the ALERT_MASK register.
SCLK
MSB
D31
Table 24. Writing to a Register
MSB
D31
Reserved
[D30:D24]
Register address
UPDATE ON SYNC HIGH
ONLY IF ERROR CHECK PASSED
SYNC
SDI
[D23:D8]
Data
LSB
[D7:D0]
CRC
ALERT
LSB D7
D8
24-BIT DATA
D0
8-BIT CRC
ALERT PIN GOES LOW
IF ERROR CHECK FAILS
21274-022
•
Figure 51. CRC Timing
SPI Interface SCLK Count Feature
An SCLK count feature is built into the SPI diagnostics. Only
SPI frames with exactly 32 SCLK falling edges are accepted by
the interface as a valid write. SPI frames of lengths other than 32,
or a multiple of 32 in streaming mode, are ignored, and the
SPI_SCLK_CNT_ERR bit flag asserts in the ALERT_STATUS
register. Mask the SPI_SCLK_CNT_ERR bit via the
ALERT_MASK register.
Rev. A | Page 47 of 66
AD74412R
Data Sheet
Readback Mode
The content of these bits is determined by setting the SPI_RD_
RET_INFO bit in the READ_SELECT register.
Two SPI frames are required to read a register location. In the
first frame, the address of the register to be read is written to the
READ_SELECT register. The second SPI frame consists of
either a no operation (NOP) command, another write to the
READ_SELECT register, or a write to any other register. The
contents of the selected register are available on the SDO during
the second frame. Figure 52 shows the timing diagram of the
two-stage readback.
The data is shifted out MSB first. The MSB (Bit 31) is always set
to 1 to allow the SPI master to detect if the SDO line is stuck
low. If the SDO line is stuck low, a CRC of all 0s is calculated.
In this case, the master cannot detect a stuck low condition. By
tying the MSB high, the master can check this bit to detect a
stuck low fault by checking the MSB is 1. Only this MSB is
timed off the falling SYNC edge. All other bits are clocked out
on the SCLK rising edge.
During the second read frame, Bits[D30:D24] provide status
information on the SDO pin, as shown in Table 25 and Table 26.
SYNC
1
32
1
32
1
SCLK
2-STAGE READBACK
SDI
*NOP
INPUT WORD SPECIFIES
REGISTER TO BE READ
*ALTERNATIVELY COULD
WRITE ANOTHER
2-STAGE READBACK
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
NOP
*SELECTED REGISTER DATA
CLOCKED OUT
21274-023
SDO
Figure 52. Two-Stage Readback Timing Diagram
Table 25. SDO Contents for a Read Operation when the SPI_RD_RET_INFO Bit = 0
MSB
D31
1
[D30:D24]
[D23:D8]
Read data
READBACK_ADDR[6:0]
LSB
[D7:D0]
CRC
Table 26. SDO Contents for a Read Operation when the SPI_RD_RET_INFO Bit = 1
MSB
D31
1
D30
0
D29
ALERT
D28
ADC_DATA_ RDY
[D27:D24]
DIN_COMP_OUT[3:0]
Rev. A | Page 48 of 66
[D23:D8]
Read data
LSB
[D7:D0]
CRC
Data Sheet
AD74412R
Streaming Mode
Auto Readback
The AD74412R incorporates a streaming mode where the data
is continuously clocked out on the SDO as long as there are
sufficient SCLKs. The SYNC line must be kept low after the
second frame of a two-stage readback (see the Readback Mode
section). The AD74412R increments through addresses clocking
out the 32-bit contents repeatedly. An SPI_SCLK_CNT_ERR
error is reported if the transaction does not end with 32 + (n × 24)
SCLK rising edges, where n is the number of transactions.
Figure 53 shows the contents on the SDO line when streaming
ADC data.
Auto readback allows the user to read from a selected register
during every SPI transaction. To enable auto readback, set the
AUTO_RD_EN bit in the READ_SELECT register.
The data appearing on the SDO includes the register address
(when the SPI_RD_RET_INFO is set to 0), the 16-bit data, and
the 8-bit CRC.
If the SYNC pin is kept low and the clocks are applied, the data
from the next sequential address is clocked out.
If auto readback is disabled, perform a read as described in the
Readback Mode section.
If auto readback is enabled, the contents of the address written
to the READ_ADDR bits are output on the SDO lines during
each SPI transfer.
At the end of readback sequence, if the SYNC pin is returned
high, the device automatically reads the address previously
written to the READ_SELECT register. If the SYNC pin is held low
after the first read, the device streams through each consecutive
address as described in the Streaming Mode section.
Writes to the register map are not supported in streaming mode.
SYNC
SCLK
7-BIT ADDRESS 16-BIT DATA
8-BIT CRC
ADC0 RESULT AFTER A
TWO STAGE READBACK
16-BIT DATA
8-BIT CRC
STREAMED ADC1 RESULT
Figure 53. Streaming Mode SDO Contents
Rev. A | Page 49 of 66
16-BIT DATA
8-BIT CRC
STREAMED ADC2 RESULT
DON’T CARE
21274-024
SDO
AD74412R
Data Sheet
BOARD DESIGN AND LAYOUT CONSIDERATIONS
This section outlines the critical board design and layout
considerations for the AD74412R.
To guarantee stability for the SENSEL_A pin, the SENSEL_B
pin, the SENSEL_C pin, and the SENSEL_D pin, limit the
capacitance to ground between the pin and the required 2 kΩ
resistor to 25 mA is
detected if the digital input comparator is enabled as described in Current Input Loop
Powered section with a trip point of AVDD/2. The debounce time of this error detect is
user-programmable via the DEBOUNCE_TIME bits in the DIN_CONFIGx registers.
Rev. A | Page 61 of 66
Reset
0x0
Access
R/W1C
0x0
R/W1C
0x0
R/W1C
AD74412R
Bits
0
Bit Name
VI_ERR_A
Data Sheet
Description
Voltage or current error detected on Channel A. This bit is interpreted differently
depending on which of the following function selected in the CH_FUNC_SETUPA register:
Voltage output: short-circuit error. The error condition is debounced for 2 ms before the
status bit is set.
Current output: open circuit error. The error condition is debounced for 2 ms before the
status bit is set.
Current input, loop powered: short-circuit error. A short to ground is detected if the
digital input comparator is enabled as described in Current Input Loop Powered section
with a trip point of AVDD/2 and the digital output is inverted via the INV_DIN_COMP_OUT
bit in the DIN_CONFIGx registers. The debounce time of this error detect is userprogrammable via the DEBOUNCE_TIME bits in the DIN_CONFIGx registers.
Current input, externally powered: short-circuit error. A current source >25 mA is
detected if the digital input comparator is enabled as described in Current Input Loop
Powered section with a trip point of AVDD/2. The debounce time of this error detect is
user-programmable via the DEBOUNCE_TIME bits in the DIN_CONFIGx registers.
Reset
0x0
Access
R/W1C
LIVE STATUS REGISTER
Address: 0x2F, Reset: 0x0000, Name: LIVE_STATUS
This register contains the live status of some of the status bits. The bits in this register are not latched and directly reflect the status bits.
Table 46. Bit Descriptions for LIVE_STATUS
Bits
15
14
Bit Name
RESERVED
ADC_DATA_RDY
13
[12:10]
ADC_BUSY
ADC_CH_CURR
9
8
7
6
5
4
ALDO1V8_STATUS
DVCC_STATUS
AVDD_STATUS
ALDO5V_STATUS
CHARGE_PUMP_STATUS
HI_TEMP_STATUS
3
2
1
0
VI_ERR_CURR_D
VI_ERR_CURR_C
VI_ERR_CURR_B
VI_ERR_CURR_A
Description
Reserved.
ADC data ready. The ADC_DATA_RDY bit asserts when a conversion cycle has
completed. The bit stays asserted until a user writes 1 to clear the bit. In single
conversion mode, the ADC_RDY pin follows the ADC_DATA_RDY bit and only
deasserts when the ADC_DATA_RDY bit is cleared. In continuous conversion
mode, the ADC_RDY pin returns high after 24 µs.
ADC busy status bit.
The channel and diagnostics currently being converted by the ADC.
000: Channel A.
001: Channel B.
010: Channel C.
011: Channel D.
100: Diagnostics 0.
101: Diagnostics 1.
110: Diagnostics 2.
111: Diagnostics 3.
Live status of the ALDO1V8_ERR bit.
Live status of the DVCC_ERR bit.
Live status of the AVDD_ERR bit.
Live status of the ALDO5V_ERR bit.
Live status of the CHARGE_PUMP_ERR bit.
Live status of the HI_TEMP_ERR bit. If the die temperature is typically at or above
115°C, the HI_TEMP_STATUS bit is asserted.
Live status of the VI_ERR_D bit.
Live status of the VI_ERR_C bit.
Live status of the VI_ERR_B bit.
Live status of the VI_ERR_A bit.
Rev. A | Page 62 of 66
Reset
0x0
0x0
Access
R
R/W1C
0x0
0x0
R
R
0x0
0x0
0x0
0x0
0x0
0x0
R
R
R
R
R
R
0x0
0x0
0x0
0x0
R
R
R
R
Data Sheet
AD74412R
ALERT MASK REGISTER
Address: 0x3C, Reset: 0x0000, Name: ALERT_MASK
This register masks the alert status bits, outlined in the ALERT_STATUS register, from activating the ALERT pin. The position of mask
bits in this register line up with the corresponding status bits in the ALERT_STATUS register.
Table 47. Bit Descriptions for ALERT_MASK
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
RESERVED
CAL_MEM_ERR_MASK
SPI_CRC_ERR_MASK
SPI_SCLK_CNT_ERR_MASK
ADC_SAT_ERR_MASK
ADC_CONV_ERR_MASK
ALDO1V8_ERR_MASK
DVCC_ERR_MASK
AVDD_ERR_MASK
ALDO5V_ERR_MASK
CHARGE_PUMP_ERR_MASK
HI_TEMP_ERR_MASK
VI_ERR_MASK_D
VI_ERR_MASK_C
VI_ERR_MASK_B
VI_ERR_MASK_A
Description
Reserved.
Mask bit for the CAL_MEM_ERR bit.
Mask bit for the SPI_CRC_ERR bit.
Mask bit for the SPI_SCLK_CNT_ERR bit.
Mask bit for the ADC_SAT_ERR bit.
Mask bit for the ADC_CONV_ERR bit.
Mask bit for the ALDO1V8_ERR bit.
Mask bit for the DVCC_ERR bit.
Mask bit for the AVDD_ERR bit.
Mask bit for the ALDO5V_ERR bit.
Mask bit for the CHARGE_PUMP_ERR bit.
Mask bit for the HI_TEMP_ERR bit.
Mask bit for the VI_ERR_D bit.
Mask bit for the VI_ERR_C bit.
Mask bit for the VI_ERR_B bit.
Mask bit for the VI_ERR_A bit.
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
READBACK SELECT REGISTER
Address: 0x41, Reset: 0x0000, Name: READ_SELECT
This register selects the address of the register required to be read back and determines the contents of the SPI readback frame.
Table 48. Bit Descriptions for READ_SELECT
Bits
[15:10]
9
Bit Name
RESERVED
AUTO_RD_EN
8
SPI_RD_RET_INFO
[7:0]
READBACK_ADDR
Description
Reserved.
Automatic read enabled. When this bit is set to 0, a read is performed by first writing the
readback address to the READ_SELECT register, followed by a frame where the read data is
returned on the SDO only for the next SPI transaction, which is called a two-stage read.
When this bit is set to 1, read data is returned on the SDO for every SPI access. The
location read is determined by the current value of the READBACK_ADDR bits, Bits[7:0].
Repeated reads of a register location can execute without needing a write to the READ_
SELECT register between each read. For streaming mode, the address starts at the value
of the READBACK_ADDR bits, Bits[7:0] and increments until the read stops. At the start of
the next burst read, the address reverts to the value of the READBACK_ADDR bits, Bits[7:0].
Repeated burst reads can execute without needing a write to the READ_SELECT register
between each burst read.
Determines the content of the MSBs in the SPI read frame. When this bit is set to 0, the
READBACK_ADDR is returned in bits, Bits[30:24] (the MSB is not shown) of any
subsequent SPI read. When this bit is set to 1, the ADC_RDY bit, alert flags, and the four
digital input outputs are returned in Bits[30:24] of any subsequent SPI read.
Bits[D7:D0] contains the register address to be read.
Rev. A | Page 63 of 66
Reset
0x0
0x0
Access
R
R/W
0x0
R/W
0x0
R/W
AD74412R
Data Sheet
80 SPS ADC CONVERSION CONTROL REGISTER
Address: 0x42, Reset: 0x0000, Name: ADC_CONV_CTRL_80SPS
This register and the ADC_CONV_CTRL register both determine what the ADC is converting. When the ADC is enabled via this
register, the ADC only converts Channel A to Channel D.
When enabling a sequence, ensure that any previous sequence has completed and wait until the LIVE_STATUS register, ADC_BUSY bit is 0.
Table 49. Bit Descriptions for ADC_CONV_CTRL_80SPS
Bits
[15:2]
[1:0]
Bit Name
RESERVED
CONV_SEQ_80SPS
Description
Reserved.
Selects single or continuous mode.
00: stops continuous conversions and either leaves the ADC powered up or powers up
the ADC. If exiting ADC power-down, it takes approximately 100 μs to power up the ADC.
The ADC_BUSY bit is set to 1 while the ADC is powering up. If using the CONV_SEQ bits
to exit ADC power-down, wait for the ADC to power up before writing to these bits to
start a single or continuous sequence.
01: starts single sequence conversion and performs a single conversion on each enabled
channel and diagnostic. These bits do not clear when a conversion completes. To enable
a subsequent conversion, the user must repeat the write to enable the conversion.
If the ADC is powered down, writing 01 to the CONV_SEQ bits automatically powers it up. The
user must repeat the write to enable the conversion.
10: starts continuous conversions. The ADC sequences continuously through the
enabled channels and diagnostics. The enabled channels and diagnostics cannot be
modified if a continuous sequence is in progress. To modify these channels, stop the
sequence, modify the channels and diagnostics, and start the sequence again.
If the ADC is powered down, writing a 01 to the CONV_SEQ bits automatically powers up
the ADC. The user must wait 100 μs before starting conversions. If moving from
continuous conversion mode to single conversion mode, enter idle mode first.
11: stops continuous conversions and powers down the ADC.
Reset
0x0
0x0
Access
R
R/W
Reset
0x0
0x0
Access
R
R/W
THERMAL RESET ENABLE REGISTER
Address: 0x43, Reset: 0x0000, Name: THERM_RST
Table 50. Bit Descriptions for THERM_RST
Bits
[15:1]
0
Bit Name
RESERVED
EN_THERM_RST
Description
Reserved.
Set to 1 to enable thermal reset functionality. If the die temperature reaches typically
140°C, a thermal reset event triggers a digital reset. This reset event is detected via a
change in the ALERT pin and the RESET_OCCURRED flag.
Rev. A | Page 64 of 66
Data Sheet
AD74412R
COMMAND REGISTER
Address: 0x44, Reset: 0x0000, Name: CMD_KEY
Specific key codes are written to this register to execute the functions shown in Table 51. Using specific keys to initiate actions such as
reset, LDAC, or clear provides extra system robustness as using these keys reduce the probability of initiating these tasks in error.
Table 51. Bit Descriptions for CMD_KEY
Bits
[15:0]
Bit Name
CMD_KEY
Description
Enter a key to execute a command.
0x0000: NOP.
0x15FA: Software Reset Key1. To trigger a software reset, write this key followed by Software
Reset Key2. The SPI writes must be back to back.
0xAF51: Software Reset Key2. To trigger a software reset, write Software Reset Key1 followed by
this key. The SPI writes must be back to back.
0x953A: LDAC key. A DAC update is triggered on all channels when this key is entered, which is
equivalent to asserting the LDAC pin.
0x73D1: DAC clear key. When entering this key, the DAC_CLR_CODEx registers for a channel are
sent to the DAC, provided that the clear function is enabled in the OUTPUT_CONFIGx registers.
Note that if slewing is enabled when the channel is cleared, the output slews at the programmed
rate to the clear code.
Reset
0x0
SCRATCH OR SPARE REGISTER
Address: 0x45, Reset: 0x0000, Name: SCRATCH
Table 52. Bit Descriptions for SCRATCH
Bits
[15:0]
Bit Name
SCRATCH_BITS
Description
Scratch or spare register field.
Reset
0x0
Access
R/W
SILICON REVISION REGISTER
Address: 0x46, Reset: 0x0003, Name: SILICON_REV
Table 53. Bit Descriptions for SILICON_REV
Bits
[15:8]
[7:0]
Bit Name
RESERVED
SILICON_REV_ID
Description
Reserved.
Silicon revision identification.
Reset
0x0
0x8
Rev. A | Page 65 of 66
Access
R
R
Access
W
AD74412R
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
49
64
1
48
0.50
BSC
7.70
7.60 SQ
7.50
EXPOSED
PAD
33
TOP VIEW
0.80
0.75
0.70
SIDE VIEW
PKG-004396
SEATING
PLANE
0.45
0.40
0.35
16
32
17
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.20 MIN
7.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WMMD
09-25-2018-A
PIN 1
INDICATOR
AREA
9.10
9.00 SQ
8.90
Figure 54. 64-Lead Lead Frame Chip Scale Package [LFCSP]
9 mm × 9 mm Body and 0.75 mm Package Height
(CP-64-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
AD74412RBCPZ
AD74412RBCPZ-REEL
AD74412RBCPZ-RL7
EV-AD74412RSDZ
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP]
64-Lead Lead Frame Chip Scale Package [LFCSP]
64-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
When ordering the EV-AD74412RSDZ, the USB interface board, EVAL-SDP-CS1Z, must be ordered separately.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D21274-0-9/19(A)
Rev. A | Page 66 of 66
Package Option
CP-64-15
CP-64-15
CP-64-15
工商网监
湘ICP备2023018690号
