Differential Input, 555 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7452
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Specified for VDD of 3 V and 5 V
Low power at max throughput rate
3.3 mW max at 555 kSPS with 3 V supplies
7.25 mW max at 555 kSPS with 5 V supplies
Fully differential analog input
Wide input bandwidth
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Power-down mode: 1 μA max
8-lead SOT-23 package
VDD
VIN+
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
VIN–
VREF
SCLK
SDATA
AD7452
CONTROL LOGIC
CS
03154-A-001
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
Motor control
GND
Figure 1.
The SAR architecture of this part ensures that there are no
pipeline delays.
GENERAL DESCRIPTION
1
The AD7452 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
fully differential analog input. This part operates from a single
3 V or 5 V power supply and features throughput rates up to
555 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies up to 3.5 MHz. The reference voltage is applied
externally to the VREF pin and can be varied from 100 mV to
3.5 V depending on the power supply and what suits the
application. The value of the reference voltage determines the
common-mode voltage range of the part. With this truly
differential input structure and variable reference input, the
user can select a variety of input ranges and bias points.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled
on the falling edge of CS, and the conversion is also initiated at
this point.
1
The AD7452 uses advanced design techniques to achieve very
low power dissipation.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
8.
Operation with Either 3 V or 5 V Power Supplies.
High Throughput with Low Power Consumption. With a
3 V supply, the AD7452 offers 3.3 mW max power
consumption for 555 kSPS throughput.
Fully Differential Analog Input.
Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. This part also
features a shutdown mode to maximize power efficiency at
lower throughput rates.
Variable Voltage Reference Input.
No Pipeline Delay.
Accurate Control of the Sampling Instant via a CS Input
and Once-Off Conversion Control.
ENOB > 8 Bits Typically with 100 mV Reference.
Protected by U.S. Patent Number 6,681,332.
Rev. C
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Technical Support
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AD7452
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Connection Diagram ................................................... 14
Applications ....................................................................................... 1
Analog Input ............................................................................... 14
General Description ......................................................................... 1
Driving Differential Inputs ....................................................... 16
Functional Block Diagram .............................................................. 1
Digital Inputs .............................................................................. 18
Product Highlights ........................................................................... 1
Reference ..................................................................................... 18
Revision History ............................................................................... 2
Single-Ended Operation ............................................................ 18
Specifications..................................................................................... 3
Serial Interface ............................................................................ 19
Timing Specifications .................................................................. 5
Modes of Operation ....................................................................... 20
Absolute Maximum Ratings............................................................ 6
Normal Mode.............................................................................. 20
ESD Caution .................................................................................. 6
Power-Down Mode .................................................................... 20
Pin Configuration and Function Descriptions ............................. 7
Power-Up Time .......................................................................... 21
Terminology ...................................................................................... 8
Power vs. Throughput Rate ....................................................... 22
Typical Performance Characteristics ........................................... 10
Application Hints ....................................................................... 22
Circuit Information ........................................................................ 13
Evaluating the AD7452’s Performance .................................... 23
Converter Operation .................................................................. 13
Outline Dimensions ....................................................................... 24
ADC Transfer Function ............................................................. 13
Ordering Guide .......................................................................... 24
REVISION HISTORY
7/15—Rev. B to Rev. C
Changed FSCLK to fSCLK .................................................... Throughout
Changes to Figure 29 ...................................................................... 16
Changes to Power vs. Throughput Rate Section ........................ 22
Deleted Microprocessor and DSP Interfacing Section and
AD7452 to ADSP-21xx Section .................................................... 22
Deleted Figure 40, Figure 41, and Figure 42; Renumbered
Sequentially ..................................................................................... 23
Deleted AD7452 to TMS320C5x/C54x Section and AD7452 to
DSP56xxx Section........................................................................... 23
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
2/04—Rev. A to Rev. B
Added Patent Note ............................................................................1
2/04—Rev. 0 to Rev. A
Updated Formatting ........................................................... Universal
Changes to Applications section .....................................................1
Changes to General Description .....................................................1
Changes to Specifications .................................................................4
Changes to Timing Specifications ...................................................5
Changes to Timing Example ......................................................... 19
9/03—Revision 0: Initial Version
Rev. C | Page 2 of 24
Data Sheet
AD7452
SPECIFICATIONS
VDD = 2.7 V to 3.6 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V;
VCM1 = VREF; TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)3
Total Harmonic Distortion (THD)3
Peak Harmonic or Spurious Noise3
Intermodulation Distortion (IMD)3
Second-Order Terms
Third-Order Terms
Aperture Delay3
Aperture Jitter3
Full Power Bandwidth3, 4
DC ACCURACY
Resolution
Integral Nonlinearity (INL) 3
Differential Nonlinearity (DNL) 3
Zero-Code Error3
Positive Gain Error3
Negative Gain Error3
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
VIN+
VIN–
DC Leakage Current
Input Capacitance
REFERENCE INPUT
VREF Input Voltage
DC Leakage Current
VREF Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN 8
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance8
Output Coding
B Version2
Unit
70
–76
–74
–76
–74
dB min
dB max
dB max
dB max
dB max
–89
–89
5
50
20
2.5
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
12
±1
± 0.95
±6
±2
±2
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
2 × VREF5
VIN+ – VIN–
V
VCM = VREF
VCM = VREF
VCM1 ± VREF/2
VCM1 ± VREF/2
±1
30/10
V
V
µA max
pF typ
2.56
V
2.07
V
±1
10/30
µA max
pF typ
2.4
0.8
±1
10
V min
V max
µA max
pF max
2.8
2.4
0.4
±1
10
Twos Complement
V min
V min
V max
µA max
pF max
Test Conditions/Comments
fIN = 100 kHz
VDD = 4.75 V to 5.25 V, –86 dB typ
VDD = 2.7 V to 3.6 V, –84 dB typ
VDD = 4.75 V to 5.25 V, –86 dB typ
VDD = 2.7 V to 3.6 V, –84 dB typ
fa = 90 kHz, fb = 110 kHz
@ –3 dB
@ –0.1 dB
Guaranteed no missed codes to 12 bits
When in track/hold
VDD = 4.75 V to 5.25 V (±1% tolerance for
specified performance)
VDD = 2.7 V to 3.6 V (±1% tolerance for
specified performance)
When in track/hold
Typically 10 nA, VIN = 0 V or VDD
VDD = 4.75 V to 5.25 V, ISOURCE = 200 µA
VDD = 2.7 V to 3.6 V, ISOURCE = 200 µA
ISINK = 200 µA
Rev. C | Page 3 of 24
AD7452
Parameter
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time3
Throughput Rate
POWER REQUIREMENTS
VDD
IDD9, 10
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Full Power-Down
Data Sheet
Test Conditions/Comments
B Version2
Unit
1.6 µs with a 10 MHz SCLK
Sine wave input
Step input
16
200
290
555
SCLK cycles
ns max
ns max
kSPS max
Range: 3 V + 20%/–10%;
5 V ± 5%
2.7/5.25
V min/V max
SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK on or off
0.5
1.5
1.2
1
mA typ
mA max
mA max
µA max
VDD = 5 V, 1.55 mW typ for 100 kSPS9
VDD = 3 V, 0.64 mW typ for 100 kSPS9
VDD = 5 V, SCLK on or off
VDD = 3 V, SCLK on or off
7.25
3.3
5
3
mW max
mW max
µW max
µW max
1
Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 23 and Figure 24.
Temperature ranges as follows: B Version: –40°C to +85°C.
3
See Terminology section.
4
Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the
converter.
5
Because the input spans of VIN+ and VIN– are both VREF and are 180° out of phase, the differential voltage is 2 × VREF.
6
The AD7452 is functional with a reference input from 100 mV; for VDD = 5 V, the reference can range up to 3.5 V.
7
The AD7452 is functional with a reference input from 100 mV; for VDD = 3 V, the reference can range up to 2.2 V.
8
Guaranteed by characterization.
9
See Power VS. Throughput Rate section.
10
Measured with a midscale dc input.
2
Rev. C | Page 4 of 24
Data Sheet
AD7452
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a 1.6 V voltage
level. See Figure 2 and the Serial Interface section.
VDD = 2.7 V to 3.6 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V;
VCM1 = VREF; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
fSCLK2
tCONVERT
tQUIET
t1
t2
t33
t43
t5
t6
t7
t84
tPOWER-UP5
Limit at TMIN, TMAX
10
10
16 × tSCLK
1.6
60
10
10
20
40
0.4 tSCLK
0.4 tSCLK
10
10
35
1
Unit
kHz min
MHz max
Description
tSCLK = 1/fSCLK
μs max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μs max
Minimum quiet time between the end of a serial read and the next falling edge of CS
Minimum CS pulse width
CS falling edge to SCLK falling edge setup time
Delay from CS falling edge until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SCLK edge to data valid hold time
SCLK falling edge to SDATA three-state enabled
SCLK falling edge to SDATA three-state enabled
Power-up time from full power-down
1
Common-mode voltage.
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, or 0.4 V or 2.0 V for VDD = 3 V.
4
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish
time of the part and is independent of the bus loading.
5
See Power-Up Time section.
2
t1
CS
1
SCLK
2
3
t3
SDATA
tCONVERT
t5
4
5
0
0
4 LEADING ZEROS
0
14
DB11
DB10
15
t6
t7
t4
0
B
13
DB2
16
t8
DB1
DB0
tQUIET
THREE-STATE
Figure 2. Serial Interface Timing Diagram
Rev. C | Page 5 of 24
03154-A-002
t2
AD7452
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
1.6mA
IOL
Table 3.
1
Rating
–0.3 V to +7 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to +7 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
±10 mA
–40°C to +85°C
–65°C to +150°C
150°C
211.5°C/W
91.99°C/W
TO OUTPUT
PIN
1.6V
CL
25pF
200µA
IOH
03154-A-003
Parameter
VDD to GND
VIN+ to GND
VIN– to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
VREF to GND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
ESD
Figure 3. Load Circuit for Digital Output Timing Specifications
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
215°C
220°C
1 kV
Transient currents of up to 100 mA will not cause SCR latch-up.
Rev. C | Page 6 of 24
Data Sheet
AD7452
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
8
AD7452
VREF
VIN+
TOP VIEW
6 VIN–
(Not to Scale)
CS 4
5 GND
7
SDATA 3
03154-A-004
VDD 1
SCLK 2
Figure 4. 8-Lead SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
Mnemonic
VREF
VIN+
VIN–
GND
CS
SDATA
SCLK
VDD
Function
Reference Input for the AD7452. An external reference must be applied to this input. For a 5 V power supply, the reference is
2.5 V (± 1%) for specified performance. For a 3 V power supply, the reference is 2 V (± 1%) for specified performance. This pin
should be decoupled to GND with a capacitor of at least 0.1 µF. See the Reference section for more details.
Positive Terminal for Differential Analog Input.
Negative Terminal for Differential Analog Input.
Analog Ground. Ground reference point for all circuitry on the AD7452. All analog input signals and any external reference
signal should be referred to this GND voltage.
Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7452 and framing
the serial data transfer.
Serial Data. Logic output. The conversion result from the AD7452 is provided on this output as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of
conversion data, which are provided MSB first. The output coding is twos complement.
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the
clock source for the conversion process.
Power Supply Input. VDD is 3 V (+20%/–10%) or 5 V (± 5%). This supply should be decoupled to GND with a 0.1 µF capacitor
and a 10 µF tantalum capacitor in parallel.
Rev. C | Page 7 of 24
AD7452
Data Sheet
TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio
The measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to
half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of
harmonics to the fundamental. For the AD7452, it is defined as
THD(dB) = 20 log
V 22 +V 32 +V 42 +V 52 +V 6 2
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second to the sixth
harmonics.
The AD7452 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dB.
Aperture Delay
The amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
The sample-to-sample variation in the effective point in time at
which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is the input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 0.1 dB or 3 dB for a full-scale input.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it is a noise
peak.
Common-Mode Rejection Ratio (CMRR)
This is the ratio of the power in the ADC output at full-scale
frequency, f, to the power of a 100 mV p-p sine wave applied to
the common-mode voltage of VIN+ and VIN– of frequency fS
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa − fb),
while the third-order terms include (2fa + fb), (2fa − fb), (fa +
2fb) and (fa − 2fb).
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
CMRR(dB) = 10 log(Pf/PfS)
Pf is the power at the frequency f in the ADC output; PfS is the
power at frequency fS in the ADC output.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Zero Code Error
The deviation of the midscale code transition (111…111 to
000...000) from the ideal VIN+ – VIN– (that is, 0 LSB)
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal VIN+ – VIN– (that is, VREF – 1 LSB), after
the zero code error has been adjusted out.
Rev. C | Page 8 of 24
Data Sheet
AD7452
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal VIN+ – VIN– (that is, –VREF + 1 LSB),
after the zero code error has been adjusted out.
Track-and-Hold Acquisition Time
The minimum time required for the track-and-hold amplifier
to remain in track mode for its output to reach and settle to
within 0.5 LSB of the applied input signal.
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the
ADC VDD supply of frequency fS. The frequency of this input
varies from 1 kHz to 1 MHz.
PSRR(dB) = 10log(Pf/PfS)
Pf is the power at frequency f in the ADC output; Pfs is the
power at frequency fS in the ADC output.
Rev. C | Page 9 of 24
AD7452
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, fS = 555 kSPS, fSCLK = 10 MHz, unless otherwise noted.
0
75
8192 POINT FFT
fSAMPLE = 555kSPS
fIN = 100kSPS
SINAD = 71.7dB
THD = –82dB
SFDR = –83dB
VDD = 4.75V
VDD = 5.25V
–20
70
–40
VDD = 2.7V
SNR (dB)
65
–60
–80
–100
03154-A-005
60
55
10
–120
–140
0
277
100
03154-A-008
SINAD (dB)
VDD = 3.6V
100
200
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 8. Dynamic Performance with VDD = 5 V
0
1.0
–10
0.8
–20
0.6
–30
0.4
DNL ERROR (LSB)
–40
–50
–60
VDD = 3V
–70
0.2
0
–0.2
–0.4
–0.6
03154-A-006
–80
–90
VDD = 5V
–100
10
–0.8
–1.0
0
10000
100
1000
FREQUENCY (kHz)
03154-A-009
CMRR (dB)
Figure 5. SINAD vs. Analog Input Frequency for Various Supply Voltages
277
1024
2048
3072
4096
CODE
Figure 6. CMRR vs. Frequency for VDD = 5 V and 3 V
Figure 9. Typical DNL for VDD = 5 V
1.0
0
100mV p-p SINE WAVE ON VDD
NO DECOUPLING ON VDD
–20
0.8
0.6
INL ERROR (LSB)
0.4
PSRR (dB)
–40
–60
VDD= 3V
VDD= 5V
–80
0.2
0
–0.2
–0.4
03154-A-007
–120
0
100
200 300 400 500 600 700 800
SUPPLY RIPPLE FREQUENCY (kHz)
03154-A-010
–0.6
–100
–0.8
–1.0
0
900 1000
1024
2048
3072
CODE
Figure 7. PSRR vs. Supply Ripple Frequency without Supply Decoupling
Rev. C | Page 10 of 24
Figure 10. Typical INL for VDD = 5 V
4096
Data Sheet
AD7452
3.0
2.0
2.5
1.5
1.5
1.0
POSITIVE DNL
0.5
–0.5
03154-A-011
0
NEGATIVE DNL
–1.0
0
0.5
1.0
1.5
2.0
VREF (V)
2.5
3.0
1.0
POSITIVE INL
0.5
0
–0.5
NEGATIVE INL
03154-A-014
CHANGE IN INL (LSB)
CHANGE IN DNL (LSB)
2.0
–1.5
–2.0
0
3.5
7
1.5
1.0
POSITIVE DNL
0.5
0
NEGATIVE DNL
–1.0
1.0
2.2
2.5
1.5
2.2
2.0
6
VDD = 5V
5
4
3
VDD = 3V
2
1
0
2.5
0
0.5
1.0
VREF (V)
Figure 12. Change in DNL vs. VREF for VDD = 3 V
1.5
2.0
VREF (V)
2.5
3.0
3.5
Figure 15. Change in Zero-Code Error vs. Reference Voltage VDD = 5 V and 3 V
5
12.0
11.5
3
11.0
2
1
POSITIVE INL
0
NEGATIVE INL
–1
–2
–3
–4
–5
0
0.5
1.0
1.5
2.0
VREF (V)
2.5
3.0
VDD = 3V
VDD = 5V
10.5
10.0
9.5
9.0
8.5
8.0
03154-A-016
EFFECTIVE NUMBER OF BITS
4
03154-A-013
CHANGE IN INL (LSB)
2.0
03154-A-015
ZERO-CODE ERROR (LSB)
2.0
03154-A-012
CHANGE IN DNL (LSB)
8
0.5
1.5
Figure 14. Change in INL vs. VREF for VDD = 3 V
2.5
0
1.0
VREF (V)
Figure 11. Change in DNL vs. VREF for VDD = 5 V
–0.5
0.5
7.5
7.0
3.5
0
Figure 13. Change in INL vs. VREF for VDD = 5 V
0.5
1.0
1.5
2.0
VREF (V)
2.5
3.0
3.5
Figure 16. Change in ENOB vs. Reference Voltage VDD = 5 V and 3 V
Rev. C | Page 11 of 24
AD7452
Data Sheet
10,000
9,000
VIN+ = VIN–
10,000 CONVERSIONS
fS = 555kSPS
10,000
CODES
8,000
7,000
6,000
5,000
4,000
3,000
03154-A-017
2,000
1,000
0
2044
2045
2046
2047
2048
2049
CODE
Figure 17. Histogram of 10,000 Conversions of a DC Input with VDD = 5 V
Rev. C | Page 12 of 24
Data Sheet
AD7452
CIRCUIT INFORMATION
When operated with a 5 V supply, the maximum reference that
can be applied is 3.5 V. When operated with a 3 V supply, the
maximum reference that can be applied is 2.2 V (see the
Reference section).
The AD7452 has an on-chip differential track-and-hold
amplifier, a successive approximation (SAR) ADC, and a serial
interface, housed in an 8-lead SOT-23 package. The serial clock
input accesses data from the part and provides the clock source
for the successive approximation ADC. The AD7452 features a
power-down option for reduced power consumption between
conversions. The power-down feature is implemented across
the standard serial interface as described in the Modes of
Operation section.
When the ADC starts a conversion (Figure 19), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC’s output code. The output impedances of the
sources driving the VIN+ and the VIN– pins must be matched;
otherwise, the two inputs will have different settling times,
resulting in errors.
CAPACITIVE
DAC
CS
B
VIN+
A
SW1
A
SW2
CONTROL
LOGIC
SW3
VIN–
CS
B
VREF
COMPARATOR
CAPACITIVE
DAC
Figure 19. ADC Conversion Phase
The AD7452 is a successive approximation ADC based around
two capacitive DACs. Figure 18 and Figure 19 show simplified
schematics of the ADC in the acquisition and conversion phase,
respectively. The ADC is comprised of control logic, an SAR,
and two capacitive DACs. In Figure 18 (acquisition phase), SW3
is closed and SW1 and SW2 are in Position A, the comparator is
held in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
ADC TRANSFER FUNCTION
The output coding for the AD7452 is twos complement. The
designed code transitions occur at successive LSB values
(that is, 1 LSB, 2 LSBs, and so on). The LSB size is 2 ×
VREF/4096. The ideal transfer characteristic of the AD7452 is
shown in Figure 20.
A
SW1
A
B
SW2
SW3
VIN–
VREF
CONTROL
LOGIC
COMPARATOR
CAPACITIVE
DAC
000...001
000...000
111...111
100...010
100...001
100...000
CS
03154-A-018
VIN+
CS
B
011...111
011...110
ADC CODE
CAPACITIVE
DAC
1LSB = 2 × VREF/4096
–VREF 1LSB
+ VREF – 1LSB
0 LSB
ANALOG INPUT
(VIN+ –VIN–)
Figure 20. Ideal Transfer Characteristic
Figure 18. ADC Acquisition Phase
Rev. C | Page 13 of 24
03154-A-020
CONVERTER OPERATION
03154-A-019
The AD7452 is a 12-bit, low power, single-supply, successive
approximation analog-to-digital converter (ADC). It can
operate with a 5 V or 3 V power supply, and is capable of
throughput rates up to 555 kSPS when supplied with a 10 MHz
SCLK. It requires an external reference to be applied to the VREF
pin, with the value of the reference chosen depending on the
power supply and what suits the application.
AD7452
Data Sheet
TYPICAL CONNECTION DIAGRAM
Figure 21 shows a typical connection diagram for the AD7452
for both 5 V and 3 V supplies. In this setup, the GND pin is
connected to the analog ground plane of the system. The VREF
pin is connected to either a 2.5 V or a 2 V decoupled reference
source, depending on the power supply, to set up the analog
input range. The common-mode voltage has to be set up
externally and is the value on which the two inputs are centered.
The conversion result is output in a 16-bit word with four
leading zeros followed by the MSB of the 12-bit result. For more
details on driving the differential inputs and setting up the
common mode, refer to the Driving Differential Inputs section.
10F
3V/5V
SUPPLY
For ease of use, the common mode can be set up to equal VREF,
resulting in the differential signal being ±VREF centered on VREF.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise-free signal of amplitude, –VREF to
+VREF, corresponding to the digital codes of 0 to 4096.
SERIAL
INTERFACE
VDD
VIN+
SCLK
AD7452
VREF
p-p
CM*
SDATA
4.5
C/P
CS
VIN–
4.0
GND
VREF
03154-A-021
2V/2.5V
VREF
0.1F
*CM IS THE COMMON-MODE VOLTAGE.
Figure 21. Typical Connection Diagram
ANALOG INPUT
3.0
2.5
COMMON-MODE RANGE
2.0
1.5
1.75V
1.0
0.5
The analog input of the AD7452 is fully differential. Differential
signals have a number of benefits over single-ended signals,
including noise immunity based on the device’s common-mode
rejection, improvements in distortion performance, doubling of
the device’s available dynamic range, and flexibility in input
ranges and bias points. Figure 22 defines the fully differential
analog input of the AD7452.
VIN+
VIN–
03154-A-022
AD7452
VREF
p-p
0
0
Figure 22. Differential Input Definition
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN– pins (that is,
VIN+ – VIN–). VIN+ and VIN– are simultaneously driven by two
signals, each of amplitude VREF, that are 180° out of phase. The
amplitude of the differential signal is therefore –VREF to +VREF
peak-to-peak (that is, 2 ×VREF). This is true regardless of the
common mode (CM).
Rev. C | Page 14 of 24
0.5
1.0
1.5
2.0
VREF (V)
2.5
3.0
3.5
Figure 23. Input Common-Mode Range vs. VREF
(VDD = 5 V and VREF (Max) = 3.5 V)
2.5
2V
COMMON-MODE VOLTAGE (V)
VREF
p-p
COMMONMODE
VOLTAGE
3.25V
3.5
03154-A-023
CM*
2.0
1.5
COMMON-MODE RANGE
1.0
1V
0.5
03154-A-024
VREF
p-p
Figure 23 and Figure 24 show how the common-mode range
typically varies with VREF for both 5 V and 3 V power supplies.
The common mode must be in this range to guarantee the
functionality of the AD7452.
COMMON-MODE VOLTAGE (V)
0.1F
The common mode is the average of the two signals, that is,
(VIN+ + VIN–)/2, and is therefore the voltage upon which the two
inputs are centered. This results in the span of each input being
CM ± VREF/2. This voltage has to be set up externally, and its
range varies with VREF. As the value of VREF increases, the
common-mode range decreases. When driving the inputs with
an amplifier, the actual common-mode range is determined by
the amplifier’s output voltage swing.
0
0
0.25
0.50
0.75
1.00
1.25
VREF (V)
1.50
1.75
Figure 24. Input Common-Mode Range vs. VREF
(VDD = 3 V and VREF (Max) = 2 V)
2.00
Data Sheet
AD7452
Figure 25 shows examples of the inputs to VIN+ and VIN– for
different values of VREF for VDD = 5 V. It also gives the maximum
and minimum common-mode voltages for each reference value
according to Figure 23.
REFERENCE = 2V
COMMON-MODE (CM)
CMMIN = 1V
CMMAX = 4V
VIN–
2V p-p
VIN+
For ac applications, removing high frequency components from
the analog input signal through the use of an RC low-pass filter
on the relevant analog input pins is recommended. In applications where harmonic distortion and signal-to-noise ratio are
critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application.
REFERENCE = 2.5V
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases, and performance degrades.
Figure 27 shows a graph of the THD versus the analog input
signal frequency for different source impedances for VDD = 5 V.
Figure 25. Examples of the Analog Inputs to VIN+ and VIN– for
Different Values of VREF for VDD = 5 V
Analog Input Structure
Figure 26 shows the equivalent circuit of the analog input
structure of the AD7452. The four diodes provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signals never exceed the supply rails by
more than 300 mV. This causes these diodes to become
forward-biased and start conducting into the substrate. These
diodes can conduct up to 10 mA without causing irreversible
damage to the part. The capacitors, C1 in Figure 26, are
typically 4 pF and can primarily be attributed to pin
capacitance. The resistors are lumped components made up of
the on resistance of the switches. The value of these resistors is
typically about 100 Ω. The capacitors C2 are the ADC’s
sampling capacitors and have a typical capacitance of 16 pF.
0
TA = 25°C
VDD = 5V
–20
–40
RIN = 1kΩ
RIN = 510Ω
–60
–80
RIN = 300Ω
RIN = 10Ω
–100
10
277
100
INPUT FREQUENCY (kHz)
VDD
03154-A-027
2.5V p-p
VIN+
THD (dB)
VIN–
03154-A-025
COMMON-MODE (CM)
CMMIN = 1.25V
CMMAX = 3.75V
Figure 27. THD vs. Analog Input Frequency for Various
Source Impedances for VDD = 5 V
D
R1
VIN+
C1
C2
Figure 28 shows a graph of the THD vs. the analog input
frequency for VDD of 5 V ± 5% and 3 V + 20%/–10%, while
sampling at 555 kSPS with an SCLK of 10 MHz. In this case, the
source impedance is 10 Ω.
D
–50
VDD
TA = 25°C
–55
C2
–60
–65
THD (dB)
D
03154-A-026
C1
R1
–70
–75
Figure 26. Equivalent Analog Input Circuit
Conversion Phase—Switches Open; Track Phase—Switches Closed
VDD = 2.7V
VDD = 3.6V
–80
–85
–90
10
VDD = 4.75V
100
VDD = 5.25V
03154-A-028
D
VIN–
277
INPUT FREQUENCY (kHz)
Figure 28. THD vs. Analog Input Frequency for 3 V and 5 V Supply Voltages
Rev. C | Page 15 of 24
AD7452
Data Sheet
DRIVING DIFFERENTIAL INPUTS
a pair of series resistors to minimize the effects of switched
capacitance on the front end of the ADCs. The RC low-pass
filter on each analog input is recommended in ac applications to
remove high frequency components of the analog input. The
architecture of the AD8138 results in outputs that are very
highly balanced over a wide frequency range without requiring
tightly matched external components. If the analog input source
being used has zero impedance, all four resistors (RG1, RG2, RF1,
RF2) should be the same. If, for example, the source has a 50 Ω
impedance and a 50 Ω termination, the value of RG2 should be
increased by 25 Ω to balance this parallel impedance on the
input and thus ensure that both the positive and negative analog
inputs have the same gain (see Figure 29). The outputs of the
amplifier are perfectly matched, balanced differential outputs of
identical amplitude, and are exactly 180° out of phase.
Differential operation requires that VIN+ and VIN– be simultaneously driven with two equal signals that are 180° out of phase.
The common mode must be set up externally and has a range
determined by VREF, the power supply, and the particular amplifier used to drive the analog inputs (see Figure 23 and
Figure 24). Differential modes of operation with either an ac or
a dc input provide the best THD performance over a wide
frequency range. Since not all applications have a signal
preconditioned for differential operation, there is often a need
to perform single-ended-to-differential conversion.
Differential Amplifier
An ideal method of applying differential drive to the AD7452 is
to use a differential amplifier such as the AD8138. This part can
be used as a single-ended-to-differential amplifier or as a
differential-to-differential amplifier. In both cases, the analog
input needs to be bipolar. It also provides common-mode level
shifting and buffering of the bipolar input signal. Figure 29
shows how the AD8138 can be used as a single-ended-todifferential amplifier. The positive and negative outputs of the
AD8138 are connected to the respective inputs on the ADC via
The AD8138 is specified with +3 V, +5 V, and ±5 V power
supplies, but the best results are obtained when it is supplied by
±5 V. The AD8132 is a lower cost device that could also be used
in this configuration with slight differences in characteristics to
the AD8138 but with similar performance and operation.
3.75V
2.5V
1.25V
RF1
RS*
RG1
+2.5V
GND
–2.5V
VOCM
VIN–
C*
AD8138
RG2
AD7452
RS*
VIN+
VREF
C*
*MOUNT AS CLOSE TO THE AD7452 AS POSSIBLE
AND ENSURE HIGH PRECISION Rs AND Cs ARE USED.
3.75V
2.5V
1.25V
EXTERNAL
VREF (2.5V)
RS = 50Ω; C = 1nF
RG1 = RF1 = RF2 = 499Ω; RG2 = 523Ω
Figure 29. Using the AD8138 as a Single-Ended-to-Differential Amplifier
Rev. C | Page 16 of 24
03154-A-029
RF2
Data Sheet
AD7452
220Ω
Op Amp Pair
2 × VREF p-p
V+
390Ω
VREF
VDD
27Ω
GND
V–
VIN+
220Ω
AD7452
220Ω
VIN–
V+
The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. The AD8022 is a
suitable dual op amp that could be used in this configuration to
provide differential drive to the AD7452.
Care must be taken when choosing the op amp because the
selection depends on the required power supply and the system
performance objectives. The driver circuits in Figure 30 and
Figure 31 are optimized for dc coupling applications that
require optimum distortion performance.
The differential op amp driver circuit in Figure 30 is configured
to convert and level shift a single-ended, ground-referenced
(bipolar) signal to a differential signal centered at the VREF level
of the ADC.
The circuit configuration shown in Figure 31 converts a
unipolar, single-ended signal into a differential signal.
220Ω
27Ω
A
V–
EXTERNAL
VREF
Figure 31. Dual Op Amp Circuit to Convert a Single-Ended
Unipolar Signal into a Differential Signal
RF Transformer
In systems that do not need to be dc-coupled, an RF transformer with a center tap offers a good solution for generating
differential inputs. Figure 32 shows how a transformer is used
for single-ended-to-differential conversion. It provides the
benefits of operating the ADC in the differential mode without
contributing additional noise and distortion. An RF transformer
also has the benefit of providing electrical isolation between the
signal source and the ADC. A transformer can be used for most
ac applications. The center tap is used to shift the differential
signal to the common-mode level required; in this case, it is
connected to the reference so the common-mode level is the
value of the reference.
V+
3.75V
2.5V
1.25V
VDD
27Ω
R
R
VIN+
V–
VIN+
220Ω
VIN–
V+
A
R
VREF
AD7452
VIN–
VREF
3.75V
2.5V
1.25V
27Ω
V–
20kΩ
C
AD7452
220Ω
0.1µF
10kΩ
EXTERNAL
VREF
03154-A-030
220Ω
EXTERNAL
VREF (2.5 V)
03154-A-032
390Ω
0.1µF
10kΩ
2 × VREF p-p
GND
VREF
03154-A-031
An op amp pair can be used to directly couple a differential
signal to the AD7452. The circuit configurations shown in
Figure 30 and Figure 31 show how a dual op amp can be used to
convert a single-ended signal into a differential signal for both a
bipolar and unipolar input signal, respectively.
Figure 32. Using an RF Transformer to Generate Differential Inputs
Figure 30. Dual Op Amp Circuit to Convert a Single-Ended
Bipolar Signal into a Differential Signal
Rev. C | Page 17 of 24
AD7452
Data Sheet
The digital inputs applied to the AD7452 are not limited by the
maximum ratings, which limit the analog limits. Instead the
digital inputs applied, that is, CS and SCLK, can go to 7 V and
are not restricted by the VDD + 0.3 V limits as on the analog
input.
The main advantage of the inputs being unrestricted to the
VDD + 0.3 V limit is that power supply sequencing issues are
avoided. If CS and SCLK are applied before VDD, there is no risk
of latch-up as there would be on the analog inputs if a signal
greater than 0.3 V was applied prior to VDD.
These examples show that the maximum reference applied to
the AD7452 is directly dependent on the value applied to VDD.
The value of the reference sets the analog input span and the
common-mode voltage range. Errors in the reference source
result in gain errors in the AD7452 transfer function and add to
specified full-scale errors on the part. A 0.1 µF capacitor should
be used to decouple the VREF pin to GND.
Figure 33 shows a typical connection diagram for the VREF pin.
VDD
REFERENCE
NC
An external reference source is required to supply the reference
to the AD7452. This reference input can range from 100 mV to
3.5 V. With a 5 V power supply, the specified reference is 2.5 V
and the maximum reference is 3.5 V. With a 3 V power supply,
the specified reference is 2 V and the maximum reference is
2.2 V. In both cases, the reference is functional from 100 mV.
It is important to ensure that when choosing the reference value
for a particular application, the maximum analog input range
(VIN max) is never greater than VDD + 0.3 V to comply with the
maximum ratings of the device. The following two examples
calculate the maximum VREF input that can be used when
operating the AD7452 at a VDD of 5 V and 3 V, respectively.
AD7452*
AD780
VDD
0.1µF
10nF
0.1µF
1
OPSEL 8
NC
7
NC
2.5V
2
VIN
3
TEMP VOUT 6
4
GND
TRIM 5
VREF
0.1µF
NC
03154-A-033
DIGITAL INPUTS
NC = NO CONNECT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 33. Typical VREF Connection Diagram for VDD = 5 V
Table 5. Examples of Suitable Voltage References
Reference
AD780
ADR421
ADR420
Output
Voltage (V)
2.5/3
2.5
2.048
Initial
Accuracy (%)
0.04
0.04
0.05
Operating
Current (µA)
1000
500
500
Example 1
VIN max = VDD + 0.3
VIN max = VREF + VREF/2
SINGLE-ENDED OPERATION
When supplied with a 5 V power supply, the AD7452 can handle a single-ended input. The design of this part is optimized for
differential operation, so with a single-ended input, performance degrades. Linearity degrades by 0.2 LSB typically, the
full-scale errors degrade by 1 LSB typically, and ac performance
is not guaranteed.
If VDD = 5 V, then VIN max = 5.3 V.
Therefore
3 × VREF/2 = 5.3 V
VREF max = 3.5 V
Thus, when operating at VDD = 5 V, the value of VREF can range
from 100 mV to a maximum value of 3.5 V. When VDD = 4.75 V,
VREF max = 3.17 V.
Example 2
VIN max = VDD + 0.3
VIN max = VREF + VREF/2
If VDD = 3 V, then VIN max = 3.3 V.
Therefore
3 × VREF/2 = 3.3 V
VREF max = 2.2 V
Thus, when operating at VDD = 3 V, the value of VREF can range
from 100 mV to a maximum value of 2.2 V. When VDD = 2.7 V,
VREF max = 2 V.
To operate the AD7452 in single-ended mode, the VIN+ input is
coupled to the signal source, while the VIN– input is biased to
the appropriate voltage corresponding to the midscale code
transition. This voltage is the common mode, which is a fixed
dc voltage (usually the reference). The VIN+ input swings around
this value and should have a voltage span of 2 × VREF to make
use of the full dynamic range of the part. The input signal
therefore has peak-to-peak values of common mode ± VREF. If
the analog input is unipolar, an op amp in a noninverting unity
gain configuration can be used to drive the VIN+ pin. Because
the ADC operates from a single supply, it is necessary to level
shift ground-based bipolar signals to comply with the input
requirements. An op amp can be configured to rescale and level
shift the ground-based bipolar signal so it is compatible with
the selected input range of the AD7452 (see Figure 34).
Rev. C | Page 18 of 24
Data Sheet
AD7452
5V
2.5V
0V
R
+2.5V
0V
–2.5V
R
VIN
SCLK falling edges beginning with the second leading zero.
Thus, the first falling clock edge on the serial clock provides the
second leading zero. The final bit in the data transfer is valid on
the 16th falling edge, having been clocked out on the previous
(15th) falling edge. Once the conversion is complete and the data
has been accessed after the 16 clock cycles, it is important to
ensure that before the next conversion is initiated, enough time
is left to meet the acquisition, and quiet time specifications (see
the Timing Example).
VIN+
R
AD7452
R
VIN–
VREF
03154-A-034
0.1F
EXTERNAL
VREF (2.5V)
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge, that is, the first rising edge of
SCLK after the CS falling edge would have the leading zero
provided and the 15th SCLK edge would have DB0 provided.
Figure 34. Applying a Bipolar Single-Ended Input to the AD7452
SERIAL INTERFACE
Figure 2 shows a detailed timing diagram for the serial interface
of the AD7452. The serial clock provides the conversion clock
and also controls the transfer of data from the device during
conversion. CS initiates the conversion process and frames the
data transfer. The falling edge of CS puts the track-and-hold
into hold mode and takes the bus out of three-state. The analog
input is sampled and the conversion is initiated at this point.
The conversion requires 16 SCLK cycles to complete.
Timing Example
Having fSCLK = 10 MHz and a throughput rate of 555 kSPS gives
a cycle time of
1/Throughput = 1/555,000 = 1.8 μs
A cycle consists of
t2 + 12.5(1/fSCLK) + tACQ = 1.8 μs
Once 13 SCLK falling edges have occurred, the track-and-hold
goes back into track on the next SCLK rising edge, as shown at
Point B in Figure 2. On the 16th SCLK falling edge, the SDATA
line goes back into three-state. If the rising edge of CS occurs
before 16 SCLKs have elapsed, the conversion is terminated and
the SDATA line goes back into three-state.
Therefore, if t2 = 10 ns
10 ns + 12.5(1/10 MHz) + tACQ = 1.8 μs
tACQ = 540 ns
This 540 ns satisfies the requirement of 290 ns for tACQ.
The conversion result from the AD7452 is provided on the
SDATA output as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input. The data stream of the
AD7452 consists of four leading zeros followed by 12 bits of
conversion data provided MSB first. The output coding is twos
complement.
From Figure 35, tACQ comprises
2.5(1/fSCLK) + t8 + tQUIET
where t8 = 35 ns. This allows a value of 255 ns for tQUIET,
satisfying the minimum requirement of 60 ns.
Sixteen serial clock cycles are required to perform a conversion
and access data from the AD7452. CS going low provides the
first leading zero to be read in by the microcontroller or DSP.
The remaining data is then clocked out on the subsequent
CS
10ns
SCLK
tCONVERT
t5
1
2
3
4
5
13
14
t6
15
16
t8
tQUIET
12.5(1/ fSCLK )
tACQUISITION
1/THROUGHPUT
Figure 35. Serial Interface Timing Example
Rev. C | Page 19 of 24
03154-A-035
t2
AD7452
Data Sheet
MODES OF OPERATION
NORMAL MODE
This mode is intended for fastest throughput rate performance.
The user does not have to worry about any power-up times with
the AD7452 remaining fully powered up all the time. Figure 36
shows the general diagram of the AD7452’s operation in this
mode. The conversion is initiated on the falling edge of CS, as
described in the Serial Interface section. To ensure that the part
remains fully powered up, CS must remain low until at least 10
SCLK falling edges have elapsed after the falling edge of CS.
If CS is brought high any time after the 10th SCLK falling edge,
but before the 16th SCLK falling edge, the part remains powered
up but the conversion is terminated and SDATA goes back into
three-state. Sixteen serial clock cycles are required to complete
the conversion and access the complete conversion result. CS
may idle high until the next conversion or may idle low until
sometime prior to the next conversion. Once a data transfer is
complete, that is, when SDATA has returned to three-state,
another conversion can be initiated after the quiet time, tQUIET,
has elapsed by again bringing CS low.
CS
SDATA
1
10
16
4 LEADING ZEROS + CONVERSION RESULT
Figure 36. Normal Mode Operation
03154-A-036
SCLK
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7452 is in powerdown mode, all analog circuitry is powered down. To enter
power-down mode, the conversion process must be interrupted
by bringing CS high anywhere after the second falling edge of
SCLK, and before the 10th falling edge of SCLK, as shown in
Figure 37.
CS
SCLK
SDATA
1 2
10
THREE-STATE
03154-A-037
The mode of operation of the AD7452 is selected by controlling
the logic state of the CS signal during a conversion. There are
two possible modes of operation, normal and power-down. The
point at which CS is pulled high after the conversion has been
initiated determines whether or not the AD7452 enters the
power-down mode. Similarly, if already in power-down, CS
controls whether the device returns to normal operation or
remains in power-down. These modes of operation are designed to
provide flexible power management options. These options can
be chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
Figure 37. Entering Power-Down Mode
Once CS has been brought high in this window of SCLKs, the
part enters power-down, the conversion that was initiated by
the falling edge of CS is terminated, and SDATA goes back into
three-state. The time from the rising edge of CS to SDATA
three-state enabled is never greater than t8 (refer to the Timing
Specifications). If CS is brought high before the second SCLK
falling edge, the part remains in normal mode and does not
power down. This avoids accidental power-down due to glitches
on the CS line.
In order to exit this mode of operation and power up the
AD7452 again, a dummy conversion is performed. On the
falling edge of CS, the device begins to power up and continues
to power up as long as CS is held low until after the falling edge
of the 10th SCLK. The device is fully powered up after 1 μs has
elapsed and, as shown in Figure 38, valid data results from the
next conversion.
If CS is brought high before the 10th falling edge of SCLK, the
AD7452 again goes back into power-down. This avoids accidental power-up due to glitches on the CS line or an inadvertent
burst of eight SCLK cycles while CS is low. So although the
device may begin to power up on the falling edge of CS, it again
powers down on the rising edge of CS as long as it occurs before
the 10th SCLK falling edge.
Rev. C | Page 20 of 24
Data Sheet
AD7452
POWER-UP TIME
The power-up time of the AD7452 is typically 1 μs, which
means that with any SCLK frequency up to 10 MHz, one
dummy cycle is always sufficient to allow the device to power
up. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal will be acquired properly. The
quiet time, tQUIET, must still be allowed from the point at which
the bus goes back into three-state after the dummy conversion
to the next falling edge of CS.
When power supplies are first applied to the AD7452, the ADC
may power up either in power-down mode or in normal mode.
Because of this, it is best to allow a dummy cycle to elapse to
ensure the part is fully powered up before attempting a valid
conversion. Likewise, if the user wants the part to power up in
power-down mode, the dummy cycle may be used to ensure the
device is in power-down by executing a cycle such as the one
shown in Figure 37.
When running at the maximum throughput rate of 555 kSPS,
the AD7452 powers up and acquires a signal within ±0.5 LSB in
one dummy cycle. When powering up from the power-down
mode with a dummy cycle, as in Figure 38, the track-and-hold,
which was in hold mode while the part was powered down,
returns to track mode after the first SCLK edge the part receives
after the falling edge of CS. This is shown as Point A in
Figure 38.
Once supplies are applied to the AD7452, the power-up time is
the same as that when powering up from power-down mode. It
takes approximately 1 μs to power up fully if the part powers up
in normal mode. It is not necessary to wait 1 μs before
executing a dummy cycle to ensure the desired mode of
operation. Instead, the dummy cycle can occur directly after
power is supplied to the ADC. If the first valid conversion is
performed directly after the dummy conversion, care must be
taken to ensure that adequate acquisition time has been
allowed.
Although at any SCLK frequency one dummy cycle is sufficient
to power up the device and acquire VIN, it does not necessarily
mean that a full dummy cycle of 16 SCLKs must always elapse
to power up the device and acquire VIN fully; 1 μs is sufficient to
power up the device and acquire the input signal.
As mentioned earlier, when powering up from the power-down
mode, the part returns to track mode upon the first SCLK edge
applied after the falling edge of CS. However, when the ADC
powers up initially after supplies are applied, the track-and-hold
is already in track mode. This means if (assuming one has the
facility to monitor the ADC supply current) the ADC powers
up in the desired mode of operation, and thus a dummy cycle is
not required to change the mode, and a dummy cycle is not
required to place the track-and-hold into track mode.
For example, if a 5 MHz SCLK frequency is applied to the ADC,
the cycle time is 3.2 μs (that is, 1/(5 MHz) × 16). In one dummy
cycle, 3.2 μs, the part is powered up and VIN fully acquired.
However, after 1 μs with a 5 MHz SCLK, only five SCLK cycles
would have elapsed. At this stage, the ADC is fully powered up
and the signal acquired. So in this case, CS can be brought high
after the 10th SCLK falling edge and brought low again after a
time, tQUIET, to initiate the conversion.
tPOWER-UP
PART BEGINS
TO POWER UP
CS
A
THIS PART IS FULLY POWERED
UP WITH VIN FULLY ACQUIRED
1
10
16
1
10
16
SDATA
INVALID DATA
VALID DATA
Figure 38. Exiting Power-Down Mode
Rev. C | Page 21 of 24
03154-A-038
SCLK
AD7452
Data Sheet
POWER vs. THROUGHPUT RATE
100
By using the power-down mode on the AD7452 when not converting, the average power consumption of the ADC decreases
at lower throughput rates. Figure 39 shows how, as the throughput rate is reduced, the device remains in its power-down state
longer and the average power consumption is reduced
accordingly. It shows this for both 5 V and 3 V power supplies.
POWER (mW)
For example, if the AD7452 is operated in continuous sampling
mode with a throughput rate of 100 kSPS and an SCLK of
10 MHz, and the device is placed in power-down mode between
conversions, the power consumption is calculated as follows:
If the throughput rate = 100 kSPS, the cycle time = 10 µs and
the average power dissipated during each cycle is
(2.66/10) × 7.25 mW = 1.92 mW
For the same scenario, if VDD = 3 V, the power dissipation
during normal operation is 3.3 mW max.
The AD7452 can now be said to dissipate 3.3 mW for 2.66 µs
during each conversion cycle. This 2.66 µs figure assumes a very
short time to enter power-down mode. This increases as the
burst of clocks used to enter the power-down mode is increased.
The average power dissipated during each cycle with a
throughput rate of 100 kSPS is therefore
(2.66/10) × 3.3 mW = 0.88 mW
This is how the power numbers in Figure 39 are calculated.
For throughput rates above 320 kSPS, it is recommended that
the serial clock frequency be reduced for optimum power
performance.
1
VDD = 3V
03154-A-039
0.1
0.01
0
Power Dissipation during Normal Operation = 7.25 mW max
(for VDD = 5 V)
If the power-up time is one dummy cycle (1.06 µs if CS is
brought high after the 10th SCLK falling edge and then brought
low after the quiet time) and the remaining conversion time is
another cycle, that is, 1.6 µs, the AD7452 can be said to dissipate
7.25 mW for 2.66 µs during each conversion cycle. This 2.66 µs
figure assumes a very short time to enter power-down mode.
This increases as the burst of clocks used to enter the powerdown mode is increased.
VDD = 5V
10
50
100
150
200
250
THROUGHPUT (kSPS)
300
350
Figure 39. Power vs. Throughput Rate for Power-Down Mode
APPLICATION HINTS
Grounding and Layout
The printed circuit board that houses the AD7452 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes as it gives the
best shielding. Digital and analog ground planes should be
joined in only one place, a star ground point established as close
as possible to the GND pin on the AD7452. Avoid running
digital lines under the device because this couples noise onto
the die. The analog ground plane should be allowed to run
under the AD7452 to avoid noise coupling. The power supply
lines to the AD7452 should use as large a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line.
Fast switching signals like clocks should be shielded with digital
ground to avoid radiating noise to other sections of the board,
and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A micro-strip technique is by far the best but is not
always possible with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to GND. To achieve the best from these
decoupling components, place them as close to the device as
possible.
Rev. C | Page 22 of 24
Data Sheet
AD7452
EVALUATING THE AD7452’S PERFORMANCE
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from a PC via the evaluation board
controller. The evaluation board controller can be used in
conjunction with the AD7452 evaluation board, as well as many
other Analog Devices evaluation boards ending with the CB
designator, to demonstrate/evaluate the ac and dc performance
of the AD7452.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7452.
For more information, see the AD7452 application note that
accompanies the evaluation kit.
Rev. C | Page 23 of 24
AD7452
Data Sheet
OUTLINE DIMENSIONS
3.00
2.90
2.80
1.70
1.60
1.50
8
7
6
5
1
2
3
4
3.00
2.80
2.60
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.38 MAX
0.22 MIN
0.22 MAX
0.08 MIN
SEATING
PLANE
8°
4°
0°
0.60
BSC
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-BA
12-16-2008-A
1.30
1.15
0.90
Figure 40. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD7452BRTZ-R2
AD7452BRTZ-REEL7
1
2
Temperature Range
–40°C to +85°C
–40°C to +85°C
Linearity Error (LSB)2
±1
±1
Z = RoHS Compliant Part.
Linearity error here refers to integral nonlinearity error.
©2003–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03154-0-7/15(C)
Rev. C | Page 24 of 24
Package Description
8-Lead SOT-23
8-Lead SOT-23
Package Option
RJ-8
RJ-8
Branding
C4P
C4P
工商网监
湘ICP备2023018690号
