AD745JR-16

a FEATURES ULTRALOW NOISE PERFORMANCE 2.9 nV/ Hz at 10 kHz 0.38 V p-p, 0.1 Hz to 10 Hz 6.9 fA/ Hz Current Noise at 1 kHz EXCELLENT AC PERFORMANCE 12.5 V/ s Slew Rate 20 MHz Gain Bandwidth Product THD = 0.0002% @ 1 kHz Internally Compensated for Gains of +5 (or –4) or Greater EXCELLENT DC PERFORMANCE 0.5 mV Max Offset Voltage 250 pA Max Input Bias Current 2000 V/mV Min Open Loop Gain Available in Tape and Reel in Accordance with EIA-481A Standard APPLICATIONS Sonar Photodiode and IR Detector Amplifiers Accelerometers Low Noise Preamplifiers High Performance Audio Ultralow Noise, High Speed, BiFET Op Amp AD745 CONNECTION DIAGRAM 16-Lead SOIC (R) Package amplifier for high-speed applications demanding low noise and high dc precision. Furthermore, the AD745 does not exhibit an output phase reversal. The AD745 also has excellent dc performance with 250 pA maximum input bias current and 0.5 mV maximum offset voltage. The internal compensation of the AD745 is optimized for higher gains, providing a much higher bandwidth and a faster slew rate. This makes the AD745 especially useful as a preamplifier where low level signals require an amplifier that provides both high amplification and wide bandwidth at these higher gains. The AD745 is available in two performance grades. The AD745J and AD745K are rated over the commercial temperature range of 0°C to 70°C, and are available in the 16-lead SOIC package. 120 120 PRODUCT DESCRIPTION The AD745 is an ultralow noise, high-speed, FET input operational amplifier. It offers both the ultralow voltage noise and high speed generally associated with bipolar input op amps and the very low input currents of FET input devices. Its 20 MHz bandwidth and 12.5 V/µs slew rate makes the AD745 an ideal 1000 RSOURCE INPUT NOISE VOLTAGE – nV/ Hz EO 100 RSOURCE OP37 AND RESISTOR 100 PHASE 80 60 GAIN 40 20 0 100 80 60 40 AD745 AND RESISTOR OR OP37 AND RESISTOR 10 AD745 AND RESISTOR 20 0 –20 100M RESISTOR NOISE ONLY 1 100 1k 10k 100k SOURCE RESISTANCE – 1M 10M –20 100 1k 10k 100k 1M FREQUENCY – Hz 10M Figure 1. Figure 2. R EV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 PHASE MARGIN – Degrees OPEN-LOOP GAIN – dB AD745–SPECIFICATIONS AD745 ELECTRICAL CHARACTERISTICS Model Conditions INPUT OFFSET VOLTAGE 1 Initial Offset Initial Offset vs. Temp. vs. Supply (PSRR) vs. Supply (PSRR) INPUT BIAS CURRENT 3 Either Input Either Input @ TMAX Either Input Either Input, VS = ± 5 V INPUT OFFSET CURRENT Offset Current @ TMAX FREQUENCY RESPONSE Gain BW, Small Signal Full Power Response Slew Rate Settling Time to 0.01% Total Harmonic Distortion4 INPUT IMPEDANCE Differential Common Mode INPUT VOLTAGE RANGE Differential5 Common-Mode Voltage Over Max Operating Range 6 Common-Mode Rejection Ratio INPUT VOLTAGE NOISE Min (@ +25 C and AD745J Typ 0.25 15 V dc, unless otherwise noted.) Max 1.0 1.5 100 98 400 8.8 600 200 150 2.2 Min AD745K Typ 0.1 2 106 105 150 250 5.5 400 125 75 1.1 20 120 12.5 5 0.0002 1 × 1010 20 3 × 1011 18 ± 20 +13.3, –10.7 +12 –10 90 88 102 0.38 5.5 3.6 3.2 2.9 6.9 2000 1800 4000 1200 +13, –12 1.0 10.0 6.0 5.0 4.0 +12 nA pA pA pA nA MHz kHz V/µs µs % Ω pF Ω pF V V V dB dB µV p-p nV/ √ Hz nV/ √ Hz nV/ √ Hz nV/ √ Hz fA/ √ Hz V/mV V/mV V/mV V +13.6, –12.6 +12, –10 +13.8, –13.1 40 ± 15 8 50 V V V mA V V mA Max 0.5 1.0 Unit mV mV µV/°C dB dB pA TMIN to TMAX TMIN to TMAX 12 V to 18 V2 TMIN to TMAX VCM = 0 V VCM = 0 V VCM = +10 V VCM = 0 V VCM = 0 V VCM = 0 V G = –4 VO = 20 V p-p G = –4 f = 1 kHz G = –4 90 88 2 96 150 250 30 40 250 30 30 20 120 12.5 5 0.0002 1 × 1010 20 3 × 1011 18 ± 20 +13.3, –10.7 –10 VCM = ± 10 V TMIN to TMAX 0.1 to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 1 kHz VO = ± 10 V RLOAD ≥ 2 kΩ TMIN to TMAX RLOAD = 600 Ω RLOAD ≥ 600 Ω RLOAD ≥ 600 Ω TMIN to TMAX RLOAD ≥ 2 kΩ Short Circuit 80 78 95 0.38 5.5 3.6 3.2 2.9 6.9 5.0 4.0 INPUT CURRENT NOISE OPEN LOOP GAIN 1000 800 4000 1200 OUTPUT CHARACTERISTICS Voltage +13, –12 +13.6, –12.6 +12, –10 ± 12 20 +13.8, –13.1 40 ± 15 8 Current POWER SUPPLY Rated Performance Operating Range Quiescent Current TRANSISTOR COUNT 20 ± 4.8 # of Transistors ± 18 10.0 ± 4.8 ± 18 10.0 50 NOTES 1 Input offset voltage specifications are guaranteed after five minutes of operations at T A = 25°C. 2 Test conditions: +VS = 15 V, –VS = 12 V to 18 V and +VS = 12 V to +18 V, –VS = 15 V. 3 Bias current specifications are guaranteed maximum at either input after five minutes of operation at T A = 25°C. For higher temperature, the current doubles every 10 °C. 4 Gain = –4, RL = 2 kΩ, CL = 10 pF. 5 Defined as voltage between inputs, such that neither exceeds ± 10 V from common. 6 The AD745 does not exhibit an output phase reversal when the negative common-mode limit is exceeded. All min and max specifications are guaranteed. Specifications subject to change without notice. –2– REV. D AD745 ABSOLUTE MAXIMUM RATINGS 1 ESD SUSCEPTIBILITY Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Internal Power Dissipation2 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS Storage Temperature Range (R) . . . . . . . . . –65°C to +125°C Operating Temperature Range AD745J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 2 16-Pin Plastic SOIC Package: θJA = 100°C/W, θJC = 30°C/W An ESD classification per method 3015.6 of MIL-STD-883C has been performed on the AD745, which is a class 1 device. Using an IMCS 5000 automated ESD tester, the two null pins will pass at voltages up to 1,000 volts, while all other pins will pass at voltages exceeding 2,500 volts. ORDERING GUIDE Model AD745JR-16 AD745KR-16 * Temperature Range 0°C to 70°C 0°C to 70°C Package Option* R-16 R-16 R = Small Outline IC. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD745 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. D –3– AD745 –Typical Performance Characteristics 20 RLOAD = 10k (@ + 25 C, VS = 15 V, unless otherwise noted.) 35 20 RLOAD = 10k OUTPUT VOLTAGE SWING – V p-p 30 25 20 15 10 5 0 10 INPUT VOLTAGE SWING – V 15 +VIN 10 –VIN 5 INPUT VOLTAGE SWING – V 15 POSITIVE SUPPLY 10 NEGATIVE SUPPLY 5 0 0 5 10 SUPPLY VOLTAGE 15 VOLTS 20 0 0 5 10 SUPPLY VOLTAGE 15 VOLTS 20 100 1k LOAD RESISTANCE – 10k TPC 1. Input Voltage Swing vs. Supply Voltage TPC 2. Output Voltage Swing vs. Supply Voltage TPC 3. Output Voltage Swing vs. Load Resistance 12 10–6 INPUT BIAS CURRENT – Amps 200 100 QUIESCENT CURRENT – mA 10–7 OUTPUT IMPEDANCE – 10–8 10–9 10–10 10–11 10–12 –60 –40 –20 0.01 10k 10 9 6 1 CLOSED LOOP GAIN = –5 0.1 3 0 0 5 10 SUPPLY VOLTAGE 15 VOLTS 20 0 20 40 60 80 100 120 140 TEMPERATURE – C 100k 1M 10M FREQUENCY – Hz 100M TPC 4. Quiescent Current vs. Supply Voltage TPC 5. Input Bias Current vs. Temperature TPC 6. Output Impedance vs. Frequency 300 10–6 28 GAIN BANDWIDTH PRODUCT – MHz 0 20 40 60 80 100 120 140 TEMPERATURE – C INPUT BIAS CURRENT – Amps INPUT BIAS CURRENT – pA 10–7 10–8 10–9 10–10 10–11 10–12 –60 –40 –20 26 24 22 20 18 16 14 –60 –40 –20 200 100 0 –12 –9 –6 –3 0 3 6 9 COMMON-MODE VOLTAGE – V 12 0 20 40 60 80 100 120 140 TEMPERATURE – C TPC 7. Input Bias Current vs. Common-Mode Voltage TPC 8. Short Circuit Current Limit vs. Temperature TPC 9. Gain Bandwidth Product vs. Temperature –4– REV. D AD745 120 100 OPEN-LOOP GAIN – dB SLEW RATE – V/ s 14 150 RL = 2k 80 60 40 20 0 –20 100 GAIN 12 OPEN-LOOP GAIN – dB PHASE 140 130 CLOSED-LOOP GAIN = 5 10 120 100 1k 10k 100k 1M FREQUENCY – Hz 10M 100M 8 –60 –40 –20 0 20 40 60 80 100 110 120 TEMPERATURE – C 80 0 10 5 SUPPLY VOLTAGE 15 VOLTS 20 TPC 10. Open-Loop Gain and Phase vs. Frequency TPC 11. Slew Rate vs. Temperature TPC 12. Open-Loop Gain vs. Supply Voltage 120 COMMON-MODE REJECTION – dB 120 35 RL = 2k POWER SUPPLY REJECTION – dB 110 100 90 80 Vcm = 70 60 50 100 10V OUTPUT VOLTAGE SWING – V p-p 100 +SUPPLY 80 30 25 20 15 10 5 0 10k 60 –SUPPLY 40 20 0 100 1k 10k 100k FREQUENCY – Hz 1M 10M 1k 10k 100k 1M FREQUENCY – Hz 10M 100M 100k 1M FREQUENCY – Hz 10M TPC 13. Common-Mode Rejection vs. Frequency TPC 14. Power Supply Rejection vs. Frequency TPC 15. Large Signal Frequency Response –60 0.1 NOISE VOLTAGE (referred to input) – nV/ Hz TOTAL HARMONIC DISTORTION (THD) – dB TOTAL HARMONIC DISTORTION (THD) – % –40 1.0 CURRENT NOISE SPECTRAL DENSITY – fA/ Hz 100 1k 10 CLOSED-LOOP GAIN = 5 100 –80 GAIN = +10 –100 GAIN = +100 –120 GAIN = –4 0.01 0.001 1.0 10 0.0001 –140 10 100 1k 10k FREQUENCY – Hz 0.00001 100k 0.1 10 1.0 1 10 100 1k FREQUENCY – Hz 10k 100k 100 1k 10k 100k FREQUENCY – Hz 1M 10M TPC 16. Total Harmonic Distortion vs. Frequency TPC 17. Input Noise Voltage Spectral Density TPC 18. Input Noise Current Spectral Density REV. D –5– AD745 72 66 60 54 NUMBER OF UNITS NUMBER OF UNITS 648 TOTAL UNITS = 760 594 540 486 432 378 324 270 216 162 108 54 –5 0 5 10 –10 15 INPUT OFFSET VOLTAGE DRIFT – V/ C 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 INPUT VOLTAGE NOISE @ 10kHz – nV Hz TOTAL UNITS = 4100 48 42 36 30 24 18 12 6 0 –15 TPC 19. Distribution of Offset Voltage Drift. TA = 25°C to 125°C TPC 20. Typical Input Noise Voltage Distribution @ 10 kHz TPC 21. Offset Null Configuration, 16-Lead Package Pinout 2µs 100 90 100 90 500ns 10 0% 10 0% 5V 50mV TPC 22a. Gain of 5 Follower, 16-Lead Package Pinout TPC 22b. Gain of 5 Follower Large Signal Pulse Response TPC 22c. Gain of 5 Follower Small Signal Pulse Response 2µs 100 90 100 90 500ns 10 0% 10 0% 5V 50mV TPC 23a. Gain of 4 Inverter, 16-Lead Package Pinout TPC 23b. Gain of 4 Inverter Large Signal Pulse Response TPC 23c. Gain of 4 Inverter Small Signal Pulse Response –6– REV. D AD745 OP AMP PERFORMANCE JFET VERSUS BIPOLAR The AD745 offers the low input voltage noise of an industry standard bipolar opamp without its inherent input current errors. This is demonstrated in Figure 3, which compares input voltage noise vs. input source resistance of the OP37 and the AD745 opamps. From this figure, it is clear that at high source impedance the low current noise of the AD745 also provides lower total noise. It is also important to note that with the AD745 this noise reduction extends all the way down to low source impedances. The lower dc current errors of the AD745 also reduce errors due to offset and drift at high source impedances (Figure 4). The internal compensation of the AD745 is optimized for higher gains, providing a much higher bandwidth and a faster slew rate. This makes the AD745 especially useful as a preamplifier, where low-level signals require an amplifier that provides both high amplification and wide bandwidth at these higher gains. 1000 RSOURCE INPUT NOISE VOLTAGE – nV/ Hz The 0.1 Hz to 10 Hz noise is typically 0.38 µV p-p. The user should pay careful attention to several design details to optimize low frequency noise performance. Random air currents can generate varying thermocouple voltages that appear as low frequency noise. Therefore, sensitive circuitry should be well shielded from air flow. Keeping absolute chip temperature low also reduces low frequency noise in two ways: first, the low frequency noise is strongly dependent on the ambient temperature and increases above 25°C. Second, since the gradient of temperature from the IC package to ambient is greater, the noise generated by random air currents, as previously mentioned, will be larger in magnitude. Chip temperature can be reduced both by operation at reduced supply voltages and by the use of a suitable clip-on heat sink, if possible. Low frequency current noise can be computed from the magnitude of the dc bias current  ~ = 2qI ∆f  B  In  and increases below approximately 100 Hz with a 1/f power spectral density. For the AD745 the typical value of current noise is 6.9 fA/√Hz at 1 kHz. Using the formula: EO 100 RSOURCE OP37 AND RESISTOR AD745 AND RESISTOR OR OP37 AND RESISTOR 10 AD745 AND RESISTOR = 4kT /R ∆ f to compute the Johnson noise of a resistor, expressed as a current, one can see that the current noise of the AD745 is equivalent to that of a 3.45 × 108 Ω source resistance. n ~ I RESISTOR NOISE ONLY 1 100 1k 10k 100k SOURCE RESISTANCE – 1M 10M At high frequencies, the current noise of a FET increases proportionately to frequency. This noise is due to the “real” part of the gate input impedance, which decreases with frequency. This noise component usually is not important, since the voltage noise of the amplifier impressed upon its input capacitance is an apparent current noise of approximately the same magnitude. In any FET input amplifier, the current noise of the internal bias circuitry can be coupled externally via the gate-to-source capacitances and appears as input current noise. This noise is totally correlated at the inputs, so source impedance matching will tend to cancel out its effect. Both input resistance and input capacitance should be balanced whenever dealing with source capacitances of less than 300 pF in value. LOW NOISE CHARGE AMPLIFIERS Figure 3. Total Input Noise Spectral Density @ 1 kHz vs. Source Resistance 100 INPUT OFFSET VOLTAGE – mV OP37G 10 1.0 AD745 KN As stated, the AD745 provides both low voltage and low current noise. This combination makes this device particularly suitable in applications requiring very high charge sensitivity, such as capacitive accelerometers and hydrophones. When dealing with a high source capacitance, it is useful to consider the total input charge uncertainty as a measure of system noise. 1M 10M 0.1 100 1k 10k 100k SOURCE RESISTANCE – Charge (Q) is related to voltage and current by the simply stated fundamental relationships: Q = CV and I = dQ dt Figure 4. Input Offset Voltage vs. Source Resistance DESIGNING CIRCUITS FOR LOW NOISE An opamp’s input voltage noise performance is typically divided into two regions: flatband and low frequency noise. The AD745 offers excellent performance with respect to both. The figure of 2.9 nV/ Hz @ 10 kHz is excellent for a JFET input amplifier. As shown, voltage, current and charge noise can all be directly related. The change in open circuit voltage (∆V) on a capacitor will equal the combination of the change in charge (∆Q/C) and the change in capacitance with a built-in charge (Q/∆C). REV. D –7– AD745 DECIBELS REFERENCED TO 1V/ Hz Figures 5 and 6 show two ways to buffer and amplify the output of a charge output transducer. Both require the use of an amplifier that has a very high input impedance, such as the AD745. Figure 5 shows a model of a charge amplifier circuit. Here, amplification depends on the principle of conservation of charge at the input of amplifier A1, which requires that the charge on capacitor CS be transferred to capacitor CF, thus yielding an output voltage of ∆Q/CF. The amplifiers input voltage noise will appear at the output amplified by the noise gain (1 + (CS/CF)) of the circuit. CF RS R1 R2 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 –200 –210 –220 0.01 0.1 1 10 100 1k 10k NOISE DUE TO RB ALONE NOISE DUE TO IB ALONE 100k FREQUENCY – Hz TOTAL OUTPUT NOISE CS CB* RB* A1 R1 CS = R2 CF Figure 7. Noise at the Outputs of the Circuits of Figures 5 and 6. Gain = 10, CS = 3000 pF, RB = 22 MΩ Figure 5. A Charge Amplifier Circuit R1 CB* However, this does not change the noise contribution of RB which, in this example, dominates at low frequencies. The graph of Figure 8 shows how to select an RB large enough to minimize this resistor’s contribution to overall circuit noise. When the equivalent current noise of RB (( 4 kT)/R) equals the noise of I B 2qI B , there is diminishing return in making RB larger. ( ) 5.2 R2 RB* CS RB A2 1010 5.2 RESISTANCE IN 109 *OPTIONAL, SEE TEXT. Figure 6. Model for A High Z Follower with Gain 5.2 108 The second circuit, Figure 6, is simply a high impedance follower with gain. Here the noise gain (1 + (R1/R2)) is the same as the gain from the transducer to the output. Resistor RB, in both circuits, is required as a dc bias current return. There are three important sources of noise in these circuits. Amplifiers A1 and A2 contribute both voltage and current noise, while resistor RB contributes a current noise of: N= 5.2 107 5.2 106 1pA 10pA 100pA 1nA INPUT BIAS CURRENT 10nA ~ 4k T ∆f RB Figure 8. Graph of Resistance vs. Input Bias Current Where the Equivalent Noise 4 kT/R, Equals the Noise of the Bias Current I B 2qI B where: k = Boltzman’s Constant = 1.381 × 10–23 Joules/Kelvin T = Absolute Temperature, Kelvin (0°C = 273.2 Kelvin) ∆f = Bandwidth – in Hz (Assuming an Ideal “Brick Wall” Filter) This must be root-sum-squared with the amplifier’s own current noise. Figure 5 shows that these two circuits have an identical frequency response and the same noise performance (provided that CS/CF = R1/ R2). One feature of the first circuit is that a “T” network is used to increase the effective resistance of RB and improve the low frequency cutoff point by the same factor. ( ) To maximize dc performance over temperature, the source resistances should be balanced on each input of the amplifier. This is represented by the optional resistor RB in Figures 5 and 6. As previously mentioned, for best noise performance care should be taken to also balance the source capacitance designated by CB The value for CB in Figure 5 would be equal to CS in Figure 6. At values of CB over 300 pF, there is a diminishing impact on noise; capacitor CB can then be simply a large mylar bypass capacitor of 0.01 µF or greater. –8– REV. D AD745 HOW CHIP PACKAGE TYPE AND POWER DISSIPATION AFFECT INPUT BIAS CURRENT INPUT BIAS CURRENT – Amps 300 TA = 25 C As with all JFET input amplifiers, the input bias current of the AD745 is a direct function of device junction temperature, IB approximately doubling every 10°C. Figure 9 shows the relationship between bias current and junction temperature for the AD745. This graph shows that lowering the junction temperature will dramatically improve IB. 10–6 VS = 15V TA = 25 C 200 JA = 165 C/W 100 JA = 115 C/W INPUT BIAS CURRENT – Amps 10–7 JA = 0 C/W 10–8 0 5 10 SUPPLY VOLTAGE – 15 Volts 10–9 Figure 11. Input Bias Current vs. Supply Voltage for Various Values of θJA TJ 10–10 10–11 A 10–12 –60 (J TO DIE MOUNT) –40 –20 0 20 40 60 80 100 JUNCTION TEMPERATURE – C 120 140 B Figure 9. Input Bias Current vs. Junction Temperature TA CASE (DIE MOUNT TO CASE) The dc thermal properties of an IC can be closely approximated by using the simple model of Figure 10 where current represents power dissipation, voltage represents temperature, and resistors represent thermal resistance (θ in °C/watt). TJ JC CA A+ B = JC Figure 12. Breakdown of Various Package Thermal Resistance REDUCED POWER SUPPLY OPERATION FOR LOWER IB PIN JA TA WHERE: PIN = DEVICE DISSIPATION TA = AMBIENT TEMPERATURE TJ = JUNCTION TEMPERATURE JC = THERMAL RESISTANCE – JUNCTION TO CASE CA = THERMAL RESISTANCE – CASE TO AMBIENT Figure 10. Device Thermal Model Reduced power supply operation lowers IB in two ways: first, by lowering both the total power dissipation and, second, by reducing the basic gate-to-junction leakage (Figure 11). Figure 13 shows a 40 dB gain piezoelectric transducer amplifier, which operates without an ac coupling capacitor, over the –40°C to +85°C temperature range. If the optional coupling capacitor, C1, is used, this circuit will operate over the entire –55°C to +125°C temperature range. 100 C1* 108 ** CT** +5V 10k From this model TJ = TA+θJA PIN. Therefore, IB can be determined in a particular application by using Figure 9 together with the published data for θJA and power dissipation. The user can modify θJA by use of an appropriate clip-on heat sink such as the Aavid #5801. Figure 11 shows bias current versus supply voltage with θJA as the third variable. This graph can be used to predict bias current after θJA has been computed. Again bias current will double for every 10°C. TRANSDUCER CT 108 AD745 –5V *OPTIONAL DC BLOCKING CAPACITOR **OPTIONAL, SEE TEXT Figure 13. A Piezoelectric Transducer REV. D –9– AD745 TWO HIGH PERFORMANCE ACCELEROMETER AMPLIFIERS Two of the most popular charge-out transducers are hydrophones and accelerometers. Precision accelerometers are typically calibrated for a charge output (pC/g).* Figures 14 and 15 show two ways in which to configure the AD745 as a low noise charge amplifier for use with a wide variety of piezoelectric accelerometers. The input sensitivity of these circuits will be determined by the value of capacitor C1 and is equal to: ∆V OUT = ∆QOUT C1 low frequency performance, the time constant of the servo loop (R4C2 = R5C3) should be:  R2  C1 Time Constant ≥ 10 R1 1 + R3    A LOW NOISE HYDROPHONE AMPLIFIER The ratio of capacitor C1 to the internal capacitance (CT) of the transducer determines the noise gain of this circuit (1 + CT/C1). The amplifiers voltage noise will appear at its output amplified by this amount. The low frequency bandwidth of these circuits will be dependent on the value of resistor R1. If a “T” network is used, the effective value is: R1 (1 + R2/R3). *pC = Picocoulombs g = Earth’s Gravitational Constant C1 1250pF R1 110M (5 22M ) Hydrophones are usually calibrated in the voltage-out mode. The circuit of Figures 16 can be used to amplify the output of a typical hydrophone. If the optional ac coupling capacitor CC is used, the circuit will have a low frequency cutoff determined by an RC time constant equal to: 1 Time Constant ≥ 10 R1 2π × CC × 100 Ω where the dc gain is 1 and the gain above the low frequency cutoff (1/(2π CC(100 Ω))) is equal to (1 + R2/R3). The circuit of Figure 17 uses a dc servo loop to keep the dc output at 0 V and to maintain full dynamic range for IB’s up to 100 nA. The time constant of R7 and C1 should be larger than that of R1 and CT for a smooth low frequency response. R2 1900 R3 100 R4* C1* R2 9k R3 1k CC B AND K TYPE 8100 HYDROPHONE R1 108 AD745 OUTPUT CT INPUT SENSITIVITY = –179dB RE. 1V/mPa** B AND K 4370 OR EQUIVALENT AD745 OUTPUT 0.8mV/pC *OPTIONAL DC BLOCKING CAPACITOR **OPTIONAL, SEE TEXT Figure 16. A Low Noise Hydrophone Amplifier Figure 14. A Basic Accelerometer Circuit C1 1250pF R1 110M 22M ) R3 1k C2 2.2 F R4 18M AD711 R5 18M C3 2.2 F B AND K 4370 OR EQUIVALENT The transducer shown has a source capacitance of 7500 pF. For smaller transducer capacitances (≤300 pF), lowest noise can be achieved by adding a parallel RC network (R4 = R1, C1 = CT) in series with the inverting input of the AD745. R2 1900 R3 100 R4* 108 (5 R2 9k C1* R4 16M OUTPUT AD745 C2 0.27 F R1 108 CT AD745 OUTPUT 0.8mV/pC R5 100k AD711K R6 1M 16M Figure 15. An Accelerometer Circuit Employing a DC Servo Amplifier DC OUTPUT 1mV FOR IB (AD745) *OPTIONAL, SEE TEXT 100nA A dc servo loop (Figure 15) can be used to assure a dc output > R1 OR R2 R2 CS RS CB RB CF CB = CF || CS RB = R1 || RS R1 RS CS CB RB AD745 INVERTING CONNECTION OUTPUT AD745 OUTPUT NONINVERTING CONNECTION Figure 40. Optional External Components for Balancing Source Impedances OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead SOIC (R) Package 0.4133 (10.50) 0.3977 (10.00) 16 9 0.2992 (7.60) 0.2914 (7.40) 1 8 0.4193 (10.65) 0.3937 (10.00) PIN 1 0.050 (1.27) BSC 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) 0.0098 (0.25) 45 0.0118 (0.30) 0.0040 (0.10) 8 0.0192 (0.49) SEATING 0 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) Revision History Location Data Sheet changed from REV. C to REV. D. Page Deleted 8-Lead Plastic Mini-DIP (N) and 8-Lead Cerdip (Q) Packages from CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . 1 Edits to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Deleted to METALIZATION PHOTOGRAPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Deleted text from HOW CHIP PACKAGE TYPE AND POWER DISSIPATION AFFECT INPUT BIAS CURRENT . . . . . . . . 9 Deleted 8-Lead Plastic Mini-DIP (N) and 8-Lead Cerdip (Q) Packages from OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . 12 –12– REV. D PRINTED IN U.S.A. C00831–0–3/02(D)