AD7478AARMZ

2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70 AD7476A/AD7477A/AD7478A Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Fast throughput rate: 1 MSPS Specified for VDD of 2.35 V to 5.25 V Low power 3.6 mW at 1 MSPS with 3 V supplies 12.5 mW at 1 MSPS with 5 V supplies Wide input bandwidth 71 dB SNR at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI/QSPI™/MICROWIRE/DSP compatible Standby mode: 1 µA maximum 6-lead SC70 package 8-lead MSOP Qualified for automotive applications VDD VIN T/H 12-/10-/8-BIT SUCCESSIVEAPPROXIMATION ADC SCLK AD7476A/AD7477A/AD7478A GND SDATA CS 02930-001 CONTROL LOGIC Figure 1. APPLICATIONS Battery-powered systems Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems High speed modems Optical sensors GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7476A/AD7477A/AD7478A are 12-bit, 10-bit, and 8-bit high speed, low power, successive-approximation analog-todigital converters (ADCs), respectively. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 13 MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is also initiated at this point. There are no pipeline delays associated with the parts. The AD7476A/AD7477A/ AD7478A use advanced design techniques to achieve low power dissipation at high throughput rates. The reference for the part is taken internally from VDD to allow the widest dynamic input range to the ADC. Thus, the analog input range for the part is 0 V to VDD. The conversion rate is determined by the SCLK. Rev. G 1. 2. 3. 4. 5. First 12-/10-/8-bit ADCs in a SC70 package. High throughput with low power consumption. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced when a power-down mode is used while not converting. The parts also feature a power-down mode to maximize power efficiency at lower throughput rates. Current consumption is 1 µA maximum and 50 nA typically when in power-down mode. Reference derived from the power supply. No pipeline delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2002–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7476A/AD7477A/AD7478A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Connection Diagram ....................................................... 16 Applications ....................................................................................... 1 Analog Input ............................................................................... 16 Functional Block Diagram .............................................................. 1 Digital Inputs .............................................................................. 17 General Description ......................................................................... 1 Modes of Operation ....................................................................... 18 Product Highlights ........................................................................... 1 Normal Mode.............................................................................. 18 Revision History ............................................................................... 2 Power-Down Mode .................................................................... 18 Specifications..................................................................................... 3 Power-Up Time .......................................................................... 18 AD7476A Specifications .............................................................. 3 Power vs. Throughput Rate ........................................................... 20 AD7477A Specifications .............................................................. 5 Serial Interface ................................................................................ 21 AD7478A Specifications .............................................................. 6 AD7478A in a 12 SCLK Cycle Serial Interface....................... 22 Timing Specifications .................................................................. 8 Microprocessor Interfacing ........................................................... 23 Absolute Maximum Ratings.......................................................... 10 AD7476A/AD7477A/AD7478A to ADSP-2181 Interface .... 23 ESD Caution ................................................................................ 10 AD7476A/AD7477A/AD7478A to DSP563xx Interface ...... 24 Pin Configurations and Function Descriptions ......................... 11 Application Hints ........................................................................... 25 Typical Performance Characteristics ........................................... 12 Grounding and Layout .............................................................. 25 Terminology .................................................................................... 14 Outline Dimensions ....................................................................... 26 Theory of Operation ...................................................................... 15 Ordering Guide .......................................................................... 26 Circuit Information .................................................................... 15 Automotive Products ................................................................. 27 The Converter Operation .......................................................... 15 ADC Transfer Function ............................................................. 15 REVISION HISTORY 1/16—Rev. F to Rev. G Changes to Table 5 .......................................................................... 10 Changed AD7476A/AD7477A/AD7478A to ADSP-218x Interface Section to AD7476A/AD7477A/AD7478A to ADSP-2181 Section ........................................................................ 23 Deleted AD7476A/AD7477A/AD7478A to TMS320C541 Interface Section and Figure 28; Renumbered Sequentially ..... 23 Deleted Evaluating the AD7476A/AD7477A Performance Section .............................................................................................. 25 Changes to Ordering Guide .......................................................... 26 1/11—Rev. E to Rev. F Changes to Features Section ............................................................1 Changes to Ordering Guide .......................................................... 26 Added Automotive Products Section .......................................... 27 2/09—Rev. D to Rev. E Changes to Features ..........................................................................1 Changes to Ordering Guide .......................................................... 26 4/06—Rev. C to Rev. D Updated Format .................................................................. Universal Changes to Ordering Guide .......................................................... 26 Rev. G | Page 2 of 28 Data Sheet AD7476A/AD7477A/AD7478A SPECIFICATIONS AD7476A SPECIFICATIONS VDD = 2.35 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 1. Parameter DYNAMIC PERFORMANCE Signal-to-Noise-and-Distortion (SINAD) 3 Signal-to-Noise Ratio (SNR)3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity3 A Grade 2 B Grade2 Y Grade2 Unit 70 69 71.5 69 68 71 70 70 69 –80 –82 70 69 71.5 69 68 71 70 70 69 –80 –82 70 69 71.5 69 68 71 70 70 69 –80 –82 dB min dB min dB typ dB min dB min dB min dB min dB min dB min dB typ dB typ –84 –84 10 30 13.5 2 –84 –84 10 30 13.5 2 –84 –84 10 30 13.5 2 dB typ dB typ ns typ ps typ MHz typ MHz typ 12 12 ±1.5 12 ±1.5 –0.9/+1.5 –0.9/+1.5 ±1.5 ±0.2 ±1.5 ±0.5 ±2 ±1.5 ±0.2 ±1.5 ±0.5 ±2 Bits LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max 0 to VDD ±0.5 20 0 to VDD ±0.5 20 0 to VDD ±0.5 20 V μA max pF typ 2.4 1.8 0.8 0.4 ±0.5 ±10 5 2.4 1.8 0.8 0.4 ±0.5 ±10 5 2.4 1.8 0.8 0.4 ±0.5 ±10 5 V min V min V max V max μA max nA typ pF max ±0.75 Differential Nonlinearity ±0.75 Offset Error3, 5 ±1.5 Gain Error3, 5 ±1.5 Total Unadjusted Error (TUE)3, 5 ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN 6 Rev. G | Page 3 of 28 Test Conditions/Comments fIN = 100 kHz sine wave VDD = 2.35 V to 3.6 V, TA = 25°C VDD = 2.4 V to 3.6 V VDD = 2.35 V to 3.6 V VDD = 4.75 V to 5.25 V, TA = 25°C VDD = 4.75 V to 5.25 V VDD = 2.35 V to 3.6 V, TA = 25°C VDD = 2.4 V to 3.6 V VDD = 4.75 V to 5.25 V, TA = 25°C VDD = 4.75 V to 5.25 V fa = 100.73 kHz, fb = 90.72 kHz fa = 100.73 kHz, fb = 90.72 kHz At 3 dB At 0.1 dB B and Y grades 4 Guaranteed no missed codes to 12 bits Track-and-hold in track; 6 pF typ when in hold VDD = 2.35 V VDD = 5 V VDD = 3 V Typically 10 nA, VIN = 0 V or VDD AD7476A/AD7477A/AD7478A Parameter LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance6 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) Power Dissipation 7 Normal Mode (Operational) Full Power-Down Mode A Grade 2 Data Sheet B Grade2 Y Grade2 Unit Test Conditions/Comments VDD – 0.2 VDD – 0.2 VDD – 0.2 0.4 0.4 0.4 ±1 ±1 ±1 5 5 5 Straight (Natural) Binary V min V max μA max pF max ISOURCE = 200 μA; VDD = 2.35 V to 5.25 V ISINK = 200 μA 800 250 1 800 250 1 800 250 1 ns max ns max MSPS max 16 SCLK cycles 2.35/5.25 2.35/5.25 2.35/5.25 V min/max 2.5 1.2 3.5 1.7 1 0.6 0.3 17.5 5.1 5 3 2.5 1.2 3.5 1.7 1 0.6 0.3 17.5 5.1 5 3 2.5 1.2 3.5 1.7 1 0.6 0.3 17.5 5.1 5 3 mA typ mA typ mA max mA max μA max mA typ mA typ mW max mW max μW max μW max Temperature ranges are as follows: A, B grades from –40°C to +85°C, Y grade from –40°C to +125°C. Operational from VDD = 2.0 V, with input low voltage (VINL) 0.35 V maximum. See the Terminology section. 4 B and Y grades, maximum specifications apply as typical figures when VDD = 4.75 V to 5.25 V. 5 SC70 values guaranteed by characterization. 6 Guaranteed by characterization. 7 See the Power vs. Throughput Rate section. 1 2 3 Rev. G | Page 4 of 28 See Serial Interface section Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V, SCLK on or off VDD = 2.35 V to 3.6 V, SCLK on or off VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS Typically 50 nA VDD = 5 V, fSAMPLE = 100 kSPS VDD = 3 V, fSAMPLE = 100 kSPS VDD = 5 V, fSAMPLE = 1 MSPS VDD = 3 V, fSAMPLE = 1 MSPS VDD = 5 V VDD = 3 V Data Sheet AD7476A/AD7477A/AD7478A AD7477A SPECIFICATIONS VDD = 2.35 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise-and-Distortion (SINAD) 3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error3, 4 Gain Error3, 4 Total Unadjusted Error (TUE)3, 4 ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN5 LOGIC OUTPUTS Output High Voltage VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance 5 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate A Grade 2 Unit 61 −72 −73 dB min dB max dB max −82 −82 10 30 13.5 2 dB typ dB typ ns typ ps typ MHz typ MHz typ 10 ±0.5 ±0.5 ±1 ±1 ±1.2 Bits LSB max LSB max LSB max LSB max LSB max 0 to VDD ±0.5 20 V µA max pF typ 2.4 1.8 0.8 0.4 ±0.5 ±10 5 V min V min V max V max μA max nA typ pF max Test Conditions/Comments fIN = 100 kHz sine wave fa = 100.73 kHz, fb = 90.7 kHz fa = 100.73 kHz, fb = 90.7 kHz At 3 dB At 0.1 dB Guaranteed no missed codes to 10 bits Track-and-hold in track; 6 pF typ when in hold VDD = 2.35 V VDD = 5 V VDD = 3 V Typically 10 nA, VIN = 0 V or VDD VDD − 0.2 V min 0.4 V max ±1 μA max 5 pF max Straight (Natural) Binary ISOURCE = 200 μA, VDD = 2.35 V to 5.25 V ISINK = 200 μA 700 250 1 14 SCLK cycles with SCLK at 20 MHz ns max ns max MSPS max Rev. G | Page 5 of 28 AD7476A/AD7477A/AD7478A Parameter POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) Power Dissipation 6 Normal Mode (Operational) Full Power-Down Mode Data Sheet A Grade 2 Unit Test Conditions/Comments 2.35/5.25 V min/max 2.5 1.2 3.5 1.7 1 0.6 0.3 17.5 5.1 5 mA typ mA typ mA max mA max μA max mA typ mA typ mW max mW max μW max Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V, SCLK on or off VDD = 2.35 V to 3.6 V, SCLK on or off VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS Typically 50 nA VDD = 5 V, fSAMPLE = 100 kSPS VDD = 3 V, fSAMPLE = 100 kSPS VDD = 5 V, fSAMPLE = 1 MSPS VDD = 3 V, fSAMPLE = 1 MSPS VDD = 5 V Temperature range is from −40°C to +85°C. Operational from VDD = 2.0 V, with input high voltage (VINH) 1.8 V minimum. 3 See the Terminology section. 4 SC70 values guaranteed by characterization. 5 Guaranteed by characterization. 6 See the Power vs. Throughput Rate section. 1 2 AD7478A SPECIFICATIONS VDD = 2.35 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter DYNAMIC PERFORMANCE Signal-to-Noise-and-Distortion (SINAD) 3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity3 Differential Nonlinearity3 Offset Error3, 4 Gain Error3, 4 Total Unadjusted Error (TUE)3, 4 ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance A Grade 2 Unit 49 −65 −65 dB min dB max dB max −76 −76 10 30 13.5 2 dB typ dB typ ns typ ps typ MHz typ MHz typ 8 ±0.3 ±0.3 ±0.3 ±0.3 ±0.5 Bits LSB max LSB max LSB max LSB max LSB max 0 to VDD ±0.5 20 V μA max pF typ Test Conditions/Comments fIN = 100 kHz sine wave Rev. G | Page 6 of 28 fa = 100.73 kHz, fb = 90.7 kHz fa = 100.73 kHz, fb = 90.7 kHz At 3 dB At 0.1 dB Guaranteed no missed codes to eight bits Track-and-hold in track; 6 pF typ when in hold Data Sheet Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN 5 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance5 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) Power Dissipation 6 Normal Mode (Operational) Full Power-Down Mode AD7476A/AD7477A/AD7478A A Grade 2 Unit 2.4 1.8 0.8 0.4 ±0.5 ±10 5 V min V min V max V max μA max nA typ pF max Test Conditions/Comments VDD = 2.35 V VDD = 5 V VDD = 3 V Typically 10 nA, VIN = 0 V or VDD V min VDD − 0.2 0.4 V max ±1 μA max 5 pF max Straight (Natural) Binary ISOURCE = 200 μA, VDD = 2.35 V to 5.25 V ISINK = 200 μA 600 225 1.2 ns max ns max MSPS max 12 SCLK cycles with SCLK at 20 MHz 2.35/5.25 V min/max 2.5 1.2 3.5 1.7 1 0.6 0.3 17.5 5.1 5 mA typ mA typ mA max mA max μA max mA typ mA typ mW max mW max μW max Temperature range is from –40°C to +85°C. Operational from VDD = 2.0 V, with input high voltage (VINH) 1.8 V minimum. See the Terminology section. 4 SC70 values guaranteed by characterization. 5 Guaranteed by characterization. 6 See the Power vs. Throughput Rate section. 1 2 3 Rev. G | Page 7 of 28 Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V, SCLK on or off VDD = 2.35 V to 3.6 V, SCLK on or off VDD = 4.75 V to 5.25 V VDD = 2.35 V to 3.6 V Typically 50 nA VDD = 5 V, fSAMPLE = 100 kSPS VDD = 3 V, fSAMPLE = 100 kSPS VDD = 5 V VDD = 3 V VDD = 5 V AD7476A/AD7477A/AD7478A Data Sheet TIMING SPECIFICATIONS VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted. 1 Table 4. Parameter fSCLK 2 tCONVERT tQUIET t1 t2 t3 4 t44 t5 t6 t7 5 t8 6 tPOWER-UP 7 Limit at TMIN, TMAX 10 20 20 16 × tSCLK 14 × tSCLK 12 × tSCLK 50 Unit kHz min 3 kHz min3 MHz max 10 10 22 40 0.4 tSCLK 0.4 tSCLK ns min ns min ns max ns max ns min ns min 10 9.5 7 36 t7 values also apply to t8 minimum values 1 ns min ns min ns min ns max ns min μs max ns min Description A, B grades Y grade AD7476A AD7477A AD7478A Minimum quiet time required between bus relinquish and start of next conversion Minimum CS pulse width CS to SCLK setup time Delay from CS until SDATA three-state disabled Data access time after SCLK falling edge SCLK low pulse width SCLK high pulse width SCLK to data valid hold time VDD ≤ 3.3 V 3.3 V < VDD ≤ 3.6 V VDD > 3.6 V SCLK falling edge to SDATA high impedance SCLK falling edge to SDATA high impedance Power-up time from full power-down Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Minimum fSCLK at which specifications are guaranteed. 4 Measured with the load circuit shown in Figure 2, and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V, and 0.8 V or 2.0 V for VDD > 2.35 V. 5 Measured with a 50 pF load capacitor. 6 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. Therefore, the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 See the Power-Up Time section. 1 2 Rev. G | Page 8 of 28 Data Sheet AD7476A/AD7477A/AD7478A Timing Diagrams Timing Example 2 1.6V CL 50pF IOH 200µA t2 + 12.5 (1/fSCLK) + tACQ = 3.174 µs where: 02930-002 TO OUTPUT PIN Having fSCLK = 5 MHz and a throughput is 315 kSPS yields a cycle time of IOL 200µA t2 = 10 ns min, this leaves tACQ to be 664 ns. This 664 ns satisfies the requirement of 250 ns for tACQ. Figure 2. Load Circuit for Digital Output Timing Specifications Timing Example 1 From Figure 4, tACQ is comprised of Having fSCLK = 20 MHz and a throughput of 1 MSPS, a cycle time of 2.5 (1/fSCLK) + t8 + tQUIET, t8 = 36 ns maximum This allows a value of 128 ns for tQUIET, satisfying the minimum requirement of 50 ns. t2 + 12.5 (1/fSCLK) + tACQ = 1 µs where: In this example and with other, slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 50 ns minimum tQUIET between conversions. In Example 2, acquire the signal fully at approximately Point C in Figure 4. t2 = 10 ns min, leaving tACQ to be 365 ns. This 365 ns satisfies the requirement of 250 ns for tACQ. From Figure 4, tACQ is comprised of 2.5 (1/fSCLK) + t8 + tQUIET where: t8 = 36 ns maximum. This allows a value of 204 ns for tQUIET, satisfying the minimum requirement of 50 ns. t1 CS t3 SDATA Z THREESTATE 4 3 5 t4 ZERO ZERO B 13 14 ZERO DB11 15 16 t5 t7 DB10 DB2 t8 DB1 tQUIET DB0 THREE-STATE 4 LEADING ZEROS 02930-003 2 1 SCLK tCONVERT t6 t2 Figure 3. AD7476A Serial Interface Timing Diagram CS SCLK 1 2 3 4 5 12.5(1/fSCLK) B 13 C 14 1/THROUGHPUT Figure 4. Serial Interface Timing Example Rev. G | Page 9 of 28 15 16 tACQ t8 tQUIET 02930-004 tCONVERT t2 AD7476A/AD7477A/AD7478A Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5. Parameter VDD to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies Operating Temperature Range Commercial (A and B Grades) Industrial (Y Grade) Storage Temperature Range Junction Temperature MSOP Package θJA Thermal Impedance θJC Thermal Impedance SC70 Package θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Reflow (10 sec to 30 sec) Pb-Free Temperature Soldering Reflow ESD AD7476AWYRMZ, AD7476AWYRMZ-RL7 All Other Models Ratings −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V 10 mA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION −40°C to +85°C −40°C to +125°C −65°C to +150°C 150°C 205.9°C/W 43.74°C/W 340.2°C/W 228.9°C/W 235 (0/+5)°C 255 (0/+5)°C 2 kV 3.5 kV Rev. G | Page 10 of 28 Data Sheet AD7476A/AD7477A/AD7478A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 6 CS VDD 1 5 SDATA 4 SCLK TOP VIEW (Not to Scale) SDATA 2 AD7476A/ AD7477A/ AD7478A 8 VIN 7 GND 6 SCLK CS 3 TOP VIEW NC 4 (Not to Scale) 5 NC NC = NO CONNECT 02930-006 VIN 3 AD7476A/ AD7477A/ AD7478A 02930-005 VDD 1 GND 2 Figure 6. 8-Lead MSOP Pin Configuration Figure 5. 6-Lead SC70 Pin Configuration Table 6. Pin Function Descriptions Mnemonic CS VDD GND VIN SDATA SCLK NC Description Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7476A/AD7477A/AD7478A and also frames the serial data transfer. Power Supply Input. The VDD range for AD7476A/AD7477A/AD7478A is from 2.35 V to 5.25 V. Analog Ground. Ground reference point for all circuitry on AD7476A/AD7477A/AD7478A. Refer all analog input signals to this GND voltage. Analog Input. Single-ended analog input channel. The input range is 0 V to VDD. Data Out. Logic output. The conversion result from AD7476A/AD7477A/AD7478A is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7476A consists of four leading zeros followed by 12 bits of conversion data that are provided MSB first. The data stream from the AD7477A consists of four leading zeros followed by 10 bits of conversion data followed by two trailing zeros, provided MSB first. The data stream from the AD7478A consists of four leading zeros followed by 8 bits of conversion data followed by four trailing zeros that are provided MSB first. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of AD7476A/AD7477A/AD7478A. No Connect. Rev. G | Page 11 of 28 AD7476A/AD7477A/AD7478A Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS Figure 7, Figure 8, and Figure 9 each show a typical FFT plot for the AD7476A, AD7477A, and AD7478A, respectively, at a 1 MSPS sample rate and 100 kHz input frequency. Figure 10 shows the signal-to-noise-and-distortion ratio performance vs. the input frequency for various supply voltages while sampling at 1 MSPS with an SCLK frequency of 20 MHz for the AD7476A. Figure 11 and Figure 12 show INL and DNL performance for the AD7476A. Figure 13 shows a graph of the total harmonic distortion vs. the analog input frequency for different source impedances when using a supply voltage of 3.6 V and sampling at a rate of 1 MSPS (see the Analog Input section). Figure 14 shows a graph of the total harmonic distortion vs. the analog input signal frequency for various supply voltages while sampling at 1 MSPS with an SCLK frequency of 20 MHz. 5 5 8192 POINT FFT VDD = 2.7V fSAMPLE = 1MSPS fIN = 100kHz SINAD = 72.05dB THD = –82.87dB SFDR = –87.24dB –15 –15 –25 SNR (dB) –55 –75 –45 –55 –65 –75 02930-007 –95 –115 –35 0 50 100 150 200 250 300 350 FREQUENCY (kHz) 400 450 –85 –95 500 Figure 7. AD7476A Dynamic Performance at 1 MSPS 02930-009 SNR (dB) –35 8192 POINT FFT VDD = 2.35V fSAMPLE = 1MSPS fIN = 100kHz SINAD = 49.77dB THD = –75.51dB SFDR = –70.71dB –5 0 50 100 150 200 250 300 350 FREQUENCY (kHz) 400 500 450 Figure 9. AD7478A Dynamic Performance at 1 MSPS –66 8192 POINT FFT VDD = 2.35V fSAMPLE = 1MSPS fIN = 100kHz SINAD = 61.67dB THD = –79.59dB SFDR = –82.93dB –68 –45 –65 VDD = 2.7V –69 VDD = 2.35V –70 VDD = 5.25V –71 –72 –85 02930-008 –105 0 50 100 150 200 250 300 350 FREQUENCY (kHz) 400 450 VDD = 4.75V –73 –74 500 Figure 8. AD7477A Dynamic Performance at 1 MSPS 02930-010 SNR (dB) –25 –67 SINAD (dB) –5 VDD = 3.6V 10 100 FREQUENCY (kHz) 1000 Figure 10. AD7476A SINAD vs. Input Frequency at 1 MSPS Rev. G | Page 12 of 28 Data Sheet AD7476A/AD7477A/AD7478A 1.0 0 VDD = 2.35V TEMP = 25°C fSAMPLE = 1MSPS 0.8 –20 0.4 –30 THD (dB) 0.2 0 –0.2 –0.8 –80 0 512 1024 1536 2048 CODE 2560 3072 3584 –90 4096 Figure 11. AD7476A INL Performance RIN = 13Ω RIN = 0Ω 10 100 INPUT FREQUENCY (kHz) 1000 Figure 13. THD vs. Analog Input Frequency for Various Source Impedances 1.0 –60 VDD = 2.35V TEMP = 25°C fSAMPLE = 1MSPS 0.8 0.6 –65 VDD = 2.35V 0.4 –70 THD (dB) 0.2 0 –0.2 VDD = 2.7V –75 VDD = 4.75V –0.4 –0.6 –0.8 –85 0 512 1024 1536 2048 CODE 2560 3072 Figure 12. AD7476A DNL Performance 3584 VDD = 5.25V VDD = 3.6V –90 4096 10 100 INPUT FREQUENCY (kHz) 02930-014 –80 02930-012 DNL ERROR (LSB) RIN = 130Ω 02930-013 –70 –1.0 RIN = 1kΩ –50 –0.6 –1.0 RIN = 10kΩ –40 –60 –0.4 02930-011 INL ERROR (LSB) 0.6 VDD = 3.6V –10 1000 Figure 14. THD vs. Analog Input Frequency for Various Supply Voltages Rev. G | Page 13 of 28 AD7476A/AD7477A/AD7478A Data Sheet TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7476A/AD7477A/AD7478A, the endpoints of the transfer function are zero scale (1 LSB below the first code transition), and full scale (1 LSB above the last code transition). Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. It is defined as Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Offset Error This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 1 LSB. Peak Harmonic or Spurious Noise (SFDR) Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum. For ADCs where the harmonics are buried in the noise floor, it is a noise peak. Gain Error This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal, that is, VREF – 1 LSB after the offset error has been adjusted out. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of a conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 0.5 LSB, after the end of conversion. See the Serial Interface section for more details. Signal-to-Noise-and-Distortion-Ratio (SINAD) This is the measured ratio of signal-to-noise-and-distortion at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-noise-and-distortion ratio for an ideal N-bit converter with a sine wave input is given by signal-tonoise-and-distortion = (6.02 N + 1.76) dB. Thus, it is 74 dB for a 12-bit converter, 62 dB for a 10-bit converter, and 50 dB for an 8-bit converter. THD(dB) = 20 log V22 + V32 + V42 + V52 + V62 V1 Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities create distortion products at sum and difference frequencies of mfa, nfb, where m and n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa – fb), and the third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). The AD7476A/AD7477A/AD7478A are tested using the CCIF standard where two input frequencies are used (see fa and fb in the Specifications section). In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Total Unadjusted Error (TUE) This is a comprehensive specification that includes the gain, linearity, and offset errors. Rev. G | Page 14 of 28 Data Sheet AD7476A/AD7477A/AD7478A THEORY OF OPERATION THE CONVERTER OPERATION CHARGE REDISTRIBUTION DAC VIN ACQUISITION PHASE AGND COMPARATOR VDD/2 COMPARATOR ADC TRANSFER FUNCTION The output coding of the AD7476A/AD7477A/AD7478A is straight binary. The designed code transitions occur at the successive integer LSB values, that is, 1 LSB, 2 LSB, and so on. The LSB size is VDD/4096 for the AD7476A, VDD/1024 for the AD7477A, and VDD/256 for the AD7478A. The ideal transfer characteristic for the AD7476A/AD7477A/AD7478A is shown in Figure 17. 111...111 111...110 111...000 Figure 15. ADC Acquisition Phase Rev. G | Page 15 of 28 1LSB = V DD/4096 (AD7476A) 1LSB = V DD/1024 (AD7477A) 1LSB = V DD/256 (AD7478A) 011...111 000...010 000...001 000...000 CONTROL LOGIC SW2 CONTROL LOGIC SW2 Figure 16. ADC Conversion Phase 02930-015 SW1 B CONVERSION PHASE VDD/2 SAMPLING CAPACITOR A SW1 B AGND CHARGE REDISTRIBUTION DAC VIN SAMPLING CAPACITOR A ADC CODE AD7476A/AD7477A/AD7478A are successive approximation, analog-to-digital converters based around a charge redistribution DAC. Figure 15 and Figure 16 show simplified schematics of the ADC. Figure 15 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on VIN. When the ADC starts a conversion (see Figure 16), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 17 shows the ADC transfer function. 02930-016 The AD7476A/AD7477A/AD7478A are fast, micropower, 12-/10-/8-bit, single-supply analog-to-digital converters (ADCs), respectively. The parts can be operated from a 2.35 V to 5.25 V supply. When operated from either a 5 V supply or a 3 V supply, the AD7476A/AD7477A/AD7478A are capable of throughput rates of 1 MSPS when provided with a 20 MHz clock. The AD7476A/AD7477A/AD7478A provide the user with an onchip, track-and-hold ADC and a serial interface housed in a tiny 6-lead SC70 package or in an 8-lead MSOP, offering the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the part but also provides the clock source for the successive-approximation ADC. The analog input range is 0 V to VDD. The ADC does not require an external reference or an on-chip reference. The reference for the AD7476A/AD7477A/AD7478A is derived from the power supply and, thus, gives the widest dynamic input range. The AD7476A/AD7477A/AD7478A also feature a powerdown option to allow power saving between conversions. The power-down feature is implemented across the standard serial interface, as described in the Modes of Operation section. 0V 1LSB ANALOG INPUT +VDD – 1LSB 02930-017 CIRCUIT INFORMATION Figure 17. AD7476A/AD7477A/AD7478A Transfer Characteristic AD7476A/AD7477A/AD7478A Data Sheet TYPICAL CONNECTION DIAGRAM Figure 18 shows a typical connection diagram for the AD7476A/ AD7477A/AD7478A. VREF is taken internally from VDD and, as such, VDD should be well decoupled. This provides an analog input range of 0 V to VDD. The conversion result is output in a 16-bit word with four leading zeros followed by the MSB of the 12-bit, 10-bit, or 8-bit result. The 10-bit result from the AD7477A is followed by two trailing zeros, and the 8-bit result from the AD7478A is followed by four trailing zeros. Alternatively, because the supply current required by the AD7476A/AD7477A/AD7478A is so low, a precision reference can be used as the supply source to the AD7476A/AD7477A/AD7478A. A REF193/REF195 voltage reference (REF193 for 3 V or REF195 for 5 V) can be used to supply the required voltage to the ADC (see Figure 18). This configuration is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 V or 3 V (for example, 15 V). The REF193/REF195 output a steady voltage to the AD7476A/ AD7477A/AD7478A. If the low dropout REF193 is used, the current it needs to supply to the AD7476A/AD7477A/AD7478A is typically 1.2 mA. When the ADC is converting at a rate of 1 MSPS, the REF193 needs to supply a maximum of 1.7 mA to the AD7476A/AD7477A/AD7478A. The load regulation of the REF193 is typically 10 ppm/mA (VS = 5 V), resulting in an error of 17 ppm (51 µV) for the 1.7 mA drawn from it. This corresponds to a 0.069 LSB error for the AD7476A with VDD = 3 V from the REF193, a 0.017 LSB error for the AD7477A, and a 0.0043 LSB error for the AD7478A. For applications where power consumption is a concern, use the power-down mode of the ADC and the sleep mode of the REF193/REF195 reference to improve power performance. See the Modes of Operation section. 3V 0.1µF 1µF TANT REF193 10µF 0.1µF 5V SUPPLY 680nF Table 7. AD7476A Typical Performance for Various Voltage References Reference Tied to VDD AD780 at 3 V REF193 AD780 at 2.5 V REF192 REF43 ANALOG INPUT Figure 19 shows an equivalent circuit of the analog input structure of the AD7476A/AD7477A/AD7478A. The two diodes, D1 and D2, provide ESD protection for the analog input. Ensure that the analog input signal never exceeds the supply rails by more than 300 mV. This causes the diodes to become forward-biased and start conducting current into the substrate. The maximum current these diodes can conduct without causing irreversible damage to the part is 10 mA. The Capacitor C1 in Figure 19 is typically about 6 pF and can primarily be attributed to pin capacitance. The Resistor R1 is a lumped component made up of the on resistance of a switch. This resistor is typically about 100 Ω. The Capacitor C2 is the ADC sampling capacitor and has a capacitance of 20 pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by use of a band-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, drive the analog input from a low impedance source. Large source impedances significantly affect the ac performance of the ADC, necessitating the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. VDD VDD VIN GND AD7476A/ AD7477A/ AD7478A SCLK D1 µC/µP SDATA R1 VIN CS 02930-018 0V TO V DD INPUT AD7476A SNR Performance (dB) 72.65 72.35 72.5 72.2 72.6 SERIAL INTERFACE Figure 18. REF193 as Power Supply to AD7476A/AD7477A/AD7478A C1 6pF C2 20pF D2 CONVERSION PHASE – SWITCH OPEN TRACK PHASE – SWITCH CLOSED Figure 19. Equivalent Analog Input Circuit Rev. G | Page 16 of 28 02930-019 1.2mA Table 7 provides typical performance data with various references used as a VDD source for a 100 kHz input tone at room temperature under the same setup conditions. Data Sheet AD7476A/AD7477A/AD7478A Table 8 provides typical performance data with various op amps used as the input buffer for a 100 kHz input tone at room temperature under the same setup conditions. Table 8. AD7476A Typical Performance with Various Input Buffers, VDD = 3 V Op Amp in the Input Buffer AD711 AD797 AD845 AD7476A SNR Performance (dB) 72.3 72.5 71.4 When no amplifier is used to drive the analog input, limit the source impedance to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases, degrading the performance (see Figure 13). DIGITAL INPUTS The digital inputs applied to the AD7476A/AD7477A/AD7478A are not limited by the maximum ratings that limit the analog input. Instead, the digital inputs applied can reach 7 V and are not restricted by the VDD + 0.3 V limit as on the analog input. For example, if operating the AD7476A/AD7477A/AD7478A with a VDD of 3 V, use 5 V logic levels on the digital inputs. However, note that the data output on SDATA still has 3 V logic levels when VDD = 3 V. Another advantage of SCLK and CS not being restricted by the VDD + 0.3 V limit is that power supply sequencing issues are avoided. If CS or SCLK are applied before VDD, there is no risk of latch-up as there would be on the analog input if a signal greater than 0.3 V were applied prior to VDD. Rev. G | Page 17 of 28 AD7476A/AD7477A/AD7478A Data Sheet MODES OF OPERATION The modes of operation for the AD7476A/AD7477A/AD7478A are selected by controlling the (logic) state of the CS signal during a conversion. There are two possible modes of operation: normal and power-down. The point at which CS is pulled high after the conversion has been initiated determines whether the AD7476A/ AD7477A/AD7478A enters power-down mode. Similarly, if already in power-down, CS can control whether the device returns to normal operation or remains in power-down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for different application requirements. NORMAL MODE This mode is intended for the fastest throughput rate performance. In normal mode, the user does not have to worry about any power-up times because AD7476A/AD7477A/AD7478A remain fully powered at all times. Figure 20 shows the general diagram of the operation of the AD7476A/AD7477A/AD7478A in this mode. The conversion is initiated on the falling edge of CS as described in the Serial Interface section. To ensure that the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge but before the end of the tCONVERT, the part remains powered up, but the conversion is terminated and SDATA goes back into three-state. For the AD7476A, 16 serial clock cycles are required to complete the conversion and access the complete conversion results. For the AD7477A and AD7478A, a minimum of 14 and 12 serial clock cycles are required to complete the conversion and access the complete conversion results, respectively. CS can idle high until the next conversion or idle low until CS returns high sometime prior to the next conversion (effectively idling CS low). Once a data transfer is complete (SDATA has returned to three-state), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again. POWER-DOWN MODE This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion, or a series of conversions is performed at a high throughput rate and the ADC is then powered down for a relatively long duration between these bursts of several conversions. When the AD7476A/AD7477A/AD7478A are in power-down, all analog circuitry is powered down. To enter power-down, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 22. Once CS has been brought high in this window of SCLKs, the part enters power-down, the conversion that was initiated by the falling edge of CS is terminated, and SDATA goes back into three-state. If CS is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power-down due to glitches on the CS line. In order to exit this mode of operation and power up the AD7476A/AD7477A/AD7478A again, a dummy conversion is performed. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up once 16 SCLKs have elapsed, and valid data results from the next conversion, as shown in Figure 24. If CS is brought high before the 10th falling edge of SCLK, then the AD7476A/AD7477A/AD7478A go back into power-down. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while CS is low. Although the device can begin to power up on the falling edge of CS, it powers down again on the rising edge of CS as long as it occurs before the 10th SCLK falling edge. POWER-UP TIME The power-up time of the AD7476A/AD7477A/AD7478A is 1 µs, meaning that with any frequency of SCLK up to 20 MHz, one dummy cycle is always sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC is fully powered up and the input signal is acquired properly. The quiet time, tQUIET, must still be allowed from the point where the bus goes back into three-state after the dummy conversion to the next falling edge of CS. When running at a 1 MSPS throughput rate, the AD7476A/AD7477A/AD7478A power up and acquire a signal within 0.5 LSB in one dummy cycle, that is, 1 µs. When powering up from the power-down mode with a dummy cycle, as in Figure 22, the track-and-hold that was in hold mode while the part was powered down returns to track mode after the first SCLK edge the part receives after the falling edge of CS. This is shown as Point A in Figure 22. Although at any SCLK frequency, one dummy cycle is sufficient to power up the device and acquire VIN, it does not necessarily mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire VIN fully; 1 µs is sufficient to power up the device and acquire the input signal. If, for example, a 5 MHz SCLK frequency is applied to the ADC, the cycle time becomes 3.2 µs. In one dummy cycle, 3.2 µs, the part powers up and VIN acquires fully. However, after 1 µs with a 5 MHz SCLK, only five SCLK cycles would have elapsed. At this stage, the ADC would fully power up and acquire the signal. In this case, the CS can be brought high after the 10th SCLK falling edge and brought low again after a time, tQUIET, to initiate the conversion. Rev. G | Page 18 of 28 Data Sheet AD7476A/AD7477A/AD7478A AD7476A/AD7477A/AD7478A CS 1 10 12 14 16 SDATA 02930-020 SCLK VALID DATA Figure 20. Normal Mode Operation CS 1 10 2 12 14 16 THREE-STATE SDATA 02930-021 SCLK Figure 21. Entering Power-Down Mode THE PART IS FULLY POWERED UP WITH VIN FULLY ACQUIRED THE PART BEGINS TO POWER UP CS A1 10 12 14 1 16 16 SDATA VALID DATA INVALID DATA 02930-022 SCLK Figure 22. Exiting Power-Down Mode When power supplies are first applied to the AD7476A/AD7477A/ AD7478A, the ADC can power up in either the power-down or normal modes. Because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. Likewise, if it is intended to keep the part in the power-down mode while not in use and the user wishes the part to power up in power-down mode, the dummy cycle can be used to ensure that the device is in power-down by executing a cycle such as that shown in Figure 22. Once supplies are applied to the AD7476A/AD7477A/AD7478A, the power-up time is the same as that when powering up from the power-down mode. It takes approximately 1 μs to power up fully if the part powers up in normal mode. It is not necessary to wait 1 μs before executing a dummy cycle to ensure the desired mode of operation. Instead, a dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is performed directly after the dummy conversion, ensure that an adequate acquisition time has been allowed. As mentioned earlier, when powering up from the power-down mode, the part returns to track upon the first SCLK edge applied after the falling edge of CS. However, when the ADC initially powers up after supplies are applied, the track-and-hold is already in track. This means, assuming one has the facility to monitor the ADC supply current, if the ADC powers up in the desired mode of operation and thus a dummy cycle is not required to change the mode, a dummy cycle is not required to place the track-and-hold into track. Rev. G | Page 19 of 28 AD7476A/AD7477A/AD7478A Data Sheet POWER VS. THROUGHPUT RATE For example, if the AD7476A/AD7477A/AD7478A operate in a continuous sampling mode with a throughput rate of 100 kSPS and an SCLK of 20 MHz (VDD = 5 V) and the devices are placed in the power-down mode between conversions, the power consumption is calculated as follows: The power dissipation during normal operation is 17.5 mW (VDD = 5 V). If the power-up time is one dummy cycle, that is, 1 μs, and the remaining conversion time is another cycle, that is, 1 μs, then the AD7476A/AD7477A/AD7478A dissipate 17.5 mW for 2 μs during each conversion cycle. If VDD = 3 V, SCLK = 20 MHz, and the devices are again in power-down mode between conversions, then the power dissipation during normal operation is 5.1 mW. Thus, the AD7476A/AD7477A/AD7478A dissipate 5.1 mW for 2 μs during each conversion cycle. With a throughput rate of 100 kSPS, the average power dissipated during each cycle is (2/10) × (5.1 mW) = 1.02 mW. Figure 23 shows the power vs. the throughput rate when using the power-down mode between conversions with both 5 V and 3 V supplies. The power-down mode is intended for use with throughput rates of approximately 333 kSPS or less, because at higher sampling rates, the power-down mode produces no power savings. If the throughput rate is 100 kSPS, the cycle time is 10 μs, then the average power dissipated during each cycle is (2/10) × (17.5 mW) = 3.5 mW. 100 VDD = 5V, SCLK = 20MHz 10 POWER (mW) By using the power-down mode on the AD7476A/AD7477A/ AD7478A when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 23 shows that as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption over time drops accordingly. 1 VDD = 3V, SCLK = 20MHz 0.01 02930-023 0.1 0 50 100 200 250 150 THROUGHPUT (kSPS) Figure 23. Power vs. Throughput Rev. G | Page 20 of 28 300 350 Data Sheet AD7476A/AD7477A/AD7478A SERIAL INTERFACE Figure 24, Figure 25, and Figure 26 show the detailed timing diagrams for serial interfacing to the AD7476A, AD7477A, and AD7478A, respectively. The serial clock provides the conversion clock and also controls the transfer of information from the AD7476A/AD7477A/AD7478A during conversion. falling edge, as shown in Figure 24. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7476A. For the AD7477A, the conversion requires 14 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the trackand-hold goes back into track on the next rising edge as shown at Point B in Figure 25. If the rising edge of CS occurs before 14 SCLKs have elapsed, the conversion is terminated and the SDATA line goes back into three-state. If 16 SCLKs are considered in the cycle, SDATA returns to three-state on the 16th SCLK falling edge, as shown in Figure 25. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode and takes the bus out of three-state; the analog input is sampled at this point. Also, the conversion is initiated at this point. For the AD7476A, the conversion requires 16 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the trackand-hold goes back into track on the next SCLK rising edge, as shown in Figure 24 at Point B. On the 16th SCLK falling edge, the SDATA line goes back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion is terminated and the SDATA line goes back into three-state; otherwise, SDATA returns to three-state on the 16th SCLK For the AD7478A, the conversion requires 12 SCLK cycles to complete. The track-and-hold goes back into track on the rising edge after the 11th falling edge, as shown in Figure 26 at Point B. If the rising edge of CS occurs before 12 SCLKs have elapsed, the conversion is terminated and the SDATA line goes back into three-state. If 16 SCLKs are considered in the cycle, SDATA returns to three-state on the 16th SCLK falling edge, as shown in Figure 26. t1 CS tCONVERT t6 SCLK 3 2 1 t3 SDATA THREESTATE Z 4 B t4 ZERO ZERO 13 5 14 t7 ZERO DB11 15 16 t5 DB10 DB2 t8 DB1 DB0 tQUIET THREE-STATE 4 LEADING ZEROS 02930-024 t2 1/THROUGHPUT Figure 24. AD7476A Serial Interface Timing Diagram t1 CS tCONVERT t6 1 2 4 3 t3 SDATA THREE-STATE Z 5 t4 ZERO ZERO ZERO DB9 13 B 15 14 t5 t7 DB8 DB0 4 LEADING ZEROS ZERO 16 t8 ZERO 2 TRAILING ZEROS 1/ THROUGHPUT Figure 25. AD7477A Serial Interface Timing Diagram Rev. G | Page 21 of 28 tQUIET THREE-STATE 02930-025 t2 SCLK AD7476A/AD7477A/AD7478A Data Sheet t1 CS tCONVERT B t6 Z ZERO ZERO ZERO 13 12 15 14 16 t8 t5 t7 t4 t3 SDATA THREE-STATE 11 4 3 2 1 DB7 ZERO ZERO ZERO ZERO 4 TRAILING ZEROS 4 LEADING ZEROS tQUIET THREE-STATE 02930-026 t2 SCLK 1/ THROUGHPUT Figure 26. AD7478A Serial Interface Timing Diagram AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE CS going low clocks out the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges beginning with the second leading zero. Thus, the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. For the AD7476A, the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. For the AD7478A, if CS is brought high in the 12th rising edge after four leading zeros and eight bits of the conversion have been provided, the part can achieve a 1.2 MSPS throughput rate. For the AD7478A, the track-and-hold goes back into track in the 11th rising edge. In this case, a fSCLK = 20 MHz and a throughput of 1.2 MSPS give a cycle time of t2 + 10.5(1/fSCLK) + tACQ = 833 ns In applications with a slower SCLK, it is possible to read in data on each SCLK rising edge. In this case, the first falling edge of SCLK clocks out the second leading zero, which can be read in the first rising edge. However, the first leading zero that was clocked out when CS went low will be missed, unless it was not read in the first falling edge. The 15th falling edge of SCLK clocks out the last bit and it can be read in the 15th rising SCLK edge. With t2 = 10 ns min, this leaves tACQ to be 298 ns. This 298 ns satisfies the requirement of 225 ns for tACQ. From Figure 27, tACQ is comprised of 0.5 (1/fSCLK) + t8 + tQUIET where t8 = 36 ns maximum. This allows a value of 237 ns for tQUIET, satisfying the minimum requirement of 50 ns. If CS goes low just after one SCLK falling edge has elapsed, CS clocks out the first leading zero as it did before, and it can be read in the SCLK rising edge. The next SCLK falling edge clocks out the second leading zero, and it can be read in the following rising edge. t1 CS tCONVERT t2 B 2 1 4 3 12 11 5 t8 10.5(1/fSCLK) SDATA THREE-STATE Z ZERO ZERO ZERO 4 LEADING ZEROS DB7 tQUIET tACQ DB6 DB0 1/THROUGHPUT Figure 27. AD7478A in a 12 SCLK Cycle Serial Interface Rev. G | Page 22 of 28 THREE-STATE 02930-027 SCLK Data Sheet AD7476A/AD7477A/AD7478A MICROPROCESSOR INTERFACING The serial interface on the AD7476A/AD7477A/AD7478A allows the part to be connected directly to a range of different microprocessors. This section explains how to interface the AD7476A/AD7477A/AD7478A with some of the more common microcontroller and DSP serial interface protocols. AD7476A/ AD7477A/ AD7478A1 ADSP-21811 SCLK SDATA CS AD7476A/AD7477A/AD7478A TO ADSP-2181 INTERFACE SCLK DR RFS The ADSP-2181 and other DSPs in its family are interfaced directly to the AD7476A/AD7477A/AD7478A without any glue logic required. Set up the SPORT control register as follows: TFSW = RFSW = 1, alternate framing INVRFS = INVTFS = 1, active low frame signal DTYPE = 00, right justify data ISCLK = 1, internal serial clock TFSR = RFSR = 1, frame every word IRFS = 0, sets up RFS as an input ITFS = 1, sets up TFS as an output SLEN = 1111, 16 bits for the AD7476A SLEN = 1101, 14 bits for the AD7477A SLEN = 1011, 12 bits for the AD7478A To implement the power-down mode, set SLEN to 0111 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 28. The ADSP-2181 has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode, and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS, and, as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC and, under certain conditions, equidistant sampling may not be achieved. 1ADDITIONAL PINS OMITTED FOR CLARITY. 02930-029 TFS Figure 28. Interfacing to the ADSP-2181 The timer registers, for example, are loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS controls the RFS and, thus, the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, that is, TX0 = AX0, the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high before transmission starts. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data can be transmitted or it can wait until the next clock edge. For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the Value 3, an SCLK of 2 MHz is obtained and eight master clock periods will elapse for every one SCLK period. If the timer registers are loaded with the Value 803, 100.5 SCLKs occur between interrupts and, subsequently, between transmit instructions. This situation results in nonequidistant sampling as the transmit instruction is occurring on an SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, equidistant sampling is implemented by the DSP. Rev. G | Page 23 of 28 AD7476A/AD7477A/AD7478A Data Sheet In summary: The connection diagram in Figure 29 shows how the AD7476A/AD7477A/AD7478A can be connected to the SSI (synchronous serial interface) of the DSP563xx family of DSPs from Motorola. The SSI is operated in synchronous and normal mode (SYN 1 = and MOD = 0 in Control Register B, CRB) with internally generated word length frame sync for both Tx and Rx (Bit FSL1 = 0 and Bit FSL0 = 0 in CRB). Set the word length in Control Register A (CRA) to 16 by setting Bit WL2 = 0, Bit WL1 = 1, and Bit WL0 = 0 for the AD7476A. The word length for the AD7478A can be set to 12 bits (WL2 = 0, WL1 = 0, and WL0 = 1). This DSP does not offer the option for a 14-bit word length, so the AD7477A word length is set up to 16 bits, the same as the AD7476A. For the AD7477A the conversion process uses 16 SCLK cycles, with the last two clock periods clocking out two trailing zeros to fill the 16-bit word. MOD = 0 SYN = 1 WL2, WL1, and WL0 depend on the word length FSL1 = 0 and FSL0 = 0 FSP = 1, negative frame sync SCD2 = 1 SCKD = 1 SHFD = 0 Note that for signal processing applications, it is imperative that the frame synchronization signal from the DSP563xx provide equidistant sampling. AD7476A/ AD7477A AD7478A1 To implement the power-down mode on the AD7476A/AD7477A/ AD7478A, the word length can be changed to eight bits by setting Bit WL2 = 0, Bit WL1 = 0, and Bit WL0 = 0 in CRA. The FSP bit in the CRB register can be set to 1, meaning the frame goes low and a conversion starts. Likewise, by means of the Bit SCD2, Bit SCKD, and Bit SHFD in the CRB register, it establishes that Pin SC2 (the frame sync signal) and Pin SCK in the serial port are configured as outputs and the MSB is shifted first. Rev. G | Page 24 of 28 DSP563xx1 SCLK SCK SDATA SRD CS SC2 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 29. Interfacing to the DSP563xx 02930-030 AD7476A/AD7477A/AD7478A TO DSP563xx INTERFACE Data Sheet AD7476A/AD7477A/AD7478A APPLICATION HINTS Avoid running digital lines under the device as these couple noise onto the die. Allow the analog ground plane to run under the AD7476A/AD7477A/AD7478A in order to avoid noise coupling. Use as large a trace as possible on the power supply lines to the AD7476A/AD7477A/AD7478A to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals like clocks with digital grounds to avoid radiating noise to other sections of the board, and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Figure 30. Recommended Supply Decoupling Scheme for the SC70 Package As can be seen in Figure 31, for the MSOP, the decoupling capacitor has been placed as close as possible to the IC with short track lengths to VDD and GND pins. The decoupling capacitor can also be placed on the underside of the PCB directly underneath the IC, between the VDD and GND pins attached by vias. This method is not recommended on PCBs above a standard 1.6 mm thickness. The best performance is realized with the decoupling capacitor on the top of the PCB next to the IC. Similarly, for the SC70 package, locate the decoupling capacitor as close as possible to the VDD and the GND pins. Because of its pinout, that is, VDD being next to GND, the decoupling capacitor can be placed extremely close to the IC. The decoupling capacitor can be placed on the underside of the PCB directly under the VDD and GND pins, but the best performance is achieved with the decoupling capacitor on the same side as the IC. Good decoupling is also very important. Decouple the supply with, for instance, a 680 nF 0805 capacitor to GND. When using the SC70 package in applications where the size of the components is of concern, a 220 nF 0603 capacitor, for example, can be used instead. However, in that case, the decoupling may not be as effective, resulting in an approximate SINAD degradation of 0.3 dB. To achieve the best performance from these decoupling components, the user should endeavor to keep the distance between the decoupling capacitor and the VDD and GND pins to a minimum with short track lengths connecting the respective pins. Figure 30 and Figure 31 and show the recommended positions of the decoupling capacitor for the SC70 package and MSOP, respectively. Rev. G | Page 25 of 28 02930-031 Design the printed circuit board that houses the AD7476A/ AD7477A/AD7478A such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes because it gives the best shielding. Join digital and analog ground planes at only one place. If the AD7476A/AD7477A/ AD7478A is in a system where multiple devices require an AGND to DGND connection, make the connection at one point only, a star ground point that is established as close as possible to the AD7476A/AD7477A/AD7478A. 02930-032 GROUNDING AND LAYOUT Figure 31. Recommended Supply Decoupling Scheme for the AD7476A/AD7477A/AD7478A MSOP AD7476A/AD7477A/AD7478A Data Sheet OUTLINE DIMENSIONS 2.20 2.00 1.80 6 5 4 1 2 3 2.40 2.10 1.80 0.65 BSC 1.30 BSC 1.00 0.90 0.70 0.40 0.10 1.10 0.80 0.10 MAX COPLANARITY 0.10 0.46 0.36 0.26 0.22 0.08 SEATING PLANE 0.30 0.15 072809-A 1.35 1.25 1.15 COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 32. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 15° MAX 1.10 MAX 0.15 0.05 COPLANARITY 0.10 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA 0.80 0.55 0.40 10-07-2009-B 0.95 0.85 0.75 Figure 33. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 AD7476AAKSZ-500RL7 AD7476AAKSZ-REEL7 AD7476ABKSZ-500RL7 AD7476ABKSZ-REEL7 AD7476ABRM AD7476ABRM-REEL7 AD7476ABRMZ AD7476ABRMZ-REEL AD7476ABRMZ-REEL7 AD7476AWYRMZ AD7476AWYRMZ-RL7 AD7476AYKSZ-500RL7 AD7476AYKSZ-REEL7 AD7476AYRMZ AD7476AYRMZ-REEL7 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Linearity Error (LSB) 3 ±0.75 typical ±0.75 typical ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum Rev. G | Page 26 of 28 Package Description 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 6-Lead SC70 6-Lead SC70 8-Lead MSOP 8-Lead MSOP Package Option 4 KS-6 KS-6 KS-6 KS-6 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 KS-6 KS-6 RM-8 RM-8 Branding C3V C3V C3W C3W CEY CEY C3W C3W C3W C45 C45 C45 C45 C45 C45 Data Sheet Model 1, 2 AD7477AAKSZ-500RL7 AD7477AAKSZ-REEL AD7477AARMZ AD7477AARMZ-REEL AD7477AARMZ-REEL7 AD7477AWARMZ AD7477AWARMZ-RL AD7478AAKSZ-500RL7 AD7478AAKSZ-REEL7 AD7478AARM AD7478AARMZ AD7478AARMZ-REEL7 AD7478AWARMZ AD7478AWARMZ-RL AD7476A/AD7477A/AD7478A Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Linearity Error (LSB) 3 ±0.5 maximum ±0.5 maximum ±0.5 maximum ±0.5 maximum ±0.5 maximum ±0.5 maximum ±0.5 maximum ±0.3 maximum ±0.3 maximum ±0.3 maximum ±0.3 maximum ±0.3 maximum ±0.3 maximum ±0.3 maximum Package Description 6-Lead SC70 6-Lead SC70 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 6-Lead SC70 6-Lead SC70 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Package Option 4 KS-6 KS-6 RM-8 RM-8 RM-8 RM-8 RM-8 KS-6 KS-6 RM-8 RM-8 RM-8 RM-8 RM-8 Branding C3X C3X C3X C3X C3X C3X C3X C48 C48 CJZ C48 C48 C48 C48 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. 3 Linearity error here refers to integral nonlinearity. 4 KS = SC70; RM = MSOP. 1 2 AUTOMOTIVE PRODUCTS The AD7476AWYRMZ, AD7476AWYRMZ-RL7, AD7477AWARMZ, AD7477AWARMZ-RL, AD7478AWARMZ, and AD7478AWARMZ-RL models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. G | Page 27 of 28 AD7476A/AD7477A/AD7478A NOTES ©2002–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02930-0-1/16(G) Rev. G | Page 28 of 28