AD7530JN

OBS OLE TE SPECIFICA TIONS (Voo = +15, VREF = +10V, TA = +25°C unlessotherwise noted) PARAMETER DC ACCURACY Resolution AD7531 AD7530 (Note Relative Accuracy ( 1) AD7530J AD7530K AD7530L Nonlinearity Tempco Gain Error Gain Error Tempco Output Leakage Current (Either Output) 10 Bits 0.2% of FSR max (8 Bit) 0.1 % of FSR max (9 Bit) 0.05% of FSR max (10 Bit) 2ppm of FSR/ C max 0.3% of FSR typ IOppm of FSR/C max 300nA max 50ppm of FSR/% Power Supply Rejection AC ACCURACY Output Current Settling Time typ OBS 'oUT! 'oun Output Noise (Both Outputs) To 0.05% All digital inputs low to high and high to low VREF = 20V p-p, 50kHz. All digital inputs low * 37pF typ 120pF typ Input Input 1J.LAtyp Binary * * * All digital inputs high * All digital input TE * * * * * * * * +5V to +15V 5nA typ 2mA max 20mW typ Total Dissipation Over specified temperature range. OLE High State Threshold POWER REQUIREMENTS Power Supply Voltage Range IDD * Over specified Over specified -2-~- - temperature temperatUre All digital inputs All digital inputs I Full scale range (FSR) is lOV for unipolar mode and :t lOV for bipolar mode. 2To minimize feedthrough with the ceramic package, the user must ground the metal lid. If the lid is not grounded, then the feedthrough is lOmV typical and 3OmV maximum. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. notice. low range range See Tables I & II NOTES *Same specifications as for AD7530. Specifications subject to change without < VREF < +lOV * :t1mA 120pF typ 37pF typ 0.8V max 2.4V min (low to high state) * -10V * :t10V :t1mA 10kD typ Equivalent to 10kD Johnson noise typ DIGITAL INPUTS (Note 3) Low State Threshold * * * * * * * 10mV p-p max REFERENCE INPUT Input Range Input Resistance ANALOG OUTPUT Output Current Range (Both Outputs) Output Capacitance 'oUT! 'oun 12 Bits * * 500ns typ Feedthrough Error (Note 2) Current Coding TEST CONDITIONS at GND high or low . ".'.~- . '" "co:'~~~~k~~~4~l~~~:;d{ ABSOLUTE (T A MAXIMUM = +2So C DIGITAL RATINGS unless otherwise i"i:lfr1~,~;~1ti¥i1/ -:;:';;, . noted) VDD(toGnd) ,. +17V VREF(toGnd) , :t2SV Digital Input Voltage Range. . , . . . . . . . . . . . VDD to Gnd Voltage at Pin I, Pin 2 . . . . . . . . . . . . . . . -IOOmV to VDD Power Dissipation (package) upto+7SoC Operating Temperature INPUT ANALOG -VREF (I - 2-1°) 1000000001 -VREF (1/2 01 111 1 1 111 -VREF (112 - 2-1°) -VREF (2'10) 0000000000 0 NOTE: 1 LSB = 2-10 Table I. Code Table OBS CAUTION: 1. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF' 2. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused units in conductive foam at all times. + 2-1°) -VREF 2 0000000001 IN,KN,LNVersions ,., Oto+7SoC JD, KD, LD Versions. . . . . . , . . . . . . . -2SoC to +8SoC Storage Temperature. . . . . . . . . . . . . . . . -6So C to +ISO°C OUTPUT 1111111111 1000000000 4S0mW ," VREF - Unipolar Binary Operation BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) Figure 2 and Table II illustrate the circuitry and code relationship for bipolar operation. With a dc reference (positive or negative polarity) or an ac reference the circuit provides offset binary operation. Protection Schottky shown in Figure 2 is not required when using TRIFET output amplifiers such as the ADS42 or ADS44. OLE APPLICA nONS With the DAC register loaded to 10 0000 0000, adjust RI for VOUT = OV (alternatively, one can omit RI and R2 and adjust the ratio of R3 to R4 for VOUT = OV). Full Scale trimming can be accomplished by adjusting the amplitude of VREF or by varying the value of RS. UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICA TION) Figure I shows the analog circuit connections required for unipolar binary (2-quadrant multiplication) operation. The logic inputs are omitted for clarity. With a dc reference voltage or current (positive or negative polarity) applied at pin IS, the circuit is a unipolar DI A converter. With an ac reference voltage or current the circuit provides 2-quadrant multiplication (digitally controlled attenuation). The inputloutput relationship is shown in Table I. Protection Schottky shown in Figure I is not required when using TRIFET output amplifiers such as the ADS42 or ADS44. RI provides full scale trim capability [i.e.-load TE As in unipolar operation, Al must be chosen for low Vas and low lB. R3, R4 and R5 must be selected for matching and tracking. Mismatch of 2R3 to R4 causes both offset and Full Scale error. Mismatch of RS to R4 or 2R3 causes Full Scale error. Cl phase compensation (lOpF to 2SpF) may be required for stability. .1OV v." voo z 0 w ~ z a: c.. -4-