CMOS,
12-Bit, Monolithic Multiplying DAC
AD7541A
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Improved version of the obsoleted product, AD7541
Full 4 quadrant multiplication
12-bit linearity (endpoint)
All parts guaranteed monotonic
TTL/CMOS compatible
Protection Schottky diodes not required
Low logic input leakage
VREF
10kΩ
10kΩ
10kΩ
20kΩ
20kΩ
20kΩ
20kΩ
S1
S2
S3
S12
20kΩ
OUT 2
OUT 1
10kΩ
BIT 3
RFEEDBACK
BIT 12 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
APPLICATIONS
LOGIC: A SWITCH IS CLOSED TO IOUT 1 FOR
ITS DIGITAL INPUT IN A HIGH STATE.
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
00718-001
BIT 1 (MSB) BIT 2
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7541A is a high performance, 12-bit monolithic
multiplying digital-to-analog converter (DAC). It is fabricated
using advanced, low noise, thin film, complementary metaloxide semiconductor (CMOS) technology. The AD7541A is
available in 18-lead PDIP, 18-lead PLCC, and 18-lead SOIC
packages.
Compatibility—The AD7541A can be used as a direct replacement
for any AD7541 type device. As with the AD7541, The digital
inputs on the AD7541A are TTL/CMOS compatible. They have
a ±1 µA maximum input current requirement so that they do
not load the driving circuitry.
The AD7541A is functionally and pin compatible with the
industry standard AD7541, and it offers improved specifications
and performance over the obsolete product, AD7541. The
improved design ensures that the AD7541A is latch-up free;
therefore, no output protection Schottky diodes are required.
The AD7541A uses laser wafer trimming to provide full 12-bit
endpoint linearity with several high performance grades.
Improvements—The AD7541A offers the following improved
specifications over the AD7541:
1.
2.
3.
4.
5.
6.
Rev. C
Gain error for all grades are reduced with premium grade
versions having a maximum gain error of ±3 LSB.
Gain error temperature coefficient are reduced to
2 ppm/°C typical and 5 ppm/°C maximum.
Digital-to-analog charge injection energy for the AD7541A
is typically 20% less than the standard AD7541.
Latch-up proof.
Laser wafer trimming provides 1/2 LSB maximum
differential nonlinearity for top grade devices over the
operating temperature range (vs. 1 LSB on previous AD7541
devices).
All grades are guaranteed monotonic to 12 bits over the
operating temperature range.
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AD7541A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .......................................................................................7
Applications ....................................................................................... 1
Theory of Operation .........................................................................8
Functional Block Diagram .............................................................. 1
Equivalent Circuit Analysis .........................................................8
General Description ......................................................................... 1
Applications Information .................................................................9
Product Highlights ........................................................................... 1
Unipolar Binary Operation (Two Quadrant Multiplication) ......9
Revision History ............................................................................... 2
Bipolar Operation (Four Quadrant Multiplication) .............. 10
Specifications..................................................................................... 3
Applications Hints ...................................................................... 11
AC Performance Characteristics ................................................ 4
Single-Supply Operation ........................................................... 11
Absolute Maximum Ratings ............................................................ 5
Supplemental Application Material ......................................... 11
ESD Caution .................................................................................. 5
Outline Dimensions ....................................................................... 12
Pin Configurations ........................................................................... 6
Ordering Guide .......................................................................... 13
REVISION HISTORY
3/2017—Rev. B to Rev. C
Updated Format .................................................................. Universal
Deleted E-20A and Q-18 .............................................. Throughout
Added Applications Section ............................................................ 1
Changes to the General Description Section ................................ 1
Changes to Figure 7 .......................................................................... 9
Changes to Bipolar Operation (Four Quadrant Multiplication)
Section, Figure 8, and Figure 9 ..................................................... 10
Changes to Figure 10 ...................................................................... 11
Changes to Output Offset Section, Temperature Coefficient
Section, Single-Supply Operation Section, and Supplemental
Application Material Section ........................................................ 11
Update Outline Dimensions ......................................................... 13
Changes to Ordering Guide .......................................................... 14
Rev. C | Page 2 of 13
Data Sheet
AD7541A
SPECIFICATIONS
VDD = 15 V, VREF = 10 V, OUT 1 = OUT 2 = GND = 0 V, unless otherwise noted. Temperature range is as follows for the J version and the
K version: 0°C to +70°C.
Table 1.
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain TC 1
ΔGain/ΔTemperature
Output Leakage Current
OUT 1 (Pin 1)
OUT 2 (Pin 2)
REFERENCE INPUT
Input Resistance (Pin 17 to
GND)
DIGITAL INPUTS
Input Voltage
High, VIH
Low, VIL
Input Current, IIN
Input Capacitance, CIN1
POWER SUPPLY REJECTION
ΔGain/ΔVDD
POWER SUPPLY
VDD Range
IDD
1
Version
TA = 25°C
TA = TMIN, TMAX
Unit
All
J
K
J
K
J
K
12
±1
±1/2
±1
±1/2
±6
±3
12
±1
±1/2
±1
±1/2
±8
±5
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
All
5
5
ppm/°C max
Typical value is 2 ppm/°C
J, K
J, K
±5
±5
±10
±10
nA max
nA max
All digital inputs = 0 V
All digital inputs = VDD
All
7 to 18
7 to 18
kΩ min/max
Typical input resistance = 11 kΩ; typical
input resistance TC = −300 ppm/°C
All
All
All
2.4
0.8
±1
2.4
0.8
±1
V min
V max
µA max
All
8
8
pF max
Logic inputs are MOS gates;
IIN typical (25°C) = 1 nA
VIN = 0 V
All
±0.01
±0.02
% per % max
ΔVDD = ±5%
All
All
5 to 16
2
100
5 to 16
2
500
V min/V max
mA max
µA max
Accuracy is not guaranteed over this range
All digital inputs VIL or VIH
All digital inputs 0 V or VDD
Guaranteed by design but not production tested.
Rev. C | Page 3 of 13
Test Conditions/Comments
±1 LSB = ±0.024% of full scale
±1/2 LSB = ±0.012% of full scale
All grades guaranteed monotonic to
12 bits, TMIN to TMAX.
Measured using internal RFEEDBACK and
includes effect of leakage current and gain
temperature coefficient (TC); gain error can
be trimmed to zero
AD7541A
Data Sheet
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance only and are not subject to test. VDD = 15 V, VIN = 10 V, and OUT 1 = OUT 2 = GND = 0 V,
unless otherwise noted. Temperature range is as follows for the J version and the K version: 0°C to +70°C.
Table 2.
Parameter
PROPAGATION DELAY (FROM DIGITAL INPUT
CHANGE TO 90% OF FINAL ANALOG OUTPUT)
DIGITAL-TO-ANALOG GLITCH IMPULSE
TA = 25°C
100
1000
nV-sec typ
MULTIPLYING FEEDTHROUGH ERROR (VREF to
OUT 1)
OUTPUT CURRENT SETTLING TIME
1.0
mV p-p typ
0.6
µs typ
To 0.01% of full-scale range; OUT 1 load = 100 Ω,
CEXT = 13 pF; digital inputs = 0 V to VDD or VDD to 0 V
pF max
pF max
pF max
pF max
Digital inputs = VIH
Digital inputs = VIL
Digital inputs = VIH
Digital inputs = VIL
OUTPUT CAPACITANCE
COUT 1 (Pin 1)
COUT 2 (Pin 2)
200
70
70
200
TA = TMIN,TMAX
200
70
70
200
Rev. C | Page 4 of 13
Unit
ns typ
Test Conditions/Comments
OUT 1 load = 100 Ω, CEXT = 13 pF; digital inputs
= 0 V to VDD or VDD to 0 V
VREF = 0 V; all digital inputs 0 V to VDD or VDD to 0 V;
measured using Model 50K as output amplifier
VREF = ±10 V, 10 kHz sine wave
Data Sheet
AD7541A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VREF to GND
VRFEEDBACK to GND
Digital Input Voltage to GND
OUT 1, OUT 2 to GND
Power Dissipation (Any Package)
To 75°C
Derates Above 75°C
Operating Temperature Range
Commercial (J Version/K Version)
Storage Temperature
Lead Temperature (Soldering, 10 secs)
Rating
17 V
±25 V
±25 V
−0.3 V, VDD + 0.3 V
−0.3 V, VDD + 0.3 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
450 mW
6 mW/°C
0°C to 70°C
−65°C to +150°C
300°C
Rev. C | Page 5 of 13
AD7541A
Data Sheet
PIN CONFIGURATIONS
OUT 1 1
18
RFEEDBACK
OUT 2 2
17
VREF IN
GND 3
BIT 1 (MSB) 4
AD7541A
BIT 2 5
16
VDD (+)
15
BIT 12 (LSB)
BIT 4 7
12
BIT 8
BIT 5 8
11
BIT 8
BIT 6 9
10
BIT 7
00718-002
14 BIT 11
TOP VIEW
(Not to Scale)
13 BIT 10
BIT 3 6
NC
RFEEDBACK
3
2
1
20 19
GND 4
BIT 1 (MSB) 5
AD7541A
BIT 2 6
TOP VIEW
(Not to Scale)
BIT 3 7
VDD
BIT 12 (LSB)
16
BIT 11
15
BIT 10
14
BIT 9
BIT 8
BIT 6
NC
10 11 12 13
BIT 7
9
BIT 5
BIT 4 8
18
17
NOTES
1. NC = NO CONNECT.
Figure 3. 20-Lead PLCC Pin Configuration
Rev. C | Page 6 of 13
00718-003
VREF
OUT 2
OUT 1
Figure 2. 18-Lead PDIP and 18-Lead SOIC Pin Configuration
Data Sheet
AD7541A
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero scale and full scale, and it is expressed in % of
full-scale range or (sub) multiples of 1 LSB.
Output Leakage Current
Current that appears at OUT I with the DAC loaded to all 0s or
at OUT 2 with the DAC loaded to all 1s.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal l LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.
Output Current Settling Time
Time required for the output function of the DAC to settle to
within 1/2 LSB for a given digital input stimulus, that is, 0 to
full scale.
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output. For the AD7541A, ideal
maximum output is
−(4095/4096)(VREF)
Gain error is adjustable to zero using external trims, as shown
in Figure 7, Figure 8, and Figure 9.
Multiplying Feedthrough Error
AC error due to capacitive feedthrough from the VREF terminal
to OUT 1 with the DAC loaded to all 0s.
Propagation Delay
The propagation delay is a measure of the internal delay of the
circuit, and it is measured from the time a digital input changes
to the point at which the analog output at OUT 1 reaches 90%
of its final value.
Digital-to-Analog Glitch Impulse (QDA)
The QDA is a measure of the amount of charge injected from
the digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV-sec
and is measured with VREF = GND and a Model 50K as the
output op amp, C1 (phase compensation) = 0 pF.
Rev. C | Page 7 of 13
AD7541A
Data Sheet
THEORY OF OPERATION
The simplified digital-to-analog circuit is shown in Figure 4. An
inverted R-2R ladder structure was used, meaning the binarily
weighted currents are switched between the OUT 1 and OUT 2
bus lines, thus maintaining a constant current in each ladder leg
independent of the switch state.
10kΩ
10kΩ
20kΩ
20kΩ
20kΩ
20kΩ
S1
S2
S3
S12
20kΩ
OUT 2
OUT 1
10kΩ
BIT 3
RFEEDBACK
BIT 12 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
LOGIC: A SWITCH IS CLOSED TO IOUT 1 FOR
ITS DIGITAL INPUT IN A HIGH STATE.
R
00718-005
BIT 1 (MSB) BIT 2
RFEEDBACK
OUT 1
Figure 4. Functional Diagram (Inputs High)
The input resistance at VREF (see Figure 4) is always equal to
RLDR, which is the R-2R ladder characteristic resistance and is
equal to value R. Because RIN at the VREF pin is constant, the
reference terminal can be driven by a reference voltage or a
reference current, ac or dc, of positive or negative polarity. If a
current source is used, a low temperature coefficient external
RFEEDBACK is recommended to define the scale factor.
VREF
ILEAKAGE
70pF
ILEAKAGE
200pF
R ≈ 15kΩ
IREF
OUT 2
I/4096
00718-006
10kΩ
The equivalent circuits for all digital inputs low and all digital
inputs high are shown in Figure 5 and Figure 6. In Figure 5 with
all digital inputs low, the reference current is switched to OUT 2.
The current source, ILEAKAGE, is composed of surface and junction
leakages to the substrate, while the I/4096 current source represents a
constant 1-bit current drain through the termination resistor on
the R-2R ladder. The on capacitance of the output N-channel
switch is 200 pF, as shown on the OUT 2 terminal. The off
switch capacitance is 70 pF, as shown on the OUT 1 terminal.
Analysis of the circuit for all digital inputs high, as shown in
Figure 5, is similar to Figure 4; however, the on switches are
now on the OUT 1 terminal; therefore, 200 pF at that terminal.
Figure 5. DAC Equivalent Circuit, All Digital Inputs Low
R
VREF
RFEEDBACK
R ≈ 15kΩ
IREF
OUT 1
I/4096
ILEAKAGE
200pF
ILEAKAGE
70pF
OUT 2
Figure 6. DAC Equivalent Circuit All Digital Inputs High
Rev. C | Page 8 of 13
00718-007
VREF
EQUIVALENT CIRCUIT ANALYSIS
Data Sheet
AD7541A
APPLICATIONS INFORMATION
UNIPOLAR BINARY OPERATION (TWO QUADRANT
MULTIPLICATION)
Figure 7 shows the analog circuit connections required for
unipolar binary (two quadrant multiplication) operation. With
a dc reference voltage or current (positive or negative polarity)
applied at Pin 17, the circuit is a unipolar DAC. With an ac
reference voltage or current, the circuit provides two quadrant
multiplication (digitally controlled attenuation). The input/output
relationship is shown in Table 5.
VDD
R21
16
R11
VDD RFEEDBACK
OUT 1 1
17 VREF IN
AD7541A
PIN 4 TO
PIN 15
4
1REFER
VOUT
OUT 2 2
GND
DIGITAL
GROUND
ANALOG
COMMON
TO TABLE 4
JN
100 Ω
47 Ω
KN
100 Ω
33 Ω
Table 5. Unipolar Binary Code Table for Circuit of Figure 7
2
15
BIT 1 TO
BIT 12
Trim Resistor
R1
R2
00718-008
VIN
Amplifier A1 must be selected or trimmed to provide VOS ≤ 10% of
the voltage resolution at VOUT. Additionally, the amplifier must
exhibit a bias current that is low over the temperature range of
interest (bias current causes output offset at VOUT equal to IB
times the DAC feedback resistance, nominally 11 kΩ).
Table 4. Recommended Trim Resistor Values vs. Grades
C1
33pF
18
C1 phase compensation (10 pF to 25 pF) may be required for
stability when using high speed amplifiers. C1 is used to cancel
the pole formed by the DAC internal feedback resistance and
output capacitance at OUT 1.
Figure 7. Unipolar Binary Operation
R1 provides full-scale trim capability (that is, load the DAC
register to 1111 1111 1111, adjust R1 for VOUT = –VREF
(4095/4096)). Alternatively, full scale can be adjusted by
omitting R1 and R2 and trimming the reference voltage
magnitude.
Binary Number in DAC
MSB
LSB
1111
1111
1000
0000
0000
0000
0000
0001
0000
0000
0000
Rev. C | Page 9 of 13
Analog Output, VOUT
−VIN(4095/4096)
−VIN(2048/4096) = −1/2VIN
−VIN(1/4096)
0V
AD7541A
Data Sheet
BIPOLAR OPERATION (FOUR QUADRANT
MULTIPLICATION)
Figure 9 and Table 7 show an alternative method of achieving
bipolar output. The circuit operates with sign plus magnitude
code and has the advantage of giving 12-bit resolution in each
quadrant, compared with 11-bit resolution per quadrant for the
circuit of Figure 8. The ADG5436F is a dual SPDT, latch-up
immune switch. R4 and R5 must match each other to 0.01% to
maintain the accuracy of the DAC. Mismatch between R4 and
R5 introduces a gain error.
Figure 8 and Table 6 illustrate the circuitry and code relationship
for bipolar operation. With a dc reference (positive or negative
polarity), the circuit provides offset binary operation. With an
ac reference, the circuit provides full four quadrant multiplication.
With the DAC loaded to 1000 0000 0000, adjust R1 for VOUT =
0 V (alternatively, omit R1 and R2 and adjust the ratio of R3 to
R4 for VOUT = 0 V). To accomplish, full-scale trimming, adjust
the amplitude of VREF or vary the R5 value.
Table 7. 12-Bit Plus Sign Magnitude Code Table for Circuit
of Figure 9
As in unipolar operation, A1 must be chosen for low VOS and
low IB. R3, R4, and R5 must be selected for matching and tracking.
Mismatch of R3 to R4 causes both offset and full-scale error.
Mismatch of R5 to R4 or R3 causes full-scale error. C1 phase
compensation (10 pF to 50 pF) may be required for stability,
depending on amplifier used.
1
Table 6. Bipolar Code Table for Offset Binary Circuit of Figure 8
Binary Number in DAC
MSB
LSB
1111
1111
1111
1000
0000
0001
1000
0000
0000
0111
1111
1111
0000
0000
0000
Binary Number in DAC
MSB
LSB
1111 1111 1111
0000 0000 0000
0000 0000 0000
1111 1111 1111
Sign Bit1
0
0
1
1
When the sign bit equals 0, it connects R3 to GND.
Analog Output, VOUT
+VIN(2047/2048)
+VIN(1/2048)
0V
−VIN(1/2048)
−VIN(2048/2048)
R21
VDD
16
VIN
17 VREF
R11
R4
20kΩ
C1
33pF
18
VDD RFEEDBACK
OUT 1 1
4
R6
5kΩ
2
15
VOUT
A2
OUT 2 2
DGND
PIN 4 TO
PIN 15
R5
20kΩ
R3
10kΩ
A1
AD7541A
10%
DIGITAL
GROUND
ANALOG
COMMON
00718-009
BIT 1 TO
BIT 12
1FOR VALUES OF R1 AND R2,
SEE TABLE 4.
Figure 8. Bipolar Operation (Four-Quadrant Multiplication)
R21
VDD
R11
17
VREF
VDD RFEEDBACK
OUT 1 1
AD7541A
A2
A1
OUT 2 2
DGND
PIN 4 TO
PIN 15
4
R5
20kΩ
2
15
1/2
ADG5436F
DIGITAL
GROUND
BIT 1 TO BIT 12
VOUT
R3
10kΩ
10%
ANALOG
COMMON
1FOR
VALUES OF R1 AND R2,
SEE TABLE 4.
Figure 9. 12-Bit Plus Sign Magnitude Operation
Rev. C | Page 10 of 13
00718-010
VIN
R4
20kΩ
C1
33pF
18
16
Analog Output, VOUT
+VIN × (4095/4096)
0V
0V
−VIN × (4095/4096)
Data Sheet
AD7541A
APPLICATIONS HINTS
SINGLE-SUPPLY OPERATION
Output Offset
Figure 10 shows the AD7541A connected in a voltage switching
mode. OUT 1 is connected to the reference voltage, and OUT 2
is connected to GND. The output voltage of the DAC is available at
the VREF pin (Pin 17) and has a constant output impedance equal to
RLDR. The feedback resistor, RFEEDBACK, is not used in this circuit.
VDD = 15V
NOT USED
16
18
VREF
2.5V
RFEEDBACK VDD
1 OUT 1
VREF 17
V+
AD7541A
2 OUT 2
GND
2
VOUT = 0V TO 10V
PIN 4 TO
PIN 15
4
15
BIT 1 TO BIT 12
V–
R2
30kΩ
R1
10kΩ
SYSTEM
GROUND
VOUT ± VREF D (1 + R2/R1) WHERE 0 ≤ D ≤ 1,
THAT IS, D IS A FRACTIONAL REPRESENTATION OF THE DIGITAL INPUT
Digital Glitches
00718-011
The CMOS DACs exhibit a code dependent, output resistance
that can cause a code dependent error voltage at the output of
the amplifier. The maximum amplitude of this offset, which
adds to the nonlinearity of the DAC, is 0.67 VOS, where VOS is
the amplifier input offset voltage. To maintain monotonic
operation, it is recommended that VOS be no greater than
(25 × 10–6) × VREF over the temperature range of operation.
Suitable op amps include the following: OP27, OP177, and OP777.
The OP27 is best suited for fixed reference applications with
low bandwidth requirements. The OP27 has extremely low
offset (25 µV), and does not require an offset trim in most
applications. The AD711 has a much wider bandwidth and
higher slew rate and is recommended for multiplying and
other applications that require fast settling.
Figure 10. Single Supply Operation Using Voltage Switching Mode
One cause of digital glitches is capacitive coupling from the digital
lines to the OUT 1 and OUT 2 terminals. This coupling can be
minimized by screening the analog pins of the AD7541A (Pin 1,
Pin 2, Pin 17, and Pin 18) from the digital pins by a ground track
run between Pin 2 and Pin 3 and between Pin 16 and Pin 17 of
the AD7541A. Note how the analog pins are at one end of the
package and are separated from the digital pins by VDD and
GND to aid screening at the board level. On-chip capacitive
coupling can also give rise to crosstalk from the digital to
analog sections of the AD7541A, particularly in circuits with
high currents and fast rise and fall times.
Temperature Coefficients
The gain temperature coefficient of the AD7541A has a maximum
value of 5 ppm/°C and a typical value of 2 ppm/°C. This coefficient
corresponds to worst case gain shifts of 2 LSB and 0.8 LSB,
respectively, over a 100°C temperature range. When trim resistors,
R1 and R2, are used to adjust the full-scale range, the temperature
coefficients of R1 and R2 must also be taken into account.
The reference voltage must always be positive. If OUT 1 goes
more than 0.3 V less than GND, an internal diode is turned on
and a heavy current may flow, causing device damage (the
AD7541A is protected from the SCR latch-up phenomenon
prevalent in many CMOS devices). Suitable references include
the ADR431, the ADR441, and the REF192.
The loading on the reference voltage source is code dependent,
and the behavior of the reference voltage with changing load
conditions often determines the response time of the circuit.
To maintain linearity, the voltage at OUT 1 must remain within
2.5 V of GND for a VDD of 15 V. If VDD is reduced from 15 V, or
if the reference voltage at OUT 1 is increased to more than 2.5 V,
the differential nonlinearity of the DAC increases, and the
linearity of the DAC degrades.
SUPPLEMENTAL APPLICATION MATERIAL
For further information on CMOS multiplying DACs, refer to
the following:
Analog-Digital Conversion Handbook, 1972, Analog Devices, Inc.
CMOS DAC Application Guide, 1984, Analog Devices
Analog-Digital Conversion Handbook, 1986, Analog Devices
Rev. C | Page 11 of 13
AD7541A
Data Sheet
OUTLINE DIMENSIONS
0.180 (4.57)
0.165 (4.19)
0.048 (1.22 )
0.042 (1.07)
3
0.048 (1.22)
0.042 (1.07)
4
0.056 (1.42)
0.042 (1.07)
0.20 (0.51)
MIN
19
PIN 1
IDENTIFIER
18
TOP VIEW
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
0.330 (8.38)
0.032 (0.81) 0.290 (7.37)
0.026 (0.66)
(PINS DOWN)
14
8
9
0.020
(0.51)
R
0.020 (0.50)
R
BOTTOM
VIEW
(PINS UP)
13
0.045 (1.14)
R
0.025 (0.64)
0.356 (9.04)
SQ
0.350 (8.89)
0.120 (3.04)
0.090 (2.29)
0.395 (10.03)
SQ
0.385 (9.78)
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 11. 20-Lead Plastic Leadless Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
0.920 (23.37)
0.900 (22.86)
0.880 (22.35)
18
10
1
9
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 12. 18-Lead Plastic Dual In-Line Package [PDIP]
(N-18)
Dimensions shown in inches and (millimeters)
Rev. C | Page 12 of 13
070706-A
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
Data Sheet
AD7541A
11.75 (0.4626)
11.35 (0.4469)
10
18
7.60 (0.2992)
7.40 (0.2913)
9
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
1.27
(0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
45°
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1.27 (0.0500)
0.40 (0.0157)
060706-A
1
Figure 13. 18-Lead Standard Small Outline Package [SOIC_W]
(RW-18)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1
AD7541AJNZ
AD7541AKNZ
AD7541AJPZ-REEL
AD7541AKPZ-REEL
AD7541AKR
AD7541AKRZ
AD7541AKRZ-REEL
AD7541AKRZ–REEL7
AD7541AACHIPS
1
Temperature Range
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
Relative Accuracy, TMIN to TMAX
±1 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1/2 LSB
±1/2 LSB
±1/2 LSB
±1/2 LSB
Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00718-0-3/17(C)
Rev. C | Page 13 of 13
Error, TA = 25°C
±6 LSB
±3 LSB
±6 LSB
±3 LSB
±3 LSB
±3 LSB
±3 LSB
±3 LSB
Package Description
18-Lead PDIP
18-Lead PDIP
20-Lead PLCC
20-Lead PLCC
18-Lead SOIC_W
18-Lead SOIC_W
18-Lead SOIC_W
18-Lead SOIC_W
DIE
Package Option
N-18
N-18
P-20
P-20
RW-18
RW-18
RW-18
RW-18
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