AD7606-6

Data Sheet FEATURES 8 simultaneously sampled inputs True bipolar analog input ranges: ±10 V, ±5 V Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 MΩ analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 18-bit ADC with 200 kSPS on all channels Oversampling capability with digital filter Flexible parallel/serial interface SPI/QSPI™/MICROWIRE™/DSP compatible Pin compatible solutions from 14-bits to 18-bits Performance 7 kV ESD rating on analog input channels 98 dB SNR, −107 dB THD Low power: 100 mW Standby mode: 25 mW 64-lead LQFP package 8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC AD7608 APPLICATIONS Power line monitoring and protection systems Multiphase motor controls Instrumentation and control systems Multiaxis positioning systems Data acquisition systems (DAS) COMPANION PRODUCTS External References: ADR421, ADR431 Digital Isolators: ADuM1402, ADuM5000, ADuM5402 Voltage Regulator Design Tool: ADIsimPower, Supervisor Parametric Search Complete list of complements on AD7608 product page Table 1. High Resolution, Bipolar Input, Simultaneous Sampling DAS Solutions SingleEnded Inputs AD76081 AD7606 AD7606-6 AD7606-4 AD7607 True Differential Inputs AD7609 Number of Simultaneous Sampling Channels 8 8 6 4 8 Resolution 18 Bits 16 Bits 14 Bits FUNCTIONAL BLOCK DIAGRAM AVCC V1 V1GND CLAMP CLAMP 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB SECOND ORDER LPF SECOND ORDER LPF SECOND ORDER LPF SECOND ORDER LPF SECOND ORDER LPF SECOND ORDER LPF SECOND ORDER LPF SECOND ORDER LPF AVCC REGCAP REGCAP REFCAPB REFCAPA T/H 2.5V LDO 2.5V LDO REFIN/REFOUT V2 V2GND CLAMP CLAMP T/H 2.5V REF T/H REF SELECT AGND OS 2 OS 1 OS 0 T/H 8:1 MUX T/H PARALLEL/ SERIAL INTERFACE SERIAL 18-BIT SAR DIGITAL FILTER DOUTA DOUTB RD/SCLK CS PAR/SER SEL VDRIVE T/H PARALLEL DB[15:0] V3 V3GND CLAMP CLAMP V4 V4GND CLAMP CLAMP V5 V5GND CLAMP CLAMP V6 V6GND CLAMP CLAMP V7 V7GND CLAMP CLAMP AD7608 T/H CLK OSC CONTROL INPUTS BUSY FRSTDATA 08938-001 V8 V8GND CLAMP CLAMP T/H AGND CONVST A CONVST B RESET RANGE Figure 1. 1 Patent pending. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved. AD7608 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Companion Products ....................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Timing Specifications .................................................................. 6 Absolute Maximum Ratings.......................................................... 10 Thermal Resistance .................................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Typical Performance Characteristics ........................................... 14 Terminology .................................................................................... 18 Theory of Operation ...................................................................... 19 Data Sheet Converter Details ....................................................................... 19 Analog Input ............................................................................... 19 ADC Transfer Function ............................................................. 20 Internal/External Reference ...................................................... 21 Typical Connection Diagram ................................................... 22 Power-Down Modes .................................................................. 22 Conversion Control ................................................................... 23 Digital Interface .............................................................................. 24 Parallel Interface (PAR/SER SEL = 0) ...................................... 24 Serial Interface (PAR/SER SEL = 1) ......................................... 25 Reading During Conversion ..................................................... 25 Digital Filter ................................................................................ 26 Layout Guidelines....................................................................... 30 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32 REVISION HISTORY 1/12—Rev. 0 to Rev. A Changes to Analog Input Ranges Section ····································19 4/11—Revision 0: Initial Version Rev. A | Page 2 of 32 Data Sheet GENERAL DESCRIPTION The AD7608 is an 18-bit, 8-channel simultaneous sampling, analog-to-digital data acquisition system (DAS). The part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, an 18-bit charge redistribution successive approximation analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. AD7608 The AD7608 operates from a single 5 V supply and can accommodate ±10 V and ±5 V true bipolar input signals while sampling at throughput rates up to 200 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to ±16.5 V. The AD7608 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The AD7608 antialiasing filter has a 3 dB cutoff frequency of 22 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the 3 dB bandwidth. Rev. A | Page 3 of 32 AD7608 SPECIFICATIONS Data Sheet VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V; fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 2, 3 Test Conditions/Comments fIN = 1 kHz sine wave unless otherwise noted Oversampling by 16; ±10 V range; fIN = 130 Hz Oversampling by 16; ±5 V range; fIN = 130 Hz No oversampling; ±10 V range No oversampling; ±5 V range No oversampling; ±10 V range No oversampling; ±5 V range No oversampling; ±10 V range No oversampling; ±5 V range Min 98 95.5 89.5 88.5 88.5 88 Typ 99.5 97.5 90.9 90 90.5 89.5 91.5 90.5 −107 −108 −110 −106 −95 23 15 10 5 11 15 18 ±0.75 ±2.5 ±15 ±40 ±15 ±40 ±2 ±7 12 30 ±3.5 ±3.5 10 5 3 21 ±15 ±40 ±4 ±8 12 30 −0.99/+2.6 ±7.5 Max Unit dB dB dB dB dB dB dB dB dB dB dB dB dB kHz kHz kHz kHz µs µs Bits LSB 4 LSB LSB LSB LSB LSB ppm/°C ppm/°C LSB LSB LSB LSB µV/°C µV/°C LSB LSB LSB LSB ppm/°C ppm/°C LSB LSB Signal-to-(Noise + Distortion) (SINAD)2 Dynamic Range Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation2 ANALOG INPUT FILTER Full Power Bandwidth −95 fa = 1 kHz, fb = 1.1 kHz fIN on unselected channels up to 160 kHz −3 dB, ±10 V range −3 dB, ±5 V range −0.1 dB, ±10 V range −0.1 dB, ±5 V range ±10 V range ±5 V range No missing codes tGROUP DELAY DC ACCURACY Resolution Differential Nonlinearity2 Integral Nonlinearity2 Total Unadjusted Error (TUE) Positive Full-Scale Error2, 5 Positive Full-Scale Error Drift Positive Full-Scale Error Matching2 Bipolar Zero Code Error2, 6 Bipolar Zero Code Error Drift Bipolar Zero Code Error Matching2 Negative Full-Scale Error2, 5 Negative Full-Scale Error Drift Negative Full-Scale Error Matching2 ±10 V range ±5 V range External reference Internal reference External reference Internal reference ±10 V range ±5 V range ±10 V range ± 5 V range ±10 V range ± 5 V range ±10 V range ±5 V range External reference Internal reference External reference Internal reference ±10 V range ±5 V range ±128 95 128 ±24 ±48 30 65 ±128 95 128 Rev. A | Page 4 of 32 Data Sheet Parameter ANALOG INPUT Input Voltage Ranges Analog Input Current Input Capacitance 7 Input Impedance REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance7 Reference Output Voltage Reference Temperature Coefficient LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)7 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance7 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVCC VDRIVE ITOTAL Normal Mode (Static) Normal Mode (Operational)8 Standby Mode Shutdown Mode Power Dissipation Normal Mode (Static) Normal Mode (Operational) 8 Standby Mode Shutdown Mode 1 2 AD7608 Test Conditions/Comments RANGE = 1 RANGE = 0 10 V; see Figure 28 5 V; see Figure 28 Min Typ Max ±10 ±5 5.4 2.5 5 1 2.475 REF SELECT = 1 REFIN/REFOUT 2.5 7.5 2.49/ 2.505 ±10 0.9 × VDRIVE 0.1 × VDRIVE ±2 5 ISOURCE = 100 µA ISINK = 100 µA VDRIVE − 0.2 ±1 5 Twos complement All eight channels included; see Table 3 Per channel, all eight channels included 4.75 2.3 Digital inputs = 0 V or VDRIVE fSAMPLE = 200 kSPS 16 20 5 2 80 100 25 10 22 27 8 11 115.5 142 42 58 mA mA mA µA mW mW mW µW 4 1 200 5.25 5.25 µs µs kSPS V V 0.2 ±20 2.525 ±1 Unit V V µA µA pF MΩ V µA pF V ppm/°C V V µA pF V V µA pF fSAMPLE = 200 kSPS Temperature range for B version is −40°C to +85°C. See the Terminology section. 3 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with VDRIVE = 5 V, SNR typically reduces by 1.5 dB and THD by 3 dB. 4 LSB means least significant bit. With ±5 V input range, 1 LSB = 38.14 µV. With ±10 V input range, 1 LSB = 76.29 µV. 5 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 6 Bipolar zero code error is calculated with respect to the analog input voltage. 7 Sample tested during initial release to ensure compliance. 8 Operational power/current figure includes contribution when running in oversampling mode. Rev. A | Page 5 of 32 AD7608 TIMING SPECIFICATIONS Data Sheet AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter PARALLEL/SERIAL/BYTE MODE tCYCLE Limit at TMIN, TMAX Min Typ Max Unit Description 1/throughput rate Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines Serial mode reading during conversion; VDRIVE = 2.7 V Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines Conversion time Oversampling off Oversampling by 2 Oversampling by 4 Oversampling by 8 Oversampling by 16 Oversampling by 32 Oversampling by 64 STBY rising edge to CONVST x rising edge; power-up time from standby mode E A 5 5 10.5 tCONV 3.45 7.87 16.05 33 66 133 257 tWAKE-UP STANDBY tWAKE-UP SHUTDOWN Internal Reference External Reference tRESET tOS_SETUP tOS_HOLD t1 t2 t3 t4 t5 2 t6 t7 PARALLEL/BYTE READ OPERATION t8 t9 t10 10F9F µs µs µs µs µs µs µs µs µs µs µs 4 4.15 9.1 18.8 39 78 158 315 100 30 13 50 20 20 40 25 25 0 0.5 25 25 ms ms ns ns ns ns ns ns ns ms ns ns STBY rising edge to CONVST x rising edge; power-up time from shutdown mode STBY rising edge to CONVST x rising edge; power-up time from shutdown mode RESET high pulse width BUSY to OS x pin setup time BUSY to OS x pin hold time CONVST x high to BUSY high Minimum CONVST x low pulse Minimum CONVST x high pulse BUSY falling edge to CS falling edge setup time Maximum delay allowed between CONVST A, CONVST B rising edges Maximum time between last CS rising edge and BUSY falling edge Minimum delay between RESET low to CONVST x high E A A E A A E A A E A A 0 0 16 21 25 32 15 22 ns ns ns ns ns ns ns ns t11 t12 CS to RD setup time CS to RD hold time RD low pulse width VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V RD high pulse width CS high pulse width (see Figure 5); CS and RD linked E E A A A A E E A A A A E A A E A A E E E A A A A A A Rev. A | Page 6 of 32 Data Sheet Parameter t13 Limit at TMIN, TMAX Min Typ Max 16 20 25 30 t143 16 21 25 32 t15 t16 t17 SERIAL READ OPERATION fSCLK 23.5 17 14.5 11.5 t18 15 20 30 t19 3 1F AD7608 Unit ns ns ns ns ns ns ns ns ns ns ns Description Delay from CS until DB[15:0] three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data access time after RD falling edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data hold time after RD falling edge CS to DB[15:0] hold time Delay from CS rising edge to DB[15:0] three-state enabled E A A E A A E A A E A A E A A 6 6 22 MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns 17 23 27 34 t20 t21 t22 t23 FRSTDATA OPERATION t24 15 20 25 30 t25 15 20 25 30 t26 16 20 25 30 0.4 tSCLK 0.4 tSCLK 7 22 Frequency of serial read clock VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE = 2.3 V to 2.7 V Data access time after SCLK rising edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V SCLK low pulse width SCLK high pulse width SCLK rising edge to DOUTA/DOUTB valid hold time CS rising edge to DOUTA/DOUTB three-state enabled E E A A A A E A A ns ns ns ns ns ns ns ns ns ns ns ns ns Delay from CS falling edge until FRSTDATA three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS falling edge until FRSTDATA high, serial mode VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from RD falling edge to FRSTDATA high VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V E A A E A A E A A Rev. A | Page 7 of 32 AD7608 Parameter t27 Limit at TMIN, TMAX Min Typ Max 19 24 t28 17 22 24 ns ns ns Unit ns ns Data Sheet Description Delay from RD falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25 V VDRIVE = 2.3 V to 2.7 V Delay from 16th SCLK falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25 V VDRIVE = 2.3 V to 2.7 V Delay from CS rising edge until FRSTDATA three-state enabled E A A E A A t29 1 2 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a 3.3 V, the SNR is reduced by ~1.5 dB when reading during a conversion. ATTENUATION (dB) –10 –15 –20 –25 –30 –35 ±10V RANGE –40 +25 +85 ±5V RANGE –40 +25 +85 0.1dB 10,303Hz 9619Hz 9326Hz 0.1dB 5225Hz 5225Hz 4932Hz 1k 3dB 24,365Hz 23,389Hz 22,607Hz 3dB 16,162Hz 15,478Hz 14,990Hz 10k 100k 08938-135 –40 100 INPUT FREQUENCY (Hz) Figure 34. Analog Antialiasing Filter Frequency Response 18 16 14 ±5V RANGE ADC TRANSFER FUNCTION The output coding of the AD7608 is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is FSR/262,144 for the AD7608. The ideal transfer characteristic for the AD7608 is shown in Figure 36. ±10V CODE = VIN × 131,072 × 10V VIN ±5V CODE = × 131,072 × 5V REF 2.5V REF 2.5V PHASE DELAY (µs) 12 10 8 6 4 ±10V RANGE 011...111 011...110 ADC CODE 2 0 –2 100 AVCC, VDRIVE = 5V fSAMPLE = 200kSPS TA = 25°C 08938-033 000...001 000...000 111...111 100...010 100...001 100...000 –FS + 1/2LSB LSB = +FS – (–FS) 218 1k 10k 100k INPUT FREQUENCY (Hz) Figure 35. Analog Antialiasing Filter Phase Response 0V – 1LSB +FS – 3/2LSB ANALOG INPUT 08938-034 Track-and-Hold Amplifiers The track-and-hold amplifiers on the AD7608 allow the ADC to accurately acquire an input sine wave of full-scale amplitude to 18-bit resolution. The track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of CONVST x. The aperture time for track-and-hold (that is, the delay time between the external CONVST x signal and the +FS ±10V RANGE +10V ±5V RANGE +5V MIDSCALE 0V 0V –FS –10V –5V LSB 76.29µV 38.15µV Figure 36. AD7608 Transfer Characteristic The LSB size is dependent on the analog input range selected. Rev. A | Page 20 of 32 Data Sheet INTERNAL/EXTERNAL REFERENCE The AD7608 contains an on-chip 2.5 V band gap reference. The REFIN/REFOUT pin allows access to the 2.5 V reference that generates the on-chip 4.5 V reference internally, or it allows an external reference of 2.5 V to be applied to the AD7608. An externally applied reference of 2.5 V is also gained up to 4.5 V, using the internal buffer. This 4.5 V buffered reference is the reference used by the SAR ADC. The REF SELECT pin is a logic input pin that allows the user to select between the internal reference or an external reference. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. The internal reference buffer is always enabled. After a reset, the AD7608 operates in the reference mode selected by the REF SELECT pin. Decoupling is required on the REFIN/REFOUT pin for both the internal and external reference options. A 10 µF ceramic capacitor is required on the REFIN/REFOUT pin. The AD7608 contains a reference buffer configured to gain the REF voltage up to ~4.5 V, as shown in Figure 37. The REFCAPA and REFCAPB pins must be shorted together externally, and a ceramic capacitor of 10 μF applied to REFGND, to ensure that the reference buffer is in closed-loop operation. The reference voltage available at the REFIN/REFOUT pin is 2.5 V. When the AD7608 is configured in external reference mode, the REFIN/REFOUT pin is a high input impedance pin. For applications using multiple AD7608 devices, the following configurations are recommended, depending on the application requirements. External Reference Mode One ADR421 external reference can be used to drive the REFIN/REFOUT pins of all AD7608 devices (see Figure 38). In this configuration, each REFIN/REFOUT pin of the AD7608 should be decoupled with at least a 100 nF decoupling capacitor. Internal Reference Mode AD7608 One AD7608 device, configured to operate in the internal reference mode, can be used to drive the remaining AD7608 devices, which are configured to operate in external reference mode (see Figure 39). The REFIN/REFOUT pin of the AD7608, configured in internal reference mode, should be decoupled using a 10 µF ceramic decoupling capacitor. The other AD7608 devices, configured in external reference mode, should use at least a 100 nF decoupling capacitor on their REFIN/REFOUT pins. REFIN/REFOUT SAR BUF REFCAPB 10µF REFCAPA 2.5V REF Figure 37. Reference Circuitry AD7608 REF SELECT REFIN/REFOUT AD7608 REF SELECT REFIN/REFOUT AD7608 REF SELECT REFIN/REFOUT 100nF 100nF 08938-035 100nF 0.1µF Figure 38. Single External Reference Driving Multiple AD7608 REFIN Pins VDRIVE AD7608 REF SELECT REFIN/REFOUT AD7608 REF SELECT REFIN/REFOUT AD7608 REF SELECT REFIN/REFOUT + Figure 39. Internal Reference Driving Multiple AD7608 REFIN Pins Rev. A | Page 21 of 32 08938-036 10µF 100nF 100nF 08938-037 ADR421 AD7608 TYPICAL CONNECTION DIAGRAM Figure 40 shows the typical connection diagram for the AD7608. There are four AVCC supply pins on the part, and each of the four pins should be decoupled using a 100 nF capacitor at each supply pin and a 10 µF capacitor at the supply source. The AD7608 can operate with the internal reference or an externally applied reference. In this configuration, the AD7608 is configured to operate with the internal reference. When using a single AD7608 device on the board, the REFIN/REFOUT pin should be decoupled with a 10 µF capacitor. Refer to the Internal/External Reference section when using an application with multiple AD7608 devices. The REFCAPA and REFCAPB pins are shorted together and decoupled with a 10 µF ceramic capacitor. The VDRIVE supply is connected to the same supply as the processor. The VDRIVE voltage controls the voltage value of the output logic signals. For layout, decoupling, and grounding hints, see the Layout Guidelines section. After supplies have been applied to the AD7608, apply a RESET signal to the device to ensure it is configured for the correct mode of operation. E A A Data Sheet The power-down mode is selected through the state of the RANGE pin when the STBY pin is low. Table 7 shows the configurations required to choose the desired power-down mode. When the AD7608 is placed in standby mode, the current consumption is 8 mA maximum and power-up time is approximately 100 µs because the capacitor on the REFCAPA and REFCAPB pins must charge up. In standby mode, the on-chip reference and regulators remain powered up, and the amplifiers and ADC core are powered down. When the AD7608 is placed in shutdown mode, the current consumption is 11 µA maximum and power-up time is approximately 13 ms (external reference mode). In shutdown mode, all circuitry is powered down. When the AD7608 is powered up from shutdown mode, a RESET signal must be applied to the AD7608 after the required power-up time has elapsed. Table 7. Power-Down Mode Selection Power-Down Mode Standby Shutdown A STBY E 0 0 RANGE 1 0 POWER-DOWN MODES There are two power-down modes available on the AD7608: standby mode and shutdown mode. The STBY pin controls whether the AD7608 is in normal mode or in one of the two power-down modes. E A ANALOG SUPPLY VOLTAGE 5V1 + DIGITAL SUPPLY VOLTAGE +2.3V TO +5V 10µF 1µF 100nF 100nF REFCAPA 10µF + REFCAPB REFGND V1 V1GND V2 V2GND V3 V3GND V4 V4GND V5 V5GND V6 V6GND V7 V7GND V8 V8GND CONVST A, B CS RD BUSY RESET OS 2 OS 1 OS 0 REF SELECT PAR/SER SEL RANGE STBY AGND DB0 TO DB15 PARALLEL INTERFACE AD7608 EIGHT ANALOG INPUTS V1 TO V8 OVERSAMPLING VDRIVE VDRIVE Figure 40. Typical Connection Diagram Rev. A | Page 22 of 32 08938-038 1DECOUPLING SHOWN ON THE AV CC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48). DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV CC PIN 37 AND PIN 38. 2DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). MICROPROCESSOR/ MICROCONVERTER/ DSP REFIN/REFOUT REGCAP2 AVCC VDRIVE Data Sheet CONVERSION CONTROL Simultaneous Sampling on All Analog Input Channels The AD7608 allows simultaneous sampling of all analog input channels. All channels are sampled simultaneously when both CONVST x pins (CONVST A, CONVST B) are tied together. A single CONVST x signal is used to control both CONVST x inputs. The rising edge of this common CONVST x signal initiates simultaneous sampling on all analog input channels. The AD7608 contains an on-chip oscillator that is used to perform the conversions. The conversion time for all ADC channels is tCONV. The BUSY signal indicates to the user when conversions are in progress, so when the rising edge of CONVST x is applied, BUSY goes logic high and transitions low at the end of the entire conversion process. The falling edge of the BUSY signal is used to place all eight track-and-hold amplifiers back into track mode. The falling edge of BUSY also indicates that the new data can now be read from the parallel bus (DB[15:0]), or the DOUTA and DOUTB serial data lines. AD7608 Simultaneously Sampling Two Sets of Channels The AD7608 also allows the analog input channels to be sampled simultaneously in two sets. This can be used in powerline protection and measurement systems to compensate for phase differences introduced by PT and CT transformers. In a 50 Hz system, this allows for up to 9° of phase compensation; and in a 60 Hz system, it allows for up to 10° of phase compensation. This is accomplished by pulsing the two CONVST x pins independently and is possible only if oversampling is not in use. CONVST A is used to initiate simultaneous sampling of the first set of channels (V1 to V4) and CONVST B is used to initiate simultaneous sampling on the second set of analog input channels (V5 to V8), as illustrated in Figure 41. On the rising edge of CONVST A, the track-and-hold amplifiers for the first set of channels are placed into hold mode. On the rising edge of CONVST B, the track-and-hold amplifiers for the second set of channels are placed into hold mode. The conversion process begins once both rising edges of CONVST x have occurred; therefore BUSY goes high on the rising edge of the later CONVST x signal. In Table 3, Time t5 indicates the maximum allowable time between CONVST x sampling points. There is no change to the data read process when using two separate CONVST x signals. Connect all unused analog input channels to AGND. The results for any unused channels are still included in the data read because all channels are always converted. V1 TO V4 TRACK-AND-HOLD ENTER HOLD V5 TO V8 TRACK-AND-HOLD ENTER HOLD CONVST A CONVST B BUSY t5 AD7608 CONVERTS ON ALL 8 CHANNELS tCONV CS, RD DATA: DB[15:0] V1 V2 V8 FRSTDATA Figure 41. Simultaneous Sampling on Channel Sets Using Independent CONVST A/CONVST B Signals—Parallel Mode Rev. A | Page 23 of 32 08938-039 AD7608 DIGITAL INTERFACE The AD7608 provides two interface options: a parallel interface and high speed serial interface. The required interface mode is selected via the PAR/SER SEL pin. E A A E Data Sheet The CS signal can be permanently tied low, and the RD signal can be used to access the conversion results as shown in Figure 4. A read operation of new data can take place after the BUSY signal goes low (Figure 2), or alternatively a read operation of data from the previous conversion process can take place while BUSY is high (Figure 3). E A A A A The operation of the interface modes is discussed in the following sections. PARALLEL INTERFACE (PAR/SER SEL = 0) Data can be read from the AD7608 via the parallel data bus with standard CS and RD signals. To read the data over the parallel bus, the PAR/SER SEL pin should be tied low. The CS and RD input signals are internally gated to enable the conversion result onto the data bus. The data lines, DB15 to DB0, leave their high impedance state when both CS and RD are logic low. E E A A A A E E E A A A A A A E E A A A A AD7608 BUSY 14 CS 13 RD/SCLK 12 INTERRUPT DB[15:0] [33:24] [22:16] 08938-040 DIGITAL HOST Figure 42. AD7608 interface diagram—One AD7608 Using the Parallel Bus; CS and RD Shorted Together E E A A A A The RD pin is used to read data from the output conversion results register. Two RD pulses are required to read the full 18-bit conversion result from each channel. Applying a sequence of 16 RD pulses to the AD7608 RD pin clocks the conversion results out from each channel onto the 16-bit parallel output bus in ascending order. The first RD falling edge after BUSY goes low clocks out DB[17:2] of the V1 result, the next RD falling edge updates the bus with DB[1:0] of V1 result. It takes 16 RD pulses to read the eight 18-bit conversion results from the AD7608. On the AD7608, the 16th falling edge of RD clocks out the DB[1:0] conversion result for Channel V8. When the RD signal is logic low, it enables the data conversion result from each channel to be transferred to the digital host (DSP, FPGA). E A A E A A E E A A A A E A A E A A E A A E A A E A A The rising edge of the CS input signal three-states the bus and the falling edge of the CS input signal takes the bus out of the high impedance state. CS is the control signal that enables the data lines, it is the function that allows multiple AD7608 devices to share the same parallel data bus. E A A E A A E A A When there is only one AD7608 in a system/board and it does not share the parallel bus, data can be read using just one control signal from the digital host. The CS and RD signals can be tied together as shown in Figure 5. In this case, the data bus comes out of three-state on the falling edge of CS/RD. The combined CS and RD signal allows the data to be clocked out of the AD7608 and to be read by the digital host. In this case, CS is used to frame the data transfer of each data channel. In this case, 16 CS pulses are required to read the eight channels of data. E E A A A A E E A A A A E E A A A A E A A E A A Rev. A | Page 24 of 32 Data Sheet SERIAL INTERFACE (PAR/SER SEL = 1) To read data back from the AD7608 over the serial interface, the PAR/SER SEL pin should be tied high. The CS and SCLK signals are used to transfer data from the AD7608. The AD7608 has two serial data output pins, DOUTA, and DOUTB. Data can be read back from the AD7608 using one or both of these DOUT lines. For the AD7608, conversion results from Channel V1 to Channel V4 first appear on DOUTA while conversion results from Channel V5 to Channel V8 first appear on DOUTB. E E A A A A E A A AD7608 The SCLK input signal provides the clock source for the serial read operation. CS goes low to access the data from the AD7608. The falling edge of CS takes the bus out of three-state and clocks out the MSB of the 18-bit conversion result. This MSB is valid on the first falling edge of the SCLK after the CS falling edge. The subsequent 17 data bits are clocked out of the AD7608 on the SCLK rising edge. Data is valid on the SCLK falling edge. Eighteen clock cycles must be provided to the AD7608 to access each conversion result. E A A E A A The CS falling edge takes the data output lines (DOUTA and DOUTB) out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data outputs, DOUTA and DOUTB. The CS input can be held low for the entire serial read, or it can be pulsed to frame each channel read of 18 SCLK cycles. E A A E A A Figure 43 shows a read of eight simultaneous conversion results using two DOUT lines on the AD7608. In this case, a 72 SCLK transfer is used to access data from the AD7608 and CS is held low to frame the entire 72 SCLK cycles. Data can also be clocked out using just one DOUT line, in which case DOUTA is recommended to access all conversion data as the channel data is output in ascending order. For the AD7608 to access all eight conversion results on one DOUT line, a total of 144 SCLK cycles are required. These 144 SCLK cycles can be framed by one CS signal or each group of 18 SCLK cycles can be individually framed by the CS signal. The disadvantage of using just one DOUT line is that the throughput rate is reduced if reading after conversion. The unused DOUT line should be left unconnected in serial mode. For the AD7608, if DOUTB is used as a single DOUT line, the channel results will output in the following order: V5, V6, V7, V8, V1, V2, V3, V4; however, the FRSTDATA indicator returns low once V5 is read on DOUTB. E A E A A E A A The FRSTDATA output signal indicates when the first channel, V1, is being read back. When the CS input is high, the FRSTDATA output pin is in three-state. In serial mode, the falling edge of CS takes FRSTDATA out of three-state and sets the FRSTDATA pin high indicating that the result from V1 is available on the DOUTA output data line. The FRSTDATA output returns to a logic low following the 18th SCLK falling edge. If all channels are read on DOUTB, the FRSTDATA output does not go high when V1 is output on the serial data output pin. It only goes high when V1 is available on DOUTA (and this is when V5 is available on DOUTB). E A A E A A READING DURING CONVERSION Data can be read from the AD7608 while BUSY is high and conversions are in progress. This has little effect on the performance of the converter and allows a faster throughput rate to be achieved. A parallel or serial read may be performed during conversions and when oversampling may or may not be in use. Figure 3 shows the timing diagram for reading while BUSY is high in parallel or serial mode. Reading during conversions allows the full throughput rate to be achieved when using the serial interface with a VDRIVE of 3.3 V to 5.25 V. Data can be read from the AD7608 at any time other than on the falling edge of BUSY because this is when the output data registers get updated with the new conversion data. Time t6, as outlined in Table 3, should be observed in this condition. Figure 6 shows the timing diagram for reading one channel of data, framed by the CS signal, from the AD7608 in serial mode. E A CS 72 SCLK DOUTA DOUTB V1 V2 V3 V4 08938-041 V5 V6 V7 V8 Figure 43. AD7608 Serial Interface with two DOUT Lines Rev. A | Page 25 of 32 AD7608 DIGITAL FILTER The AD7608 contains an optional digital first-order sinc filter that should be used in applications where slower throughput rates are used or where higher signal-to-noise ratio or dynamic range is desirable. The oversampling ratio of the digital filter is controlled using the oversampling pins, OS [2:0] (see Table 8). OS 2 is the MSB control bit, and OS 0 is the LSB control bit. Table 8 provides the oversampling bit decoding to select the different oversample rates. The OS pins are latched on the falling edge of BUSY. This sets the oversampling rate for the next conversion (see Figure 45). In addition to the oversampling function, the output result is decimated to 18-bit resolution. If the OS pins are set to select an OS ratio of 8, the next CONVST x rising edge takes the first sample for each channel, and the remaining seven samples for all channels are taken with an internally generated sampling signal. These samples are then averaged to yield an improvement in SNR performance. Table 8 shows typical SNR performance for both the ±10 V and the ±5 V range. As Table 8 indicates, there is an improvement in SNR as the OS ratio increases. As the OS ratio increases, the 3 dB frequency is reduced, and the allowed sampling frequency is also reduced. In an application where the required sampling frequency is 10 kSPS, an OS ratio of up to 16 can be used. In this case, the application sees an improvement in SNR, but the input 3 dB bandwidth is limited to ~6 kHz. The CONVST A and CONVST B pins must be tied/driven together when oversampling is turned on. When the oversampling function is turned on, the BUSY high time for the conversion process extends. The actual BUSY high time depends on the oversampling rate selected: the higher the oversampling rate, the longer the BUSY high, or total conversion time (see Table 3). CONVST A, CONVST B OVERSAMPLE RATE LATCHED FOR CONVERSION N + 1 Data Sheet Figure 44 shows that the conversion time extends as the oversampling rate is increased, and the BUSY signal lengthens for the different oversampling rates. For example, a sampling frequency of 10 kSPS yields a cycle time of 100 µs. Figure 44 shows OS × 2 and OS × 4; for a 10 kSPS example, there is adequate cycle time to further increase the oversampling rate and yield greater improvements in SNR performance. In an application where the initial sampling or throughput rate is at 200 kSPS, for example, and oversampling is turned on, the throughput rate must be reduced to accommodate the longer conversion time and to allow for the read. To achieve the fastest throughput rate possible when oversampling is turned on, the read can be performed during the BUSY high time. The falling edge of BUSY is used to update the output data registers with the new conversion data; therefore, the reading of conversion data should not occur on this edge. tCYCLE CONVST A, CONVST B tCONV 19µs 9µs 4µs BUSY OS = 0 OS = 2 OS = 4 t4 CS t4 t4 RD DATA: DB[15:0] 08938-043 Figure 44. No Oversampling, Oversampling × 2, and Oversampling × 4 While Using Read After Conversion CONVERSION N BUSY CONVERSION N + 1 tOS_HOLD OS x 08938-042 tOS_SETUP Figure 45. OS Pin Timing Table 8. Oversample Bit Decoding OS [2:0] 000 001 010 011 100 101 110 111 1 OS Ratio No OS 2 4 8 16 32 64 Invalid SNR ±5 V Range (dB)1 90.5 92.5 94.45 96.5 99.1 101.7 103 SNR ±10 V Range (dB)1 91.2 93.4 95.7 98 100.4 102.8 103.5 3 dB BW ±5 V Range (kHz) 15 15 13.7 10.3 6 3 1.5 3 dB BW ±10 V Range (kHz) 22 22 18.5 11.9 6 3 1.5 Maximum Throughput CONVST x Frequency (kHz) 200 100 50 25 12.5 6.25 3.125 SNR values taken with a full scale 100 Hz input signal. Rev. A | Page 26 of 32 Data Sheet Figure 46 to Figure 52 illustrates the effect of oversampling on the code spread in a dc histogram plot. As the oversample rate is increased, the spread of codes is reduced. (In Figure 46 to Figure 52, AVCC = VDRIVE = 5 V and the sampling rate was scaled with OS ratio.) 1600 NO OVERSAMPLING 1400 1377 1170 1208 1200 1001 1000 852 800 600 411 400 200 0 3 3 35 82 2 3 4 188 328 708 588 AD7608 3500 OVERSAMPLING BY 8 3027 3000 NUMBER OF OCCURENCES 2500 2176 2000 1500 1000 648 500 0 4 –4 78 –3 –2 –1 0 CODE 1 2 457 44 3 1756 NUMBER OF OCCURENCES 4 Figure 49. Histogram of Codes—OS × 8 (9 Codes) 4500 3947 OVERSAMPLING BY 16 146 66 5 6 08938-044 21 5 7 0 4000 NUMBER OF OCCURENCES –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 CODE 89 3500 3000 2500 2000 1500 1081 1000 500 385 69 0 –2 –1 0 CODE 1 2 08938-148 08938-149 Figure 46. Histogram of Codes—No OS (18 Codes) 2000 OVERSAMPLING BY 2 1800 NUMBER OF OCCURENCES 2703 1759 1524 1397 1600 1400 1200 1000 800 600 400 200 0 0 1 15 54 208 538 1065 902 7 3 498 6000 165 57 1 2 3 4 5 08938-045 Figure 50. Histogram of Codes—OS × 16 (6 Codes) OVERSAMPLING BY 32 9 6 5000 NUMBER OF OCCURENCES 5403 –8 –7 –6 –5 –4 –3 –2 –1 0 CODE Figure 47. Histogram Of Codes—OS × 2 (14 Codes) 2500 OVERSAMPLING BY 4 2000 1551 1500 1072 1000 684 500 199 08938-046 4000 2224 1913 3000 NUMBER OF OCCURENCES 2000 1301 1000 11 –2 –1 0 CODE 1 17 2 1460 0 427 Figure 51. Histogram of Codes—OS × 32 (5 Codes) 0 4 –5 40 –4 –3 –2 –1 0 CODE 1 2 3 64 4 14 5 Figure 48. Histogram of Codes—OS × 4 (11 Codes) Rev. A | Page 27 of 32 08938-047 2 AD7608 7000 OVERSAMPLING BY 64 6000 NUMBER OF OCCURENCES –20 Data Sheet 6489 0 –10 AVCC = 5V VDRIVE = 5V TA = 25°C ±10V RANGE OS BY 4 ATTENUATION (dB) 5000 4000 3000 2000 1238 1000 465 08938-150 –30 –40 –50 –60 –70 –80 –90 –1 0 CODE 1 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 52. Histogram of Codes—OS × 64 (3 Codes) Figure 54. Digital Filter Response for OS × 4 0 –10 –20 AVCC = 5V VDRIVE = 5V TA = 25°C ±10V RANGE OS BY 8 Figure 53 to Figure 58 show the digital filter frequency profiles for oversampling by 2 to oversampling by 64. The combination of the analog antialiasing filter and the oversampling digital filter can be used to eliminate or reduce the complexity of the design of the filter before the AD7608. The digital filtering combines steep roll-off and linear phase response. 0 –10 –20 AVCC = 5V VDRIVE = 5V TA = 25°C ±10V RANGE OS BY 2 ATTENUATION (dB) When the oversampling mode is selected, this has the effect of adding a digital filter function after the ADC. The different oversampling rates and the CONVST x sampling frequency produces different digital filter frequency profiles. –30 –40 –50 –60 –70 –80 –90 08938-153 08938-154 –100 100 1k 10k 100k 1M 10M FREQUENCY (Hz) ATTENUATION (dB) –30 0 –40 –10 –50 –20 –60 –70 –80 08938-151 Figure 55. Digital Filter Response for OS × 8 AVCC = 5V VDRIVE = 5V TA = 25°C ±10V RANGE OS BY 16 ATTENUATION (dB) –30 –40 –50 –60 –70 –80 –90 –100 100 –90 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 53. Digital Filter OS × 2 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 56. Digital Filter Response for OS × 16 Rev. A | Page 28 of 32 08938-152 0 –100 100 Data Sheet 0 –10 –20 AVCC = 5V VDRIVE = 5V TA = 25°C ±10V RANGE OS BY 32 0 –10 –20 AD7608 AVCC = 5V VDRIVE = 5V TA = 25°C ±10V RANGE OS BY 64 ATTENUATION (dB) –40 –50 –60 –70 –80 –90 08938-155 ATTENUATION (dB) –30 –30 –40 –50 –60 –70 –80 –90 08938-156 –100 100 1k 10k 100k 1M 10M –100 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 57. Digital Filter Response for OS × 32 Figure 58. Digital Filter Response for OS × 64 Rev. A | Page 29 of 32 AD7608 LAYOUT GUIDELINES The printed circuit board that houses the AD7608 should be designed so that the analog and digital sections are separated and confined to different areas of the board. Use at least one ground plane. It can be common or split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably as close as possible to the AD7608. If the AD7608 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point: a star ground point should be established as close as possible to the AD7608. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Individual vias or multiple vias to the ground plane should be used for each ground pin. Avoid running digital lines under the devices because doing so couples noise onto the die. Allow the analog ground plane to run under the AD7608 to avoid noise coupling. Fast switching signals like CONVST A, CONVST B, or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Avoid crossover of digital and analog signals. Run traces on layers in close proximity on the board at right angles to each other to reduce the effect of feedthrough through the board. The power supply lines to the AVCC and VDRIVE pins on the AD7608 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Where possible, use supply planes. Good connections should be made between the AD7608 supply pins and the power tracks on the board. Use a single via or multiple vias for each supply pin. Good decoupling is also important to lower the supply impedance presented to the AD7608 and to reduce the magnitude of the supply spikes. The decoupling capacitors should be placed close to (ideally right up against) these pins and their corresponding ground pins. Place the decoupling capacitors for the REFIN/ REFOUT pin and the REFCAPA and REFCAPB pins as close as possible to their respective AD7608 pins and where possible they should be placed on the same side of the board as the AD7608 device. Figure 59 shows the recommended decoupling on the top layer of the AD7608 board. Figure 60 shows bottom layer decoupling. Bottom layer decoupling is for the four AVCC pins and the VDRIVE pin. Data Sheet Figure 59. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and REGCAP Pins Figure 60. Bottom Layer Decoupling Rev. A | Page 30 of 32 08938-052 08938-051 Data Sheet To ensure good device-to-device performance matching, in a system that contains multiple AD7608 devices, a symmetrical layout between the AD7608 devices is important. Figure 61 shows a layout with two devices. The AVCC supply plane runs to the right of both devices. The VDRIVE supply track runs to the left of the two devices. The reference chip is positioned between both the two devices and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 to U2. A solid ground plane is used. These symmetrical layout principles can be applied to a system that contains more than two AD7608 devices. The AD7608 devices can be placed in a north-south direction with the reference voltage located midway between the AD7608 devices with the reference track running in the north-south direction similar to Figure 61. U1 AVCC AD7608 U2 Figure 61. Layout for Multiple AD7608 Devices—Top Layer and Supply Plane Layer Rev. A | Page 31 of 32 08938-053 AD7608 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 1 PIN 1 Data Sheet 12.20 12.00 SQ 11.80 64 49 48 TOP VIEW (PINS DOWN) 10.20 10.00 SQ 9.80 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 16 17 32 33 0.08 COPLANARITY VIEW A VIEW A ROTATED 90° CCW 0.50 BSC LEAD PITCH 0.27 0.22 0.17 051706-A COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 62. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7608BSTZ AD7608BSTZ-RL EVAL-AD7608EDZ CED1Z 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board for the AD7608 Converter Evaluation Development Package Option ST-64-2 ST-64-2 Z = RoHS Compliant Part. ©2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08938-0-1/12(A) Rev. A | Page 32 of 32