AD7606BBSTZ-RL

Design Note Improving SystemLevel Performance and Robustness in Power Line Monitoring Lluis Beltran Gil, Applications Engineer Background For many applications, monitoring power lines implies the use of current transformers and resistor divider networks in order to sense the three phases and neutral voltages and currents, as shown in Figure 1. The AD7606B, due to its high input impedance, can directly interface with a sensor, easing the data acquisition system design as AD7606B provides all the required building blocks. Each of these channels is comprised of 21 V analog input clamp protection, a resistive programmable gain amplifier with 5 MΩ input impedance, a first-order antialiasing filter, and a 16-bit SAR ADC. Also, an optional digital averaging filter with oversampling ratios of up to 256 and a low drift 2.5 V reference are included to help build a complete power line data acquisition system. The AD7606B integrates, on-chip, eight individual signal chains that accept either ±10 V or ±5 V true bipolar analog input signals despite working from a single 5 V supply. These features eliminate the need for driver op amps and external bipolar supplies. In addition to the complete analog signal chain provided, the AD7606B has plenty of calibration and diagnostic features to improve system-level performance and robustness. AVCC ALDO Phase A Phase B Phase C Neutral V1 V1GND IAP RPD IAN V2 VAP V2GND VAN V3 IBP RPD V3GND IBN V4 VBP V4GND VBN V5 ICP RPD ICN V5GND VCP V6 VCN V6GND INP V7 V7GND Load Load Load INN V8 V8GND Clamp Clamp Clamp Clamp Clamp Clamp Clamp Clamp Clamp Clamp Clamp Clamp Clamp PGA LPF PGA 5 MΩ LPF       SAR 5 MΩ PGA 5 MΩ LPF SAR LPF SAR LPF SAR LPF SAR LPF SAR LPF SAR 5 MΩ PGA 5 MΩ 5 MΩ PGA 5 MΩ 5 MΩ PGA 5 MΩ PGA Clamp 5 MΩ Clamp Clamp CLK OSC CONVST Control Inputs RESET RANGE Programmable Digital Filter SW/HW Mode Control ADC, PGA, and Channel Control and Configuration OS[2:0] BUSY FRSTDATA Serial Parallel/ Serial Interface System Gain, Offset, and Phase Calibration SDI SCLK CS Parallel DB[15:0] PAR/SER SEL REFCAPA Diagnostics and Sensor Disconnect Configuration REFCAPB REFIN/REFOUT PGA VISIT ANALOG.COM DOUT [A:D] RD WR 5 MΩ 5 MΩ REGCAP VDRIVE DLDO 5 MΩ Figure 1. AD7606B in a typical power line monitoring application.   SAR 5 MΩ AGND   AD7606B 5 MΩ 5 MΩ AVCC REGCAP 2.5 V REF REFGND REF SELECT Direct Sensor Interface Unlike AD7606, AD7606B input impedance has been increased to 5 MΩ, which allows for it to directly interface with a wide variety of sensors while granting two straightforward benefits: X The gain error introduced by external series resistors (for example, the filtering or the resistor divider network) is reduced. X The offset seen when the sensor is disconnected decreases, allowing for easy sensor disconnect detection features. It is recommended to have an RPD much larger than the source impedance of the sensor in order to minimize the error that this parallel resistor may introduce. However, the larger the RPD, the larger the ADC output code generated when the sensor disconnects, which is not desired. A large ADC output code may lead to unnoticed sensor disconnection. Because the AD7606B has larger RIN than the AD7606, for a given RPD, the ADC output code is lower if the sensor disconnects, as shown in Figure 3, reducing the risk of false alarms. 120 100 Gain Error Due to External Resistors The higher the RFILTER, the greater the gain error becomes, which will require compensation on the controller side. But the higher the RIN, the less effect the same RFILTER will have. Unlike the AD7606’s 1 MΩ input impedance, the AD7606B has 5 MΩ input, meaning that the gain error will reduce about 1 over 5 for the same series resistor (RFILTER) without any calibration, as shown Figure 2. 80 60 ADC Code In factory trimming, there is tight control over RFB and RIN (5 MΩ typical) on a PGA, such that the AD7606B gain is accurately set. However, if an external resistor is placed in the front end, as shown in Figure 1, the actual gain then differs from the ideal trimmed RFB/RIN. 40 20 0 –20 AD7606 AD7606B 0 4k 8k 12k 16k 20k RPD (Ω) 0 Figure 3. Offset error when the sensor gets disconnected from the ADC’s analog inputs. When entering software mode for the AD7606B, there is an open-circuit detection feature, eliminating the burden on the back-end software that detects the sensor disconnection. After programming the number of samples N (N = 3 on the example of Figure 4), if the analog input remains for several samples reporting a small dc value, the algorithm will automatically run and assert a flag if the analog input signal has been disconnected. Gain Error (%) –0.5 –1.0 300 –1.5 280 AD7606 Gain Error AD7606B Gain Error (%) AD7606B Gain Compensated (%) –2.0 0 5k 10k PGA Common-Mode Low Error Flag Set 200 180 15k 20k RFILTER (Ω) Figure 2. Gain error introduced by a series resistor. However, by using the AD7606B in software mode, this system gain error can be automatically compensated on-chip, on a per channel basis, and completely eliminate the need for doing any gain calibration computation on the controller side. PGA Common-Mode High 100 80 0 PT/CT Disconnect –80 –100 –180 –200 Sensor Disconnect Detection –280 Traditionally, having a pull-down resistor (RPD) in parallel with the sensor (current transformer shown in Figure 1) allows users to detect when the sensor disconnects by monitoring if an ADC output code lower than 20 LSBs repeats for a number of samples (N). –300 0.015 0.016 0.018 0.02 Time Figure 4. Sensor disconnect detection. 2 Improving System-Level Performance and Robustness in Power Line Monitoring 0.022 0.02425 System-Level Performance Conclusions System Offset Calibration The AD7606B brings a complete data acquisition system on a chip to the market. All the analog front-end building blocks are implemented. It provides a complete set of advanced diagnostic features, as well as gain, offset, and phase-calibration. With this, the AD7606B reduces component cost and system design complexity, easing the journey to designing power line monitoring applications. When using a pair of external resistors, as seen in Figure 1, any mismatch between them will cause an offset. This offset can be measured as the ADC output code when the sensor is shortcut to ground. An offset from –128 LSBs to +127 LSBs can be then added to or subtracted from the conversion result by programming the corresponding channel offset register in order to compensate for that system offset. System Phase Calibration The CONVST pin manages the start of a conversion such that it triggers the process simultaneously on all channels. However, on applications where currents are measured through current transformers (CTs) while voltages are scaled down through a voltage divider, there will be a phase mismatch between current and voltage channels. To compensate for that, AD7606B can delay the sampling instant on any channels, such that the output signals can be realigned in phase, as shown in Figure 5. About the Author Lluis Beltran Gil received his B.S. in electronics engineering in 2009 and in industrial engineering in 2012, both from the Universitat Politècnica de València, UPV (Technical University of Valencia). After graduation, Lluis joined Analog Devices in 2013 as an applications engineer in the Precision Converter Group in Limerick, supporting temperature sensors. Currently, Lluis is working on the SAR ADC Applications Team within the Precision Converters Group, and he is based in Valencia, Spain. He can be reached at lluis.beltrangil@analog.com. Engage with the ADI technology experts in our online support community. Ask your tough design questions, browse FAQs, or join a conversation. Input V1 Input V4 CONVST Internal CONVST CH1 tPHASE_REG Internal CONVST CH4 Visit ez.analog.com tCONV Busy V1 Code V4 Code Figure 5. Phase realignment. System Robustness In order to increase system reliability, several diagnostic features have been included on-chip, namely: X Overvoltage/undervoltage comparators on every channel. X An interface check that clocks out fixed data on each channel in order to verify the communication. X SPI invalid read/write alerts if there is an attempt to write to or read from an invalid register. X BUSY STUCK HIGH alerts if the BUSY line continues longer than the normal time after a conversion has been initiated. X Reset detection alerts if a reset has been detected for either a full, partial, or power-on reset on the internal LDO regulator. X CRC can be performed in the memory map, ROM, and every interface communication in order to guarantee correct initialization and/or operation. For regional headquarters, sales, and distributors or to contact customer service and technical support, visit analog.com/contact. ©2020 Analog Devices, Inc. All rights reserved. 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