AD7606C-18BSTZ-RL

8-Channel DAS with 18-Bit, 1 MSPS Bipolar Input, Simultaneous Sampling ADC AD7606C-18 Data Sheet FEATURES CALIBRATION AND DIAGNOSTICS 18-bit ADC with 1 MSPS on all channels Input buffer with 1 MΩ minimum analog input impedance (RIN) Single 5 V analog supply and 1.71 V to 5.25 V VDRIVE Per channel selectable analog input ranges Bipolar single-ended: ±12.5 V, ±10 V, ±6.25 V, ±5 V, ±2.5 V Unipolar single-ended: 0 V to 12.5 V, 0 V to 10 V, 0 V to 5 V Bipolar differential: ±20 V, ±12.5 V, ±10 V, ±5 V Two bandwidth options: 25 kHz and 220 kHz, per channel Flexible digital filter, oversampling ratio up to 256 −40°C to +125°C operating range ±21 V input clamp protection with 6 kV ESD Pin to pin compatible to the AD7606B, AD7608, and AD7609 Performance 93 dB typical SNR for ±20 V bipolar differential range 102 dB SNR, oversampling by 32 −100 dB typical THD for all other ranges TUE = 0.05% of FSR maximum, external reference ±0.5 ppm/°C typical PFS and NFS error drift ±3 ppm/°C typical reference temperature coefficient Per channel system phase, offset, and gain calibration Analog input open circuit detection feature Self diagnostics and monitoring features CRC error checking on read and write data and registers APPLICATIONS Power line monitoring Protective relays Multiphase motor control Instrumentation and control systems Data acquisition systems COMPANION PRODUCTS Voltage References: ADR4525, LT6657, LTC6655 Digital Isolators: ADuM142E, ADuM6422A, ADuM5020, ADuM5028 AD7606x Family Software Model Additional companion products on the AD7606C-18 product page FUNCTIONAL BLOCK DIAGRAM 5V 5V 1.71V TO 5.25V 100nF 100nF 1µF AV CC AV CC REGCAP V1– CLAMP CLAMP 1MΩ 1MΩ PGA LPF 100nF VDRIVE REGCAP DLDO ALDO V1+ 1µF SAR CONVST RESET RANGE CLK OSC CONTROL INPUTS V8+ V8– OPTIONAL RC FILTER CLAMP CLAMP 1MΩ PGA LPF SAR SERIAL 10µF + VIN VOUT 1µF 0.1µF ADR4525 GND +2.5V REFCAPB REFIN/REFOUT + 100nF REFSELECT REFGND INTERNAL REFERENCE 2.5V REF GAIN, OFFSET AND PHASE CALIBRATION DIAGNOSTICS AND SENSOR DISCONNECT PARALLEL/ SERIAL INTERFACE DOUTA TO DOUTH SDI SCLK CS PARALLEL DB0 TO DB17 RD WR PAR/SER SEL AD7606C-18 24593-001 AVCC BUSY FRSTDATA PROGRAMMABLE DIGITAL FILTER ADC, PGA, AND CHANNEL CONFIGURATION REFCAPA OPTIONAL EXTERNAL REFERENCE OS0 TO OS2 1MΩ AGND Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2021 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7606C-18 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Padding Oversampling .............................................................. 37 Calibration and Diagnostics ........................................................... 1 External Oversampling Clock .................................................. 37 Applications ...................................................................................... 1 System Calibration Features ......................................................... 38 Companion Products ....................................................................... 1 System Phase Calibration.......................................................... 38 Functional Block Diagram .............................................................. 1 System Gain Calibration ........................................................... 38 Revision History ............................................................................... 2 System Offset Calibration ......................................................... 39 General Description ......................................................................... 3 Analog Input Open Circuit Detection .................................... 39 Specifications .................................................................................... 4 Digital Interface .............................................................................. 41 Timing Specifications .................................................................. 7 Parallel Interface......................................................................... 42 Absolute Maximum Ratings ......................................................... 11 Serial Interface ............................................................................ 45 Thermal Resistance .................................................................... 11 Diagnostics ...................................................................................... 50 Electrostatic Discharge (ESD) Ratings .................................... 11 Reset Detection ........................................................................... 50 ESD Caution................................................................................ 11 Digital Error ................................................................................ 50 Pin Configuration and Function Descriptions .......................... 12 Diagnostics Multiplexer ............................................................ 53 Typical Performance Characteristics ........................................... 16 Typical Connection Diagram ....................................................... 54 Terminology .................................................................................... 27 Applications Information ............................................................. 56 Theory of Operation ...................................................................... 29 Layout Guidelines ...................................................................... 56 Analog Front-End ...................................................................... 29 Register Summary .......................................................................... 58 SAR ADC ..................................................................................... 30 Register Details ............................................................................... 59 Reference ..................................................................................... 32 Outline Dimensions ....................................................................... 75 Operation Modes........................................................................ 32 Ordering Guide .......................................................................... 75 Digital Filter .................................................................................... 35 REVISION HISTORY 4/2021—Rev. 0 to Rev. A Changes to Features Section ........................................................... 1 Change to Table 1 ............................................................................. 3 Changes to Specifications Section and Table 2 ............................ 4 Change to Table 3 ............................................................................. 7 Changes to Figure 45 and Figure 46 ............................................ 22 Changes to Figure 58, Figure 59, and Figure 62......................... 24 Changes to Figure 78 and Figure 80 ............................................ 30 Changes to Table 18 ....................................................................... 35 Changes to Table 19 ....................................................................... 36 Change to System Gain Calibration Section .............................. 38 Added Figure 94; Renumbered Sequentially .............................. 38 Change to Table 23 ........................................................................ 41 Change to Figure 106 ..................................................................... 45 Changes to Temperature Sensor Section .................................... 53 10/2020—Revision 0: Initial Version Rev. A | Page 2 of 75 Data Sheet AD7606C-18 GENERAL DESCRIPTION The AD7606C-18 is an 18-bit, simultaneous sampling, analogto-digital data acquisition system (DAS) with eight channels. Each channel contains analog input clamp protection, a programmable gain amplifier (PGA), a low-pass filter (LPF), and an 18-bit successive approximation register (SAR) analogto-digital converter (ADC). The AD7606C-18 also contains a flexible digital filter, a low drift, 2.5 V precision reference, a reference buffer to drive the ADC, and flexible parallel and serial interfaces. The AD7606C-18 operates from a single 5 V supply and accommodates the following input ranges when sampling at throughput rates of 1 MSPS for all channels: • • • throughput rates, the AD7606C-18 flexible digital filter can be used to improve noise performance. In hardware mode, the AD7606C-18 is fully compatible with the AD7608 and AD7609. In software mode, the following advanced features are available: • • • • Bipolar single-ended: ±12.5 V, ±10 V, ±6.25 V, ±5 V, and ±2.5 V Unipolar single-ended: 0 V to 12.5 V, 0 V to 10 V, and 0 V to 5 V Bipolar differential: ±20 V, ±12.5 V, ±10 V, and ±5 V The input clamp protection tolerates voltages up to ±21 V. The single supply operation, on-chip filtering, and high input impedance eliminate the need for external driver op amps, which require bipolar supplies. For applications with lower • • • Analog input range selectable per channel with added ranges available High bandwidth mode (220 kHz) selectable per channel Additional oversampling options with an oversampling ratio up to 256 System gain, system offset, and system phase calibration, per channel Analog input open circuit detector Diagnostic multiplexer Monitoring functions (serial peripheral interface (SPI) invalid read and write, cyclic redundancy check (CRC), busy stuck monitor, and reset detection) Note that throughout this data sheet, multifunction pins, such as the RD/SCLK pin, are referred to either by the entire pin name or by a single function of the pin, for example, the SCLK pin, when only that function is relevant. Table 1. Bipolar Input, Simultaneous Sampling, Pin to Pin Compatible Family of Devices Input Type Single-Ended True Differential 1 2 Resolution (Bits) 18 16 14 18 RIN1 = 1 MΩ, 200 kSPS AD7608 AD7606 AD7606-6 AD7606-4 AD7607 AD7609 RIN = 5 MΩ, 800 kSPS AD7606B2 RIN = 1 MΩ, 1 MSPS AD7606C-182 AD7606C-16 AD7606C-182 RIN is input impedance. This state-of-the-art device is recommended for newer designs as an alternative to the AD7606, AD7608, and AD7609. Rev. A | Page 3 of 75 Number of Channels 8 8 6 4 8 8 AD7606C-18 Data Sheet SPECIFICATIONS Voltage reference (VREF) = 2.5 V external and internal, analog supply voltage (AVCC) = 4.75 V to 5.25 V, logic supply voltage (VDRIVE) = 1.71 V to 5.25 V, sample frequency (fSAMPLE) = 1 MSPS, TA = −40°C to +125°C, and all input voltage ranges, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Low Bandwidth Mode High Bandwidth Mode Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Channel to Channel Isolation Full-Scale (FS) Step Settling Time ANALOG INPUT FILTER −3 dB Full Power Bandwidth −0.1 dB Full Power Bandwidth Phase Delay Test Conditions/Comments Input frequency (fIN) = 1 kHz sine wave, unless otherwise noted Min Typ ±20 V bipolar differential range ±20 V bipolar differential range, oversampling by 32, fIN = 50 Hz ±12.5 V bipolar differential range ±10 V bipolar differential range ±5 V bipolar differential range ±12.5 V bipolar single-ended range ±10 V bipolar single-ended range ±6.25 V bipolar single-ended range ±5 V bipolar single-ended range ±2.5 V bipolar single-ended range 0 V to 12.5 V unipolar single-ended range 0 V to 10 V unipolar single-ended range 0 V to 5 V unipolar single-ended range ±20 V bipolar differential range ±12.5 V bipolar differential range ±10 V bipolar differential range ±5 V bipolar differential range ±12.5 V bipolar single-ended range ±10 V bipolar single-ended range ±6.25 V bipolar single-ended range ±5 V bipolar single-ended range ±2.5 V bipolar single-ended range 0 V to 12.5 V unipolar single-ended range 0 V to 10 V unipolar single-ended range 0 V to 5 V unipolar single-ended range Low bandwidth mode Unipolar input ranges All other ranges 91 93 102 dB dB 90 90 89 90 90.5 89 89 86.5 88.5 88 84.5 92 91.5 90.5 92 92.5 91.5 91 88 90 90 86.5 89 87 86 83.5 87.5 87 84.5 83.5 82 83 82 80 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB fIN on unselected channels up to 200 kHz 0.01% of FS, low bandwidth mode 0.01% of FS, high bandwidth mode Low bandwidth mode High bandwidth mode High bandwidth mode, 2.5 V bipolar, 0 V to 5 V unipolar Low bandwidth mode High bandwidth mode High bandwidth mode, 2.5 V bipolar, 0 V to 5 V unipolar Low bandwidth mode High bandwidth mode High bandwidth mode, ±2.5 V range, 0 V to 5 V unipolar Rev. A | Page 4 of 75 −97 −100 −105 −110 80 15 25 220 150 3.9 25 20 6.8 1.1 1.5 Max −95 Unit dB dB dB dB μs μs kHz kHz kHz kHz kHz kHz µs µs Data Sheet Parameter Phase Delay Matching AD7606C-18 Test Conditions/Comments Min Typ Max Unit 200 30 ns ns Bipolar input ranges Unipolar input ranges ±0.5 ±2 ±4 ±0.99 ±7.5 Bits LSB1 LSB1 LSB External reference External reference, ±2.5 V range Unipolar input ranges ±25 ±25 ±60 ±130 ±180 ±280 LSB LSB LSB ±20 ±120 LSB ±0.5 15 ±3 60 ppm/°C LSB 2.5 V range All other input ranges ±10 ±10 ±160 ±80 LSB1 LSB1 2.5 V range All other input ranges ±2 ±0.5 20 ±5 ±2.5 90 ppm/°C ppm/°C LSB1 ±40 ±1 20 ±40 ±2.5 20 ±240 ±7 160 ±200 ±7 160 LSB ppm/°C LSB LSB ppm/°C LSB Low bandwidth mode High bandwidth mode DC ACCURACY Resolution Differential Nonlinearity (DNL) Integral Nonlinearity (INL) No missing codes 18 Total Unadjusted Error (TUE)2 Bipolar Ranges Positive Full-Scale (PFS) and Negative Full-Scale (NFS) Error 3 PFS and NFS Error Drift PFS and NFS Error Matching Bipolar Zero Code Error Bipolar Zero Code Error Drift Bipolar Zero Code Error Matching Unipolar Ranges FS Error FS Error Drift FS Error Matching Zero Scale Error Zero Scale Error Drift Zero Scale Error Matching SYSTEM CALIBRATION PFS and NFS Calibration Range Offset Calibration Range Phase Calibration Range PFS and NFS Error Offset Error Phase Error ANALOG INPUT Input Voltage (VIN) Ranges Series resistor in front of the Vx+ and Vx− inputs 1 1 1 After gain calibration After offset calibration After phase calibration VIN = Vx+ − Vx− ±20 V bipolar differential range ±12.5 V bipolar differential range ±10 V bipolar differential range ±5 V bipolar differential range ±12.5 V bipolar single-ended range ±10 V bipolar single-ended range ±6.25 V bipolar single-ended range ±5 V bipolar single-ended range ±2.5 V bipolar single-ended range 0 V to 12.5 V unipolar single-ended range 0 V to 10 V unipolar single-ended range 0 V to 5 V unipolar single-ended range Rev. A | Page 5 of 75 64 512 255 ±60 ±2 ±1 −20 −12.5 −10 −5 −12.5 −10 −6.25 −5 −2.5 0 0 0 +20 +12.5 +10 +5 +12.5 +10 +6.25 +5 +2.5 12.5 10 5 kΩ LSB μs LSB LSB µs V V V V V V V V V V V V AD7606C-18 Parameter Absolute Voltage Negative Input Common-Mode Input Range Input Impedance (RIN) Analog Input Current Input Capacitance (CIN)4 Input Impedance Drift REFERENCE INPUT AND OUTPUT Reference Input Voltage DC Leakage Current Input Capacitance (CIN) Reference Output Voltage Reference Temperature Coefficient Reference Voltage to the ADC LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN) LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating State Leakage Current Output Capacitance4 Output Coding Bipolar Ranges Output Coding Unipolar Ranges CONVERSION RATE Conversion Time Acquisition Time5 Throughput Rate POWER REQUIREMENTS AVCC VDRIVE AVCC Current (IAVCC) Normal Mode (Static) Normal Mode (Operational) Standby Shutdown Mode VDRIVE Current (IVDRIVE) Normal Mode (Static) Normal Mode (Operational) Data Sheet Test Conditions/Comments Vx− − AGND ±12.5 V bipolar single-ended range ±10 V bipolar single-ended range ±6.25 V bipolar single-ended range ±5 V bipolar single-ended range ±2.5 V bipolar single-ended range 0 V to 12.5 V unipolar single-ended range 0 V to 10 V unipolar single-ended range 0 V to 5 V unipolar single-ended range ±20 V bipolar differential range ±12.5 V bipolar differential range ±10 V bipolar differential range ±5 V bipolar differential range Min −1 −0.6 −0.4 −0.1 −0.05 −6.5 −4.9 −2.3 −10 −7.8 −6 −3 1 Typ Max Unit +1.6 +1.9 +2.5 +2.7 +3 +1.2 +1.7 +4 +10 +7.8 +7 +5 V V V V V V V V V V V V MΩ µA pF ppm/°C 1.2 (VIN − 2)/RIN 5 ±1 ±25 External reference 2.495 2.5 Internal reference, TA = 25°C 2.4975 7.5 2.5 ±3 REFCAPA (Pin 44) and REFCAPB (Pin 45) 4.39 2.505 ±0.12 2.5025 ±10 4.41 0.7 × VDRIVE 0.2 × VDRIVE ±1 V V µA pF 0.2 ±1 V V µA pF 5 Source current (ISOURCE) = 100 µA Sink current (ISINK) = 100 µA V µA pF V ppm/°C V VDRIVE − 0.2 5 Twos complement Straight binary See Table 3 550 450 1000 ns ns kSPS 5 5.25 5.25 V V 9 45 8.5 5 0.5 11 50 10 6 5 mA mA mA mA µA 2.8 1.8 21 5 1.9 24 µA mA µA Per channel 4.75 1.71 fSAMPLE = 1 MSPS fSAMPLE = 10 kSPS fSAMPLE = 1 MSPS fSAMPLE = 10 kSPS Rev. A | Page 6 of 75 Data Sheet AD7606C-18 Parameter Standby Shutdown Mode Power Dissipation Normal Mode (Static) Normal Mode (Operational) Test Conditions/Comments Min fSAMPLE = 1 MSPS fSAMPLE = 10 kSPS Standby Shutdown Mode Typ 2.5 0.5 Max 4 1.5 Unit µA µA 47 245 45 26 5 58 272 52 32 24 mW mW mW mW µW LSB means least significant bit. With a ±2.5 V input range, 1 LSB = 19µV. With a ±5 V input range, 1 LSB = 38.14 µV. With a ±10 V input range, 1 LSB = 76.293 µV. TUE (% FSR) = TUE (LSB)/218 × 100. For example, 130 LSBs = 0.05 % of FSR. These specifications include the full temperature range variation and contribution from the reference buffer. 4 Not production tested. Sample tested during initial release to ensure compliance. 5 The ADC input is settled by the internal PGA. Therefore, the acquisition time is the time between the end of the conversion and the start of the next conversion with no impact on external components. 1 2 3 TIMING SPECIFICATIONS Universal Timing Specifications AVCC = 4.75 V to 5.25 V, VDRIVE = 1.71 V to 5.25 V, VREF = 2.5 V external reference and internal reference, and TA = −40°C to +125°C, unless otherwise noted. Interface timing tested using a load capacitance of 20 pF, dependent on VDRIVE and load capacitance for the serial interface. Table 3. Parameter tCYCLE tLP_CNV tHP_CNV tD_CNV_BSY tS_BSY Min 1 10 10 0 Unit µs ns ns ns ns tD_BSY 25 ns tACQ tCONV 0.35 0.5 1.7 3.6 7.6 15.5 31.0 62.75 126 252 0.65 1.75 3.8 7.85 16 32.5 65.0 130 256 μs μs μs μs μs μs μs μs μs μs Description Minimum time between consecutive CONVST rising edges (excluding oversampling modes)1 CONVST low pulse width CONVST high pulse width CONVST high to BUSY high delay time Minimum time from BUSY falling edge to RD falling edge setup time (in parallel interface) or to MSB being available on the DOUTx line (in serial interface) Minimum time between last RD falling edge (in parallel interface) or last LSB being clocked out (serial interface) and the following BUSY falling edge, read during conversion Acquisition time Conversion time, no oversampling Oversampling by 2 Oversampling by 4 Oversampling by 8 Oversampling by 16 Oversampling by 32 Oversampling by 64 Oversampling by 128 Oversampling by 256 55 2000 ns Partial RESET high pulse width Full RESET high pulse width Time between RESET falling edge and first CONVST rising edge 50 ns µs ns 274 µs 1 10 10 µs ms ms tRESET Partial Reset Full Reset tDEVICE_SETUP Partial Reset Full Reset tWAKE-UP Standby Shutdown tPOWER-UP 1 Typ Max 22 3200 Wake-up time after standby and shutdown mode (see Figure 86) Time between stable AVCC and VDRIVE and assert of RESET Applies to serial mode when all eight DOUTx lines are selected. Rev. A | Page 7 of 75 AD7606C-18 Data Sheet Universal Timing Diagram AVCC VDRIVE tPOWER-UP tRESET RESET tCYCLE tHP_CNV tDEVICE_SETUP tLP_CNV CONVST BUSY tACQ tS_BSY tD_BSY DOUTx DBx 24593-002 tCONV tD_CNV_BSY Figure 2. Universal Timing Diagram Parallel Mode Timing Specifications Table 4. Parameter tS_CS_RD Min 0 tH_RD_CS tHP_RD Typ Max Unit ns Description CS falling edge to RD falling edge setup time 0 ns RD rising edge to CS rising edge hold time 10 ns RD high pulse width tLP_RD 10 ns RD low pulse width tHP_CS 10 ns CS high pulse width 35 ns Delay from CS until DBx three-state disabled 30 25 ns ns ns VDRIVE > 2.7 V VDRIVE < 2.7 V Data hold time after falling edge of RD 40 ns CS rising edge to DBx high impedance tD_CS_DB tD_RD_DB tH_RD_DB Data access time after falling edge of RD 12 tDHZ_CS_DB tCYC_RD ns RD falling edge to next RD falling edge tD_CS_FD 30 20 ns Delay from CS falling edge until FRSTDATA three-state disabled tD_RD_FDH 30 ns Delay from RD falling edge until FRSTDATA high tD_RD_FDL 30 ns Delay from RD falling edge until FRSTDATA low tDHZ_CS_FD 25 ns Delay from CS rising edge until FRSTDATA three-state enabled tS_CS_WR 0 ns CS to WR setup time tHP_WR 2 ns WR high pulse width tLP_WR 35 ns WR low pulse width tH_WR_CS 0 ns WR hold time tS_DB_WR 5 ns Configuration data to WR setup time tH_WR_DB 5 ns Configuration data to WR hold time tCYC_WR 180 ns Configuration data settle time, WR rising edge to next WR rising edge Rev. A | Page 8 of 75 Data Sheet AD7606C-18 Parallel Mode Timing Diagrams CS tS_CS_RD tHP_RD tH_RD_CS tLP_RD RD tD_RD_DB tD_CS_DB tD_CS_FD tH_CS_DB tDHZ_CS_DB tH_RD_DB x ADC DATA ADC DATA tD_RD_FDH ADC DATA ADC DATA ADC DATA ADC DATA ADC DATA tD_RD_FDL ADC DATA tDHZ_CS_FD 24593-003 DB0 TO DB17 tCYC_RD FRSTDATA Figure 3. Parallel Mode Read, Separate CS and RD Pulses tCYC_RD tHP_CS CS AND RD tLP_RD DB0 TO DB17 ADC DATA tD_CS_FD ADC DATA ADC DATA tH_CS_DB tDHZ_CS_DB ADC DATA ADC DATA ADC DATA ADC DATA ADC DATA tDHZ_CS_FD tD_RD_FDL FRSTDATA 24593-004 tD_RD_DB Figure 4. Parallel Mode Read, Linked CS and RD Pulses CS tHP_WR tS_CS_WR tH_WR_CS tCYC_WR WR tH_WR_DB tLP_WR DB0 TO DB17 Figure 5. Parallel Mode Write Operation Serial Mode Timing Specifications Table 5. Parameter fSCLK Min Typ Max Unit 60 40 Description SCLK frequency, fSCLK = 1/tSCLK VDRIVE > 2.7 V VDRIVE < 2.7 V Minimum SCLK period CS to SCLK falling edge setup time tSCLK tS_CS_SCK 1/fSCLK 2 MHz MHz μs ns tH_SCK_CS 2 ns SCLK to CS rising edge hold time tLP_SCK tHP_SCK tD_CS_DO 0.4 × tSCLK 0.4 × tSCLK 18 ns ns ns SCLK low pulse width SCLK high pulse width Delay from CS until DOUTx three-state disabled 17 25 ns ns tD_SCK_DO tH_SCK_DO tS_SDI_SCK tH_SCK_SDI 5 10 9 0 ns ns ns ns Data out access time after SCLK rising edge VDRIVE > 2.7 V VDRIVE < 2.7 V Data out hold time after SCLK rising edge VDRIVE > 2.7 V VDRIVE < 2.7 V Data in setup time before SCLK falling edge Data in hold time after SCLK falling edge Rev. A | Page 9 of 75 24593-005 tS_DB_WR AD7606C-18 Parameter tDHZ_CS_DO Min tWR 25 Data Sheet Typ Max 25 Unit ns Description CS rising edge to DOUTx high impedance ns Time between writing and reading the same register or between two writes, if fSCLK >50 MHz tD_CS_FD 16 ns Delay from CS until DOUTx three-state disabled or delayed from CS until MSB valid tD_SCK_FDL tDHZ_FD 18 20 ns ns 18th SCLK falling edge to FRSTDATA low CS rising edge until FRSTDATA three-state enabled Serial Mode Timing Diagrams CS 2 1 3 16 tH_SCK_CS 17 18 tLP_SCK tD_CS_DO DB2 DB15 DB16 DB17 tDHZ_CS_DO tH_SCK_DO tD_SCK_DO DB0 DB1 tD_SCK_FDL tD_CS_FD tDHZ_FD 24593-006 SCLK DOUTx tHP_SCK tSCLK tS_CS_SCK FRSTDATA Figure 6. Serial Timing Diagram, ADC Mode (Channel 1) CS tSCLK tS_CS_SCK 1 SCLK 2 tHP_SCK 3 tH_SCK_CS 9 8 16 tLP_SCK tH_SCK_SDI tS_SDI_SCK tWR WEN tD_CS_DO DOUTx R/W ADD5 ADD0 DIN7 DIN0 tD_SCK_DO DOUT7 DOUT0 Figure 7. Serial Timing Interface, Register Map Read and Write Operations Rev. A | Page 10 of 75 24593-007 SDI Data Sheet AD7606C-18 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 6. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Parameter AVCC to AGND VDRIVE to AGND Analog Input Voltage to AGND1 Digital Input Voltage to AGND Digital Output Voltage to AGND REFIN to AGND Input Current to Any Pin Except Supplies1 Temperature Operating Range Storage Range Junction Pb/Sn, Soldering Reflow (10 sec to 30 sec) Pb-Free, Soldering Reflow 1 Rating −0.3 V to +6.5 V −0.3 V to AVCC + 0.3 V ±21 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to AVCC + 0.3 V ±10 mA −40°C to +125°C −65°C to +150°C 150°C 240 (+0)°C θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 7. Thermal Resistance Package Type ST-64-2 1 θJA1 40 θJC 7 Unit °C/W Simulated data based on JEDEC 2s2p thermal test PCB in a JEDEC natural convention environment. ELECTROSTATIC DISCHARGE (ESD) RATINGS The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only. 260 (+0)°C Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) latch-up. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Field induced charged device model (FICDM) per ANSI/ESDA/ JEDEC JS-002. ESD Ratings for AD7606C-18 Table 8. AD7606C-18, 64-Lead LQFP ESD Model HBM Analog Inputs Only All Other Pins FICDM ESD CAUTION Rev. A | Page 11 of 75 Withstand Threshold (V) 6000 4000 750 Class 3A C4 AD7606C-18 Data Sheet V1– V1+ V2+ V3+ V2– V4+ V3– V5+ V4– V6+ V5– V7+ V6– V8+ V7– V8– PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ANALOG INPUT DECOUPLING CAP PIN POWER SUPPLY GROUND PIN DATA OUTPUT DIGITAL OUTPUT DIGITAL INPUT REFERENCE INPUT/OUTPUT AVCC 1 48 AV CC PIN 1 AGND 2 OS 0 3 47 AGND 46 REFGND OS 1 4 45 REFCAPB OS 2 5 44 REFCAPA PAR/SER SEL 6 43 REFGND AD7606C-18 STBY 7 42 REFIN/REFOUT TOP VIEW (Not to Scale) RANGE 8 41 AGND 40 AGND CONVST 9 39 REGCAP WR 10 38 AV CC RESET 11 37 AV CC RD/SCLK 12 36 REGCAP CS 13 BUSY 14 35 AGND FRSTDATA 15 34 REF SELECT DB2 16 33 DB17/DB1 24593-008 DB16/DB0 DB15 DB14 DB13/SDI DB12/DOUT D AGND DB11/DOUT C DB9/DOUT A DB10/DOUT B VDRIVE DB8/DOUT H DB6/DOUTF DB7/DOUTG DB5/DOUTE DB3 DB4 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 8. Pin Configuration Table 9. Pin Function Description Pin No. 1, 37, 38, 48 Type1 P Mnemonic AVCC 2, 26, 35, 40, 41, 47 P AGND 3 to 5 DI OS0 to OS2 6 DI PAR/SER SEL 7 DI STBY 8 DI RANGE 9 DI CONVST 10 DI WR Description Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end amplifiers and to the ADC core. Decouple these supply pins to AGND. Analog Ground. The AGND pins are the ground reference points for all analog circuitry on the AD7606C-18. All analog input signals and external reference signals must be referred to the AGND pins. All six of the AGND pins must connect to the AGND plane of a system. Oversampling Mode Pins. OS0 to OS2 select the oversampling ratio or enable software mode (see Table 14 for oversampling bit decoding). See the Digital Filter section for more details about the oversampling mode of operation. Parallel/Serial Interface Selection Input. If the PAR/SER SEL pin is tied to a logic low, the parallel interface is selected. If the PAR/SER SEL pin is tied to a logic high, the serial interface is selected. See the Digital Interface section for more information on each interface available. Standby Mode Input. In hardware mode, the STBY pin, in combination with the RANGE pin, places the AD7606C-18 into one of two power-down modes: standby mode or shutdown mode. In software mode, the STBY pin is ignored. Therefore, it is recommended to connect the STBY pin to logic high. See the Power-Down Modes section for more information on both hardware mode and software mode. Analog Input Range Selection Input. In hardware mode, the RANGE pin determines the input range of the analog input channels (see Table 10). If the STBY pin is at logic low, the RANGE pin determines the power-down mode (see Table 16). In software mode, the RANGE pin is ignored. However, the RANGE pin must be tied high or low. Conversion Start Input. When the CONVST pin transitions from low to high, the analog input is sampled on all eight SAR ADCs. In software mode, the CONVST pin can be configured as an external oversampling clock. Providing a low jitter external clock helps improve the SNR performance for large oversampling ratios. See the External Oversampling Clock section for further details. Parallel Write Control Input. In hardware mode, the WR pin has no function. Therefore, the WR pin can be tied high, tied low, or shorted to CONVST. In software mode, the WR pin is the active low write pin for writing registers using the parallel interface. See the Parallel Interface section for more information. Rev. A | Page 12 of 75 Data Sheet AD7606C-18 Pin No. 11 Type1 DI Mnemonic RESET 12 DI RD/SCLK 13 DI CS 14 DO BUSY 15 DO FRSTDATA 16 to 18 DO/DI DB2 to DB4 19 DO/DI DB5/DOUTE 20 DO/DI DB6/DOUTF 21 DO/DI DB7/DOUTG 22 DO/DI DB8/DOUTH 23 P VDRIVE 24 DO/DI DB9/DOUTA 25 DO/DI DB10/DOUTB Description Reset Input, Active High. Full and partial reset options are available. The type of reset is determined by the length of the reset pulse. It is recommended that the device receives a full reset pulse after power-up. See the Reset Functionality section for further details. Parallel Data Read Control Input when the Parallel Interface is Selected (RD). Serial Clock Input when the Serial Interface is Selected (SCLK). See the Digital Interface section for more details. Chip Select. The CS pin is the active low chip select input for ADC data reads or register data reads and writes, in both the serial and parallel interfaces. See the Digital Interface section for more details. Busy Output. The BUSY pin transitions to a logic high along with the CONVST rising edge. The BUSY output remains high until the conversion process for all channels is complete. First Data Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back on the parallel interface (see Figure 3) or the serial interface (see Figure 6). See the Digital Interface section for more details. Parallel Output/Input Data Bits. When using the parallel interface, the DB2 to DB4 pins act as three-state parallel digital input and output pins (see the Parallel Interface section). When CS and RD are low, the DB2 to DB4 pins are used to output DB2 to DB4 of the conversion result during the first RD pulse and zeros during the second RD pulse (see Figure 99). When using the serial interface, tie the DB2 to DB4 pins to AGND. Parallel Output/Input Data Bit 5/Serial Interface Data Output Pin. When using the parallel interface, the DB5/DOUTE pin acts as a three-state parallel digital input/output pin. When CS and RD are low, the DB5/DOUTE pin is used to output DB5 of the conversion result during the first RD pulse and zero during the second RD pulse (see Figure 99). When using the serial interface, the DB5/DOUTE pin functions as DOUTE. See Table 23 for more details on each data interface and operation mode. Parallel Output/Input Data Bit 6/Serial Interface Data Output Pin. When using the parallel interface, the DB6/DOUTF pin acts as a three-state parallel digital input/output pin. When CS and RD are low, the DB6/DOUTF pin is used to output DB6 of the conversion result during the first RD pulse and zero during the second RD pulse (see Figure 99). When using the serial interface, the DB6/DOUTF pin functions as DOUTF. See Table 23 for more details on each data interface and operation mode. Parallel Output/Input Data Bit 7/Serial Interface Data Output Pin. When using the parallel interface, the DB7/DOUTG pin acts as a three-state parallel digital input/output pin. When CS and RD are low, the DB7/DOUTG pin is used to output DB7 of the conversion result during the first RD pulse and zero during the second RD pulse (see Figure 99). When using the serial interface, the DB7/DOUTG pin functions as DOUTG. See Table 23 for more details on each data interface and operation mode. Parallel Output/Input Data Bit 8/Serial Interface Data Output Pin. When using the parallel interface, the DB8/DOUTH pin acts as a three-state parallel digital input/output pin. When CS and RD are low, the DB8/DOUTH pin is used to output DB8 of the conversion result during the first RD pulse and zero during the second RD pulse (see Figure 99). When using the serial interface, the DB8/DOUTH pin functions as DOUTH. See Table 23 for more details on each data interface and operation mode. Logic Power Supply Input. The voltage (1.71 V to 5.25 V) supplied at the VDRIVE pin determines the operating voltage of the interface. The VDRIVE pin is nominally at the same supply as the supply of the host interface, that is, the data signal processor (DSP) and field programmable gate array (FPGA). Parallel Output/Input Data Bit 9/Serial Interface Data Output Pin. When using the parallel interface, the DB9/DOUTA pin acts as a three-state parallel digital input/output pin. When CS and RD are low, the DB9/DOUTA pin is used to output DB9 of the conversion result during the first RD pulse and zero during the second RD pulse (see Figure 99). When using the serial interface, the DB9/DOUTA pin functions as DOUTA. See Table 23 for more details on each data interface and operation mode. Parallel Output/Input Data Bit 10/Serial Interface Data Output Pin. When using the parallel interface, the DB10/DOUTB pin acts as a three-state parallel digital input and output pin. When CS and RD are low, the DB10/DOUTB pin is used to output DB10 of the conversion result during the first RD pulse and zero during the second RD pulse (see Figure 99). When using the serial interface, the DB10/DOUTB pin functions as DOUTB. See Table 23 for more details on each data interface and operation mode. Rev. A | Page 13 of 75 AD7606C-18 Data Sheet Pin No. 27 Type1 DO/DI Mnemonic DB11/DOUTC 28 DO/DI DB12/DOUTD 29 DO/DI DB13/SDI 30, 31 DO/DI DB14, DB15 32 DO/DI DB16/DB0 33 DO/DI DB17/DB1 34 DI REF SELECT 36, 39 P REGCAP 42 REF REFIN/REFOUT 43, 46 44, 45 REF REF REFGND REFCAPA, REFCAPB 49 50 51 52 53 54 55 56 57 AI AI AI AI AI AI AI AI AI V1+ V1− V2+ V2− V3+ V3− V4+ V4− V5+ Description Parallel Output/Input Data Bit 11/Serial Interface Data Output Pin. When using the parallel interface, the DB11/DOUTC pin acts as a three-state parallel digital input and output pin. When CS and RD are low, the DB11/DOUTC pin is used to output DB11 of the conversion result during the first RD pulse and zero during the second RD pulse (see Figure 99). When using the serial interface, the DB11/DOUTC pin functions as DOUTC if in software mode and using the 4 DOUTx line option or 8 DOUTx line option. See Table 23 for more details on each data interface and operation mode. Parallel Output/Input Data Bit 12/Serial Interface Data Output Pin. When using the parallel interface, the DB12/DOUTD pin acts as a three-state parallel digital input/output pin. When CS and RD are low, the DB12/DOUTD pin is used to output DB12 of the conversion result during the first RD pulse and zero during the second RD pulse (see Figure 99). When using serial interface, the DB12/DOUTD pin functions as DOUTD if in software mode and using the 4 DOUTx line option or 8 DOUTx line option. See Table 23 for more details on each data interface and operation mode. Parallel Output/Input Data Bit 13/Serial Data Input. When using parallel interface, the DB13/SDI pin acts as a three-state parallel digital input and output pin. When CS and RD are low, the DB13/SDI pin is used to output DB13 of the conversion result during the first RD pulse and zero during the second RD pulse (see Figure 99). When using the serial interface in software mode, the DB13/SDI pin functions as SDI. See Table 23 for more details on each data interface and operation mode. Parallel Output/Input Data Bits. When using the parallel interface, the DB14 and DB15 pins act as three-state parallel digital input and output pins (see the Parallel Interface section). When CS and RD are low, the DB14 and DB15 pins are used to output DB14 and DB15 of the conversion result during the first RD pulse and zeros during the second RD pulse (see Figure 99). When using the serial interface, tie the DB14 and DB15 pins to AGND. Parallel Output/Input Data Bits. When using the parallel interface, the DB16/DB0 pin acts as a three-state parallel digital input and output pin (see the Parallel Interface section). When CS and RD are low, the DB16/DB0 pin is used to output DB16 of the conversion result during the first RD pulse and DB0 of the same conversion result during the second RD pulse (see Figure 99). When using the serial interface, tie the DB16/DB0 pin to AGND. Parallel Output/Input Data Bits. When using the parallel interface, the DB17/DB1 pin acts as a three-state parallel digital input and output pin (see the Parallel Interface section). When CS and RD are low, the DB17/DB1 pin is used to output DB17 of the conversion result during the first RD pulse and DB1 of the same conversion result during the second RD pulse (see Figure 99). When using the serial interface, tie the DB17/DB1 pin to AGND. Internal/External Reference Selection Logic Input. If the REF SELECT pin is set to logic high, the internal reference is selected and enabled. If the REF SELECT pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. Decoupling Capacitor Pin for Voltage Output from 1.9 V Internal Regulator, Analog Low Dropout (ALDO) and Digital Low Dropout (DLDO). The REGCAP output pins must be decoupled separately to AGND using a 1 μF capacitor. The voltage on the REGCAP pins is in the range of 1.875 V to 1.93 V. Reference Input/Reference Output. The internal 2.5 V reference is available on the REFOUT pin for external use while the REF SELECT pin is set to logic high. Alternatively, by setting the REF SELECT pin to logic low, the internal reference is disabled and an external reference of 2.5 V must be applied to this input (REFIN). A 100 nF capacitor must be applied from the REFIN pin to ground, close to the REFGND pins, for both internal and external reference options. See the Reference section for more details. Reference Ground Pins. The REFGND pins must be connected to AGND. Reference Buffer Output Force and Sense Pins. The REFCAPA and REFCAPB pins must be connected together and decoupled to AGND using a low effective series resistance (ESR), 10 μF ceramic capacitor. The voltage on the REFCAPA and REFCAPB pins is typically 4.4 V. Channel 1 Positive Analog Input Pin. Channel 1 Negative Analog Input Pin. Channel 2 Positive Analog Input Pin. Channel 2 Negative Analog Input Pin. Channel 3 Positive Analog Input Pin. Channel 3 Negative Analog Input Pin. Channel 4 Positive Analog Input Pin. Channel 4 Negative Analog Input Pin. Channel 5 Positive Analog Input Pin. Rev. A | Page 14 of 75 Data Sheet Pin No. 58 59 60 61 62 63 64 1 Type1 AI AI AI AI AI AI AI AD7606C-18 Mnemonic V5− V6+ V6− V7+ V7− V8+ V8− Description Channel 5 Negative Analog Input Pin. Channel 6 Positive Analog Input Pin. Channel 6 Negative Analog Input Pin. Channel 7 Positive Analog Input Pin. Channel 7 Negative Analog Input Pin. Channel 8 Positive Analog Input Pin. Channel 8 Negative Analog Input Pin. P is power supply, DI is digital input, DO is digital output, REF is reference input/output, AI is analog input, and GND is ground. Rev. A | Page 15 of 75 AD7606C-18 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AMPLITUDE (dB) –60 –40 –80 –100 –120 –100 –120 –140 –160 –160 10 100 –180 0.1 24593-100 1 INPUT FREQUENCY (kHz) 0 –40 0 –40 –80 –100 –120 –60 –80 –100 –120 –140 –140 –160 –160 1 10 100 INPUT FREQUENCY (kHz) –180 0.1 24593-101 –180 0.1 0 0 –40 –80 –100 –120 –60 –80 –100 –120 –140 –140 –160 –160 1 10 INPUT FREQUENCY (kHz) 100 –180 0.1 24593-102 –180 0.1 100 0V TO 10V SINGLE-ENDED RANGE fSAMPLE = 1MSPS fIN = 1kHz 131072 POINT FFT SNR = 82dB THD = –100.4dB –20 AMPLITUDE (dB) –60 10 Figure 13. FFT, ±10 V Single-Ended Range, High Bandwidth Mode 0V TO 10V SINGLE-ENDED RANGE fSAMPLE = 1MSPS fIN = 1kHz 131072 POINT FFT SNR = 89.9dB THD = –98.2dB –40 1 INPUT FREQUENCY (kHz) Figure 10. FFT, ±10 V Single-Ended Range, Low Bandwidth Mode –20 100 ±10V SINGLE-ENDED RANGE fSAMPLE = 1MSPS fIN = 1kHz 131072 POINT FFT SNR = 86.9dB THD = –100.3dB –20 AMPLITUDE (dB) –60 10 Figure 12. FFT, ±20 V Differential Range, High Bandwidth Mode ±10V SINGLE-ENDED RANGE fSAMPLE = 1MSPS fIN = 1kHz 131072 POINT FFT SNR = 92.2dB THD = –104dB –20 1 INPUT FREQUENCY (kHz) Figure 9. Fast Fourier Transform (FFT), ±20 V Differential Range, Low Bandwidth Mode AMPLITUDE (dB) –80 –140 –180 0.1 AMPLITUDE (dB) –60 24593-103 –40 ±20V DIFFERENTIAL RANGE fSAMPLE = 1MSPS fIN = 1kHz 131072 POINT FFT SNR = 89.4dB THD = –100.4dB –20 24593-104 –20 AMPLITUDE (dB) 0 ±20V DIFFERENTIAL RANGE fSAMPLE = 1MSPS fIN = 1kHz 131072 POINT FFT SNR = 92.7dB THD = –103.5dB Figure 11. FFT, 0 V to 10 V Single-Ended Range, Low Bandwidth Mode 1 10 INPUT FREQUENCY (kHz) 100 24593-105 0 Figure 14. FFT, 0 V to 10 V Single-Ended Range, High Bandwidth Mode Rev. A | Page 16 of 75 Data Sheet AD7606C-18 110 106 103 110 OS 32 OS 64 OS 128 OS 256 NO OS OS 2 OS 4 OS 8 OS 16 103 95 91 88 ±20V DIFFERENTIAL RANGE LOW BW MODE INTERNAL OS CLOCK 0.1 84 1 10 50 INPUT FREQUENCY (kHz) Figure 15. SNR vs. Input Frequency for Different Oversampling Ratio (OSR) Values, ±20 V Differential Range, Low Bandwidth Mode, Internal Oversampling Clock (OS = Oversampling) 110 NO OS OS 2 OS 4 OS 8 OS 16 105 ±20V DIFFERENTIAL RANGE HIGH BW MODE, INTERNAL OS CLOCK 80 0.01 0.1 1 110 100 85 90 1 10 50 Figure 16. SNR vs. Input Frequency for Different OSR Values, ±10 V SingleEnded Range, Low Bandwidth Mode, Internal Oversampling Clock 110 100 10 Figure 19. SNR vs. Input Frequency for Different OSR Values, ±10 V SingleEnded Range, High Bandwidth Mode, Internal Oversampling Clock 110 105 fSAMPLE = 1MSPS/OSR NO OS OS 2 OS 4 OS 8 OS 16 OS 32 OS 64 OS 128 OS 256 0V TO 10V SINGLE-ENDED RANGE HIGH BW MODE, INTERNAL OS CLOCK 100 SNR (dB) 95 90 50 INPUT FREQUENCY (kHz) OS 32 OS 64 OS 128 OS 256 NO OS OS 2 OS 4 OS 8 OS 16 105 ±10V SINGLE-ENDED RANGE HIGH BW MODE, INTERNAL OS CLOCK 75 0.01 0.1 1 24593-107 0.1 fSAMPLE = 1MSPS/OSR 24593-110 80 ±10V SINGLE-ENDED RANGE LOW BW MODE INTERNAL OS CLOCK INPUT FREQUENCY (kHz) 95 90 85 85 fSAMPLE = 1MSPS/OSR 80 0V TO 10V SINGLE-ENDED RANGE LOW BW MODE, INTERNAL OS CLOCK 0.1 1 INPUT FREQUENCY (kHz) 10 50 75 0.01 24593-108 75 0.01 Figure 17. SNR vs. Input Frequency for Different OSR Values, 0 V to 10 V Single-Ended Range, Low Bandwidth Mode, Internal Oversampling Clock 0.1 1 INPUT FREQUENCY (kHz) 10 50 24593-111 SNR (dB) 95 85 fSAMPLE = 1MSPS/OSR 75 0.01 80 OS 32 OS 64 OS 128 OS 256 NO OS OS 2 OS 4 OS 8 OS 16 105 90 30 Figure 18. SNR vs. Input Frequency for Different OSR Values, ±20 V Differential Range, High Bandwidth Mode, Internal Oversampling Clock OS 32 OS 64 OS 128 OS 256 95 10 INPUT FREQUENCY (kHz) SNR (dB) SNR (dB) 100 fSAMPLE = 1MSPS/OSR 24593-109 fSAMPLE = 1MSPS/OSR 80 0.01 80 95 91 24593-106 84 OS 32 OS 64 OS 128 OS 256 99 SNR (dB) SNR (dB) 99 88 NO OS OS 2 OS 4 OS 8 OS 16 106 Figure 20. SNR vs. Input Frequency for Different OSR Values, 0 V to 10 V Single-Ended Range, High Bandwidth Mode, Internal Oversampling Clock Rev. A | Page 17 of 75 Data Sheet 110 105 105 100 100 95 95 SNR (dB) 110 90 75 0.01 0.1 1 85 OS 32 OS 64 OS 128 OS 256 10 80 50 INPUT FREQUENCY (kHz) 75 0.01 105 105 100 100 95 95 SNR (dB) 110 85 80 ±10V SINGLE-ENDED RANGE LOW BW MODE EXTERNAL OS CLOCK 75 0.01 0.1 1 10 50 Figure 22. SNR vs. Input Frequency for Different OSR Values, ±10 V SingleEnded Range, Low Bandwidth Mode, External Oversampling Clock 105 ±10V SINGLE-ENDED RANGE HIGH BW MODE EXTERNAL OS CLOCK 0.1 1 OS 32 OS 64 OS 128 OS 256 10 50 Figure 25. SNR vs. Input Frequency for Different OSR Values, ±10 V SingleEnded Range, High Bandwidth Mode, External Oversampling Clock 110 105 100 95 95 SNR (dB) 100 85 fSAMPLE = 1MSPS/OSR 0V TO 10V SINGLE-ENDED RANGE HIGH BW MODE, EXTERNAL OS CLOCK 90 85 NO OS OS 2 OS 4 OS 8 OS 16 OS 32 0.1 80 OS 64 OS 128 OS 256 1 INPUT FREQUENCY (kHz) 10 50 75 0.01 24593-114 75 0.01 50 INPUT FREQUENCY (kHz) 0V TO 10V SINGLE-ENDED RANGE LOW BW MODE, EXTERNAL OS CLOCK 90 10 NO OS OS 2 OS 4 OS 8 OS 16 fSAMPLE = 1MSPS/OSR 75 0.01 fSAMPLE = 1MSPS/OSR 80 1 90 80 INPUT FREQUENCY (kHz) 110 0.1 OS 64 OS 128 OS 256 85 OS 32 OS 64 OS 128 OS 256 NO OS OS 2 OS 4 OS 8 OS 16 fSAMPLE = 1MSPS/OSR OS 8 OS 16 OS 32 Figure 24. SNR vs. Input Frequency for Different OSR Values, ±20 V Differential Range, High Bandwidth Mode, External Oversampling Clock 110 90 NO OS OS 2 OS 4 INPUT FREQUENCY (kHz) 24593-113 SNR (dB) Figure 21. SNR vs. Input Frequency for Different OSR Values, ±20 V Differential Range, Low Bandwidth Mode, External Oversampling Clock SNR (dB) 90 24593-115 ±20V DIFFERENTIAL RANGE LOW BW MODE EXTERNAL OS CLOCK ±20V DIFFERENTIAL RANGE HIGH BW MODE, EXTERNAL OS CLOCK Figure 23. SNR vs. Input Frequency for Different OSR Values, 0 V to 10 V Single-Ended Range, Low Bandwidth Mode, External Oversampling Clock NO OS OS 2 OS 4 OS 8 OS 16 OS 32 0.1 OS 64 OS 128 OS 256 1 INPUT FREQUENCY (kHz) 10 50 24593-117 80 NO OS OS 2 OS 4 OS 8 OS 16 fSAMPLE = 1MSPS/OSR fSAMPLE = 1MSPS/OSR 24593-116 85 24593-112 SNR (dB) AD7606C-18 Figure 26. SNR vs. Input Frequency for Different OSR Values, 0 V to 10 V Single-Ended Range, High Bandwidth Mode, External Oversampling Clock Rev. A | Page 18 of 75 Data Sheet THD (dB) –90 –95 –100 –95 –100 –105 –110 –110 –115 –115 –120 –25 –120 –25 –20 –15 –10 –5 0 Figure 27. THD vs. Input Level, ±20 V Differential Range, Low Bandwidth Mode –70 –75 –70 –75 THD (dB) –100 –90 –100 –105 –110 –110 –115 –115 –15 –10 –5 0 INPUT LEVEL (dBFS) Figure 28. THD vs. Input Level, ±10 V Single-Ended Range, Low Bandwidth Mode –70 –75 –120 –25 24593-119 –20 –85 –75 –85 THD (dB) –95 –90 –110 –115 –115 –10 –5 0 INPUT LEVEL (dBFS) 24593-120 –105 –15 0 Figure 29. THD vs. Input Level, 0 V to 10 V Single-Ended Range, Low Bandwidth Mode 1kHz INPUT FREQUENCY 10kHz INPUT FREQUENCY 50kHz INPUT FREQUENCY 100kHz INPUT FREQUENCY –95 –110 –20 –5 –100 –105 –120 –25 –10 0V TO 10V SINGLE-ENDED RANGE HIGH BW MODE –80 1kHz INPUT FREQUENCY 10kHz INPUT FREQUENCY –100 –15 Figure 31. THD vs. Input Level, ±10 V Single-Ended Range, High Bandwidth Mode –70 –90 –20 INPUT LEVEL (dBFS) 0V TO 10V SINGLE-ENDED RANGE LOW BW MODE –80 0 –95 –105 –120 –25 –5 1kHz INPUT FREQUENCY 10kHz INPUT FREQUENCY 50kHz INPUT FREQUENCY 100kHz INPUT FREQUENCY –85 –95 –10 ±10V SINGLE-ENDED RANGE HIGH BW MODE –80 –90 –15 Figure 30. THD vs. Input Level, ±20 V Differential Range, High Bandwidth Mode 1kHz INPUT FREQUENCY 10kHz INPUT FREQUENCY –85 –20 INPUT LEVEL (dBFS) ±10V SINGLE-ENDED RANGE LOW BW MODE –80 THD (dB) –90 –105 INPUT LEVEL (dBFS) THD (dB) 1kHz INPUT FREQUENCY 10kHz INPUT FREQUENCY 50kHz INPUT FREQUENCY 100kHz INPUT FREQUENCY –85 24593-118 THD (dB) –80 1kHz INPUT FREQUENCY 10kHz INPUT FREQUENCY –85 ±20V DIFFERENTIAL RANGE HIGH BW MODE 24593-121 –80 –75 24593-122 –75 –70 ±20V DIFFERENTIAL RANGE LOW BW MODE –120 –25 –20 –15 –10 –5 0 INPUT LEVEL (dBFS) Figure 32. THD vs. Input Level, 0 V to 10 V Single-Ended Range, High Bandwidth Mode Rev. A | Page 19 of 75 24593-123 –70 AD7606C-18 AD7606C-18 –80 –85 THD (dB) –90 –95 –105 –105 1 40 10 –110 0.01 24593-124 0.1 –75 –80 –75 –80 –85 –90 –90 THD (dB) –85 –100 0.1 1 10 40 INPUT FREQUENCY (kHz) –90 –75 –80 0.1 1 10 40 0V TO 10V SINGLE-ENDED RANGE HIGH BW MODE fSAMPLE = 1MSPS RSOURCE MATCHED ON Vx+ AND Vx– –85 0Ω 50Ω 1kΩ 10kΩ 50kΩ –95 –90 –95 –100 –105 –105 0.1 1 INPUT FREQUENCY (kHz) 10 40 24593-126 –100 –110 0.01 0Ω 50Ω 1kΩ 10kΩ 50kΩ Figure 37. THD vs. Input Frequency for Various Source Impedances, ±10 V Single-Ended Range, High Bandwidth Mode 0V TO 10V SINGLE-ENDED RANGE LOW BW MODE fSAMPLE = 1MSPS RSOURCE MATCHED ON Vx+ AND Vx– –85 –95 INPUT FREQUENCY (kHz) THD (dB) –80 40 ±10V SINGLE-ENDED RANGE HIGH BW MODE fSAMPLE = 1MSPS RSOURCE MATCHED ON Vx+ AND Vx– –110 0.01 Figure 34. THD vs. Input Frequency for Various Source Impedances, ±10 V Single-Ended Range, Low Bandwidth Mode –75 10 –105 24593-125 –110 0.01 1 –100 0Ω 50Ω 1kΩ 10kΩ 50kΩ –105 0.1 Figure 36. THD vs. Input Frequency for Various Source Impedances, ±20 V Differential Range, High Bandwidth Mode ±10V SINGLE-ENDED RANGE LOW BW MODE fSAMPLE = 1MSPS RSOURCE MATCHED ON Vx+ AND Vx– –95 0Ω 50Ω 1kΩ 10kΩ 50kΩ INPUT FREQUENCY (kHz) Figure 33. THD vs. Input Frequency for Various Source Impedances (RSOURCE), ±20 V Differential Range, Low Bandwidth Mode THD (dB) –95 –100 INPUT FREQUENCY (kHz) THD (dB) –90 –100 –110 0.01 ±20V DIFFERENTIAL RANGE HIGH BW MODE fSAMPLE = 1MSPS RSOURCE MATCHED ON Vx+ AND Vx– 24593-127 –85 THD (dB) –75 0Ω 50Ω 1kΩ 10kΩ 50kΩ 24593-128 –80 ±20V DIFFERENTIAL RANGE LOW BW MODE fSAMPLE = 1MSPS RSOURCE MATCHED ON Vx+ AND Vx– Figure 35. THD vs. Input Frequency for Various Source Impedances, 0 V to 10 V Single-Ended Range, Low Bandwidth Mode –110 0.01 0Ω 50Ω 1kΩ 10kΩ 50kΩ 0.1 1 INPUT FREQUENCY (kHz) 10 40 24593-129 –75 Data Sheet Figure 38. THD vs. Input Frequency for Various Source Impedances, 0 V to 10 V Single-Ended Range, High Bandwidth Mode Rev. A | Page 20 of 75 0 65536 131072 196608 262144 CODE 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –1.0 ±10V SINGLE-ENDED RANGE HIGH BW MODE INTERNAL REFERENCE 0 65536 4.0 ±10V SINGLE-ENDED RANGE LOW BW MODE INTERNAL REFERENCE ±10V SINGLE-ENDED RANGE HIGH BW MODE INTERNAL REFERENCE 3.5 3.0 2.5 2.0 INL (LSB) 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 65536 131072 196608 262144 65536 0 94 92 92 90 90 SNR (dB) 88 AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 1MSPS LOW BW MODE 84 AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 1MSPS HIGH BW MODE 88 86 ±20V DIFFERENTIAL RANGE ±10V SINGLE-ENDED RANGE 0V TO 10V SINGLE-ENDED RANGE 84 ±20V DIFFERENTIAL RANGE ±10V SINGLE-ENDED RANGE 0V TO 10V SINGLE-ENDED RANGE –20 0 20 45 65 82 85 105 TEMPERATURE (°C) 125 24593-132 SNR (dB) Figure 43. Typical INL, High Bandwidth Mode 94 80 –40 262144 196608 CODE Figure 40. Typical INL, Low Bandwidth Mode 82 131072 Figure 41. SNR vs. Temperature, Low Bandwidth Mode 80 –40 –20 0 20 45 65 85 105 TEMPERATURE (°C) Figure 44. SNR vs. Temperature, High Bandwidth Mode Rev. A | Page 21 of 75 125 24593-135 0 –3.0 –3.5 –4.0 24593-134 –2.5 CODE 86 262144 Figure 42. Typical DNL, High Bandwidth Mode 24593-131 INL (LSB) –3.0 –3.5 –4.0 196608 CODE Figure 39. Typical DNL, Low Bandwidth Mode 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 131072 24593-133 ±10V SINGLE-ENDED RANGE LOW BW MODE INTERNAL REFERENCE DNL (LSB) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –1.0 AD7606C-18 24593-130 DNL (LSB) Data Sheet AD7606C-18 LOW BW MODE ±20V DIFFERENTIAL RANGE 30 NFS 10 0 –10 PFS –20 –30 –20 CH3 CH4 0 20 CH5 CH6 40 CH7 CH8 25 20 15 60 80 5 100 120 TEMPERATURE (°C) 0 –1.0 LOW BW MODE ±10V SINGLE-ENDED RANGE NUMBER OF HITS 35 NFS PFS –20 2.0 30 25 20 15 –20 CH 5 CH 6 CH 3 CH 4 0 20 40 60 5 CH 7 CH 8 80 100 120 TEMPERATURE (°C) 0 –1.0 Figure 46. PFS and NFS Error vs. Temperature, ±10 V Single-Ended Range 0.5 1.0 1.5 50 FS 45 40 35 NUMBER OF HITS 30 20 10 0 –10 –20 2.0 Figure 49. Bipolar Zero Code (BZC) Drift Histogram, ±10 V Single-Ended Range LOW BW MODE 0V TO 10V SINGLE-ENDED RANGE ZS 30 25 20 15 10 –30 CH 3 CH 4 CH 1 CH 2 –20 0 20 CH 5 CH 6 40 60 5 CH 7 CH 8 80 100 120 TEMPERATURE (°C) Figure 47. FS Error vs. Temperature, 0 V to 10 V Single-Ended Range 0 –1.0 24593-138 –50 –40 0 BZC DRIFT (PPM/°C) fSAMPLE = 1MSPS –40 –0.5 24593-140 –50 –40 CH 1 CH 2 24593-137 –40 40 1.5 10 –30 50 1.0 45 20 –10 0.5 50 fSAMPLE = 1MSPS 40 0 0 Figure 48. PFS and NFS Drift Histogram, ±10 V Single-Ended Range 30 10 –0.5 PFS AND NFS DRIFT (PPM/°C) Figure 45. Positive Full-Scale (PFS) and Negative Full-Scale (NFS) Error vs. Temperature, ±20 V Differential Range PFS AND NFS ERROR (LSB) 30 24593-139 CH1 CH2 24593-136 –50 –40 FS ERROR (LSB) 35 10 –40 40 NFS 40 20 50 PFS 45 NUMBER OF HITS PFS AND NFS ERROR (LSB) 40 50 fSAMPLE = 1MSPS –0.5 0 0.5 1.0 FS AND ZS DRIFT (PPM/°C) 1.5 2.0 24593-141 50 Data Sheet Figure 50. FS and Zero-Scale (ZS) Drift Histogram, 0 V to 10 V Single-Ended Range Rev. A | Page 22 of 75 Data Sheet 30 700 NUMBER OF HITS 10 0 –10 –20 –40 –50 –40 –20 CH 5 CH 6 CH 3 CH 4 CH 1 CH 2 0 20 40 60 80 100 120 –40 –30 –20 –10 0 10 20 30 800 LOW BW MODE ±10V SINGLE-ENDED RANGE 30 600 NUMBER OF HITS 10 0 –10 –20 500 400 300 200 –30 –40 –20 CH 5 CH 6 CH 3 CH 4 CH 1 CH 2 0 20 40 60 100 120 TEMPERATURE (°C) 0 –50 900 LOW BW MODE 0V TO 10V SINGLE-ENDED RANGE 30 700 NUMBER OF HITS 0 –10 –20 –10 0 10 20 30 40 50 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 600 500 400 300 200 –30 CH 3 CH 4 CH 1 CH 2 –20 0 20 CH 5 CH 6 40 60 TEMPERATURE (°C) 100 CH 7 CH 8 80 100 120 24593-144 –50 –40 –20 VIN = 1mV TA = 25°C 4096 SAMPLES PEAK TO PEAK = 20 800 10 –30 Figure 55. Histogram of Codes, ±10 V Single-Ended Range fSAMPLE = 1MSPS 20 –40 ADC CODE Figure 52. Bipolar Zero Code Error vs. Temperature, ±10 V Single-Ended Range –40 Vx+ AND Vx– SHORTED TO AGND TA = 25°C 4096 SAMPLES AVERAGE = –13.5076 PEAK TO PEAK = 16 100 CH 7 CH 8 80 50 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 700 20 40 Figure 54. Histogram of Codes, ±20 V Differential Range 24593-143 BIPOLAR ZERO CODE ERROR (LSB) Vx+ AND Vx– SHORTED TO AGND TA = 25°C 4096 SAMPLES AVERAGE = –15.8679 PEAK TO PEAK = 14 ADC CODE fSAMPLE = 1MSPS –50 –40 ZS ERROR (LSB) 300 0 –50 Figure 51. Bipolar Zero Code Error vs. Temperature, ±20 V Differential Range 40 400 100 CH 7 CH 8 TEMPERATURE (°C) 50 500 200 –30 40 600 24593-146 20 50 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 800 24593-145 LOW BW MODE ±20V DIFFERENTIAL RANGE 24593-142 BIPOLAR ZERO CODE ERROR (LSB) 40 900 fSAMPLE = 1MSPS 0 0 10 20 30 40 50 ADC CODE Figure 56. Histogram of Codes, 0 V to 10 V Single-Ended Range Figure 53. ZS Error vs. Temperature, 0 V to 10 V Single-Ended Range Rev. A | Page 23 of 75 24593-147 50 AD7606C-18 AD7606C-18 30 25 20 15 TA = –40°C TA = +25°C TA = +125°C 0 200 400 600 800 1000 Figure 57. AVCC Supply Current vs. Throughput Rate for Various Temperatures 10 5 0 Vx+ –10 100 200 –10 –5 0 5 10 15 20 900 1000 2.501 2.500 2.499 2.498 –20 Vx+ –15 40 –5.0 –2.5 0 2.5 5.0 7.5 INPUT VOLTAGE, [Vx+] – [Vx–] (V) 10.0 12.5 Figure 59. Analog Input Current vs. Input Voltage for Various Bipolar SingleEnded Ranges 60 80 100 120 AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 1MSPS TA = 25°C Vx– TIED TO AGND 0V TO 12.5V 0V TO 10V 0V TO 5V 8 7 6 5 3 2 Vx+ 1 0 –1 Vx– –2 –3 24593-150 –20 –12.5 –10.0 –7.5 20 Figure 61. Reference Drift 9 Vx– 0 TEMPERATURE (°C) ANALOG INPUT CURRENT (µA) ANALOG INPUT CURRENT (µA) 800 2.502 10 AV CC = 5V, VDRIVE = 3.3V fSAMPLE = 1MSPS TA = 25°C Vx– TIED TO AGND ±12.5V ±10V ±6.25V ±5V ±2.5V –5 –10 700 2.503 2.495 –40 24593-149 –15 5 0 600 AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 1MSPS Figure 58. Analog Input Current vs. Input Voltage for Various Differential Ranges 10 500 2.496 INPUT VOLTAGE, [Vx+] – [Vx–] (V) 15 400 2.497 –15 20 300 Figure 60. AVCC Supply Current vs. Throughput Rate, Normal Mode and Autostandby Mode 2.504 0 –20 –20 AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE LOW BW MODE TA = 25°C 10 2.505 Vx– –5 15 THROUGHPUT RATE (kSPS) REFERENCE VOLTAGE (V) ANALOG INPUT CURRENT (µA) 15 20 0 AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 1MSPS TA = 25°C ±20V ±12.5V ±10V ±5V 25 5 THROUGHPUT RATE (kSPS) 20 30 24593-148 5 35 24593-151 35 10 40 AVCC SUPPLY CURRENT (µA) 40 0 NORMAL MODE AUTOSTANDBY MODE 45 24593-152 45 AVCC SUPPLY CURRENT (µA) 50 AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE LOW BW MODE 0 2 4 6 8 10 INPUT VOLTAGE, [Vx+] – [Vx–] (V) 12 24593-153 50 Data Sheet Figure 62. Analog Input Current vs. Input Voltage for Various Unipolar Single-Ended Ranges Rev. A | Page 24 of 75 Data Sheet AD7606C-18 5000 104858 52429 26214 0 LOW BW RISING HIGH BW RISING LOW BW FALLING HIGH BW FALLING –26214 –52429 –78643 0 10 20 30 40 50 60 70 TIME (µs) –1000 –2000 LOW BW RISING HIGH BW RISING LOW BW FALLING HIGH BW FALLING –3000 –4000 0 10 20 30 40 50 60 70 Figure 66. Step Response, ±20 V Differential Range, Fine Settling DEVIATION FROM FINAL VALUE (LSB) ±10V SINGLE-ENDED RANGE 1kHz SQUARE WAVE 78643 52429 26214 0 –26214 –52429 LOW BW RISING HIGH BW RISING LOW BW FALLING HIGH BW FALLING –78643 –104858 0 10 20 30 40 50 60 70 TIME (µs) 4000 ±10V SINGLE-ENDED RANGE 1kHz SQUARE WAVE 3000 2000 1000 0 –1000 LOW BW RISING HIGH BW RISING LOW BW FALLING HIGH BW FALLING –2000 –3000 –4000 –5000 24593-155 ADC OUTPUT CODE (LSB) 0 5000 104858 10 0 20 30 40 50 60 70 TIME (µs) Figure 64 Step Response, ±10 V Single-Ended Range Figure 67. Step Response, ±10 V Single-Ended Range, Fine Settling 262144 5000 235930 4000 0V TO 10V SINGLE-ENDED RANGE 1kHz SQUARE WAVE 183501 157286 131072 LOW BW RISING HIGH BW RISING LOW BW FALLING HIGH BW FALLING 104858 78643 52429 0V TO 10V SINGLE-ENDED RANGE 1kHz SQUARE WAVE 3000 ADC OUTPUT CODE (LSB) 209715 2000 1000 0 LOW BW RISING HIGH BW RISING LOW BW FALLING HIGH BW FALLING –1000 –2000 –3000 26214 –4000 0 10 20 30 40 50 60 TIME (µs) Figure 65. Step Response, 0 V to 10 V Single-Ended Range 70 –5000 24593-156 ADC OUTPUT CODE (LSB) 1000 TIME (µs) 131072 0 2000 –5000 Figure 63. Step Response, ±20 V Differential Range –131072 ±20V DIFFERENTIAL RANGE 1kHz SQUARE WAVE 3000 24593-758 –131072 24593-154 –104858 4000 0 10 20 30 40 50 TIME (µs) 60 70 80 90 100 24593-759 ADC OUTPUT CODE (LSB) 78643 DEVIATION FROM FINAL VALUE (LSB) ±20V DIFFERENTIAL RANGE 1kHz SQUARE WAVE 24593-157 131072 Figure 68. Step Response, 0 V to 10 V Single-Ended Range, Fine Settling Rev. A | Page 25 of 75 AD7606C-18 –70 –100 –110 –120 –130 –140 0.01 0.1 1 10 100 300 NOISE FREQUENCY (kHz) –100 –110 –120 –130 –140 0.01 –55 –60 –60 –65 –65 AC PSRR (dB) –55 –70 ±20V DIFFERENTIAL RANGE ±10V SINGLE-ENDED RANGE 0V TO 10V SINGLE-ENDED RANGE –90 10 100 1k 10k 1M FREQUENCY (Hz) Figure 70. AC Power Supply Rejection Ratio (PSRR) vs. Frequency, Low Bandwidth Mode 1.176 1.175 CH3 CH4 CH1 CH2 1.173 1.172 1.171 1.170 1.169 1.168 1.167 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 24593-762 INPUT IMPEDANCE (MΩ) 1.174 1.166 –40 300 –90 RECOMMENDED DECOUPLING USED fSAMPLE = 1MSPS HIGH BW MODE 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 73. AC PSRR vs. Frequency, High Bandwidth Mode CH7 CH8 CH5 CH6 100 ±20V DIFFERENTIAL RANGE ±10V SINGLE-ENDED RANGE 0V TO 10V SINGLE-ENDED RANGE –75 –85 100k 10 –70 –80 RECOMMENDED DECOUPLING USED fSAMPLE = 1MSPS LOW BW MODE 24593-761 AC PSRR (dB) –50 –85 1 Figure 72. Channel to Channel Isolation vs. Noise Frequency, High Bandwidth Mode –50 –80 0.1 NOISE FREQUENCY (kHz) Figure 69. Channel to Channel Isolation vs. Noise Frequency, Low Bandwidth Mode –75 ±20V DIFFERENTIAL RANGE ±10V SINGLE-ENDED RANGE 0V TO 10V SINGLE-ENDED RANGE –90 24593-763 ±20V DIFFERENTIAL RANGE ±10V SINGLE-ENDED RANGE 0V TO 10V SINGLE-ENDED RANGE –90 INTERNAL REFERENCE HIGH BW MODE INTERFERER IN ALL UNSELECTED CHANNELS –80 Figure 71. Input Impedance vs. Temperature Rev. A | Page 26 of 75 24593-764 –80 CHANNEL TO CHANNEL ISOLATION (dB) INTERNAL REFERENCE LOW BW MODE INTERFERER IN ALL UNSELECTED CHANNELS 24593-760 CHANNEL TO CHANNEL ISOLATION (dB) –70 Data Sheet Data Sheet AD7606C-18 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale at ½ LSB below the first code transition and full scale at ½ LSB above the last code transition. Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Bipolar Zero Code Error Bipolar zero code error is the deviation of the midscale transition (all 1s to all 0s) from the ideal, which is 0 V − ½ LSB. Bipolar Zero Code Error Matching Bipolar zero code error matching is the absolute difference in bipolar zero code error between any two input channels. Open Circuit Code Error Open circuit code error is the ADC output code when there is an open circuit on the analog input and a pull-down resistor (RPD) connected between the analog input pair of pins. See Figure 95 for more details. Positive Full-Scale (PFS) Error In bipolar ranges, PFS error is the deviation of the actual last code transition from the ideal last code transition (for example, 10 V − 1½ LSB (9.99988), 5 V − 1½ LSB (4.99994), or 2.5 V − 1½ LSB (2.49997)) after the bipolar zero code error is adjusted out. The PFS error includes the contribution from the reference buffer. Positive Full-Scale (PFS) Error Matching PFS error matching is the absolute difference in positive full-scale error between any two input channels. Negative Full-Scale (NFS) Error In bipolar ranges, NFS error is the deviation of the first code transition from the ideal first code transition (for example, −10 V + ½ LSB (−9.99996), −5 V + ½ LSB (−4.99998), or −2.5 V + ½ LSB (−2.49999)) after the bipolar zero code error is adjusted out. The NFS error includes the contribution from the reference buffer. Negative Full-Scale (NFS) Error Matching NFS error matching is the absolute difference in negative full-scale error between any two input channels. Full-Scale (FS) Error In unipolar ranges, FS error is the deviation of the actual last code transition from the ideal last code transition (for example, 10 V − 1½ LSB (9.99954), or 5 V − 1½ LSB (4.99977)) after the zero scale error is adjusted out. The FS error includes the contribution from the reference buffer Zero Scale (ZS) Error In unipolar ranges, ZS error is the deviation of the first code transition from the ideal first code transition, which is 0 V − ½ LSB. Total Unadjusted Error (TUE) TUE is the maximum deviation of the output code from the ideal. TUE includes INL errors, bipolar zero code and positive and negative full-scale errors, and reference errors. Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD ratio is the measured ratio of signal-to-noise-anddistortion at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half of the sampling frequency (fS/2, excluding dc). The ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical SINAD for an ideal N-bit converter with a sine wave input is given by SINAD = (6.02N + 1.76) dB Thus, for a 16-bit converter, the SINAD is 98 dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the harmonics to the fundamental. For the AD7606C-18, it is defined as THD (dB) = 20log V22 + V32 + V4 2 + V52 + V62 + V7 2 + V82 + V92 V1 where: V2 to V9 are the rms amplitudes of the second through ninth harmonics. V1 is the rms amplitude of the fundamental. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, the value is determined by a noise peak. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. The power supply rejection (PSR) is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. The PSRR is defined as the ratio of the 100 mV p-p sine wave applied to the AVCC supplies of the ADC frequency, fS, to the power of the ADC output at that frequency, fS. PSRR (dB) = 20 log (0.1/PfS) where: PfS is equal to the power at frequency, fS, coupled onto the AVCC supply. Rev. A | Page 27 of 75 AD7606C-18 Data Sheet Channel to Channel Isolation Channel to channel isolation is a measure of the level of crosstalk between all input channels. It is measured by applying a full-scale sine wave signal, up to 200 kHz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 kHz sine wave signal applied (see Figure 58). Phase Delay Phase delay is a measure of the absolute time delay between when an input is sampled by the converter and when the result associated with that sample is available to be read back from the ADC, including delay induced by the analog front end of the device. Phase Delay Drift Phase delay drift is the change in phase delay per unit temperature across the entire operating temperature of the device. Phase Delay Matching Phase delay matching is the maximum phase delay seen between any simultaneously sampled pair. Box Method The box method is represented by the following equation: TCVOUT = max{VOUT (T1 ,T2 ,T3 )} − min{VOUT (T1 ,T2 ,T3 )} VOUT (T2 ) × (T3 − T1 ) × 106 where: TCVOUT is expressed in ppm/°C. VOUT(TX) is the output voltage at temperature TX. T1 = −40°C. T2 = +25°C. T3 = +125°C. This box method ensures that TCVOUT accurately portrays the maximum difference between any of the three temperatures at which the output voltage of the device is measured. Rev. A | Page 28 of 75 Data Sheet AD7606C-18 THEORY OF OPERATION 15 Analog Input Ranges In hardware mode, the logic level on the RANGE pin determines either ±10 V or ±5 V single-ended as the analog input range of all analog input channels, as shown in Table 10. A logic change on the RANGE pin has an immediate effect on the analog input range. However, there is typically a settling time of approximately 80 µs in addition to the normal acquisition time requirement. Changing the RANGE pin during a conversion is not recommended for fast throughput rate applications. Table 10. Analog Input Range Selection Hardware Mode1 RANGE pin high ±5 Single-Ended RANGE pin low Any Other Range Not applicable 1 2 Software Mode2 Address 0x03 through Address 0x06 Address 0x03 through Address 0x06 Address 0x03 through Address 0x06 The same analog input range, ±10 V or ±5 V, applies to all eight channels. The analog input range is selected on a per channel basis using the memory map. Analog Input Impedance The analog input impedance of the AD7606C-18 is 1 MΩ minimum. This is a fixed input impedance that does not vary with the AD7606C-18 sampling frequency. This high analog input impedance eliminates the need for a driver amplifier in front of the AD7606C-18, allowing direct connection to the source or sensor. Therefore, bipolar supplies can be removed from the signal chain. INPUT CLAMP CURRENT (mA) 10 The AD7606C-18 can handle true bipolar differential, bipolar single-ended, and unipolar single-ended input voltages. In software mode, it is possible to configure an individual analog input range per channel, from Address 0x03 through Address 0x06. The logic level on the RANGE pin is ignored in software mode. Range (V) ±10 Single-Ended CLAMP 18-BIT SAR ADC LPF –20 –10 0 10 20 30 Figure 75. Input Protection Clamp Profile It is recommended to place a series resistor on the analog input channels to limit the current to ±10 mA for input voltages greater than ±21 V. In an application where there is a series resistance (R) on an analog input channel, Vx+, it is recommended to match the resistance (R) with the resistance on Vx− to eliminate any offset introduced into the system, as shown in Figure 76. However, in software mode, there is a per channel system offset calibration that removes the offset of the full system (see the System Offset Calibration section). During normal operation, it is not recommended to leave the AD7606C-18 in a condition where the analog input is greater than the input range for extended periods of time because this can degrade the bipolar zero code error performance. In shutdown or standby mode, there is no such concern. R Vx+ R C Vx– AD7606C-18 CLAMP CLAMP 1MΩ 1MΩ Figure 76. Input Resistance Matching on the Analog Input of the AD7606C-18 for Single-Ended Ranges (Vx− Tied to Ground) 1MΩ 1MΩ –5 SOURCE VOLTAGE (V) 24593-047 Vx– 0 –15 –30 Figure 74 shows the analog input circuitry of the AD7606C-18. Each analog input of the AD7606C-18 contains clamp protection circuitry. Despite single, 5 V supply operation, the analog input clamp protection allows an input overvoltage of up to ±21 V. CLAMP 5 –10 Analog Input Clamp Protection Vx+ TA = –40°C TA = +25°C TA = +125°C 24593-248 The AD7606C-18 is an 18-bit, simultaneous sampling, analogto-digital DAS with eight channels. Each channel contains analog input clamp protection, a PGA, an LPF, and an 18-bit SAR ADC. Figure 75 shows the input clamp current vs. the source voltage characteristic of the clamp circuit. For input voltages of up to ±21 V, no current flows in the clamp circuit. For input voltages that are above ±21 V, the AD7606C-18 clamp circuitry turns on. 24593-049 ANALOG FRONT-END Figure 74. Analog Input Circuitry for Each Channel Rev. A | Page 29 of 75 AD7606C-18 Data Sheet 0 PGA 0 ±20V DIFFERENTIAL ±12.5V DIFFERENTIAL ±10V DIFFERENTIAL ±5V DIFFERENTIAL ±12.5V SINGLE-ENDED ±10V SINGLE-ENDED ±6.25V SINGLE-ENDED ±5V SINGLE-ENDED ±2.5V SINGLE-ENDED 0V to 12.5V SINGLE-ENDED 0V to 10V SINGLE-ENDED 0V to 5V SINGLE-ENDED 300 5 4 1 0V TO 10V SINGLE-ENDED 0V TO 12.5V SINGLE-ENDED ±5V DIFFERENTIAL ±10V DIFFERENTIAL ±12.5V DIFFERENTIAL ±20V DIFFERENTIAL 10 FREQUENCY (kHz) 100 300 24593-777 PHASE DELAY (µs) 6 0 0.1 300 Figure 79. Analog Antialiasing Filter Frequency Response, High Bandwidth Mode 3.0 2.5 ±2.5V SINGLE-ENDED ±5V SINGLE-ENDED ±6.25V SINGLE-ENDED ±10V SINGLE-ENDED ±12.5V SINGLE-ENDED 0V TO 5V SINGLE-ENDED 0V TO 10V SINGLE-ENDED 0V TO 12.5V SINGLE-ENDED ±5V DIFFERENTIAL ±10V DIFFERENTIAL ±12.5V DIFFERENTIAL ±20V DIFFERENTIAL 2.0 1.5 1.0 AV CC = 5V, VDRIVE = 3.3V fSAMPLE = 1MSPS TA = 25°C 1 10 100 300 The AD7606C-18 allows the ADC to accurately acquire an input signal of full-scale amplitude to 18-bit resolution. All eight SAR ADCs sample their respective inputs simultaneously on the rising edge of the CONVST signal. The BUSY signal indicates when conversions are in progress. Therefore, when the rising edge of the CONVST signal is applied, the BUSY pin goes logic high and transitions low at the end of the entire conversion process. The end of the conversion process across all eight channels is indicated by the falling edge of the BUSY signal. When the BUSY signal edge falls, the acquisition time for the next set of conversions begins. The rising edge of the CONVST signal has no effect while the BUSY signal is high. 8 1 100 SAR ADC AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 1MSPS TA = 25°C ±2.5V SINGLE-ENDED ±5V SINGLE-ENDED ±6.25V SINGLE-ENDED ±10V SINGLE-ENDED ±12.5V SINGLE-ENDED 0V TO 5V SINGLE-ENDED 10 Figure 80. Analog Antialiasing Filter Phase Response, High Bandwidth Mode 100 Figure 77. Analog Antialiasing Filter Frequency Response, Low Bandwidth Mode 3 TA = 25°C HIGH BW MODE FREQUENCY (kHz) FREQUENCY (kHz) 9 1 fSAMPLE = 1MSPS 24593-778 –10 0.1 0 0.1 10 10 –7 0.5 24593-776 ATTENUATION (dB) –1 1 –6 –9 PHASE DELAY (µs) fSAMPLE = 1MSPS TA = 25°C LOW BW MODE –4 0.1 –5 ±12.5V SINGLE-ENDED ±10V SINGLE-ENDED ±6.25V SINGLE-ENDED ±5V SINGLE-ENDED ±2.5V SINGLE-ENDED 0V to 12.5V SINGLE-ENDED 0V to 10V SINGLE-ENDED 0V to 5V SINGLE-ENDED ±20V DIFFERENTIAL ±12.5V DIFFERENTIAL ±10V DIFFERENTIAL ±5V DIFFERENTIAL FREQUENCY (kHz) An analog antialiasing filter is provided on the AD7606C-18. Figure 77 and Figure 78 show the frequency response and phase response, respectively, of the analog antialiasing filter. The −3 dB frequency is typically 25 kHz. –3 –4 –8 Analog Input Antialiasing Filter –2 –3 24593-779 Input impedance on each input of the PGA is accurately trimmed to keep overall gain error. This trimmed value is then used when the gain calibration is enabled to compensate for the gain error introduced by an external series resistor. See the System Gain Calibration section for more information on the PGA feature. –2 ATTENUATION (dB) A PGA is provided at each input channel. The gain is configured depending on the analog input range selected (see Table 10) to scale the analog input signal, either bipolar differential or bipolar or unipolar single-ended, to the ADC fully differential input range. –1 Figure 78. Analog Antialiasing Filter Phase Response, Low Bandwidth Mode New data can be read from the output register via the parallel or serial interface after the BUSY output goes low. Alternatively, data from the previous conversion can be read while the BUSY pin is high, as explained in the Reading During Conversion section. In addition, the AD7606C-18 allows the ADC to enable the high bandwidth mode, on a per channel basis, that moves the −3 dB frequency up to 220 kHz, as shown in Figure 79 and Figure 80. This mode is dedicated for fast analog input settling applications, as shown in Figure 63 to Figure 68. Rev. A | Page 30 of 75 Data Sheet AD7606C-18 The AD7606C-18 contains an on-chip oscillator that performs the conversions. The conversion time for all ADC channels is tCONV (see Table 3). In software mode, there is an option to apply an external clock through the CONVST pin. Providing a low jitter external clock improves SNR performance for large oversampling ratios. See the Digital Filter section and Figure 15 to Figure 18 for further information. (Vx+ – Vx–) CODE = PFS (V) × 131,072 ADC CODE 011...111 011...110 000...001 000...000 111...111 LSB = PFS – (NFS) 2N 24593-052 100...010 100...001 100...000 NFS + 1/2LSB 0V – 1/2LSB PFS – 3/2LSB Connect all unused analog input channels to AGND. The results for any unused channels are still included in the data read because all channels are always converted. ANALOG INPUT Figure 81. AD7606C-18 Ideal Transfer Characteristics, Bipolar Analog Input Ranges (Twos Complement Output Coding) ADC Transfer Function The output coding of the AD7606C-18 is twos complement for the bipolar analog input ranges, either single-ended or differential. In unipolar ranges, the output coding is straight binary. CODE = The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB and 3/2 LSB. The LSB size is FSR/262,144 for the AD7606C-18. Figure 81 shows the ideal transfer characteristics for the AD7606C-18. The LSB size is dependent on the analog input range selected, as shown in Table 11 and Table 12. (Vx+ – Vx–) FS (V) × 262,144 100...001 100...000 011...111 LSB = 000...010 000...001 000...000 ZS + 1/2LSB FS/2 – 1/2LSB FS – ZS 2N 24593-650 ADC CODE 111...111 111...110 FS – 3/2LSB ANALOG INPUT Figure 82. AD7606C-18 Ideal Transfer Characteristics, Unipolar Analog Input Ranges (Straight Binary Output Coding) Table 11. Bipolar Input Voltage Ranges Range Differential, Bipolar ±20 V ±12.5 V ±10 V ±5 V Single-Ended, Bipolar ±12.5 V ±10 V ±6.25 V ±5 V ±2.5 V PFS (V) Midscale (V) NFS (V) LSB (μV) +20 +12.5 +10 +5 0 0 0 0 −20 −12.5 −10 −5 152.58 95.36 76.3 38.1 +12.5 +10 +6.25 +5 +2.5 0 0 0 0 0 −12.5 −10 −6.25 −5 −2.5 95.36 76.3 47.7 38.1 19 Table 12. Unipolar Input Voltage Ranges Range Single-Ended, Unipolar 0 V to 12.5 V 0 V to 10 V 0 V to 5 V FS (V) Midscale (V) ZS (V) LSB (μV) 12.5 10 5 6.25 5 2.5 0 0 0 47.7 38.1 19 Rev. A | Page 31 of 75 AD7606C-18 Data Sheet REFERENCE The AD7606C-18 contains an on-chip, 2.5 V, band gap reference. The REFIN/REFOUT pin allows either of the following: Reference Selected Internal reference enabled Internal reference disabled, an external 2.5 V reference voltage must be applied to the REFIN/REFOUT pin The AD7606C-18 contains a reference buffer configured to gain the reference voltage up to approximately 4.4 V, as shown in Figure 83. The 4.4 V buffered reference is the reference used by the SAR ADC, as shown in Figure 83. After a reset, the AD7606C-18 operates in the reference mode selected by the REF SELECT pin. The REFCAPA and REFCAPB pins must be shorted together externally, and a ceramic capacitor of 10 μF must be applied to the REFGND pin to ensure that the reference buffer is in closedloop operation. A 0.1 µF ceramic capacitor is required on the REFIN/REFOUT pin. REFIN/REFOUT AD7606C-18 REFIN/REFOUT REFIN/REFOUT 100nF 100nF 1µF Figure 84. Single External Reference Driving Multiple AD7606C-18 REFIN/REFOUT Pins Internal Reference Mode One AD7606C-18 device, configured to operate in the internal reference mode, can drive the remaining AD7606C-18 devices, which are configured to operate in external reference mode (see Figure 85). Decouple the REFIN/REFOUT pin of the AD7606C-18, configured in internal reference mode, using a 10 µF ceramic decoupling capacitor. The other AD7606C-18 devices, configured in external reference mode, must use at least a 100 nF decoupling capacitor on their REFIN/REFOUT pins. VDRIVE AD7606C-18 When the AD7606C-18 is configured in external reference mode, the REFIN/REFOUT pin is a high input impedance pin. AD7606C-18 AD7606C-18 REF SELECT REF SELECT REF SELECT REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT + 10µF 100nF 100nF Figure 85. Internal Reference Driving Multiple AD7606C-18 REFIN/REFOUT Pins SAR BUF REF SELECT REFIN/REFOUT 100nF REF Table 13. Reference Configuration REF SELECT Pin Logic High Logic Low REF SELECT 24593-054 • Access to the internal 2.5 V reference if the REF SELECT pin is tied to logic high Application of an external reference of 2.5 V if the REF SELECT pin is tied to logic low AD7606C-18 REF SELECT 24593-055 • AD7606C-18 OPERATION MODES REFCAPA REFCAPB 24593-053 2.5V REF 10µF Figure 83. Reference Circuitry Using Multiple AD7606C-18 Devices For applications using multiple AD7606C-18 devices, the configurations in the External Reference Mode section and the Internal Reference Mode section are recommended, depending on the application requirements. External Reference Mode One external reference can drive the REFIN/REFOUT pins of all AD7606C-18 devices (see Figure 84). In this configuration, decouple each REFIN/REFOUT pin of the AD7606C-18 with at least a 100 nF decoupling capacitor. The AD7606C-18 can be operated in hardware or software mode by controlling the OSx pins, as described in Table 14. In hardware mode, the AD7606C-18 is configured depending on the logic level on the RANGE, OSx, or STBY pins. The AD7606C18 is backwards compatible to the AD7606, AD7606B, AD7608, and AD7609. In software mode, when all three OSx pins are connected to logic high level, the AD7606C-18 is configured by the corresponding registers accessed via the serial or parallel interface. Additional features are available, as described in Table 15. The reference and the data interface is selected through the REFSELECT and PAR/SER SEL pins in both hardware and software modes. Table 14. Oversample Pin Decoding OS2 0 0 0 0 1 1 1 1 Rev. A | Page 32 of 75 OS1 0 0 1 1 0 0 1 1 OS0 0 1 0 1 0 1 0 1 AD7606C-18 No oversampling 2 4 8 16 32 64 Enters software mode Data Sheet AD7606C-18 Table 15. Functionality Matrix Parameter Analog Input Range1 Hardware Mode ±10 V or ±5 V2 System Gain, Phase, and Offset Calibration OSR Not accessible From no oversampling to OSR = 64 Not accessible 2 Not accessible Standby and shutdown Analog Input Open Circuit Detection Serial Data Output Lines Diagnostics Power-Down Modes See Table 10 for the analog input range selection. Same input range configured in all input channels. 3 On a per channel basis Software Mode Single-ended, bipolar: ±12.5 V, ±10 V, ±6.25 V, ±5 V, and ±2.5 V3 Single-ended, unipolar: 0 V to 12.5 V, 0 V to 10 V, 0 V to 5 V3 Differential, bipolar: ±20 V, ±12.5 V, ±10 V, and ±5 V3 Available3 From no oversampling to OSR = 256 Available3 Selectable: 1, 2, 4, or 8 Available Standby, shutdown, and autostandby 1 2 Reset Functionality Power-Down Modes The AD7606C-18 has two reset modes: full or partial. The reset mode selected is dependent on the length of the reset high pulse. A partial reset requires the RESET pin to be held high between 55 ns and 2 μs. After 50 ns from the release of the RESET pin (tDEVICE_SETUP, partial reset), the device is fully functional and a conversion can be initiated. A full reset requires the RESET pin to be held high for a minimum of 3.2 µs. After 274 μs (tDEVICE_SETUP, full reset) from the release of the RESET pin, the device is completely reconfigured and a conversion can be initiated. In hardware mode, two power-down modes are available on the AD7606C-18: standby mode and shutdown mode. The STBY pin controls whether the AD7606C-18 is in normal mode or in one of the two power-down modes, as shown in Table 16. If the STBY pin is low, the power-down mode is selected by the state of the RANGE pin. A partial reset reinitializes the following modules: • • • • Digital filter SPI and parallel, resetting to ADC mode SAR ADCs CRC logic A full reset returns the device to its default power-on state, the RESET_DETECT bit on the status register asserts (Address 0x01, Bit 7), and the current conversion result is discarded. The following features, in addition to those listed above, are configured when the AD7606C-18 is released from full reset: Hardware mode or software mode Interface type, serial or parallel Power Mode Normal Standby Shutdown 1 After the partial reset, the RESET_DETECT bit on the status register asserts (Address 0x01, Bit 7). The current conversion result is discarded after the completion of a partial reset. The partial reset does not affect the register values programmed in software mode or the latches that store the user configuration in both hardware and software modes. • • Table 16. Power-Down Mode Selection, Hardware Mode STBY Pin 1 0 0 RANGE Pin X1 1 0 X = don’t care. In software mode, the power-down mode is selected through the OPERATION_MODE bits on the CONFIG register (Address 0x02, Bits[1:0]), within the memory map. There is an extra power-down mode available in software mode called autostandby mode. Table 17. Power-Down Mode Selection, Software Mode, Through CONFIG Register (Address 0x02) Operation Mode Normal Standby Autostandby Shutdown Address 0x02, Bit 1 0 0 1 1 Address 0x02, Bit 0 0 1 0 1 When the AD7606C-18 is placed in shutdown mode, all circuitry is powered down and the current consumption reduces to 4.5 µA maximum. The power-up time is approximately 10 ms. When the AD7606C-18 is powered up from shutdown mode, a full reset must be applied to the AD7606C-18 after the required power-up time elapses. Rev. A | Page 33 of 75 AD7606C-18 Data Sheet CONVST BUSY POWER MODE When the AD7606C-18 is placed in autostandby mode, which is available only in software mode, the device automatically enters standby mode on the BUSY signal falling edge. The AD7606C-18 exits standby mode automatically on the CONVST signal rising edge. Therefore, the CONVST signal low pulse time is longer than tWAKE_UP (standby mode) = 1 μs (see Figure 86). Rev. A | Page 34 of 75 STANDBY NORMAL STANDBY tWAKE_UP Figure 86. Autostandby Mode Operation 24593-056 When the AD7606C-18 is placed in standby mode, all of the PGAs and all of the SAR ADCs enter a low power mode, such that the overall current consumption reduces to 6.5 mA maximum. No reset is required after exiting standby mode. Data Sheet AD7606C-18 DIGITAL FILTER For example, if oversampling by eight is configured, eight samples are taken, averaged, and the result is provided on the output. A CONVST signal rising edge triggers the first sample, and the remaining seven samples are taken with an internally generated sampling signal (OS_CLOCK). Consequently, turning on the averaging of multiple samples leads to an improvement in SNR performance at the expense of reducing the maximum throughput rate. When the oversampling function is turned on, the BUSY signal high time (tCONV) extends, as shown in Table 3. The AD7606C-18 contains an optional digital averaging filter that can be enabled in slower throughput rate applications that require higher SNR or dynamic range. In hardware mode, the oversampling ratio of the digital filter is controlled using the oversampling pins, OSx, as shown in Table 14. The OSx pins are latched on either the falling edge of the BUSY signal or upon a full reset. In software mode, if all OSx pins are tied to logic high, the oversampling ratio is selected through the oversampling register (Address 0x08). Two additional oversampling ratios (oversampling by 128 and oversampling by 256) are available in software mode. Table 18 and Table 19 show the trade off in SNR vs. bandwidth and throughput for the ±10 V single-ended range, ±20 V differential range, and 0 V to 10 V single-ended range. In oversampling mode, the ADC takes the first sample for each channel on the rising edge of the CONVST signal. After converting the first sample, the subsequent samples are taken by the internally generated sampling signal, as shown in Figure 87. Alternatively, this sampling signal can be applied externally as described in the External Oversampling Clock section. Figure 87 shows that the conversion time (tCONV) extends when oversampling is turned on. The throughput rate (1/tCYCLE) must be reduced to accommodate the longer conversion time and to allow the read operation to occur. To achieve the fastest throughput rate possible when oversampling is turned on, the read can be performed during the BUSY signal high time, as explained in the Reading During Conversion section. tCYCLE CONVST OS_CLOCK BUSY tCONV CS 24593-655 RD DB0 TO DB17 Figure 87. AD7606C-18 Oversampling by 8 Example, Read After Conversion, Parallel Interface, OS_CLOCK Is the Internally Generated Sampling Signal Table 18. Oversampling Performance, Low Bandwidth Mode Oversampling Ratio No oversampling 2 4 8 16 32 64 128 256 Input Frequency (Hz) 1000 1000 1000 1000 1000 160 160 50 50 ±10 V Single-Ended Range −3 dB Bandwidth SNR (dB) (kHz) 92.5 25 94.5 24.6 96.5 24 98 22.3 100 17.8 101.5 11.6 103.3 6.5 104.5 3.3 105 1.7 ±20 V Differential Range −3 dB Bandwidth SNR (dB) (kHz) 93 25 95 24.4 97.5 23.7 99.5 22.2 101 17.6 103 11.5 104 6.4 104.4 3.4 105 1.7 Rev. A | Page 35 of 75 0 V to 10 V SingleEnded Range −3 dB SNR Bandwidth (dB) (kHz) 90 25 91.5 24.6 92.3 24 93.3 22.3 94.3 17.8 96 11.6 97.5 6.4 99 3.3 100 1.7 Maximum Throughput (kSPS) 1000 500 250 125 62.5 31.25 15.6 7.8 3.9 AD7606C-18 Data Sheet Table 19. Oversampling Performance, High Bandwidth Mode Oversampling Ratio No oversampling 2 4 8 16 32 64 128 256 Input Frequency (Hz) 1000 1000 1000 1000 1000 160 160 50 50 ±10 V Single-Ended Range −3 dB Bandwidth SNR (dB) (kHz) 87 220 89 154 92 97.5 95 53 97.5 27.5 99.8 13.8 102 7 104 3.5 104.5 1.7 ±20 V Differential Range −3 dB Bandwidth SNR (dB) (kHz) 89 220 91.5 154 94.5 97.5 97 53 99.5 27.5 101.5 13.7 103 7 104.5 3.5 105.2 1.7 Rev. A | Page 36 of 75 0 V to 10 V SingleEnded Range −3 dB Bandwidth SNR (dB) (kHz) 82 220 84.5 155 87 97.5 89.5 53.5 91.5 27.5 94 13.8 95.5 7 97 3.5 97.7 1.7 Maximum Throughput (kSPS) 1000 500 250 125 62.5 31.25 15.6 7.8 3.9 Data Sheet AD7606C-18 PADDING OVERSAMPLING As shown in Figure 87, an internally generated clock triggers the samples to be averaged, and then the ADC remains idle until the following CONVST signal rising edge. In software mode, through the oversampling register (Address 0x08), the internal clock (OS_CLOCK) frequency can be changed such that idle time is minimized and sampling instants are equally spaced, as shown in Figure 88. As a result, the actual oversampling clock frequency depends on the OS_PAD bits configuration, as per the following equation: OS _ CLOCK(kHz) = 1 OS _ PAD 1000 × (1 + ) 16 tCYCLE CONVST BUSY tCONV 24593-158 OS_CLOCK That is, the sampling signal is provided externally through the CONVST pin, and after every OSR number of clocks, an output is averaged and provided, as shown in Figure 90. This feature is available using either the parallel interface or serial interface. Simultaneous Sampling of Several AD7606C-18 Devices In general, synchronizing several SAR ADCs is achieved by using a common CONVST signal. However, when oversampling is enabled, an internal clock is used to trigger the subsequent samples by default. Any deviation between these internal clocks may impede device to device synchronization. This deviation can be minimized by using external oversampling, as the CONVST signal of all the samples is managed externally. A partial reset (tRESET < 2 µs) interrupts the oversampling process and empties the data register. Therefore, if by any reason the different AD7606C-18 devices are not synchronized, issuing a partial reset resynchronizes the devices, as shown in Figure 89. RESET Figure 88. Oversampling by 8 Example, Oversampling Padding Enabled EXTERNAL OVERSAMPLING CLOCK To enable the external oversampling clock, Bit 5 in the CONFIG register (Address 0x02, Bit 5) must be set. Then, the throughput rate is Throughput = CONVST AD7606C-18 BUSY1 CONVST AD7606C-18 BUSY2 AD7606C-18 BUSY3 CONVST RESET BUSY1 BUSY2 BUSY3 24593-657 In software mode, there is an option to apply an external clock through the CONVST pin when oversampling mode is enabled. Providing a low jitter external clock helps improve SNR performance for large oversampling ratios. By applying an external clock, the input is sampled at regular time intervals, which is optimum for antialiasing performance. Figure 89. Synchronizing Several AD7606C-18 Devices When External Oversampling Clock Is Enabled 1 t CYCLE × OSR tCYCLE BUSY CS 24593-658 RD DB0 TO DB17 Figure 90. External Oversampling Clock Applied on the CONVST Pin (OSR = 4), Parallel Interface Rev. A | Page 37 of 75 AD7606C-18 Data Sheet SYSTEM CALIBRATION FEATURES Note that system gain calibration is only available on bipolar analog input ranges, both single-ended and differential. System gain calibration is not available in unipolar single-ended ranges. The following system calibration features are available in software mode by writing to corresponding registers in the memory map: Phase calibration Gain calibration Offset calibration Analog input open circuit detection AD7606C-18 ANALOG INPUT SIGNAL RFILTER C RFILTER Vx+ 1MΩ Vx– 1MΩ 24593-060 SYSTEM PHASE CALIBRATION –1000 BUSY –2000 –1 –3000 –5000 –6000 tCONV = n+1 V1 CODE V4 CODE –2 ON-CHIP CALIBRATION ENABLE ON-CHIP CALIBRATION DISABLED n 0 10 20 30 40 50 60 RFILTER (kΩ) Figure 93. System Gain Calibration, with and Without Calibration, ±10 V Single-Ended Range 24593-160 INTERNAL CONVST CH4 –0.5 –4000 CONVST INTERNAL CONVST CH1 –0.1 100 80 Figure 91. System Phase Calibration Functionality SYSTEM GAIN CALIBRATION 0.03 60 0.02 40 ERROR (LSB) Note that delaying any channel extends the BUSY signal high time, and tCONV extends until tCONV = n + 1 μs, with n as the CHx_PHASE register content of the most delayed channel. In the previously explained example, if only the CH4_PHASE register is programmed, tCONV is 11 μs. Therefore, this scenario must be considered when running at higher throughput rates. 0.01 20 0 0 –20 –0.01 –40 –0.02 –60 Using an external RFILTER, which is a resistor placed in a series to the analog input front-end, see Figure 92, generates a system gain error. This gain error can be compensated for in software mode, on a per channel basis, by writing the series resistor value used on the corresponding register, Address 0x09 through Address 0x10. These registers can compensate up to 65 kΩ series resistors with a resolution of 1024 Ω. ERROR (% OF FSR) INPUT V1 INPUT V4 0.1 0 24593-792 For example, if the CH4_PHASE register (Address 0x1C) is written with 10 decimal, Channel 4 is effectively sampled 10 μs after the CONVST signal rising edge, as shown in Figure 91. For example, if a 27 kΩ resistor is placed in series to the analog input of Channel 5, the resistor generates about −2% positive full-scale error on the system (at ±10 V range), as seen in Figure 93. In software mode, this error is eliminated by writing 27 decimal to the CH5_GAIN register (Address 0x0D), which keeps the error within 0.05% of FSR, no matter the RFILTER value of the series resistor, as shown in Figure 94 –0.03 –80 –100 Rev. A | Page 38 of 75 ERROR (% OF FSR) The sampling instant on any particular channel can be delayed with regards to the CONVST signal rising edge, with a resolution of 1 μs, and up to 255 μs, by writing to the corresponding CHx_PHASE register (Address 0x19 through Address 0x20). Figure 92. System Gain Error ERROR (LSB) When using an external filter, as shown in Figure 92, any mismatch on the discrete components or in the sensor used can cause phase mismatch between channels. This phase mismatch can be compensated for in software mode, on a per channel basis, by delaying the sampling instant on individual channels. 0 10 20 30 40 50 60 RFILTER (kΩ) Figure 94. System Error with Gain Calibration Enabled 24593-795 • • • • Data Sheet AD7606C-18 SYSTEM OFFSET CALIBRATION Manual Mode A potential offset on the sensor, or any offset caused by a mismatch between the RFILTER pair placed on a particular channel (as described in the Analog Front-End section), can be compensated in software mode on a per channel basis. The CHx_OFFSET registers (Address 0x11 through Address 0x18) allow the ability to add or subtract up to 512 LSBs to the ADC code automatically with a resolution of 4 LSB, as shown in Table 20. Manual mode is enabled by writing 0x01 to the OPEN_DETECT_ QUEUE register (Address 0x2C). In manual mode, each PGA common-mode voltage is controlled by the corresponding CHx_OPEN_DETECT_EN bit on the OPEN_DETECT_ENABLE register (Address 0x23). Setting this bit high shifts up the PGA common-mode voltage. If there is an open circuit on the analog input, the ADC output changes proportionally to the RPD, as shown in Figure 96. If there is not an open circuit, any change on the PGA common-mode voltage has no effect on the ADC output. Table 20. CHx_OFFSET Register Bit Decoding Offset Calibration (LSB) −512 −236 0 +12 +508 1MΩ RPD RFILTER SAR ADC Vx– 1MΩ 24593-061 RS AD7606C-18 CFILTER 1000 800 600 400 0 The AD7606C-18 has an analog input open circuit detection feature available in software mode. To use this feature, an RPD must be placed as shown in Figure 95. If the analog input is disconnected, for example, if a switch opens in Figure 95, the source impedance changes from the burden resistor (RS) to RPD, as long as RS < RPD. It is recommended to use RPD = 20 kΩ so that the AD7606C-18 can detect changes in the source impedance by internally switching the PGA common-mode voltage. Analog input open circuit detection operates in manual mode or in automatic mode. Vx+ 1200 200 ANALOG INPUT OPEN CIRCUIT DETECTION RFILTER ±2.5V SINGLE-ENDED ±5V SINGLE-ENDED ±6.25V SINGLE-ENDED ±10V SINGLE-ENDED ±12.5V SINGLE-ENDED ±5V DIFFERENTIAL ±10V DIFFERENTIAL ±12.5V DIFFERENTIAL ±20V DIFFERENTIAL 1400 Figure 95. Analog Front End with RPD Note that analog input open circuit detection is only available on bipolar analog input ranges, both single-ended and differential. Analog input open circuit detection is not available in unipolar single-ended ranges. Rev. A | Page 39 of 75 0 10 20 30 40 50 60 70 80 90 100 RPD (kΩ) Figure 96. Open Circuit Code Error increment, Dependent of RPD 24593-794 CHx_OFFSET Register Code 0x00 0x45 0x80 (Default) 0x83 0xFF 1600 ADC CODE INCREMENT (LSB) For example, if the signal connected to Channel 3 has a 9 mV offset, and the analog input range is set to ±10 V range (where LSB size = 76.3 μV) to compensate for this offset, program −30 LSB to the corresponding register (that is, 9 mV/76.3 μV/4). Writing 128 decimal – 30 decimal = 0x80 − 0x1E = 0x62 into the CH3_OFFSET register (Address 0x13) removes such offset. AD7606C-18 Data Sheet Automatic Mode Automatic mode is enabled by writing any value greater than 0x01 to the OPEN_DETECT_QUEUE register (Address 0x2C), as shown in Table 21. If the AD7606C-18 detects that the ADC reported a number (specified in the OPEN_DETECT_QUEUE register) of consecutive unchanged conversions, the analog input open circuit detection algorithm is performed internally and automatically. The analog input open circuit detection algorithm automatically changes the PGA common-mode voltage, checks the ADC output, and returns to the initial common-mode voltage, as shown in Figure 97. If the ADC code changes in any channel with the PGA common-mode change, this implies there is no input signal connected to that analog input, and the corresponding flag asserts within the OPEN_DETECTED register (Address 0x24). Each channel can be individually enabled or disabled through the OPEN_DETECT_ENABLE register (Address 0x23). If no oversampling is used, the recommended minimum number of conversions to be programmed for the AD7606C-18 to automatically detect an open circuit on the analog input is OPEN _ DETECT _ QUEUE = 10 × fSAMPLE ( R PD + 2 × R FILTER ) × (C FILTER + 10 pF) However, when oversampling mode is enabled, the recommended minimum number of conversions to use is OPEN _ DETECT _ QUEUE = ( 1 + fSAMPLE × 2 ( R PD + 2 × R FILTER ) × (C FILTER + 10 pF) × OSR START CONVERSION 0 < ADC CODE < 1400 LSB NO i=0 YES NO i = N? i=i+1 N = NUMBER OF CONSECUTIVE REPEATED (WITHIN 10 LSB) ADC OUTPUT CODE YES, SET COMMON-MODE HIGH NO i=0 ΔADC CODE > 20 LSB YES, SET COMMON-MODE LOW NO i=0 ADC CODE BACK TO ORIGINAL? ERROR FLAG 24593-165 YES Figure 97. Automatic Analog Input Open Circuit Detect Flowchart Table 21. Analog Input Open-Circuit Detect Mode Selection and Register Functionality OPEN_DETECT_QUEUE (Address 0x2C) 0x00 (Default) 0x01 0x021 to 0xFF 1 Open Detect Mode Disabled. Manual. Automatic. OPEN_DETECT_QUEUE is the number of consecutive conversions before asserting any CHx_OPENED flag. It is recommended to write to OPEN_DETECT_QUEUE a value greater than 5. Rev. A | Page 40 of 75 OPEN_DETECT_ENABLE (Address 0x23) Not applicable. Sets common-mode voltage high or low on a per channel basis. Enables or disables automatic analog input open circuit detection on a per channel basis. ) Data Sheet AD7606C-18 DIGITAL INTERFACE See the Reading Conversion Results (Parallel ADC Mode) section and the Reading Conversion Results (Serial ADC Mode) section for more details on how the ADC mode operates. The AD7606C-18 provides two interface options: a parallel interface and a high speed serial interface. The required interface mode is selected via the PAR/SER SEL pin. Software Mode Table 22. Interface Mode Selection PAR/SER SEL Setting 0 1 Interface Mode Parallel interface Serial interface Operation of the interface modes is discussed in the Hardware Mode section and the Software Mode section. Hardware Mode In hardware mode, only ADC mode is available. ADC data can be read from the AD7606C-18 via the parallel data bus with standard CS and RD signals or via the serial interface with standard CS, SCLK, and two DOUTx signals. In software mode, which is active only when all three OSx pins are tied high, both ADC mode and register mode are available. ADC data can be read from the AD7606C-18, and registers can also be read from and written to the AD7606C-18 via the parallel data bus with standard CS, RD, and WR signals or via the serial interface with standard CS, SCLK, SDI, and DOUTA lines. See the Parallel Register Mode (Writing Register Data) section and the Parallel Register Mode (Reading Register Data) section for more details on how register mode operates. Pin functions differ depending on the interface selected (parallel or serial) and the operation mode (hardware or software), as shown in Table 23. Table 23. Data Interface Pin Function per Mode of Operation Pin Mnemonic DB2 to DB4 DB5/DOUTE DB6/DOUTF DB7/DOUTG DB8/DOUTH DB9/DOUTA DB10/DOUTB DB11/DOUTC DB12/DOUTD DB13/SDI DB14 DB15 DB16/DB0 DB17/DB1 Pin No. 16 to 18 19 20 21 22 24 25 27 28 29 30 31 32 33 Parallel Interface Software Mode Hardware Mode ADC Mode Register Mode DB2 to DB4 Register data DB5 Register data DB6 Register data DB7 Register data DB8 Register data DB9 Register data (MSB) DB10 ADD0 DB11 ADD1 DB12 ADD2 DB13 ADD3 DB14 ADD4 DB15 ADD5 DB16/DB05 ADD6 DB17/DB15 R/W Serial Interface Software Mode Hardware Mode ADC Mode Register Mode N/A1 N/A N/A DOUTE2 Unused N/A DOUTF2 Unused N/A DOUTG2 Unused N/A DOUTH2 Unused DOUTA DOUTA DOUTA DOUTB DOUTB3 Unused N/A DOUTC4 Unused 4 N/A DOUTD Unused N/A Unused SDI N/A N/A N/A N/A N/A N/A N/A N/A N/A means not applicable. Tie all N/A pins to AGND. Only used if 8 DOUTx mode is selected on the CONFIG register, otherwise leave unconnected. Only used if 2 DOUTx, 4 DOUTx, or 8 DOUTx mode is selected on the CONFIG register, otherwise leave unconnected. 4 Only used if 4 DOUTx or 8 DOUTx mode is selected on the CONFIG register, otherwise leave unconnected. 5 Pin functionality depends on whether it is the first or second read frame during an ADC read operation, see Figure 100. 1 2 3 Rev. A | Page 41 of 75 AD7606C-18 Data Sheet PARALLEL INTERFACE The parallel interface consists of 16 parallel lines on Pin 16 to Pin 22 and Pin 24 to Pin 33. Because the ADC data is 18 bit, two parallel frames are required as follows: To read ADC data, or to read and write the register content over the parallel interface, tie the PAR/SER SEL pin low. The rising edge of the CS input signal three-states the bus, and the falling edge of the CS input signal takes the bus out of the high impedance state. CS is the control signal that enables the data lines and it is the function that allows multiple AD7606C-18 devices to share the same parallel data bus. AD7606C-18 INTERRUPT BUSY 14 CS 13 RD/SCLK 12 DIGITAL HOST WR 10 24593-166 24 TO 33 16 TO 22 DB17 TO DB0 Figure 98. AD7606C-18 Interface Diagram—One AD7606C-18 Using the Parallel Bus with CS and RD Shorted Together Reading Conversion Results (Parallel ADC Mode) The falling edge of the RD pin reads data from the output conversion results register. Applying a sequence of RD pulses to the RD pin clocks the conversion results out from each channel onto the parallel bus, DB17 to DB0, in ascending order, from V1 to V8, as shown in Figure 99. • • 1st frame clocks out ADC data from Bit 2 to Bit 17 (MSB) 2nd frame clocks out ADC data from Bit 1 and Bit 0 (LSB) The CS signal can be permanently tied low, and the RD signal can access the conversion results, as shown in Figure 3. A read operation of new data can take place after the BUSY signal goes low (see Figure 2). Alternatively, a read operation of data from the previous conversion process can take place while the BUSY pin is high. When there is only one AD7606C-18 in a system and it does not share the parallel bus, data can be read using one control signal from the digital host. The CS and RD signals can be tied together, as shown in Figure 4. In this case, the falling edge of the CS and RD signals brings the data bus out of three-state and clocks out the data. The FRSTDATA output signal indicates when the first channel, V1, is being read back, as shown in Figure 4. When the CS input is high, the FRSTDATA output pin is in three-state. The falling edge of CS takes the FRSTDATA pin out of three-state. The falling edge of the RD signal corresponding to the result of V1 sets the FRSTDATA pin high, indicating that the result from V1 is available on the output data bus. The FRSTDATA pin returns to a logic low following the next falling edge of RD. CONVST BUSY CS RD DB17/DB1 V1[17] V1[1] V2[17] V2[1] V7[17] V7[1] V8[17] V8[1] DB16/DB0 V1[16] V1[0] V2[16] V2[0] V7[16] V7[0] V8[16] V8[0] DB15 V1[15] V2[15] V7[15] V8[15] DB14 V1[14] V2[14] V7[14] V8[14] DB13 V1[13] V2[13] V7[13] V8[13] DB12 V1[12] V2[12] V7[12] V8[12] DB11 V1[11] V2[11] V7[11] V8[11] DB10 V1[10] V2[10] V7[10] DB9 STATUS1[7] V2[9] STATUS2[7] V7[9] STATUS7[7] V8[9] STATUS8[7] DB8 V1[8] STATUS1[6] V2[8] STATUS2[6] V7[8] STATUS7[6] V8[8] STATUS8[6] DB7 V1[7] STATUS1[5] V2[7] STATUS2[5] V7[7] STATUS7[5] V8[7] STATUS8[5] DB6 V1[6] STATUS1[4] V2[6] STATUS2[4] V7[6] STATUS7[4] V8[6] STATUS8[4] DB5 V1[5] STATUS1[3] V2[5] STATUS2[3] V7[5] STATUS7[3] V8[5] STATUS8[3] DB4 V1[4] STATUS1[2] V2[4] STATUS2[2] V7[4] STATUS7[2] V8[4] STATUS8[2] DB3 V1[3] STATUS1[1] V2[3] STATUS2[1] V7[3] STATUS7[1] V8[3] STATUS8[1] V2[2] STATUS2[0] V7[2] STATUS7[0] V8[2] STATUS8[0] DB2 V1[2] STATUS1[0] Figure 99. Parallel Interface, ADC Mode with Status Header Enabled Rev. A | Page 42 of 75 24593-667 V8[10] V1[9] Data Sheet AD7606C-18 Reading During Conversion Parallel ADC Mode with Status Enabled Data read operations from the AD7606C-18, as shown in Figure 100, can occur in the following three scenarios: In software mode, the 8-bit status header is enabled (see Table 25) by setting Bit 6 in the CONFIG register (Address 0x02, Bit 6), and each channel then takes the following two frames of data: • • • After a conversion while the BUSY line is low During a conversion while the BUSY line is high Starting while the BUSY line is low and ending while the following conversion is in progress, see Figure 2 • • Reading during conversions has little effect on the performance of the converter, and it allows a faster throughput rate to be achieved. Data can be read from the AD7606C-18 at any time other than on the falling edge of the BUSY signal because this is when the output data registers are updated with the new conversion data. Any data read while the BUSY signal is high must be completed before the falling edge of the BUSY signal. The first frame clocks the ADC data out normally through DB17 to DB2 from the MSB to Bit 2. The second frame clocks out the status header of the channel on DB9 to DB2, DB9 being the MSB and DB2 being the LSB of the status header, while DB1 to DB0 clock out the two LSBs of the conversion result and the DB15 to DB10 pins clock out zeros. This sequence is shown in Figure 99. Table 25 explains the status header content and describes each bit. Table 24. CH.ID Bits Decoding in Status Header Parallel ADC Mode with CRC Enabled CH.ID2 0 0 0 0 1 1 1 1 In software mode, the parallel interface supports reading the ADC data with the CRC appended, when enabled through the INT_CRC_ERR_EN bit (Address 0x21, Bit 2). The CRC is 16 bits, and it is clocked out after reading all eight channel conversions, as shown in Figure 101. The CRC calculation includes all data on the DBx pins: data, status (when appended), and zeros. See the Diagnostics section for more details on CRC. CH.ID1 0 0 1 1 0 0 1 1 CH.ID0 0 1 0 1 0 1 0 1 Channel Number Channel 1 (V1) Channel 2 (V2) Channel 3 (V3) Channel 4 (V4) Channel 5 (V5) Channel 6 (V6) Channel 7 (V7) Channel 8 (V8) Table 25. Status Header, Parallel Interface Content Meaning1 1 Bit 7 (MSB) RESET_DETECT Reset detected Bit 6 DIGITAL_ERROR Error flag on Address 0x22 Bit 5 OPEN_DETECTED The analog input of this channel is open Bit 4 Bit 3 RESERVED Bit 2 Bit 1 Bit 0 (LSB) CH. ID 2 CH. ID 1 CH. ID 0 Channel ID (see Table 24) See the Diagnostics section for more information. CONVST tACQ_C tACQ_B BUSY tCONV_A tCONV_B 24593-266 DOUTx DBx ADC_DATAB ADC_DATAA Figure 100. ADC Data Read Can Happen After Conversion and/or During the Following Conversion CONVST BUSY DBx V1[17:2] V1[1:0] V2[17:2] V2[1:0] V7[17:2] V7[1:0] V8[17:2] Figure 101. Parallel Interface, ADC Mode with CRC Enabled Rev. A | Page 43 of 75 V8[1:0] CRC 24593-169 CS RD AD7606C-18 Data Sheet Parallel Register Mode (Reading Register Data) To revert to ADC mode, keep all DBx pins low during one WR cycle, as shown in the Parallel Register Mode (Writing Register Data) section. No ADC data can be read while the device is in register mode. In software mode, all of the registers in Table 31 can be read over the parallel interface. Bits[DB17:DB2] leave a high impedance state when both the CS signal and RD signal are logic low for reading register content, or when both the CS signal and WR signal are logic low for writing register address and/or register content. Parallel Register Mode (Writing Register Data) In software mode, all of the R/W registers in Table 31 can be written to over the parallel interface. To write a sequence of registers, exit ADC mode (default mode) by reading any register on the memory map. A register write command is performed by a single frame, via the parallel bus (Bits[DB17:DB2]), CS signal, and WR signal. The format for a write command, as shown in Figure 102, is structured as follows: A register read is performed through two frames: first, a read command is sent to the AD7606C-18 and second, the AD7606C-18 clocks out the register content. The format for a register read command is shown in Figure 102. On the first frame, perform the following: • • Bit DB17 must be set to 1 to select a read command. The read command puts the AD7606C-18 into register mode. Bits[DB16:DB10] must contain the register address. The subsequent eight bits, Bits[DB9:DB2], are ignored. • • • The register address is latched on the AD7606C-18 on the rising edge of the WR signal. The register content can then be read from the latched register by bringing the RD line low on the following frame, as follows: • • • Bit DB17 must be set to 0 to select a write command. Bits[DB16:DB10] contain the register address. The subsequent eight bits, Bits[DB9:DB2], contain the data to be written to the selected register. Data is latched onto the device on the rising edge of the WR pin. To revert back to ADC mode, keep all DBx pins low during one WR cycle. No ADC data can be read while the device is in register mode. Bit DB17 is pulled to 0 by the AD7606C-18. Bits[DB16: DB10] provide the register address being read. The subsequent eight bits, Bits[DB9: DB2], provide the register content. CS RD WR R/W = 1 R/W = 0 R/W = 0 R/W = 0 DB10 TO DB16 DB17 REG. ADDRESS REG. ADDRESS REG. ADDRESS ADDRESS = 0x00 DB2 TO DB9 DON’T CARE REGISTER DATA REGISTER DATA DON’T CARE MODE ADC MODE REGISTER MODE Figure 102. Parallel Interface Register Read Operation Followed by a Write Operation Rev. A | Page 44 of 75 ADC MODE 24593-170 • Data Sheet AD7606C-18 SERIAL INTERFACE CS To read ADC data or to read and write the register content over the serial interface, tie the PAR/SER SEL pin high. INTERRUPT CS 13 RD/SCLK 12 V1 V2 DOUTB V3 V4 DOUTC V5 V6 DOUTD V7 V8 24593-174 BUSY 14 DOUTA Figure 105. Serial Interface ADC Reading, Four DOUTx Lines DB13/SDI 29 CS DIGITAL HOST DB9/DOUTA 24 DB10/D OUTB 25 SCLK DB11/DOUTC 27 DOUTA V1 DB5/DOUT E 19 DOUTB V2 DB6/DOUT F 20 DOUTC V3 DOUTD V4 DOUTE V5 DOUT F V6 DOUT G V7 DOUTH V8 DB12/D OUTD 28 24593-172 DB7/DOUT G 21 DB8/DOUTH 22 Figure 103. AD7606C-18 Interface Diagram—One AD7606C-18 Using the Serial Interface with Eight DOUTx Lines Reading Conversion Results (Serial ADC Mode) The AD7606C-18 has eight serial data output pins, DOUTA to DOUTH. In software mode, data can be read back from the AD7606C-18 using either one (see Figure 107), two (see Figure 104), four (see Figure 105), or eight (see Figure 106) DOUTx lines depending on the configuration set through the CONFIG register. Figure 106. Serial Interface ADC Reading, Eight DOUTx Lines Table 26. DOUTx Format Selection Using the CONFIG Register (Address 0x02) DOUTx Format 1 DOUTx 2 DOUTx 4 DOUTx 8 DOUTx CONVST CS SCLK DOUTA V1 V2 V3 V4 DOUTB V5 V6 V7 V8 Address 0x02, Bit 4 0 0 1 1 Address 0x02, Bit 3 0 1 0 1 In hardware mode, only the 2 DOUTx lines option is available. However, all channels can be read from DOUTA by providing eight 18-bit SPI frames between two CONVST pulses. 24593-173 DOUTC 24593-793 AD7606C-18 SCLK DOUTD Figure 104. Serial Interface ADC Reading, Two DOUTx Lines CS FRSTDATA SCLK DOUTA V1 V2 V3 V4 V5 V6 V7 V8 DOUTB 24593-171 DOUTC DOUTD Figure 107. Serial Interface ADC Reading, One DOUTx Line Rev. A | Page 45 of 75 AD7606C-18 Data Sheet CS 9 18 MSB DOUT x LSB 24593-672 1 SCLK Figure 108. Serial Interface Data Read Back (One Channel) CS DOUTx 1 2 3 4 5 6 7 8 9 18 ADC DATA 26 STATUS HEADER 24593-175 SCLK Figure 109. Serial Interface, ADC Mode, Status On The CS falling edge takes the data output lines, DOUTx, out of three-state and clocks out the MSB of the conversion result, as shown in Figure 108. In 3-wire mode (CS tied low), instead of CS clocking out the MSB, the falling edge of the BUSY signal clocks out the MSB. The rising edge of the SCLK signal clocks all the subsequent data bits on the serial data outputs, DOUTx, as shown in Figure 6. The CS input can be held low for the entire serial read operation, or it can be pulsed to frame each channel read of 24 SCLK cycles (see Figure 104). However, if CS is pulsed during a channel conversion result transmission, the channel that was interrupted retransmits on the next frame, completely starting from the MSB. Data can also be clocked out using only the DOUTA pin, as shown in Figure 107. For the AD7606C-18 to access all eight conversion results on one DOUTx line, a total of 144 SCLK cycles is required. In hardware mode, these 144 SCLK cycles must be framed on groups of 18 SCLK cycles by the CS signal. The disadvantage of using just one DOUTx line is that the throughput rate is reduced if reading occurs after conversion. Leave the unused DOUTx lines disconnected in serial mode. Figure 105 shows a read of eight simultaneous conversion results using four DOUTx lines on the AD7606C-18, available in software mode. In this case, a 36 SCLK transfer accesses data from the AD7606C-18, and CS is either held low to frame the entire 36 SCLK cycles or is pulsed between two 18-bit frames. This mode is only available in software mode, and it is configured through the CONFIG register (Address 0x02). Figure 6 shows the timing diagram for reading one channel of data, framed by the CS signal, from the AD7606C-18 in serial mode. The SCLK input signal provides the clock source for the serial read operation. The CS signal goes low to access the data from the AD7606C-18. The FRSTDATA output signal indicates when the first channel, V1, is being read back. When the CS input is high, the FRSTDATA output pin is in three-state. In serial mode, the falling edge of the CS signal takes the FRSTDATA pin out of three-state and sets the FRSTDATA pin high if the BUSY line is already deasserted, indicating that the result from V1 is available on the DOUTA output data line. The FRSTDATA output returns to a logic low following the 18th SCLK falling edge. If the CS pin is tied permanently low (3-wire mode), the falling edge of the BUSY line sets the FRSTDATA pin high when the result from V1 is available on DOUTA. If the SDI is tied low or high, nothing is clocked to the AD7606C-18. Therefore, the device remains reading conversion results. When using the AD7606C-18 in 3-wire mode, keep the SDI at high level. While in ADC mode, single write operations can be performed, as shown in Figure 109. For writing a sequence of registers, switch to register mode, as described in the Serial Register Mode (Writing Register Data) section. Reading During Conversion Data read operations from the AD7606C-18, as shown in Figure 100, can occur in the following three scenarios: • • • After a conversion while the BUSY line is low During a conversion while the BUSY line is high Starting while the BUSY line is low and ending while the following conversion is in progress, see Figure 2 Reading during conversions has little effect on the performance of the converter, and it allows a faster throughput rate to be achieved. Data can be read from the AD7606C-18 at any time other than on the falling edge of the BUSY signal because this is when the output data registers are updated with the new conversion data. Any data read while the BUSY signal is high must be completed before the falling edge of the BUSY signal. Rev. A | Page 46 of 75 Data Sheet AD7606C-18 Serial ADC Mode with CRC Enabled • In software mode, the CRC can be enabled by writing to the register map. In this case, the CRC is appended on each DOUTx line after the last channel is clocked out, as shown in Figure 115. See the Interface CRC section for more information on how the CRC is calculated. • • Serial ADC Mode with Status Enabled If the AD7606C-18 is in ADC mode, the DOUTx lines keep clocking ADC data on Bits[9:16], and then the AD7606C-18 switches to register mode. In software mode, the 8-bit status header (see Table 27) can be turned on when using the serial interface so that it is appended after each 18-bit data conversion, extending the frame size to 26 bits per channel, as shown in Figure 109. If the AD7606C-18 is in register mode, the DOUTx lines read back the content from the previous addressed register, no matter if the previous frame was a read or a write command. To exit register mode, keep the SDI line low for 16 SCLK cycles, as shown in Figure 111. Serial Register Mode (Reading Register Data) All the registers in Table 31 can be read over the serial interface. The format for a read command is shown in Figure 110. It consists of two 16-bit frames. On the first frame, perform the following: • The second bit clocked in SDI must be set to 1 to select a read command. Bits[3:8] clocked in SDI contain the register address to be clocked out on DOUTA on the following frame. The subsequent eight bits, Bits[9:16], clocked in SDI are ignored. The first bit clocked in SDI must be set to 0 to enable writing the address. CS SCLK 8 1 16 SDI ADC DATA (8LSB) OR PREVIOUS REGISTER READ/WRITTEN ADC DATA (8LSB) OR XX REGISTER [ADD5:ADD0] CONTENT 24593-073 READ OR WRITE COMMAND WEN R/W DOUTA Figure 110. Serial Interface Read Command, First Frame Provides the Address, Second Frame Provides the Register Content CS SCLK READ COMMAND R/W COMMAND R/W COMMAND WRITE COMMAND SDI MODE ADC DATA ADC DATA ADC MODE REGISTER MODE ADC MODE 24593-176 DOUT x ADC DATA Figure 111. AD7606C-18 Register Mode Table 27. Status Header, Serial Interface Content Meaning1 1 Bit 7 (MSB) RESET_DETECT Reset detected Bit 6 DIGITAL_ERROR Error flag on Address 0x22 Bit 5 OPEN_DETECTED The analog input of this channel is open Bit 4 See the Diagnostics section for more information. Rev. A | Page 47 of 75 Bit 3 RESERVED Bit 2 Bit 1 Bit 0 (LSB) CH.ID 2 CH.ID 1 CH. ID 0 Channel ID (see Table 24) AD7606C-18 Data Sheet Serial Register Mode (Writing Register Data) When writing continuously to the device, the data that appears on DOUTA is from the register address that was written to on the previous frame, as shown in Figure 112. The DOUTB, DOUTC, and DOUTD pins are kept low during the transmission. In software mode, all the read and write registers in Table 31 can be written to over the serial interface. To write a sequence of registers, exit ADC mode (default mode) by reading any register on the memory map. A register write command is performed by a single 16-bit SPI access. The format for a write command, as shown in Figure 112, is structured as follows: • • • • While in register mode, no ADC data is clocked out because the DOUTx lines are used to clock out register content. After writing all required registers, keeping the SDI line low for 16 SCLK cycles returns the AD7606C-18 to ADC mode, where the ADC data is again clocked out on the DOUTx lines, as shown in Figure 111. The first bit clocked in SDI must be set to 0 to enable a write command. The second bit clocked in SDI, the R/W bit, must be cleared to 0. Bit ADD5 to Bit ADD0 clocked in SDI contain the register address to be written. The subsequent eight bits (Bits[DIN7:DIN0]) clocked in SDI contain the data to be written to the selected register. Data is clocked in from SDI on the falling edge of SCLK, while data is clocked out on DOUTA on the rising edge of SCLK. In software mode, when the CRC is turned on, eight additional bits are clocked in and out on each frame. Therefore, 24-bit frames are required. CS DOUTA TO DOUTH SDI 1 2 3 4 DB17 DB16 DB15 DB14 WEN R/W ADD5 ADD4 17 18 DB1 DB0 CRC7 19 CRC7 CRC6 CRC5 26 CRC0 24593-078 SCLK Figure 112. AD7606C-18 Serial Interface, Single Write Command, SDI Clocks in the Address Bit ADD5 to Bit ADD0 and the Register Content Bit DIN7 to Bit DIN0 During the Same Frame, DOUTA Provides Register Content Requested on the Previous Frame Rev. A | Page 48 of 75 Data Sheet AD7606C-18 Serial Register Mode with CRC With the CRC enabled, the SPI frames extend to 24 bits in length, as shown in Figure 113. Registers can be written to and read from the AD7606C-18 with CRC enabled, in software mode, by asserting the INT_CRC_ERR_EN bit (Address 0x21, Bit 2). When reading a register, the AD7606C-18 provides eight additional bits on the DOUTA pin with the CRC resultant of the data shifted out previously on the same frame. The controller can then check whether the data received is correct by applying the following polynomial: x8 + x2 + x + 1 When writing a register, the controller must clock the data (register address plus register content) in the AD7606C-18 followed by an 8-bit CRC word, calculated from the previous 16 bits using the above polynomial. The AD7606C-18 reads the register address and the register content, calculates the corresponding 8-bit CRC word, and asserts the INT_CRC_ERR bit (Address 0x22, Bit 2) if the calculated CRC word does not match the CRC word received between the 17th and 24th bit through the SDI, as shown in Figure 114. CS SDI 1 WEN R/W 9 8 16 24 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 MSB DOUTA LSB 24593-179 SCLK 8-BIT CRC Figure 113. Reading Registers Through the SPI with CRC Enabled CS SDI 1 WEN R/W 8 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 9 16 MSB LSB Figure 114. Writing Registers Through the SPI with CRC Enabled Rev. A | Page 49 of 75 24 8-BIT CRC 24593-180 SCLK AD7606C-18 Data Sheet DIAGNOSTICS Diagnostic features are available in software mode to verify the correct operation of the AD7606C-18. The list of diagnostic monitors includes reset detection, overvoltage detection, undervoltage detection, analog input open circuit detection, and digital error detection. If an error is detected, a flag asserts on the status header, if enabled, as described in the Digital Interface section. This flag points to the registers on which the error is located, as explained in the following sections. In addition, a diagnostic multiplexer can dedicate any channel to verify a series of internal nodes, as explained in the Diagnostics Multiplexer section. RESET DETECTION The RESET_DETECT bit on the status register (Address 0x01, Bit 7) asserts if either a partial reset or full reset pulse is applied to the AD7606C-18. On power-up, a full reset is required. This reset asserts the RESET_DETECT bit, indicating that the power-on reset (POR) initialized properly on the device. The POR monitors the REGCAP voltage and issues a full reset if the voltage drops under a certain threshold. The RESET_DETECT bit can be used to detect an unexpected device reset or a large glitch on the RESET pin, or a voltage drop on the supplies. The RESET_DETECT bit is only cleared by reading the status register. DIGITAL ERROR If the calculated and stored CRC values do not match, the error checking and correction (ECC) block can detect up to 3 bit errors (hamming distance of 4). Otherwise, the ROM_CRC_ERR (Address 0x22, Bit 0) asserts. When ROM_CRC_ERR asserts after power-up, it is recommended to issue a full reset to reload all factory settings. This ROM CRC monitoring feature is enabled by default but can be disabled by clearing the ROM_CRC_ERR_EN bit (Address 0x21, Bit 0). Memory Map CRC The memory map CRC is disabled by default. After the AD7606C-18 is configured in software mode through writing the required registers, the memory map CRC can be enabled through the MM_CRC_ERR_EN bit (Address 0x21, Bit 1). When enabled, the CRC calculation is performed on the entire memory map and stored. Every 4 μs, the CRC on the memory map is recalculated and compared to the stored CRC value. The AD7606C-18 uses the following 16-bit CRC polynomial to calculate the CRC checksum value on the memory map: x16 + x14 + x13 + x12 + x10 + x8 +x6 + x4 + x3 + x + 1 (0xBAAD) If the calculated and the stored CRC values do not match, the ECC block can detect up to 3 bit errors (hamming distance of 4). Otherwise, the memory map is corrupted and the MM_CRC_ERR bit (Address 0x22, Bit 1) asserts. Every time the memory map is written, the CRC is recalculated and the new value stored. Both the status register and status header contain a DIGITAL_ERROR bit. This bit asserts when any of the following monitors trigger: If the MM_CRC_ERR bit asserts, it is recommended to write the memory map to recalculate the CRC. If the MM_CRC_ERR bit persists, it is recommended to issue a full reset to restore the default contents of the memory map. • Interface CRC Checksum • • Memory map CRC, read only memory (ROM) CRC, and digital interface CRC. SPI invalid read or write. BUSY stuck high. To find out which monitor triggered the DIGITAL_ERROR bit, the DIGITAL_DIAG_ERR register (Address 0x22) has a bit dedicated for each of them, as explained in the ROM CRC, Memory Map CRC, Interface CRC Checksum, Interface Check, SPI Invalid Read and Write, and BUSY Stuck High sections. ROM CRC The ROM stores the factory trimming settings for the AD7606C-18. After power-up, the ROM content is loaded to registers during device initialization. After the load, a CRC is calculated on the loaded data and verified if the result matches the CRC stored in the ROM. The AD7606C-18 uses the following 16-bit CRC polynomial to calculate the CRC checksum value on the memory map: x16 + x14 + x13 + x12 + x10 + x8 +x6 + x4 + x3 + x + 1 (0xBAAD) The AD7606C-18 has a CRC checksum mode to improve interface robustness by detecting errors in data transmission. The CRC feature is available in both ADC modes (serial and parallel) and register mode (serial only). The AD7606C-18 uses the following 16-bit CRC polynomial to calculate the CRC checksum value: x16 + x14 + x13 + x12 + x10 + x8 +x6 + x4 + x3 + x + 1 (0xBAAD) To replicate the polynomial division in the controller, the data shifts left by 16 bits to create a number ending in 16 Logic 0s. The polynomial is aligned so that the MSB is adjacent to the leftmost Logic 1 of the data. An exclusive OR (XOR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned so that the MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure repeats. This process repeats until the original data is reduced to a value less than the polynomial, which results in the 16-bit checksum. Rev. A | Page 50 of 75 Data Sheet AD7606C-18 An example of the CRC calculation for the 16-bit data is shown in Table 28. The CRC corresponding to the data 0x064E, using the previously described polynomial, is 0x2137. use after reading all the channels. An example using four DOUTx lines is shown in Figure 115. If using two DOUTx lines (DOUTA and DOUTB), each 16-bit CRC word is calculated using data from four channels (72 bits), as shown in Figure 116. If using only one DOUTx line, all eight channels are clocked out through DOUTA, followed by the 16-bit CRC word calculated using data from the eight channels (144 bits). The serial interface supports the CRC when enabled via the INT_CRC_ERR_EN bit (Address 0x21, Bit 2). The CRC is a 16-bit word that is appended to the end of each DOUTx line in Table 28. Example CRC Calculation for 16-Bit Data1, 2 Data 0 Process Data 0 Polynomial 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 1 0 1 1 0 0 0 0 0 CRC X 0 1 1 0 1 1 0 1 1 1 0 X 0 1 1 1 0 0 0 0 0 1 1 X 0 0 0 1 1 1 0 1 1 1 0 X 0 1 1 0 1 1 0 0 0 0 0 X 0 1 1 1 0 0 0 1 1 1 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 This table represents the division of the data. Blank cells are for formatting purposes. X = don’t care. CONVST CS SCLK DOUTA V1 V2 CRC(V1,V2) DOUTB V3 V4 CRC(V3,V4) DOUTC V5 V6 CRC(V5,V6) DOUTD V7 V8 CRC(V7,V8) Figure 115. Serial Interface ADC Reading with CRC On, Four DOUTx Lines CONVST CS SCLK DOUTA V1 V2 V3 V4 CRC(V1,V4) DOUTB V5 V6 V7 V8 CRC(V5,V8) DOUTC 24593-077 2 X 0 0 0 1 1 0 1 1 0 0 0 24593-076 1 0 0 1 1 0 1 1 0 1 1 1 DOUTD Figure 116. Serial Interface ADC Reading with CRC On, Two DOUTx Lines Rev. A | Page 51 of 75 AD7606C-18 Data Sheet SPI Invalid Read and Write When the AD7606C-18 is in register mode and registers are being read or written, the CRC polynomial used is x8 + x2 + x + 1 (0x83). When reading a register, and CRC is enabled, each SPI frame is 26 bits long and the CRC 8-bit word is clocked out from the 17th to 24th SCLK cycle. Similarly, when writing a register, a CRC word can be appended on the SDI line, as shown in Figure 117. The AD7606C-18 checks and triggers an error, INT_CRC_ERR (Address 0x22, Bit 2), if the CRC word given and the CRC word internally calculated do not match. When attempting to read back an invalid register address, the SPI_READ_ERR bit (Address 0x22, Bit 4) is set. The invalid readback address detection can be enabled by setting the SPI_READ_ERR_EN bit (Address 0x21, Bit 4). If an SPI read error is triggered, it is cleared by overwriting that bit or disabling the checker. The parallel interface also supports CRC in ADC mode only, and it is clocked out through DB17 to DB2 after Channel 8, as shown in Figure 101. The 16-bit CRC word is calculated using data from the eight channels (128 bits). When attempting to write to an invalid register address or a read only register, the SPI_WRITE_ERR bit (Address 0x22, Bit 3) is set. The invalid write address detection can be enabled by setting the SPI_WRITE _ERR_EN bit (Address 0x21, Bit 3). If an SPI write error is triggered, it is cleared by overwriting that bit or disabling the checker. Interface Check BUSY Stuck High The integrity of the digital interface can be checked by setting the INTERFACE_CHECK_EN bit (Address 0x21, Bit 7). Selecting the interface check forces the conversion result registers to a known value, as shown in Table 29. BUSY stuck high monitoring is enabled by setting the BUSY_STUCK_HIGH_ERR_EN bit (Address 0x21, Bit 5). After this bit is enabled, the conversion time (tCONV in Table 3) is monitored internally with an independent clock. If tCONV exceeds 4 μs, the AD7606C-18 automatically issues a partial reset and asserts the BUSY_STUCK_HIGH_ERR bit (Address 0x22, Bit 5). To clear this error flag, the BUSY_STUCK_HIGH_ERR bit must be overwritten with a 1. Verifying that the controller receives the data in Table 29 ensures that the interface between the AD7606C-18 and the controller operates properly. If the interface CRC is enabled because the data transmitted is known, this mode verifies that the controller performs the CRC calculation properly. When oversampling mode is enabled, the individual conversion time for each internal conversion is monitored. Table 29. Interface Check Conversion Results Conversion Result Forced (Hex) 0x2ACCA 0x15CC5 0x2A33A 0x15335 0x0CAAC 0x0C55C 0x33AA3 0x33553 CS SCLK DOUTA TO DOUTH SDI 1 2 3 4 DB17 DB16 DB15 DB14 WEN R/W ADD5 ADD4 17 18 DB1 DB0 CRC7 19 CRC7 CRC6 CRC5 Figure 117. Register Write with CRC On Rev. A | Page 52 of 75 26 CRC0 24593-078 Channel Number V1 V2 V3 V4 V5 V6 V7 V8 Data Sheet AD7606C-18 10 DIAGNOSTICS MULTIPLEXER 8 All eight input channels contain a diagnostics multiplexer in front of the PGA that monitors the internal nodes described in Table 30 to ensure the correct operation of the AD7606C-18. For accurate measurements, it is recommended to use Channel 8, where the offset and gain for diagnostic channels have been trimmed in production. 6 ERROR (°C) 4 Table 30 shows the bit decoding for the diagnostic mux register on Channel 1 as an example. When an internal node is selected, the input voltage at the input pins is deselected from the PGA, as shown in Figure 118. Table 30. Channel 1 Diagnostic Mux Register Bit Decoding TEMPERATURE SENSOR VREF ALDO DLDO VDRIVE AGND AVCC Bit 0 0 1 0 1 0 1 0 1 Signal on Channel 1 V1 Temperature sensor VREF ALDO DLDO VDRIVE AGND AVCC –2 –4 –6 –8 ONLY CHANNEL 8 SHOWN 20 DEVICES –10 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 Figure 119. Temperature Sensor Error Reference Voltage The reference voltage can be selected through the diagnostic multiplexer and converted with the ADC, as shown in Figure 120. The internal or external reference is selected as an input to the diagnostic multiplexer based on the REF SELECT pin. Ideally, the ADC output follows the voltage reference level ratiometrically. Therefore, if the ADC output goes beyond the expected 2.5 V, either the reference buffer or the PGA is malfunctioning. AD7606C-18 INT REF 4.4V EXT REF AD7606C-18 2.5V MUX RFB 1MΩ MUX 1MΩ Vx+ RFB Vx– ADC 1MΩ RFB Vx+ Vx– 1MΩ 24593-080 Bit 2 0 0 0 0 1 1 1 1 Address 0x18 Bit 1 0 0 1 1 0 0 1 1 0 24592-010 Each diagnostic multiplexer configuration is accessed in software mode through the corresponding register (Address 0x28 to Address 0x2B). To use the multiplexer on one channel, the ±10 V range must be selected on that channel. 2 Figure 120. Reference Voltage Signal Path Through the Diagnostic Multiplexer RFB 24593-079 Internal LDOs Figure 118. Diagnostic Multiplexer (Channel 1 Shown as an Example) (RFB = Feedback Resistor) Temperature Sensor The temperature sensor can be selected through the diagnostic multiplexer and converted with the ADC, as shown in Figure 118. The temperature sensor voltage is measured and is proportional to the die temperature as per the following equation: Temperature ( °C ) = ADC OUT ( V ) − 0.19502 ( V ) 0.000618 ( V / °C ) + 25 ( °C ) The analog and digital LDO (REGCAP pins) can be selected through the diagnostic multiplexer and converted with the ADC, as shown in Figure 118. The ADC output is four times the voltage on the REGCAP pins. This measurement verifies that each LDO is at the correct operating voltage so that the internal circuitry is biased correctly. Supply Voltages AVCC, VDRIVE, and AGND can be selected through the diagnostic multiplexer and converted with the ADC, as shown in Figure 118. This setup ensures the voltage and grounds are correctly applied to the device to ensure correct operation. Rev. A | Page 53 of 75 AD7606C-18 Data Sheet TYPICAL CONNECTION DIAGRAM There are four AVCC supply pins on the AD7606C-18 and it is recommended that each of the four pins are decoupled using a 100 nF capacitor at each supply pin and a 10 µF capacitor at the supply source. The AD7606C-18 can operate with the internal reference or an externally applied reference. When using a single AD7606C-18 device on the PCB, decouple the REFIN/REFOUT pin with a 100 nF capacitor. Refer to the Reference section when using an application with multiple AD7606C-18 devices. The REFCAPA and REFCAPB pins are shorted together and decoupled with a 10 µF ceramic capacitor. uses the parallel interface because the PAR/SER SEL pin is tied to AGND. The analog input range for all eight channels is ±10 V, provided the RANGE pin is tied to a high level and the oversampling ratio is controlled through the OSx pins by the controller. In Figure 121, the AD7606C-18 is configured in software mode because the OSx pins are at logic level high. The oversampling ratio, as well as each channel range, are configured by accessing the memory map. In this example, the PAR/SER SEL pin is at logic level high. Therefore, the serial interface is used for both reading the ADC data and reading and writing the memory map. The REF SELECT pin is tied to AGND. Therefore, the internal reference is disabled and an external reference is connected externally to the REFIN/REFOUT pin and decoupled through a 100 nF capacitor. The VDRIVE supply is connected to the same supply as the processor. The VDRIVE voltage controls the voltage value of the output logic signals. For more information on layout, decoupling, and grounding, see the Layout Guidelines section. After supplies are applied to the AD7606C-18, apply a full reset to the AD7606C-18 to ensure that it is configured for the correct mode of operation. Figure 120 and Figure 121 are examples of typical connection diagrams. Other combinations of the reference, data interface, and operation mode are also possible, depending on the logic levels applied to each configuration pin. 100nF + REFIN/REFOUT ANALOG SUPPLY VOLTAGE 5V1 1µF 100nF 100nF REGCAP2 AVCC REFCAPA 10µF + DIGITAL SUPPLY VOLTAGE 1.71V TO 5.25V VDRIVE DB0 TO DB17 REFCAPB REFGND CONVST V1+ CS V1– RD V2+ BUSY V2– V3+ V3– EIGHT ANALOG INPUTS V1 TO V8 PARALLEL INTERFACE MICROPROCESSOR/ MICROCONVERTER/ DSP In Figure 120, the AD7606C-18 is configured in hardware mode and is operating with the internal reference because the REF SELECT pin is set to logic high. In this example, the device also AD7606C-18 V4+ RESET OS2 OS1 V4– OVERSAMPLING OS0 V5+ V5– REF SELECT V6+ VDRIVE PAR/SER SEL V6– V7+ RANGE V7– STBY VDRIVE V8+ AGND 1DECOUPLING SHOWN ON THE AV CC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48). DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV CC PIN 37 AND PIN 38. 2DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). Figure 120. Typical Connection Diagram, Hardware Mode Rev. A | Page 54 of 75 24593-081 V8– Data Sheet AD7606C-18 ANALOG SUPPLY VOLTAGE 5V1 REF 100nF + REFIN/REFOUT DIGITAL SUPPLY VOLTAGE 1.71V to 5.25V 100nF 100nF 1µF REGCAP 2 AVCC VDRIVE 10µF + DB0 TO DB17 REFCAPB REFGND CONVST V1+ CS V1– SDI V2+ DOUT x SCLK RESET V2– V3+ V3– EIGHT ANALOG INPUTS V1 TO V8 AD7606C-18 MICROPROCESSOR/ MICROCONVERTER/ DSP REFCAPA OS2 V4+ OS1 V4– V5+ OS0 V5– REF SELECT OVERSAMPLING = 111b V6+ V6– PAR/SER SEL V7+ RANGE V7– V8+ AGND 1DECOUPLING SHOWN ON THE AVCC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48). DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AVCC PIN 37 AND PIN 38. SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). 2DECOUPLING Figure 121. Typical Connection Diagram, Software Mode Rev. A | Page 55 of 75 24593-082 V8– VDRIVE STBY AD7606C-18 Data Sheet The following layout guidelines are recommended to be followed when designing the PCB that houses the AD7606C-18: • • • • • • • • If the AD7606C-18 is in a system where multiple devices require analog-to-digital ground connections, use a solid ground plane (without splitting between analog and digital grounds). Make stable connections to the ground plane. Avoid sharing one connection for multiple ground pins. Use individual vias or multiple vias to the ground plane for each ground pin. Avoid running digital lines under the devices because doing so couples noise on the die. Allow the analog ground plane to run under the AD7606C-18 to avoid noise coupling. Shield fast switching signals like CONVST or clocks with digital ground to avoid radiating noise to other sections of the board and ensure that they do not run near analog signal paths. Avoid crossover of digital and analog signals. Ensure traces on layers in close proximity on the board run at right angles to each other to reduce the effect of feedthrough through the board. Ensure power supply lines to the AVCC and VDRIVE pins on the AD7606C-18 use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Where possible, use supply planes and make stable connections between the AD7606C-18 supply pins and the power tracks on the board. Use a single via or multiple vias for each supply pin. Place the decoupling capacitors close to (ideally, directly against) the supply pins and their corresponding ground pins. Place the decoupling capacitors for the REFIN/REFOUT pin and the REFCAPA pin and REFCAPB pin as close as possible to their respective AD7606C-18 pins. Where possible, place the pins on the same side of the board as the AD7606C-18 device. Figure 122 shows the recommended decoupling on the top layer of the AD7606C-18 PCB. Figure 123 shows bottom layer decoupling, which is used for the four AVCC pins and the VDRIVE pin decoupling. Where the ceramic 100 nF capacitors for the AVCC pins are placed close to their respective device pins, a single 100 nF capacitor can be shared between Pin 37 and Pin 38. 24593-083 LAYOUT GUIDELINES Figure 122. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and REGCAP Pins 24593-084 APPLICATIONS INFORMATION Figure 123. Bottom Layer Decoupling To ensure stable device to device performance matching in a system that contains multiple AD7606C-18 devices, a symmetrical layout between the AD7606C-18 devices is important. Rev. A | Page 56 of 75 Data Sheet AD7606C-18 Figure 124 shows a layout with two AD7606C-18 devices. The AVCC supply plane runs to the right of both devices, and the VDRIVE supply track runs to the left of the two devices. The reference chip is positioned between the two devices, and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 of U2. A solid ground plane is used. AVCC U2 These symmetrical layout principles can also be applied to a system that contains more than two AD7606C-18 devices. The AD7606C-18 devices can be placed in a north to south direction, with the reference voltage located midway between the devices and the reference track running in the north to south direction, similar to Figure 124. 24593-085 U1 Figure 124. Layout for Multiple AD7606C-18 Devices—Top Layer and Supply Plane Layer Rev. A | Page 57 of 75 AD7606C-18 Data Sheet REGISTER SUMMARY Table 31. AD7606C-18 Register Summary Addr 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 Name STATUS CONFIG RANGE_CH1_ CH2 RANGE_CH3_ CH4 RANGE_CH5_ CH6 RANGE_CH7_ CH8 BANDWIDTH OVERSAMPLING CH1_GAIN CH2_GAIN CH3_GAIN CH4_GAIN CH5_GAIN CH6_GAIN CH7_GAIN CH8_GAIN CH1_OFFSET CH2_OFFSET CH3_OFFSET CH4_OFFSET CH5_OFFSET CH6_OFFSET CH7_OFFSET CH8_OFFSET CH1_PHASE CH2_PHASE CH3_PHASE CH4_PHASE CH5_PHASE CH6_PHASE CH7_PHASE CH8_PHASE DIGITAL_ DIAG_ ENABLE DIGITAL_ DIAG_ERR Bit 7 RESET_DETECT RESERVED CH8_BW INTERFACE_ CHECK_EN Bit 6 Bit 5 DIGITAL_ERROR OPEN_DETECTED STATUS_HEADER EXT_OS_CLOCK CH2_RANGE CH6_RANGE CH5_RANGE 0x33 R/W CH8_RANGE CH7_RANGE 0x33 R/W 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00 R/W 0x00 R/W 0x00 R/W CH1_DIAG_MUX_CTRL 0x00 R/W CH7_BW OS_PAD RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED CLK_FS_OS_ COUNTER_EN RESERVED CH3_BW CH2_BW OS_RATIO CH1_BW CH1_GAIN CH2_GAIN CH3_GAIN CH4_GAIN CH5_GAIN CH6_GAIN CH7_GAIN CH8_GAIN BUSY_STUCK_ HIGH_ERR_EN CH1_OFFSET CH2_OFFSET CH3_OFFSET CH4_OFFSET CH5_OFFSET CH6_OFFSET CH7_OFFSET CH8_OFFSET CH1_PHASE CH2_PHASE CH3_PHASE CH4_PHASE CH5_PHASE CH6_PHASE CH7_PHASE CH8_PHASE SPI_READ _ERR_EN SPI_ WRITE_ ERR_EN SPI_ WRITE_ ERR CH4_ OPEN_ DETECT_ EN CH4_ OPEN INT_CRC_ ERR_EN MM_CRC_ ERR_EN INT_CRC_ ERR MM_CRC_ ERR CH3_OPEN_ DETECT_EN CH2_OPEN_ DETECT_EN CH3_OPEN CH2_OPEN ROM_ CRC_ ERR_EN ROM_ CRC_ ERR CH1_ OPEN_ DETECT_ EN CH1_ OPEN RESERVED CH4_DIAG_MUX_CTRL CH3_DIAG_MUX_CTRL 0x00 R/W RESERVED CH6_DIAG_MUX_CTRL CH5_DIAG_MUX_CTRL 0x00 R/W RESERVED CH8_DIAG_MUX_CTRL CH7_DIAG_MUX_CTRL 0x00 R/W OPEN_DETECT_QUEUE 0x00 R/W CLK_FS_COUNTER 0x00 R CLK_OS_COUNTER 0x00 R 0x31 R CH7_OPEN 0x2F CH4_BW RESERVED CH8_OPEN 0x2E CH5_BW SPI_ READ_ ERR CH6_OPEN_ CH5_ DETECT_EN OPEN_ DETECT_ EN CH6_OPEN CH5_ OPEN CH2_DIAG_MUX_CTRL OPEN_ DETECTED DIAGNOSTIC_ MUX_CH1_2 DIAGNOSTIC_ MUX_CH3_4 DIAGNOSTIC_ MUX_CH5_6 DIAGNOSTIC_ MUX_CH7_8 OPEN_DETECT_ QUEUE FS_CLK_ COUNTER OS_CLK_ COUNTER ID 0x2D CH6_BW BUSY_STUCK_ HIGH_ERR 0x24 0x2C R/W R R/W R/W R/W CH7_OPEN_ DETECT_EN 0x2B Reset 0x00 0x08 0x33 0x33 CH8_OPEN_ DETECT_EN 0x2A DOUT_FORMAT Bit 2 Bit 1 Bit 0 RESERVED RESERVED OPERATION_MODE CH1_RANGE CH3_RANGE OPEN_ DETECT_ ENABLE 0x29 Bit 3 CH4_RANGE 0x23 0x28 Bit 4 DEVICE_ID SILICON_REVISION Rev. A | Page 58 of 75 Data Sheet AD7606C-18 REGISTER DETAILS Address: 0x01, Reset: 0x00, Name: STATUS 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESET_DETECT (R) Reset Detected. Either a full, partial, or power-on reset has been detected on the internal LDO. [4:0] RESERVED [5] OPEN_DETECTED (R) Open Circuit Detected. Check the OPEN_DETECTED register (Address 0x24) to determine which channel is affected. [6] DIGITAL_ERROR (R) Digital Error Present. Read the DIGITAL_DIAG_ERR register (Address 0x22) to determine the type of digital error. Table 32. Bit Descriptions for STATUS Bits 7 Bit Name RESET_DETECT 6 DIGITAL_ERROR 5 OPEN_DETECTED [4:0] RESERVED Description Reset Detected. Either a full, partial, or power-on reset has been detected on the internal LDO. Digital Error Present. Read the DIGITAL_DIAG_ERR register (Address 0x22) to determine the type of digital error. Open Circuit Detected. Check the OPEN_DETECTED register (Address 0x24) to determine which channel is affected. Reserved. Reset 0x0 Access R 0x0 R 0x0 R 0x0 R Reset 0x0 0x0 Access R R/W 0x0 R/W 0x1 R/W 0x0 0x0 R R/W Address: 0x02, Reset: 0x08, Name: CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 [7] RESERVED [6] STATUS_HEADER (R/W) Enables STATUS Header to be Appended to ADC Data in Both Serial and Parallel Interface Modes [5] EXT_OS_CLOCK (R/W) External Oversampling Clock. In oversampling mode, enables external oversampling clock. Oversampling conversions are triggered through a clock signal applied to CONVST pin and not managed by the internal oversampling clock [1:0] OPERATION_MODE (R/W) Operation Mode 00: normal mode. 01: standby mode. 10: autostandby mode. 11: shutdown mode. [2] RESERVED [4:3] DOUT_FORMAT (R/W) Number of DOUTX Lines Used in Serial Mode when Reading Conversions 00: 1 DOUTx. 01: 2 DOUTx. 10: 4 DOUTx. 11: 8 DOUTx. Table 33. Bit Descriptions for CONFIG Bits 7 6 Bit Name RESERVED STATUS_HEADER 5 EXT_OS_CLOCK [4:3] DOUT_FORMAT 2 [1:0] RESERVED OPERATION_MODE Description Reserved. Enables STATUS Header to be Appended to ADC Data in Both Serial and Parallel Interface Modes. External Oversampling Clock. In oversampling mode, enables external oversampling clock. Oversampling conversions are triggered through a clock signal applied to CONVST pin and not managed by the internal oversampling clock. Number of DOUTx Lines Used in Serial Mode when Reading Conversions. 00: 1 DOUTx. 01: 2 DOUTx. 10: 4 DOUTx. 11: 8 DOUTx. Reserved. Operation Mode. 00: normal mode. 01: standby mode. 10: autostandby mode. 11: shutdown mode. Rev. A | Page 59 of 75 AD7606C-18 Data Sheet Address: 0x03, Reset: 0x33, Name: RANGE_CH1_CH2 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 1 [7:4] CH2_RANGE (R/W) Range Options for Channel 2 0000: ±2.5 V single-ended range. 0001: ± 5V single-ended range. 0010: ±6.25 V single-ended range. ... 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. [3:0] CH1_RANGE (R/W) Range Options for Channel 1 0000: ±2.5V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. ... 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. Table 34. Bit Descriptions for RANGE_CH1_CH2 Bits [7:4] Bit Name CH2_RANGE [3:0] CH1_RANGE Description Range Options for Channel 2. 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. 0011: ±10 V single-ended range. 0100: ±12.5 V single-ended range. 0101: 0 V to 5 V single-ended range. 0110: 0 V to 10 V single-ended range. 0111: 0 V to 12.5 V single-ended range. 1000: ±5 V differential range. 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. Range Options for Channel 1. 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. 0011: ±10 V single-ended range. 0100: ±12.5 V single-ended range. 0101: 0 V to 5 V single-ended range. 0110: 0 V to 10 V single-ended range. 0111: 0 V to 12.5 V single-ended range. 1000: ±5 V differential range. 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. Reset 0x3 Access R/W 0x3 R/W Reset 0x3 Access R/W Address: 0x04, Reset: 0x33, Name: RANGE_CH3_CH4 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 1 [7:4] CH4_RANGE (R/W) Range Options for Channel 4 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. ... 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. [3:0] CH3_RANGE (R/W) Range Options for Channel 3 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. ... 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. Table 35. Bit Descriptions for RANGE_CH3_CH4 Bits [7:4] Bit Name CH4_RANGE Description Range Options for Channel 4. 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. Rev. A | Page 60 of 75 Data Sheet Bits Bit Name [3:0] CH3_RANGE AD7606C-18 Description 0011: ±10 V single-ended range. 0100: ±12.5 V single-ended range. 0101: 0 V to 5 V single-ended range. 0110: 0 V to 10 V single-ended range. 0111: 0 V to 12.5 V single-ended range. 1000: ±5 V differential range. 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. Range Options for Channel 3. 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. 0011: ±10 V single-ended range. 0100: ±12.5 V single-ended range. 0101: 0 V to 5 V single-ended range. 0110: 0 V to 10 V single-ended range. 0111: 0 V to 12.5 V single-ended range. 1000: ±5 V differential range. 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. Reset Access 0x3 R/W Reset 0x3 Access R/W 0x3 R/W Address: 0x05, Reset: 0x33, Name: RANGE_CH5_CH6 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 1 [7:4] CH6_RANGE (R/W) Range Options for Channel 6 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. ... 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. [3:0] CH5_RANGE (R/W) Range Options for Channel 5 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. ... 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. Table 36. Bit Descriptions for RANGE_CH5_CH6 Bits [7:4] Bit Name CH6_RANGE [3:0] CH5_RANGE Description Range Options for Channel 6. 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. 0011: ±10 V single-ended range. 0100: ±12.5 V single-ended range. 0101: 0 V to 5 V single-ended range. 0110: 0 V to 10 V single-ended range. 0111: 0 V to 12.5 V single-ended range. 1000: ±5 V differential range. 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. Range Options for Channel 5. 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. 0011: ±10 V single-ended range. Rev. A | Page 61 of 75 AD7606C-18 Bits Bit Name Data Sheet Description 0100: ±12.5 V single-ended range. 0101: 0 V to 5 V single-ended range. 0110: 0 V to 10 V single-ended range. 0111: 0 V to 12.5 V single-ended range. 1000: ±5 V differential range. 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. Reset Access Reset 0x3 Access R/W 0x3 R/W Address: 0x06, Reset: 0x33, Name: RANGE_CH7_CH8 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 1 [7:4] CH8_RANGE (R/W) Range Options for Channel 8 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. ... 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. [3:0] CH7_RANGE (R/W) Range Options for Channel 7 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. ... 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. Table 37. Bit Descriptions for RANGE_CH7_CH8 Bits [7:4] Bit Name CH8_RANGE [3:0] CH7_RANGE Description Range Options for Channel 8. 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. 0011: ±10 V single-ended range. 0100: ±12.5 V single-ended range. 0101: 0 V to 5 V single-ended range. 0110: 0 V to 10 V single-ended range. 0111: 0 V to 12.5 V single-ended range. 1000: ±5 V differential range. 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. Range Options for Channel 7. 0000: ±2.5 V single-ended range. 0001: ±5 V single-ended range. 0010: ±6.25 V single-ended range. 0011: ±10 V single-ended range. 0100: ±12.5 V single-ended range. 0101: 0 V to 5 V single-ended range. 0110: 0 V to 10 V single-ended range. 0111: 0 V to 12.5 V single-ended range. 1000: ±5 V differential range. 1001: ±10 V differential range. 1010: ±12.5 V differential range. 1011: ±20 V differential range. Rev. A | Page 62 of 75 Data Sheet AD7606C-18 Address: 0x07, Reset: 0x00, Name: BANDWIDTH 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] CH8_BW (R/W) Enables high bandwidth mode on Channel 8 [0] CH1_BW (R/W) Enables high bandwidth mode on Channel 1 [6] CH7_BW (R/W) Enables high bandwidth mode on Channel 7 [1] CH2_BW (R/W) Enables high bandwidth mode on Channel 2 [5] CH6_BW (R/W) Enables high bandwidth mode on Channel 6 [2] CH3_BW (R/W) Enables high bandwidth mode on Channel 3 [4] CH5_BW (R/W) Enables high bandwidth mode on Channel 5 [3] CH4_BW (R/W) Enables high bandwidth mode on Channel 4 Table 38. Bit Descriptions for BANDWIDTH Bits 7 6 5 4 3 2 1 0 Bit Name CH8_BW CH7_BW CH6_BW CH5_BW CH4_BW CH3_BW CH2_BW CH1_BW Description Enables high bandwidth mode on Channel 8. Enables high bandwidth mode on Channel 7. Enables high bandwidth mode on Channel 6. Enables high bandwidth mode on Channel 5. Enables high bandwidth mode on Channel 4. Enables high bandwidth mode on Channel 3. Enables high bandwidth mode on Channel 2. Enables high bandwidth mode on Channel 1. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0x0 Access R/W 0x0 R/W Address: 0x08, Reset: 0x00, Name: OVERSAMPLING 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] OS_PAD (R/W) Oversampling Padding. Extends the internal oversampling period allowing evenly spaced sampling between CONVST rising edges. [3:0] OS_RATIO (R/W) Oversampling Ratio 0: oversampling off. 1: oversampling by 2. 10: oversampling by 4. ... 110: oversampling by 64. 111: oversampling by 128. 1000: oversampling by 256. Table 39. Bit Descriptions for OVERSAMPLING Bits [7:4] Bit Name OS_PAD [3:0] OS_RATIO Description Oversampling Padding. Extends the internal oversampling period allowing evenly spaced sampling between CONVST rising edges. Oversampling Ratio. 0000: oversampling off. 0001: oversampling by 2. 0010: oversampling by 4. 0011: oversampling by 8. 0100: oversampling by 16. 0101: oversampling by 32. 0110: oversampling by 64. 0111: oversampling by 128. 1000: oversampling by 256. Rev. A | Page 63 of 75 AD7606C-18 Data Sheet Address: 0x09, Reset: 0x00, Name: CH1_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH1_GAIN (R/W) Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω Table 40. Bit Descriptions for CH1_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH1_GAIN Description Reserved. Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Address: 0x0A, Reset: 0x00, Name: CH2_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH2_GAIN (R/W) Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω Table 41. Bit Descriptions for CH2_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH2_GAIN Description Reserved. Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. Address: 0x0B, Reset: 0x00, Name: CH3_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH3_GAIN (R/W) Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω Table 42. Bit Descriptions for CH3_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH3_GAIN Description Reserved. Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. Address: 0x0C, Reset: 0x00, Name: CH4_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH4_GAIN (R/W) Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω Table 43. Bit Descriptions for CH4_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH4_GAIN Description Reserved. Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. Rev. A | Page 64 of 75 Data Sheet AD7606C-18 Address: 0x0D, Reset: 0x00, Name: CH5_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH5_GAIN (R/W) Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω Table 44. Bit Descriptions for CH5_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH5_GAIN Description Reserved. Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Address: 0x0E, Reset: 0x00, Name: CH6_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH6_GAIN (R/W) Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω Table 45. Bit Descriptions for CH6_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH6_GAIN Description Reserved. Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. Address: 0x0F, Reset: 0x00, Name: CH7_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH7_GAIN (R/W) Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω Table 46. Bit Descriptions for CH7_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH7_GAIN Description Reserved. Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. Address: 0x10, Reset: 0x00, Name: CH8_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH8_GAIN (R/W) Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω Table 47. Bit Descriptions for CH8_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH8_GAIN Description Reserved. Gain Register to Remove Gain Error Caused by External RFILTER. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. Rev. A | Page 65 of 75 AD7606C-18 Data Sheet Address: 0x11, Reset: 0x80, Name: CH1_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH1_OFFSET (R/W) Offset Register to Remove External System Offset Errors. Range from –512 LSB to +511 LSB. Table 48. Bit Descriptions for CH1_OFFSET Bits [7:0] Bit Name CH1_OFFSET Description Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB. Reset 0x80 Access R/W Reset 0x80 Access R/W Reset 0x80 Access R/W Reset 0x80 Access R/W Reset 0x80 Access R/W Address: 0x12, Reset: 0x80, Name: CH2_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH2_OFFSET (R/W) Offset Register to Remove External System Offset Errors. Range from –512 LSB to +511 LSB. Table 49. Bit Descriptions for CH2_OFFSET Bits [7:0] Bit Name CH2_OFFSET Description Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB. Address: 0x13, Reset: 0x80, Name: CH3_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH3_OFFSET (R/W) Offset Register to Remove External System Offset Errors. Range from –512 LSB to +511 LSB. Table 50. Bit Descriptions for CH3_OFFSET Bits [7:0] Bit Name CH3_OFFSET Description Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB. Address: 0x14, Reset: 0x80, Name: CH4_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH4_OFFSET (R/W) Offset Register to Remove External System Offset Errors. Range from –512 LSB to +511 LSB. Table 51. Bit Descriptions for CH4_OFFSET Bits [7:0] Bit Name CH4_OFFSET Description Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB. Address: 0x15, Reset: 0x80, Name: CH5_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH5_OFFSET (R/W) Offset Register to Remove External System Offset Errors. Range from –512 LSB to +511 LSB. Table 52. Bit Descriptions for CH5_OFFSET Bits [7:0] Bit Name CH5_OFFSET Description Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB. Rev. A | Page 66 of 75 Data Sheet AD7606C-18 Address: 0x16, Reset: 0x80, Name: CH6_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH6_OFFSET (R/W) Offset Register to Remove External System Offset Errors. Range from –512 LSB to +511 LSB. Table 53. Bit Descriptions for CH6_OFFSET Bits [7:0] Bit Name CH6_OFFSET Description Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB. Reset 0x80 Access R/W Reset 0x80 Access R/W Reset 0x80 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x17, Reset: 0x80, Name: CH7_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH7_OFFSET (R/W) Offset Register to Remove External System Offset Errors. Range from –512 LSB to +511 LSB. Table 54. Bit Descriptions for CH7_OFFSET Bits [7:0] Bit Name CH7_OFFSET Description Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB. Address: 0x18, Reset: 0x80, Name: CH8_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH8_OFFSET (R/W) Offset Register to Remove External System Offset Errors. Range from –512 LSB to +511 LSB. Table 55. Bit Descriptions for CH8_OFFSET Bits [7:0] Bit Name CH8_OFFSET Description Offset Register to Remove External System Offset Errors. Range from −512 LSB to +511 LSB. Address: 0x19, Reset: 0x00, Name: CH1_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_PHASE (R/W) Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Table 56. Bit Descriptions for CH1_PHASE Bits [7:0] Bit Name CH1_PHASE Description Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Address: 0x1A, Reset: 0x00, Name: CH2_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_PHASE (R/W) Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Table 57. Bit Descriptions for CH2_PHASE Bits [7:0] Bit Name CH2_PHASE Description Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Rev. A | Page 67 of 75 AD7606C-18 Data Sheet Address: 0x1B, Reset: 0x00, Name: CH3_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_PHASE (R/W) Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Table 58. Bit Descriptions for CH3_PHASE Bits [7:0] Bit Name CH3_PHASE Description Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x1C, Reset: 0x00, Name: CH4_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_PHASE (R/W) Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Table 59. Bit Descriptions for CH4_PHASE Bits [7:0] Bit Name CH4_PHASE Description Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Address: 0x1D, Reset: 0x00, Name: CH5_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_PHASE (R/W) Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Table 60. Bit Descriptions for CH5_PHASE Bits [7:0] Bit Name CH5_PHASE Description Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Address: 0x1E, Reset: 0x00, Name: CH6_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_PHASE (R/W) Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Table 61. Bit Descriptions for CH6_PHASE Bits [7:0] Bit Name CH6_PHASE Description Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Rev. A | Page 68 of 75 Data Sheet AD7606C-18 Address: 0x1F, Reset: 0x00, Name: CH7_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_PHASE (R/W) Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Table 62. Bit Descriptions for CH7_PHASE Bits [7:0] Bit Name CH7_PHASE Description Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W 0x0 0x0 R/W R/W 0x0 0x0 0x0 0x0 0x1 R/W R/W R/W R/W R/W Address: 0x20, Reset: 0x00, Name: CH8_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH8_PHASE (R/W) Phase Register to Remove External System Phase Errors Between Channels.. Phase delay from 0 µs to 255 µs in steps of 1 µs. Table 63. Bit Descriptions for CH8_PHASE Bits [7:0] Bit Name CH8_PHASE Description Phase Register to Remove External System Phase Errors Between Channels. Phase delay from 0 µs to 255 µs in steps of 1 µs. Address: 0x21, Reset: 0x01, Name: DIGITAL_DIAG_ENABLE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7] INTERFACE_CHECK_EN (R/W) Enables interface check. Provides a fixed data on each channel when reading ADC data. [0] ROM_CRC_ERR_EN (R/W) Enables ROM CRC check. [6] CLK_FS_OS_COUNTER_EN (R/W) Enables FS_CLOCK and OS_CLOCK counter. [5] BUSY_STUCK_HIGH_ERR_EN (R/W) Enables busy line stuck high which is a monitor of the conversion time to ensure ADC operation. [4] SPI_READ_ERR_EN (R/W) Enables checking if attempting to read from an invalid address. [1] MM_CRC_ERR_EN (R/W) Enables memory map CRC check. [2] INT_CRC_ERR_EN (R/W) Enables interface CRC check. [3] SPI_WRITE_ERR_EN (R/W) Enables checking if attempting to write to an invalid address. Table 64. Bit Descriptions for DIGITAL_DIAG_ENABLE Bits 7 Bit Name INTERFACE_CHECK_EN 6 5 CLK_FS_OS_COUNTER_EN BUSY_STUCK_HIGH_ERR_EN 4 3 2 1 0 SPI_READ_ERR_EN SPI_WRITE_ERR_EN INT_CRC_ERR_EN MM_CRC_ERR_EN ROM_CRC_ERR_EN Description Enables interface check. Provides a fixed data on each channel when reading ADC data. Enables FS_CLOCK and OS_CLOCK counter. Enables busy line stuck high which is a monitor of the conversion time to ensure ADC operation. Enables checking if attempting to read from an invalid address. Enables checking if attempting to write to an invalid address. Enables interface CRC check. Enables memory map CRC check. Enables ROM CRC check. Rev. A | Page 69 of 75 AD7606C-18 Data Sheet Address: 0x22, Reset: 0x00, Name: DIGITAL_DIAG_ERR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] ROM_CRC_ERR (R/W1C) ROM CRC Error. [5] BUSY_STUCK_HIGH_ERR (R/W1C) Busy Stuck High Error. Busy pin has been at a high logic level for longer than 4 µs. [1] MM_CRC_ERR (R/W1C) Memory Map CRC Error. [4] SPI_READ_ERR (R/W1C) SPI Invalid Read Address. [2] INT_CRC_ERR (R/W1C) Interface CRC Error. [3] SPI_WRITE_ERR (R/W1C) SPI Invalid Write Address. Table 65. Bit Descriptions for DIGITAL_DIAG_ERR Bits [7:6] 5 4 3 2 1 0 Bit Name RESERVED BUSY_STUCK_HIGH_ERR SPI_READ_ERR SPI_WRITE_ERR INT_CRC_ERR MM_CRC_ERR ROM_CRC_ERR Description Reserved. Busy Stuck High Error. Busy pin has been at high logic level for longer than 4 μs. SPI Invalid Read Address. SPI Invalid Write Address. Interface CRC Error. Memory Map CRC Error. ROM CRC Error. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Address: 0x23, Reset: 0x00, Name: OPEN_DETECT_ENABLE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] CH8_OPEN_DETECT_EN (R/W) In automatic mode, enables analog input open circuit detection for Channel 8. In manual mode, sets the PGA common mode to high. [0] CH1_OPEN_DETECT_EN (R/W) In automatic mode, enables analog input open circuit detection for Channel 1. In manual mode, sets the PGA common mode to high. [6] CH7_OPEN_DETECT_EN (R/W) In automatic mode, enables analog input open circuit detection for Channel 7. In manual mode, sets the PGA common mode to high. [1] CH2_OPEN_DETECT_EN (R/W) In automatic mode, enables analog input open circuit detection for Channel 2. In manual mode, sets the PGA common mode to high. [5] CH6_OPEN_DETECT_EN (R/W) In automatic mode, enables analog input open circuit detection for Channel 6. In manual mode, sets the PGA common mode to high. [2] CH3_OPEN_DETECT_EN (R/W) In automatic mode, enables analog input open circuit detection for Channel 3. In manual mode, sets the PGA common mode to high. [4] CH5_OPEN_DETECT_EN (R/W) In automatic mode, enables analog input open circuit detection for Channel 5. In manual mode, sets the PGA common mode to high. [3] CH4_OPEN_DETECT_EN (R/W) In automatic mode, enables analog input open circuit detection for Channel 4. In manual mode, sets the PGA common mode to high. Table 66. Bit Descriptions for OPEN_DETECT_ENABLE Bits 7 Bit Name CH8_OPEN_DETECT_EN 6 CH7_OPEN_DETECT_EN 5 CH6_OPEN_DETECT_EN 4 CH5_OPEN_DETECT_EN 3 CH4_OPEN_DETECT_EN 2 CH3_OPEN_DETECT_EN 1 CH2_OPEN_DETECT_EN 0 CH1_OPEN_DETECT_EN Description In automatic mode, enables analog input open circuit detection for Channel 8. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open circuit detection for Channel 7. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open circuit detection for Channel 6. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open circuit detection for Channel 5. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open circuit detection for Channel 4. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open circuit detection for Channel 3. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open circuit detection for Channel 2. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open circuit detection for Channel 1. In manual mode, sets the PGA common mode to high. Rev. A | Page 70 of 75 Data Sheet AD7606C-18 Address: 0x24, Reset: 0x00, Name: OPEN_DETECTED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] CH8_OPEN (R/W1C) Analog Input 8 Open Circuit Detected [0] CH1_OPEN (R/W1C) Analog Input 1 Open Circuit Detected [6] CH7_OPEN (R/W1C) Analog Input 7 Open Circuit Detected [1] CH2_OPEN (R/W1C) Analog Input 2 Open Circuit Detected [5] CH6_OPEN (R/W1C) Analog Input 6 Open Circuit Detected [2] CH3_OPEN (R/W1C) Analog Input 3 Open Circuit Detected [4] CH5_OPEN (R/W1C) Analog Input 5 Open Circuit Detected [3] CH4_OPEN (R/W1C) Analog Input 4 Open Circuit Detected Table 67. Bit Descriptions for OPEN_DETECTED Bits 7 6 5 4 3 2 1 0 Bit Name CH8_OPEN CH7_OPEN CH6_OPEN CH5_OPEN CH4_OPEN CH3_OPEN CH2_OPEN CH1_OPEN Description Analog Input 8 Open Circuit Detected. Analog Input 7 Open Circuit Detected. Analog Input 6 Open Circuit Detected. Analog Input 5 Open Circuit Detected. Analog Input 4 Open Circuit Detected. Analog Input 3 Open Circuit Detected. Analog Input 2 Open Circuit Detected. Analog Input 1 Open Circuit Detected. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C Address: 0x28, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH1_2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:3] CH2_DIAG_MUX_CTRL (R/W) Channel 2 Diagnostic Mux Control. Select ±10 V range. 000: Analog Input pin. 001: Temperature sensor. 010: 2.5 V reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. [2:0] CH1_DIAG_MUX_CTRL (R/W) Channel 1 Diagnostic Mux Control. Select ±10 V range. 000: Analog Input pin. 001: Temperature sensor. 010: 2.5 V reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. Table 68. Bit Descriptions for DIAGNOSTIC_MUX_CH1_2 Bits [7:6] [5:3] Bit Name RESERVED CH2_DIAG_MUX_CTRL [2:0] CH1_DIAG_MUX_CTRL Description Reserved. Channel 2 Diagnostic Mux Control. Select ±10 V range. 000: Analog input pin. 001: Temperature sensor. 010: 2.5 V reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. Channel 1 Diagnostic Mux Control. Select ±10 V range. 000: Analog input pin. 001: Temperature sensor. 010: 2.5 V reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. Rev. A | Page 71 of 75 Reset 0x0 0x0 Access R R/W 0x0 R/W AD7606C-18 Data Sheet Address: 0x29, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH3_4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [2:0] CH3_DIAG_MUX_CTRL (R/W) Channel 3 Diagnostic Mux Control. Select ±10 V range. 000: Analog Input pin. 001: Temperature sensor. 010: 2.5 V Reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. [5:3] CH4_DIAG_MUX_CTRL (R/W) Channel 4 Diagnostic Mux Control. Select ±10 V range. 000: Analog Input pin. 001: Temperature sensor. 010: 2.5 V Reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. Table 69. Bit Descriptions for DIAGNOSTIC_MUX_CH3_4 Bits [7:6] [5:3] Bit Name RESERVED CH4_DIAG_MUX_CTRL [2:0] CH3_DIAG_MUX_CTRL Description Reserved. Channel 4 Diagnostic Mux Control. Select ±10 V range. 000: Analog input pin. 001: Temperature sensor. 010: 2.5 V reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. Channel 3 Diagnostic Mux Control. Select ±10 V range. 000: Analog input pin. 001: Temperature sensor. 010: 2.5 V reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. Reset 0x0 0x0 Access R R/W 0x0 R/W Reset 0x0 0x0 Access R R/W Address: 0x2A, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH5_6 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:3] CH6_DIAG_MUX_CTRL (R/W) Channel 6 Diagnostic Mux Control. Select ±10 V range. 000: Analog Input pin. 001: Temperature sensor. 010: 2.5 V Reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. [2:0] CH5_DIAG_MUX_CTRL (R/W) Channel 5 Diagnostic Mux Control. Select ±10 V range. 000: Analog Input pin. 001: Temperature sensor. 010: 2.5 V Reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. Table 70. Bit Descriptions for DIAGNOSTIC_MUX_CH5_6 Bits [7:6] [5:3] Bit Name RESERVED CH6_DIAG_MUX_CTRL Description Reserved. Channel 6 Diagnostic Mux Control. Select ±10 V range. 000: Analog input pin. 001: Temperature sensor. 010: 2.5 V reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. Rev. A | Page 72 of 75 Data Sheet Bits Bit Name [2:0] CH5_DIAG_MUX_CTRL AD7606C-18 Description 101: VDRIVE. 110: AGND. 111: AVCC. Channel 5 Diagnostic Mux Control. Select ±10 V range. 000: Analog input pin. 001: Temperature sensor. 010: 2.5 V reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. Reset Access 0x0 R/W Reset 0x0 0x0 Access R R/W 0x0 R/W Address: 0x2B, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH7_8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:3] CH8_DIAG_MUX_CTRL (R/W) Channel 8 Diagnostic Mux Control. Select ±10 V range. 000: Analog Input pin. 001: Temperature sensor. 010: 2.5 V Reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. [2:0] CH7_DIAG_MUX_CTRL (R/W) Channel 7 Diagnostic Mux Control. Select ±10 V range. 000: Analog Input pin. 001: Temperature sensor. 010: 2.5 V Reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. Table 71. Bit Descriptions for DIAGNOSTIC_MUX_CH7_8 Bits [7:6] [5:3] Bit Name RESERVED CH8_DIAG_MUX_CTRL [2:0] CH7_DIAG_MUX_CTRL Description Reserved. Channel 8 Diagnostic Mux Control. Select ±10 V range. 000: Analog input pin. 001: Temperature sensor. 010: 2.5 V reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. Channel 7 Diagnostic Mux Control. Select ±10 V range. 000: Analog input pin. 001: Temperature sensor. 010: 2.5 V reference. 011: ALDO 1.8 V. 100: DLDO 1.8 V. 101: VDRIVE. 110: AGND. 111: AVCC. Rev. A | Page 73 of 75 AD7606C-18 Data Sheet Address: 0x2C, Reset: 0x00, Name: OPEN_DETECT_QUEUE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] OPEN_DETECT_QUEUE (R/W) Open Detect Queue. When set to 1, open detect is configured in manual mode. When set to >1, open detect operates in automatic mode and the value set in this register specifies the number of conversions when there is no change in output code before the PGA common mode is switched. Table 72. Bit Descriptions for OPEN_DETECT_QUEUE Bits [7:0] Bit Name OPEN_DETECT_QUEUE Description Open Detect Queue. When set to 1, open detect is configured in manual mode. When set to >1, open detect operates in automatic mode and the value set in this register specifies the number of conversions when there is no change in output code before the PGA common mode is switched. Reset 0x0 Access R/W Reset 0x0 Access R Reset 0x0 Access R Address: 0x2D, Reset: 0x00, Name: FS_CLK_COUNTER 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CLK_FS_COUNTER (R) A counter that is incremented at a frequency of 16 Meg/64. Reading this register verifies the operation and frequency of the FS_CLOCK. Table 73. Bit Descriptions for FS_CLK_COUNTER Bits [7:0] Bit Name CLK_FS_COUNTER Description A counter that is incremented at a frequency of 16 Meg/64. Reading this register verifies the operation and frequency of the FS_CLOCK. Address: 0x2E, Reset: 0x00, Name: OS_CLK_COUNTER 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CLK_OS_COUNTER (R) A counter that is incremented at a frequency of 12.5 Meg/64. Reading this register verifies the operation and frequency of the oversampling clock. Table 74. Bit Descriptions for OS_CLK_COUNTER Bits [7:0] Bit Name CLK_OS_COUNTER Description A counter that is incremented at a frequency of 12.5 Meg/64. Reading this register verifies the operation and frequency of the oversampling clock. Address: 0x2F, Reset: 0x31, Name: ID 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 1 [7:4] DEVICE_ID (R) Generic 0001: AD7606B generic. 0011: AD7606C-18 generic. [3:0] SILICON_REVISION (R) Silicon Revision. Table 75. Bit Descriptions for ID Bits [7:4] Bit Name DEVICE_ID [3:0] SILICON_REVISION Description Generic. 0001: AD7606B generic. 0011: AD7606C-18 generic. Silicon Revision. Rev. A | Page 74 of 75 Reset 0x3 Access R 0x1 R Data Sheet AD7606C-18 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY VIEW A ROTATED 90° CCW 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 126. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model1 AD7606C-18BSTZ AD7606C-18BSTZ-RL EVAL-AD7606C18FMCZ EVAL-SDP-CH1Z 1 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board for the AD7606C-18 Evaluation Controller Board Z = RoHS Compliant Part. ©2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D24593-4/21(A) Rev. A | Page 75 of 75 Package Option ST-64-2 ST-64-2