AD7609

Data Sheet FEATURES 8 simultaneously sampled inputs True differential inputs True bipolar analog input ranges: ±10 V, ±5 V Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 MΩ analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 18-bit ADC with 200 kSPS on all channels Oversampling capability with digital filter Flexible parallel/serial interface SPI/QSPI™/MICROWIRE™/DSP compatible Performance 7 kV ESD rating on analog input channels 98 dB SNR, −107 dB THD Dynamic range: up to 105 dB typical Low power: 100 mW Standby mode: 25 mW 64-lead LQFP package 8-Channel Differential DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC AD7609 APPLICATIONS Power line monitoring and protection systems Multiphase motor control Instrumentation and control systems Multiaxis positioning systems Data acquisition systems (DAS) COMPANION PRODUCTS External References: ADR421, ADR431 Digital Isolators: ADuM1402, ADuM5000, ADuM5402 Power: ADIsimPower, Supervisor Parametric Search Additional companion products on the AD7609 product page Table 1. High Resolution, Bipolar Input, Simultaneous Sampling DAS Solutions Resolution 18 Bits 16 Bits SingleEnded Inputs AD7608 AD7606 AD7606-6 AD7606-4 AD7607 True Differential Inputs AD7609 1 Number of Simultaneous Sampling Channels 8 8 6 4 8 14 Bits 1 Patent pending. FUNCTIONAL BLOCK DIAGRAM AVCC AVCC REGCAP REGCAP REFCAPB REFCAPA V1+ V1– CLAMP CLAMP 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF T/H 2.5V LDO 2.5V LDO REFIN/REFOUT V2+ V2– CLAMP CLAMP T/H 2.5V REF REF SELECT AGND OS 2 OS 1 OS 0 V3+ V3– CLAMP CLAMP T/H V4+ V4– CLAMP CLAMP T/H 8:1 MUX T/H SERIAL 18-BIT SAR DIGITAL FILTER PARALLEL/ SERIAL INTERFACE DOUTA DOUTB RD/SCLK CS PAR/SER SEL VDRIVE V5+ V5– CLAMP CLAMP V6+ V6– CLAMP CLAMP T/H PARALLEL DB[15:0] V7+ V7– AD7609 T/H CLK OSC CONTROL INPUTS BUSY FRSTDATA 09760-001 CLAMP CLAMP V8+ V8– CLAMP CLAMP T/H AGND CONVST A CONVST B RESET RANGE Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. AD7609 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Companion Products ....................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Timing Specifications .................................................................. 7 Absolute Maximum Ratings.......................................................... 11 Thermal Resistance .................................................................... 11 ESD Caution ................................................................................ 11 Pin Configuration and Function Descriptions ........................... 12 Typical Performance Characteristics ........................................... 15 Terminology .................................................................................... 19 Theory of Operation ...................................................................... 21 Data Sheet Converter Details ....................................................................... 21 Analog Input ............................................................................... 21 ADC Transfer Function ............................................................. 22 Internal/External Reference ...................................................... 23 Typical Connection Diagram ................................................... 24 Power-Down Modes .................................................................. 24 Conversion Control ................................................................... 25 Digital Interface .............................................................................. 26 Parallel Interface (PAR/SER SEL = 0) ...................................... 26 Serial Interface (PAR/SER SEL = 1) ......................................... 26 Reading During Conversion ..................................................... 27 Digital Filter ................................................................................ 28 Layout Guidelines....................................................................... 32 Outline Dimensions ....................................................................... 34 Ordering Guide .......................................................................... 34 REVISION HISTORY 2/12—Rev. 0 to Rev. A Changes to Analog Input Ranges Section ....................................21 7/11—Revision 0: Initial Version Rev. A | Page 2 of 36 Data Sheet GENERAL DESCRIPTION The AD7609 is an 18-bit, 8-channel, true differential, simultaneous sampling analog-to-digital data acquisition system (DAS). The part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, an 18-bit charge redistribution successive approximation analogto-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. AD7609 The AD7609 operates from a single 5 V supply and can accommodate ±10 V and ±5 V true bipolar differential input signals while sampling at throughput rates up to 200 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to ±16.5 V. The AD7609 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The AD7609 antialiasing filter has a −3 dB cutoff frequency of 32 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the −3 dB bandwidth. Rev. A | Page 3 of 36 AD7609 SPECIFICATIONS Data Sheet VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V; fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 2, 3 Test Conditions/Comments fIN = 1 kHz sine wave unless otherwise noted Oversampling by 16; ±10 V range; fIN = 160 Hz Oversampling by 16; ±5 V range; fIN = 160 Hz No oversampling; ±10 V range No oversampling; ±5 V range No oversampling; ±10 V range No oversampling; ±5 V range No oversampling; ±10 V range No oversampling; ±5 V range No oversampling; ±10 V range No oversampling; ±5 V range fa = 1 kHz, fb = 1.1 kHz −110 −106 −95 32 23 13 10 7.1 10.2 18 ±0.75 ±3 ±10 ±90 ±8 ±40 ±2 ±7 12 40 ±3 ±3 10 5 2.7 13 ±8 ±40 ±4 ±8 12 40 −0.99/+2 ±7.5 dB dB dB kHz kHz kHz kHz µs µs Bits LSB 4 LSB LSB LSB LSB LSB ppm/°C ppm/°C LSB LSB LSB LSB µV/°C µV/°C LSB LSB LSB LSB ppm/°C ppm/°C LSB LSB Min 98 90 89.5 89.5 89 Typ 101 100 91 90.5 91 90 91.5 90.5 −107 −110 −108 Max Unit dB dB dB dB dB dB dB dB dB dB dB Signal-to-(Noise + Distortion) (SINAD)2 Dynamic Range Total Harmonic Distortion (THD)2, 3 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation2 ANALOG INPUT FILTER Full Power Bandwidth −97 −96 fIN on unselected channels up to 160 kHz −3 dB, ±10 V range −3 dB, ±5 V range −0.1 dB, ±10 V range −0.1 dB, ±5 V range ±10 V range ±5 V range No missing codes tGROUP DELAY DC ACCURACY Resolution Differential Nonlinearity2 Integral Nonlinearity2 Total Unadjusted Error (TUE) Positive Full-Scale Error2, 5 Positive Full-Scale Error Drift Positive Full-Scale Error Matching2 Bipolar Zero Code Error2, 6 Bipolar Zero Code Error Drift Bipolar Zero Code Error Matching2 Negative Full-Scale Error2, 5 Negative Full-Scale Error Drift Negative Full-Scale Error Matching2 ±10 V range ±5 V range External reference Internal reference External reference Internal reference ±10 V range ±5 V range ±10 V range ± 5 V range ±10 V range ± 5 V range ±10 V range ±5 V range External reference Internal reference External reference Internal reference ±10 V range ±5 V range Rev. A | Page 4 of 36 ±140 80 100 ±24 ±48 30 65 ±140 80 100 Data Sheet Parameter ANALOG INPUT Differential Input Voltage Ranges Test Conditions/Comments VIN = Vx+ − (Vx−) RANGE = 1; ±10 V RANGE = 0; ±5 V ±10 V range, see the Analog Input Clamp Protection section ±5 V range, see the Analog Input Clamp Protection section Min Typ Max AD7609 Unit Absolute Voltage Input −20 −10 −10 −5 −4 ±5 −70 5.4 2.5 5 1 2.5 7.5 2.49/ 2.505 ±10 0.7 × VDRIVE +20 +10 +10 +5 +4 V V V V V dB µA µA pF MΩ V µA pF V ppm/°C V V µA pF V V µA pF Common-Mode Input Range CMRR Analog Input Current Input Capacitance 7 Input Impedance REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance7 Reference Output Voltage Reference Temperature Coefficient LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)7 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance7 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVCC VDRIVE ITOTAL Normal Mode (Static) Normal Mode (Operational)8 Standby Mode Shutdown Mode 10 V, see Figure 28 5 V, see Figure 28 2.475 REF SELECT = 1 REFIN/REFOUT 2.525 ±1 0.3 × VDRIVE ±2 5 ISOURCE = 100 µA ISINK = 100 µA VDRIVE − 0.2 ±1 5 Twos complement All eight channels included Per channel, all eight channels included 4.75 2.3 Digital inputs = 0 V or VDRIVE fSAMPLE = 200 kSPS 16 20 5 2 22 28.5 8 11 4 1 200 5.25 5.25 0.2 ±20 µs µs kSPS V V mA mA mA µA Rev. A | Page 5 of 36 AD7609 Parameter Power Dissipation Normal Mode (Static) Normal Mode (Operational) 8 Standby Mode Shutdown Mode 1 2 3 Data Sheet Test Conditions/Comments Min Typ 80 100 25 10 Max 115.5 157 42 60.5 Unit mW mW mW µW fSAMPLE = 200 kSPS Temperature range for B version is −40°C to +85°C. See the Terminology section. This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel and serial modes with VDRIVE = 5 V, SNR typically reduces by 1.5 dB and THD by 3 dB. 4 LSB means least significant bit. With ±5 V input range, 1 LSB = 76.29 µV. With ±10 V input range, 1 LSB = 152.58 µV. 5 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 6 Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section. 7 Sample tested during initial release to ensure compliance. 8 Operational power/current figure includes contribution when running in oversampling mode. Rev. A | Page 6 of 36 Data Sheet TIMING SPECIFICATIONS AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/ internal reference, TA = TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter PARALLEL/SERIAL/BYTE MODE tCYCLE Limit at TMIN, TMAX Min Typ Max Unit Description AD7609 5 5 10.1 11.5 tCONV 3.45 7.87 16.05 33 66 133 257 tWAKE-UP STANDBY tWAKE-UP SHUTDOWN Internal Reference External Reference tRESET tOS_SETUP tOS_HOLD t1 t2 t3 t4 t5 2 t6 t7 PARALLEL READ OPERATION t8 t9 t10 50 20 20 45 25 25 0 0.5 25 25 0 0 19 24 30 37 15 22 4 4.15 9.1 18.8 39 78 158 315 100 30 13 µs µs µs µs µs µs µs µs µs µs µs µs ms ms ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns 1/throughput rate Parallel mode, reading during; or after conversion VDRIVE = 2.7 V to 5.25 V; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines Parallel mode reading after conversion VDRIVE = 2.3 V Serial mode reading after conversion; VDRIVE = 2.7 V, DOUTA and DOUTB lines Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines Conversion time Oversampling off Oversampling by 2 Oversampling by 4 Oversampling by 8 Oversampling by 16 Oversampling by 32 Oversampling by 64 STBY rising edge to CONVST x rising edge; power-up time from standby mode STBY rising edge to CONVST x rising edge; power-up time from shutdown mode STBY rising edge to CONVST x rising edge; power-up time from shutdown mode RESET high pulse width BUSY to OS x pin setup time BUSY to OS x pin hold time CONVST x high to BUSY high Minimum CONVST x low pulse Minimum CONVST x high pulse BUSY falling edge to CS falling edge setup time Maximum delay allowed between CONVST A, CONVST B rising edges Maximum time between last CS rising edge and BUSY falling edge Minimum delay between RESET low to CONVST x high CS to RD setup time CS to RD hold time RD low pulse width VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V RD high pulse width CS high pulse width (see Figure 5); CS and RD linked t11 t12 Rev. A | Page 7 of 36 AD7609 Parameter t13 Limit at TMIN, TMAX Min Typ Max 19 24 30 37 t143 19 24 30 37 t15 t16 t17 SERIAL READ OPERATION fSCLK 20 15 12.5 10 t18 18 23 35 t19 3 20 26 32 39 t20 t21 t22 t23 FRSTDATA OPERATION t24 18 23 30 35 t25 18 23 30 35 t26 19 23 30 35 ns ns ns ns ns ns ns ns ns ns ns ns ns 0.4 tSCLK 0.4 tSCLK 7 22 ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz 6 6 22 ns ns ns ns ns ns ns Unit ns ns ns ns Data Sheet Description Delay from CS until DB[15:0] three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data access time after RD falling edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data hold time after RD falling edge CS to DB[15:0] hold time Delay from CS rising edge to DB[15:0] three-state enabled Frequency of serial read clock VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE = 2.3 V to 2.7 V Data access time after SCLK rising edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V SCLK low pulse width SCLK high pulse width SCLK rising edge to DOUTA/DOUTB valid hold time CS rising edge to DOUTA/DOUTB three-state enabled Delay from CS falling edge until FRSTDATA three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS falling edge until FRSTDATA high, serial mode VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from RD falling edge to FRSTDATA high VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Rev. A | Page 8 of 36 Data Sheet Parameter t27 Limit at TMIN, TMAX Min Typ Max 22 29 t28 20 27 29 ns ns ns Unit ns ns Description Delay from RD falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25 V VDRIVE = 2.3 V to 2.7 V Delay from 18th SCLK falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25 V VDRIVE = 2.3 V to 2.7 V Delay from CS rising edge until FRSTDATA three-state enabled AD7609 t29 1 2 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (30% to 70% of VDD) and timed from a voltage level of 1.6 V. The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a 3.3 V, the SNR is reduced by ~1.5 dB when reading during a conversion. ATTENUATION (dB) –15 –20 –25 –30 –35 –40 100 TEMP –40°C 25°C 85°C –40°C 5V 25°C 85°C 0.1dB 13,354Hz 12,769Hz 12,427Hz 10,303Hz 9619Hz 9326Hz 3dB 33,520Hz 32,397Hz 31,177Hz 24,365Hz 23,389Hz 22,607Hz ADC TRANSFER FUNCTION The output coding of the AD7609 is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is FSR/262,144 for the AD7609. The FSR for the AD7609 is 40 V for the ±10 V range and 20 V for the ±5 V range. The ideal transfer characteristic for the AD7609 is shown in Figure 37. ±10V CODE = V+ ± (V–) × 131,072 × 10V V+ ± (V–) ±5V CODE = × 131,072 × 5V REF 2.5V REF 2.5V 10V 1k 10k FREQUENCY (Hz) 100k Figure 35. Analog Antialiasing Filter Frequency Response 14 13 12 11 09760-032 011...111 011...110 ADC CODE PHASE DELAY (µs) 10 9 8 7 6 5 4 3 2 1 0 10 ±5V RANGE 000...001 000...000 111...111 100...010 100...001 100...000 –FS + 1/2LSB LSB = +FSR – (–FSR) 218 ±10V RANGE 0V – 1LSB +FS – 3/2LSB ANALOG INPUT AVCC, VDRIVE = 5V fSAMPLE = 200kSPS TA = 25°C 1k 10k 100k 09760-133 Figure 37. AD7609 Transfer Characteristic The LSB size is dependent on the analog input range selected (see Table 7). Table 7. Output Codes and Ideal Input Values Analog Input (V+ − (V−) 10 V Range +19.99992 V +152.58 µV 0V −152.58 µV −19.99984 V −20 V Analog Input V+ − (V−) 5 V Range 9.999961 V 76 µV 0V −76 µV −9.99992 V −10 V Digital Output Code (Hex) 0x1FFFF 0x00001 0x00000 0x3FFFF 0x20001 0x20000 INPUT FREQUENCY (Hz) Figure 36. Analog Antialiasing Filter Phase Response Track-and-Hold Amplifiers The track-and-hold amplifiers on the AD7609 allow the ADC to accurately acquire an input sine wave of full-scale amplitude to 18-bit resolution. The track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of CONVST x. The aperture time for track-and-hold (that is, the delay time between the external CONVST x signal and the track-and-hold actually going into hold) is well matched, by design, across all eight track-and-holds on one device and from device to device. This matching allows more than one AD7609 device to be sampled simultaneously in a system. The end of the conversion process across all eight channels is indicated by the falling edge of BUSY; and it is at this point that the track-and-holds return to track mode and the acquisition time for the next set of conversions begins. Rev. A | Page 22 of 36 Description FSR − 0.5 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB −FSR + 1 LSB −FSR 09760-034 Data Sheet INTERNAL/EXTERNAL REFERENCE The AD7609 contains an on-chip 2.5 V band gap reference. The REFIN/REFOUT pin allows access to the 2.5 V reference that generates the on-chip 4.5 V reference internally, or it allows an external reference of 2.5 V to be applied to the AD7609. An externally applied reference of 2.5 V is also amplified to 4.5 V using the internal buffer. This 4.5 V buffered reference is the reference used by the SAR ADC. The REF SELECT pin is a logic input pin that allows the user to select between the internal reference and the external reference. If this pin is set to logic high, the internal reference is selected and is enabled; if this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. The internal reference buffer is always enabled. After a reset, the AD7609 operates in the reference mode selected by the REF SELECT pin. Decoupling is required on the REFIN/REFOUT pin for both the internal or external reference options. A 10 µF ceramic capacitor is required on the REFIN/REFOUT to ground close to the REFGND pins. The AD7609 contains a reference buffer configured to amplify the REF voltage up to ~4.5 V, as shown in Figure 38. The REFCAPA and REFCAPB pins must be shorted together externally and a ceramic capacitor of 10 μF applied to REFGND to ensure the reference buffer is in closed-loop operation. The reference voltage available at the REFIN/REFOUT pin is 2.5 V. When the AD7609 is configured in external reference mode, the REFIN/REFOUT pin is a high input impedance pin. For applications using multiple AD7609 devices, the following configurations are recommended depending on the application requirements. REFIN/REFOUT SAR BUF REFCAPB 10µF REFCAPA 2.5V REF AD7609 Figure 38. Reference Circuitry VDRIVE AD7609 REF SELECT REFIN/REFOUT AD7609 REF SELECT REFIN/REFOUT AD7609 REF SELECT REFIN/REFOUT + Figure 39. Single External Reference Driving Multiple AD7609 REFIN/REFOUT Pins AD7609 REF SELECT REFIN/REFOUT AD7609 REF SELECT REFIN/REFOUT AD7609 REF SELECT REFIN/REFOUT 100nF 100nF 100nF 0.1µF Figure 40. Internal Reference Driving Multiple AD7609 REFIN Pins External Reference Mode One ADR421 external reference can be used to drive the REFIN/REFOUT pins of all AD7609 devices (see Figure 39). In this configuration, each AD7609 REFIN/REFOUT pin should be decoupled with a 100 nF decoupling capacitor. Internal Reference Mode One AD7609 device, configured to operate in the internal reference mode, can be used to drive the remaining AD7609 devices, which are configured to operate in external reference mode (see Figure 40). The REFIN/REFOUT pin of the AD7609, configured in internal reference mode, should be decoupled using a 10 µF ceramic decoupling capacitor. The other AD7609 devices, configured in external reference mode, should use a 100 nF decoupling capacitor on their REFIN/REFOUT pins. Rev. A | Page 23 of 36 09760-037 ADR421 09760-036 10µF 100nF 09760-035 100nF AD7609 TYPICAL CONNECTION DIAGRAM Figure 41 shows the typical connection diagram for the AD7609. There are four AVCC supply pins on the part that can be tied together and decoupled using a 100 nF capacitor at each supply pin and a 10 µF capacitor at the supply source. The AD7609 can operate with the internal reference or an externally applied reference. In this configuration, the AD7609 is configured to operate with the internal reference. When using a single AD7609 device on the board, the REFIN/REFOUT pin should be decoupled with a 10 µF capacitor. In an application with multiple AD7609 devices, see the Internal/External Reference section. The REFCAPA and REFCAPB pins are shorted together and decoupled with a 10 µF ceramic capacitor. The VDRIVE supply is connected to the same supply as the processor. The voltage on VDRIVE controls the voltage value of the output logic signals. For layout, decoupling, and grounding hints, see the Layout Guidelines section. After supplies are applied to the AD7609, a reset should be applied to the AD7609 to ensure that it is configured for the correct mode of operation. Data Sheet POWER-DOWN MODES There are two power-down modes available on the AD7609. The STBY pin controls whether the AD7609 is in normal mode or one of the two power-down modes. The two power-down modes available are standby mode and shutdown mode. The power-down mode is selected through the state of the RANGE pin when the STBY pin is low. Table 8 shows the configurations required to choose the desired power-down mode. When the AD7609 is placed in standby mode, the current consumption is 8 mA maximum and power-up time is approximately 100 µs because the capacitor on the REFCAPA/REFCAPB pins must charge up. In standby mode, the on-chip reference and regulators remain powered up and the amplifiers and ADC core are powered down. When the AD7609 is placed in shutdown mode, the current consumption is 11 µA maximum and power up time is about 13 ms. In shutdown mode, all circuitry is powered down. When the AD7609 is powered up from shutdown mode, a reset signal must be applied to the AD7609 after the required power-up time has elapsed. Table 8. Power-Down Mode Selection Power-Down Mode Standby Shutdown STBY 0 0 RANGE 1 0 ANALOG SUPPLY VOLTAGE 5V1 + DIGITAL SUPPLY VOLTAGE +2.3V TO +5V 10µF 1µF 100nF 100nF REFCAPA 10µF + REFCAPB REFGND V1+ V1– V2+ V2– V3+ V3– V4+ V4– V5+ V5– V6+ V6– V7+ V7– V8+ V8– CONVST A, B CS RD BUSY RESET OS 2 OS 1 OS 0 REF SELECT PAR/SER SEL RANGE STBY DB0 TO DB15 PARALLEL INTERFACE AD7609 OVERSAMPLING VDRIVE EIGHT DIFFERENTIAL ANALOG INPUT PAIRS VDRIVE AGND Figure 41. Typical Connection Diagram Rev. A | Page 24 of 36 09760-038 1DECOUPLING SHOWN ON THE AV CC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48). DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV CC PIN 37 AND PIN 38. 2DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). MICROPROCESSOR/ MICROCONVERTER/ DSP REFIN/REFOUT REGCAP2 AVCC VDRIVE Data Sheet CONVERSION CONTROL Simultaneous Sampling on All Analog Input Channels The AD7609 allows simultaneous sampling of all analog input channels. All channels are sampled simultaneously when both CONVST x pins (CONVST A, CONVST B) are tied together. A single CONVST x signal is used to control both CONVST x inputs. The rising edge of this common CONVST x signal initiates simultaneous sampling on all analog input channels. The AD7609 contains an on-chip oscillator that is used to perform the conversions. The conversion time for all ADC channels is tCONV. The BUSY signal indicates to the user when conversions are in progress, so that when the rising edge of CONVST x is applied, BUSY goes logic high and transitions low at the end of the entire conversion process. The falling edge of the BUSY signal is used to place all eight track-and-hold amplifiers back into track mode. The falling edge of BUSY also indicates that the new data can now be read from the parallel bus (DB[15:0]) or the serial data lines, DOUTA and DOUTB. AD7609 Simultaneously Sampling Two Sets of Channels The AD7609 also allows the analog input channels to be sampled simultaneously in two sets. This can be used in power line protection and measurement systems to compensate for phase differences between PT and CT transformers. In a 50 Hz system, this allows for up to 9° of phase compensation, and in a 60 Hz system, it allows for up to 10° of phase compensation. This is accomplished by pulsing the two CONVST x pins independently and is only possible if oversampling is not in use. CONVST A is used to initiate simultaneous sampling of the first set of channels (V1 to V4). CONVST B is used to initiate simultaneous sampling on the second set of analog input channels (V5 to V8), as illustrated in Figure 42. On the rising edge of CONVST A, the track-and-hold amplifiers for the first set of channels are placed into hold mode. On the rising edge of CONVST B, the track-and-hold amplifiers for the second set of channels are placed into hold mode. The conversion process begins after both rising edges of CONVST x have occurred; therefore, BUSY goes high on the rising edge of the later CONVST x signal. The falling edge of BUSY also indicates that the new data can now be read from the parallel bus or the serial data lines, DOUTA and DOUTB. There is no change to the data read process when using two separate CONVST x signals. Connect all unused analog input channel to AGND. The results for any unused channels are still included in the data read because all channels are always converted. V1 TO V4 TRACK-AND-HOLD ENTER HOLD V5 TO V8 TRACK-AND-HOLD ENTER HOLD CONVST A CONVST B BUSY t5 AD7609 CONVERTS ON ALL 8 CHANNELS tCONV CS, RD DATA: DB[15:0] V1 V2 V8 FRSTDATA Figure 42. Simultaneous Sampling on Channel Sets Using Independent CONVST A/CONVST B Signals—Parallel Mode Rev. A | Page 25 of 36 09760-039 AD7609 DIGITAL INTERFACE The AD7609 provides two interface options: a parallel interface and a high speed serial interface. The required interface mode is selected via the PAR/SER SEL pin. The operation of the interface modes is described in the following sections. AD7609 BUSY 14 CS 13 INTERRUPT RD 12 DB[15:0] 33:16 DIGITAL HOST Data Sheet PARALLEL INTERFACE (PAR/SER SEL = 0) Data can be read from the AD7609 via the parallel data bus with standard CS and RD signals. To read the data over the parallel bus, the PAR/SER SEL pin should be tied low. The CS and RD input signals are internally gated to enable the conversion result onto the data bus. The data lines, DB15 to DB0, leave their high impedance state when both CS and RD are logic low. The rising edge of the CS input signal three-states the bus and the falling edge of the CS input signal takes the bus out of the high impedance state. CS is the control signal that enables the data lines; it is the function that allows multiple AD7609 devices to share the same parallel data bus. The CS signal can be permanently tied low, and the RD signal can be used to access the conversion results, as shown in Figure 4. A read operation of new data can take place after the BUSY signal goes low (Figure 2), or, alternatively, a read operation of data from the previous conversion process can take place while BUSY is high (Figure 3). The RD pin is used to read data from the output conversion results register. Two RD pulses are required to read the full 18-bit conversion result from each channel. Applying a sequence of 16 RD pulses to the AD7609 RD pin clocks the conversion results out from each channel onto the parallel output bus, DB[15:0], in ascending order. The first RD falling edge after BUSY goes low clocks out DB[17:2] of the V1 result, the next RD falling edge updates the bus with DB[1:0] of the V1 result. It takes 16 RD pulses to read the eight 18-bit conversion results from the AD7609. The 16th falling edge of RD clocks out the DB[1:0] conversion result for Channel V8. When the RD signal is logic low, it enables the data conversion result from each channel to be transferred to the digital host (DSP, FPGA). When there is only one AD7609 in a system/board and it does not share the parallel bus, data can be read using only one control signal from the digital host. The CS and RD signals can be tied together, as shown in Figure 5. In this case, the data bus comes out of three-state on the falling edge of CS/RD. The combined CS and RD signal allows the data to be clocked out of the AD7609 and to be read by the digital host. In this case, CS is used to frame the data transfer of each data channel and 16 CS pulses are required to read the eight channels of data. Figure 43. AD7609 Interface Diagram: One AD7609 Using the Parallel Bus; CS and RD Shorted Together SERIAL INTERFACE (PAR/SER SEL = 1) To read data back from the AD7609 over the serial interface, the PAR/SER SEL pin should be tied high. The CS and SCLK signals are used to transfer data from the AD7609. The AD7609 has two serial data output pins, DOUTA and DOUTB. Data can be read back from the AD7609 using one or both of these DOUT lines. For the AD7609, conversion results from Channel V1 to Channel V4 first appear on DOUTA, whereas conversion results from Channel V5 to Channel V8 first appear on DOUTB. The CS falling edge takes the data output lines (DOUTA and DOUTB) out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data outputs, DOUTA and DOUTB. The CS input can be held low for the entire serial read or it can be pulsed to frame each channel read of 18 SCLK cycles. Figure 44 shows a read of eight simultaneous conversion results using two DOUT lines on the AD7609. In this case, a 72 SCLK transfer is used to access data from the AD7609 and CS is held low to frame the entire 72 SCLK cycles. Data can also be clocked out using only one DOUT line, in which case DOUTA is recommended to access all conversion data, because the channel data is output in ascending order. For the AD7609 to access all eight conversion results on one DOUT line, a total of 144 SCLK cycles are required. These 144 SCLK cycles can be framed by one CS signal or each group of 18 SCLK cycles can be individually framed by the CS signal. The disadvantage of using only one DOUT line is that the throughput rate is reduced if reading after conversion. The unused DOUT line should be left unconnected in serial mode. For the AD7609, if DOUTB is to be used as a single DOUT line, the channel results are output in the following order: V5, V6, V7, V8, V1, V2, V3, V4; however, the FRSTDATA indicator returns low after V5 is read on DOUTB. Rev. A | Page 26 of 36 09760-040 Data Sheet Figure 6 shows the timing diagram for reading one channel of data, framed by the CS signal, from the AD7609 in serial mode. The SCLK input signal provides the clock source for the serial read operation. CS goes low to access the data from the AD7609. The falling edge of CS takes the bus out of three-state and clocks out the MSB of the 18-bit conversion result. This MSB is valid on the first falling edge of the SCLK after the CS falling edge. The subsequent 17 data bits are clocked out of the AD7609 on the SCLK rising edge. Data is valid on the SCLK falling edge. Eighteen clock cycles must be provided to the AD7609 to access each conversion result. The FRSTDATA output signal indicates when the first channel, V1, is being read back. When the CS input is high, the FRSTDATA output pin is in three-state. In serial mode, the falling edge of CS takes FRSTDATA out of three-state and sets the FRSTDATA pin high indicating that the result from V1 is available on the DOUTA output data line. The FRSTDATA output returns to a logic low following the 18th SCLK falling edge. If all channels AD7609 are read on DOUTB, the FRSTDATA output does not go high when V1 is being output on this serial data output pin. It only goes high when V1 is available on DOUTA (and this is when V5 is available on DOUTB). READING DURING CONVERSION Data can be read from the AD7609 while BUSY is high and conversions are in progress. This has little effect on the performance of the converter and allows a faster throughput rate to be achieved. A parallel or serial read can be performed during conversions and when oversampling may or may not be in use. Figure 3 shows the timing diagram for reading while BUSY is high in parallel or serial mode. Reading during conversions allows the full throughput rate to be achieved when using the serial interface with a VDRIVE of 3.3 V to 5.25 V. Data can be read from the AD7609 at any time other than on the falling edge of BUSY because this is when the output data registers are updated with the new conversion data. t6, outlined in Table 3, should be observed in this condition. CS 72 SCLK DOUTA DOUTB V1 V2 V3 V4 09760-041 V5 V6 V7 V8 Figure 44. AD7609 Serial Interface with Two DOUT Lines Rev. A | Page 27 of 36 AD7609 DIGITAL FILTER The AD7609 contains an optional digital filter. This digital filter is a first-order sinc filter. This digital filter should be used in applications where slower throughput rates are used or where higher signal-to-noise ratio or dynamic range is desirable. The oversampling ratio of the digital filter is controlled using the oversampling pins, OS [2:0] (see Table 9). OS 2 is the MSB control bit and OS 0 is the LSB control bit. Table 9 provides the oversampling bit decoding to select the different oversample rates. The OS pins are latched on the falling edge of BUSY. This sets the oversampling rate for the next conversion (see Figure 45). In addition to the oversampling function, the output result is decimated to 18-bit resolution. If the OS pins are set to select an OS ratio of 8, the next CONVST x rising edge takes the first sample for each channel and the remaining seven samples for all channels are taken with an internally generated sampling signal. These samples are then averaged to yield an improvement in SNR performance. Table 9 shows typical SNR performance for both the ±10 V and the ±5 V ranges. As Table 9 indicates, there is an improvement in SNR as the OS ratio increases. As the OS ratio increases, the 3 dB frequency is reduced and the allowed sampling frequency is also reduced. In an application where the required sampling frequency is 10 kSPS, an OS ratio of up to 16 can be used. In this case, the application sees an improvement in SNR but the input −3 dB bandwidth is limited to ~6 kHz. CONVST A, CONVST B OVERSAMPLE RATE LATCHED FOR CONVERSION N + 1 Data Sheet The CONVST A and CONVST B pins must be tied/driven together when oversampling is turned on. When the oversampling function is turned on, the BUSY high time for the conversion process extends. The actual BUSY high time depends on the oversampling rate selected; the higher the oversampling rate, the longer the BUSY high, or total conversion time, see Table 9. Figure 46 shows that the conversion time extends as the oversampling rate is increased, and the BUSY signal lengthens for the different oversampling rates. For example, a sampling frequency of 10 kSPS yields a cycle time of 100 µs. Figure 46 shows OS × 2 and OS × 4; for a 10 kSPS example, there is adequate cycle time to further increase the oversampling rate and yield greater improvements in SNR performance. In an application where the initial sampling or throughput rate is at 200 kSPS, for example, and oversampling is turned on, the throughput rate must be reduced to accommodate the longer conversion time and to allow for the read. To achieve the fastest throughput rate possible when oversampling is turned on, the read can be performed during the BUSY high time. The falling edge of BUSY is used to update the output data registers with the new conversion data; therefore, the reading of conversion data should not occur on this edge. Figure 47 to Figure 53 illustrate the effect of oversampling on the code spread in a dc histogram plot. As the oversample rate is increased, the spread of codes is reduced. (In Figure 47 to Figure 53, AVCC = VDRIVE = 5 V and the sampling rate was scaled with OS ratio.) CONVERSION N BUSY CONVERSION N + 1 tOS_HOLD OS x 09760-042 tOS_SETUP Figure 45. OS Pin Timing Table 9. Oversampling Bit Decoding (100 Hz Input Signal) OS [2:0] 000 001 010 011 100 101 110 111 OS Ratio No OS 2 4 8 16 32 64 Invalid SNR ±5 V Range (dB) 90.8 93.3 95.5 98 100.6 101.8 102.7 SNR ±10 V Range (dB) 91.5 93.9 96.4 98.9 101 102 102.9 −3 dB BW 5 V Range (kHz) 22 22 18.5 11.9 6 3 1.5 −3 dB BW 10 V Range (kHz) 33 28.9 21.5 12 6 3 1.5 Maximum Throughput CONVST x Frequency (kHz) 200 100 50 25 12.5 6.25 3.125 Rev. A | Page 28 of 36 Data Sheet tCYCLE CONVST A, CONVST B AD7609 tCONV 19µs 9µs 4µs BUSY OS = 0 OS = 2 OS = 4 t4 CS t4 t4 RD 09760-043 DATA: DB[15:0] Figure 46. AD7609—No Oversampling, Oversampling × 4, and Oversampling × 8 Using Read After Conversion 1600 NO OVERSAMPLING 1400 1384 1373 3000 OVERSAMPLING BY 4 2500 1167 1062 2363 2394 NUMBER OF OCCURRENCES 1200 1000 NUMBER OF OCCURRENCES 2000 840 800 600 450 727 1500 1191 1000 1340 492 400 210 219 100 32 11 2 09760-044 500 5 –5 49 –4 200 83 341 422 79 8 4 09760-046 09760-047 0 2 10 27 1 0 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 CODE 2 3 4 5 6 7 89 –3 –2 –1 0 CODE 1 2 3 Figure 47. Histogram of Codes—No OS (19 Codes) 2000 1800 1785 1772 Figure 49. Histogram of Codes—OS × 4 (10 Codes) 4000 OVERSAMPLING BY 8 3500 3392 OVERSAMPLING BY 2 NUMBER OF OCCURRENCES NUMBER OF OCCURRENCES 1600 1400 1200 1000 800 600 400 214 599 788 1146 1389 3000 2500 2000 1568 2397 1500 1000 500 549 229 1 41 15 317 105 15 09760-045 200 0 1 12 46 2 1 0 –7 –6 –5 –4 –3 –2 –1 01 CODE 2 3 4 5 6 7 –4 –3 –2 –1 CODE 0 1 2 3 Figure 48. Histogram Of Codes—OS × 2 (15 Codes) Figure 50. Histogram of Codes—OS × 8 (Eight Codes) Rev. A | Page 29 of 36 AD7609 4500 OVERSAMPLING BY 16 4000 3833 3279 Data Sheet When the oversampling mode is selected, this has the effect of adding a digital filter function after the ADC. The different oversampling rates and the CONVST x sampling frequency produces different digital filter frequency profiles. Figure 54 to Figure 59 show the digital filter frequency profiles for the different oversampling rates. The combination of the analog antialiasing filter and the oversampling digital filter can be used to eliminate or reduce the complexity of the design of the filter before the AD7609. The digital filtering combines steep roll-off and linear phase response. 0 14 09760-048 NUMBER OF OCCURENCES 3500 3000 2500 2000 1500 1000 500 0 3 –3 –2 406 657 385 –1 CODE 0 1 2 –10 –20 ATTENUATION (dB) Figure 51. Histogram of Codes—OS × 16 (Six Codes) 6000 OVERSAMPLING BY 32 5090 5000 AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 2 –30 –40 –50 –60 –70 NUMBER OF OCCURENCES 4000 3000 2716 –80 09760-051 09760-052 2000 –90 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 1000 341 45 09760-049 Figure 54. Digital Filter Response for OS × 2 0 –10 –20 AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 4 0 –2 –1 CODE 0 1 Figure 52. Histogram of Codes—OS × 32 (Four Codes) 7000 OVERSAMPLING BY 64 6000 5871 ATTENUATION (dB) –30 –40 –50 –60 –70 –80 –90 NUMBER OF OCCURENCES 5000 4000 3000 2245 2000 1000 1 0 –2 –1 CODE 0 1 75 09760-050 –100 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 55. Digital Filter Response for OS × 4 Figure 53. Histogram of Codes – OS × 64 (Four Codes) Rev. A | Page 30 of 36 Data Sheet 0 –10 –20 AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 8 0 –10 –20 AD7609 AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 32 ATTENUATION (dB) –40 –50 –60 –70 –80 –90 09760-053 ATTENUATION (dB) –30 –30 –40 –50 –60 –70 –80 –90 09760-055 09760-056 –100 100 1k 10k 100k 1M 10M –100 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 56. Digital Filter Response for OS × 8 0 –10 –20 0 –10 –20 Figure 58. Digital Filter Response for OS × 32 AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 16 AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 64 ATTENUATION (dB) –40 –50 –60 –70 –80 –90 09760-054 ATTENUATION (dB) 1k 10k 100k 1M 10M –30 –30 –40 –50 –60 –70 –80 –90 –100 100 –100 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 57. Digital Filter Response for OS × 16 Figure 59. Digital Filter Response for OS × 64 Rev. A | Page 31 of 36 AD7609 LAYOUT GUIDELINES The printed circuit board that houses the AD7609 should be designed so that the analog and digital sections are separated and confined to different areas of the board. Use at least one ground plane. It can be common or split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably as close as possible to the AD7609. If the AD7609 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point, a star ground point, which should be established as close as possible to the AD7609. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Individual vias or multiple vias to the ground plane should be used for each ground pin. Avoid running digital lines under the devices because doing so couples noise onto the die. Allow the analog ground plane to run under the AD7609 to avoid noise coupling. Shield fastswitching signals like CONVST A, CONVST B, or clocks with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Avoid crossover of digital and analog signals. Run traces on layers in close proximity on the board at right angles to each other to reduce the effect of feedthrough through the board. The power supply lines to the AVCC and VDRIVE pins on the AD7609 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Where possible, use supply planes. Good connections should be made between the AD7609 supply pins and the power tracks on the board; this should involve the use of a single via or multiple vias for each supply pin. Good decoupling is also important to lower the supply impedance presented to the AD7609 and to reduce the magnitude of the supply spikes. Place the decoupling capacitors close to, ideally right up against, these pins and their corresponding ground pins. Place the decoupling capacitors for the REFIN/ REFOUT pin and the REFCAPA and REFCAPB pins as close as possible to their respective AD7609 pins. Where possible, they should be placed on the same side of the board as the AD7609 device. Figure 60 shows the recommended decoupling on the top layer of the AD7609 board. Figure 61 shows bottom layer decoupling. Bottom layer decoupling is for the four AVCC pins and the VDRIVE pin. Data Sheet Figure 60. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and REGCAP Pins Figure 61. Bottom Layer Decoupling Rev. A | Page 32 of 36 09760-058 09760-057 Data Sheet To ensure good device-to-device performance matching in a system that contains multiple AD7609 devices, a symmetrical layout between the AD7609 devices is important. Figure 62 shows a layout with two AD7609 devices. The AVCC supply plane runs to the right of both devices. The VDRIVE supply track runs to the left of the two AD7609 devices. The reference chip is positioned between both AD7609 devices and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 to U2. A solid ground plane is used. These symmetrical layout principles can be applied to a system that contains more than two AD7609 devices. The AD7609 devices can be placed in a north-to-south direction with the reference voltage located midway between the AD7609 devices and the reference track running in the north-to-south direction similar to Figure 62. AD7609 Figure 62. Multiple AD7609 Layout, Top Layer and Supply Plane Layer Rev. A | Page 33 of 36 09760-059 AD7609 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 1 PIN 1 Data Sheet 12.20 12.00 SQ 11.80 64 49 48 TOP VIEW (PINS DOWN) 10.20 10.00 SQ 9.80 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 16 17 32 33 0.08 COPLANARITY VIEW A VIEW A ROTATED 90° CCW 0.50 BSC LEAD PITCH 0.27 0.22 0.17 051706-A COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 63. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7609BSTZ AD7609BSTZ-RL EVAL-AD7609EDZ CED1Z 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board for the AD7609 Converter Evaluation Development Package Option ST-64-2 ST-64-2 Z = RoHS Compliant Part. Rev. A | Page 34 of 36 Data Sheet NOTES AD7609 Rev. A | Page 35 of 36 AD7609 NOTES Data Sheet ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09760-0-2/12(A) Rev. A | Page 36 of 36