AD7617BSTZ-RL

16-Channel DAS with 14-Bit, Bipolar Input, Dual Simultaneous Sampling ADC AD7617 Data Sheet FEATURES APPLICATIONS 16-channel, dual, simultaneously sampled inputs Independently selectable channel input ranges True bipolar: ±10 V, ±5 V, ±2.5 V Single 5 V analog supply and 2.3 V to 3.6 V VDRIVE supply Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 MΩ analog input impedance First-order antialiasing analog filter On-chip accurate reference and reference buffer Dual 14-bit SAR ADC Throughput rate: 2× 1 MSPS per channel pair Oversampling capability with digital filter Flexible sequencer with burst mode Flexible parallel/serial interface SPI/QSPI/MICROWIRE/DSP compatible Optional CRC error checking Hardware/software configuration Performance 85.3 dB typical SNR at 500 kSPS (2× oversampling) 85 dB typical SNR at 1 MSPS −103 dB typical THD at ±10 V range ±0.3 LSB INL (typical), ±0.99 LSB DNL (maximum) 8 kV ESD analog input pins only On-chip self detect function 80-lead LQFP package Power line monitoring Protective relays Multiphase motor control Instrumentation and control systems Data acquisition systems (DASs) GENERAL DESCRIPTION The AD7617 is a 14-bit, DAS that supports dual simultaneous sampling of 16 channels. The AD7617 operates from a single +5 V supply and can accommodate ±10 V, ±5 V, and ±2.5 V true bipolar input signals while sampling at throughput rates up to 1 MSPS per channel pair with 85 dB signal-to-noise ratio (SNR). Higher SNR performance can be achieved with the on-chip oversampling mode (85.3 dB for an oversampling ratio (OSR) of 2). The input clamp protection circuitry can tolerate voltages up to ±21 V. The AD7617 has 1 MΩ analog input impedance, regardless of sampling frequency. The single-supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The device contains analog input clamp protection, a dual, 14-bit charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. The AD7617 is serial peripheral interface (SPI)/QSPI™/DSP/MICROWIRE compatible. FUNCTIONAL BLOCK DIAGRAM VCC V7A V7AGND V0B V0BGND V7B V7BGND CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 2.5V REF FIRSTORDER LPF 1.8V ALDO 1.8V DLDO 9:1 MUX SERIAL 14-BIT SAR FIRSTORDER LPF 14-BIT SAR FIRSTORDER LPF SER/PAR SER1W OSR DIGITAL FILTER PARALLEL VCC ALDO DB15 TO DB0 OS2 TO OS0 9:1 MUX RESET BURST SEQEN HW_RNGSEL0, HW_RNGSEL1 CHSEL2 TO CHSEL0 FLEXIBLE SEQUENCER FIRSTORDER LPF CONTROL INPUTS AD7617 SDOx/SDI CLK OSC 2:1 MUX AGND BUSY CONVST DGND NOTES 1. MULTIFUNCTION PINS, SUCH AS DB15/OS2, ARE REFERRED TO BY A SINGLE FUNCTION OF THE PIN, FOR EXAMPLE, DB15, WHEN ONLY THAT FUNCTION IS RELEVANT. REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION FOR MORE INFORMATION. 16077-001 V0A V0AGND REFCAP REFINOUT REFSEL REGCAP REGCAPD VDRIVE Figure 1. AD7617 Functional Block Diagram Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7617 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Digital Interface .......................................................................... 28  Applications ....................................................................................... 1  Hardware Mode .......................................................................... 28  General Description ......................................................................... 1  Software Mode ............................................................................ 29  Functional Block Diagram .............................................................. 1  Reset Functionality..................................................................... 29  Revision History ............................................................................... 2  Pin Function Overview ............................................................. 30  Specifications..................................................................................... 3  Digital Interface .............................................................................. 31  Timing Specifications .................................................................. 6  Channel Selection....................................................................... 31  Absolute Maximum Ratings.......................................................... 10  Parallel Interface ......................................................................... 32  Thermal Resistance .................................................................... 10  Serial Interface ............................................................................ 33  ESD Caution ................................................................................ 10  Sequencer ........................................................................................ 36  Pin Configuration and Function Descriptions ........................... 11  Hardware Mode Sequencer ....................................................... 36  Typical Performance Characteristics ........................................... 15  Software Mode Sequencer ......................................................... 36  Terminology .................................................................................... 21  Burst Sequencer .......................................................................... 37  Theory of Operation ...................................................................... 23  Diagnostics ...................................................................................... 39  Converter Details........................................................................ 23  Diagnostic Channels .................................................................. 39  Analog Input ............................................................................... 23  Interface Self Test ....................................................................... 39  ADC Transfer Function ............................................................. 24  CRC .............................................................................................. 39  Internal/External Reference ...................................................... 24  Register Summary .......................................................................... 41  Shutdown Mode.......................................................................... 25  Addressing Registers .................................................................. 42  Digital Filter ................................................................................ 25  Configuration Register .............................................................. 43  Applications Information .............................................................. 26  Channel Register ........................................................................ 44  Functionality Overview ............................................................. 26  Input Range Registers ................................................................ 45  Power Supplies ............................................................................ 26  Sequencer Stack Registers ......................................................... 49  Typical Connections .................................................................. 26  Status Register ............................................................................. 50  Device Configuration..................................................................... 28  Outline Dimensions ....................................................................... 51  Operational Mode ...................................................................... 28  Ordering Guide .......................................................................... 51  Internal/External Reference ...................................................... 28  REVISION HISTORY 7/2017—Revision 0: Initial Version Rev. 0 | Page 2 of 51 Data Sheet AD7617 SPECIFICATIONS VREF = 2.5 V external/internal, VCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 3.6 V, sampling frequency (fSAMPLE) = 1 MSPS, TA = −40°C to +125°C, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 1, 2 Signal-to-Noise-and-Distortion (SINAD)1 Dynamic Range Total Harmonic Distortion (THD)1 Peak Harmonic or Spurious Noise1 Intermodulation Distortion (IMD)1 Second-Order Terms Third-Order Terms Channel to Channel Isolation1 ANALOG INPUT FILTER Full Power Bandwidth Phase Delay1, 3 Drift1, 3 Matching (Dual Simultaneous Pair)1, 3 DC ACCURACY Resolution Differential Nonlinearity (DNL)1 Integral Nonlinearity (INL)1 Total Unadjusted Error (TUE) Positive Full-Scale Error (PFS) 5 External Reference Test Conditions/Comments fIN = 1 kHz sine wave, unless otherwise noted No oversampling, ±10 V range OSR = 2, ±10 V range, 3 fSAMPLE = 500 kSPS OSR = 4, ±10 V range3 No oversampling, ±5 V range No oversampling, ±2.5 V range No oversampling, ±10 V range No oversampling, ±5 V range No oversampling, ±2.5 V range No oversampling, ±10 V range No oversampling, ±5 V range No oversampling, ±2.5 V range No oversampling, ±10 V range No oversampling, ±5 V range No oversampling, ±2.5 V range Min Typ 84.5 85 85.3 85.5 84.5 83.5 84.5 84 83.5 85.5 85.1 84.5 −103 −100 −97 −103 84 83 84 83.5 82.5 Max −93.5 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB fa = 1 kHz, fb = 1.1 kHz fIN on unselected channels up to 5 kHz −105 −113 −106 dB dB dB −3 dB, ±10 V range −3 dB, ±5 V/+2.5 V range −0.1 dB ±10 V range ±5 V range ±2.5 V range ±10 V range ±10 V range ±5 V range ±2.5 V range 39 33 5.5 4.4 5 4.9 ±0.55 4.4 4.7 4.1 kHz kHz kHz µs µs µs ns/°C ns ns ns No missing codes 6 +5 100 14 ±0.99 ±1 ±10 V range ±5 V range ±2.5 V range ±0.1 ±0.3 ±1.5 ±2 ±2.5 ±10 V range ±5 V range ±2.5 V range ±1.25 ±1 ± 0.5 ±8 ±10 V range ±1.25 Bits LSB 4 LSB LSB LSB LSB LSB LSB LSB Internal Reference Rev. 0 | Page 3 of 51 LSB AD7617 Parameter Drift3 Matching1 Bipolar Zero Code Error1 Drift3 Matching1 Negative Full-Scale (NFS) Error1, 5 Drift3 Matching1 ANALOG INPUT Input Voltage Ranges Analog Input Current Input Capacitance6 Input Impedance Input Impedance Drift3 REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance6 Reference Output Voltage Reference Temperature Coefficient3 LOGIC INPUTS Input Voltage High (VINH) Low (VINL) Data Sheet Test Conditions/Comments External reference Internal reference ±10 V range ±5 V range ±2.5 V range ±10 V range ±5 V range ±2.5 V range ±10 V range ±5 V range ±2.5 V range ±10 V range ±5 V range ±2.5 V range External reference ±10 V range ±5 V range ±2.5 V range Internal reference ±10 V range External reference Internal reference ±10 V range ±5 V range ±2.5 V range Min Max ±5 ±10 3 ±1 ±0.75 ±1.5 ±8 ±1 ±2 ±4 1 1 2 Software/hardware selectable, ±10 V range Software/hardware selectable, ±5 V range Software/hardware selectable, ±2.5 V range ±10 V range, see Figure 34 ±5 V range, see Figure 34 ±2.5 V range, see Figure 34 See the Analog Input section Typ ±2 ±3 1 1 1 ±0.15 ±0.2 ±0.7 ±1.5 ±1 ±0.5 ±0.5 ±0.75 ±0.75 ±2.5 ±2.5 ±3.5 ±21 ±2.5 ±5 ±10 3 ±10 ±5 ±2.5 0.85 ±10.5 ±6.5 ±4 10 1 25 See the ADC Transfer Function section 2.495 REFSEL = 1 Measured at REFINOUT 2.495 2.5 7.5 ±2 VDRIVE = 2.7 V to 3.6 V VDRIVE = 2.3 V to 2.7 V VDRIVE = 2.7 V to 3.6 V VDRIVE = 2.3 V to 2.7 V Input Current (IIN) Input Capacitance (CIN)6 2.505 ±15 2 1.7 0.8 0.7 ±1 5 Rev. 0 | Page 4 of 51 2.505 ±1 Unit ppm/°C ppm/°C LSB LSB LSB LSB LSB LSB μV/°C μV/°C μV/°C LSB LSB LSB LSB LSB LSB LSB ppm/°C ppm/°C LSB LSB LSB V V V μA μA μA pF MΩ ppm/°C V μA pF V ppm/°C V V V V μA pF Data Sheet Parameter LOGIC OUTPUTS Output Voltage High (VOH) Low (VOL) Floating State Leakage Current Floating State Output Capacitance6 Output Coding CONVERSION RATE Conversion Time Acquisition Time Throughput Rate POWER REQUIREMENTS VCC VDRIVE IVCC Normal Mode Static Operational Shutdown Mode IDRIVE Normal Mode Static Operational Shutdown Mode Power Dissipation Normal Mode Static Operational Shutdown Mode AD7617 Test Conditions/Comments Min ISOURCE = 100 µA ISINK = 100 µA VDRIVE − 0.2 Typ ±0.005 5 Max Unit 0.4 ±1 V V µA pF Twos complement Per channel pair Per channel pair Per channel pair 0.5 0.5 1 µs µs MSPS 5.25 3.6 V V 37 42 28 57 65 mA mA µA fSAMPLE = 1 MSPS 0.3 2.4 20 0.75 3.2 mA mA µA fSAMPLE = 1 MSPS 185 230 0.25 300 350 mW mW mW 4.75 2.3 fSAMPLE = 1 MSPS Digital inputs = 0 V or VDRIVE See the Terminology section. The user can achieve 85.3 dB SNR by enabling oversampling. The values are valid for manual mode. In burst mode, values degrade by ~1 dB. 3 Not production tested. Sample tested during initial release to ensure compliance. 4 LSB means least significant bit. With a ±2.5 V input range, 1 LSB = 305.175 µV. With a ±5 V input range, 1 LSB = 610.351 µV. With a ±10 V input range, 1 LSB = 1.220 mV. 5 Positive and negative full-scale error for the internal reference excludes reference errors. 6 Supported by simulation data. 1 2 Rev. 0 | Page 5 of 51 AD7617 Data Sheet TIMING SPECIFICATIONS Universal Timing Specifications VCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 3.6 V, VREF = 2.5 V external reference/internal reference, TA = −40°C to +125°C, unless otherwise noted. Interface timing tested using a load capacitance (CLOAD) of 30 pF, dependent on VDRIVE and load capacitance for serial interface (see Table 15). Table 2. Parameter 1 tCYCLE Min 1 tCONV_LOW tCONV_HIGH tBUSY_DELAY tCS_SETUP tCH_SETUP tCH_HOLD tCONV tACQ tQUIET tRESET_LOW 50 50 Typ Max ns ns ns ns ns ns ns ns ns Description Minimum time between consecutive CONVST rising edges (excluding burst and oversampling modes) CONVST low pulse width CONVST high pulse width CONVST high to BUSY high (manual mode) BUSY falling edge to CS falling edge setup time Channel select setup time in hardware mode for CHSELx Channel select hold time in hardware mode for CHSELx Conversion time for the selected channel pair Acquisition time for the selected channel pair CS rising edge to next CONVST rising edge ns µs Partial RESET low pulse width Full RESET low pulse width 50 15 ns ms Time between partial RESET high and CONVST rising edge Time between full RESET high and CONVST rising edge 50 240 1 ns µs ms Time between partial RESET high and CS for write operation Time between full RESET high and CS for write operation Time between stable VCC/VDRIVE and release of RESET (see Figure 51) 10 0.05 ns ms 32 20 50 20 475 520 480 50 Partial Reset Full Reset tDEVICE_SETUP Partial Reset Full Reset tWRITE Partial Reset Full Reset tRESET_WAIT 40 1.2 500 Unit µs Time prior to release of RESET that queried hardware inputs must be stable for (see Figure 51) tRESET_SETUP Partial Reset Full Reset Time after release of RESET that queried hardware inputs must be stable for (see Figure 51) tRESET_HOLD Partial Reset Full Reset ns ms Not production tested. Sample tested during initial release to ensure compliance. tCYCLE tCONV_LOW t CONV_HIGH tQUIET tBUSY_DELAY CONVST BUSY tCONV t ACQ t CS_SETUP CS t CH_SETUP HARDWARE MODE ONLY CHSEL0 TO CHSEL2 t CH_HOLD CHx CHy Figure 2. Universal Timing Diagram Across All Interfaces Rev. 0 | Page 6 of 51 16077-102 1 10 0.24 Data Sheet AD7617 RESET_WAIT DEVICE_SETUP VCC VDRIVE RESET RESET_LOW CONVST BUSY tWRITE CS RESET_SETUP RESET_HOLD REFSEL SER/PAR, SER1W ALL MODES HW_RNGSEL0, HW_RNGSEL1 MODE RANGE SETTING IN HW MODE CRCEN, BURST SEQEN, OS0 TO OS2 CHSEL0 TO CHSEL2 CHy CHx ADC INTERNAL ACTION ACQx CHz CONVx ACQy CONVy Figure 3. Reset Timing Parallel Mode Timing Specifications Table 3. Parameter tRD_SETUP Min 10 Typ Max Unit ns Description CS falling edge to RD falling edge setup time tRD_HOLD 10 ns RD rising edge to CS rising edge hold time tRD_HIGH 10 ns RD high pulse width tRD_LOW 30 tDOUT_SETUP tDOUT_3STATE tWR_SETUP tWR_HIGH ns RD low pulse width 10 ns ns ns Data access time after falling edge of RD CS rising edge to DBx high impedance CS to WR setup time 20 ns WR high pulse width 30 11 tWR_LOW 30 ns WR low pulse width tWR_HOLD 10 ns WR hold time tDIN_SETUP tDIN_HOLD tCONF_SETTLE 30 10 20 ns ns ns Configuration data to WR setup time Configuration data to WR hold time Configuration data settle time, WR rising edge to CONVST rising edge Rev. 0 | Page 7 of 51 16077-103 HARDWARE MODE ONLY AD7617 Data Sheet CONVST BUSY tRD_HIGH tRD_HOLD tDOUT_3STATE CS RD DB0 TO DB15 CONV A CONV B tRD_LOW 16077-104 tRD_SETUP tDOUT_SETUP Figure 4. Parallel Read Timing Diagram tWR_SETUP tCONF_SETTLE CONVST CS tWR_HIGH tWR_HOLD WR DB0 TO DB15 WRITE REG 1 tWR_LOW WRITE REG 2 tDIN_SETUP Figure 5. Parallel Write Timing Diagram Serial Mode Timing Specifications Table 4. Parameter fSCLK1 tSCLK tSCLK_SETUP1 tSCLK_HOLD tSCLK_LOW tSCLK_HIGH tDOUT_SETUP1 tDOUT_HOLD tDIN_SETUP tDIN_HOLD tDOUT_3STATE 1 Min Typ Max 40/50 1/fSCLK 10.5 13.5 10 8 9 9 11 4 10 8 10 Unit MHz ns ns ns ns ns ns ns ns ns ns ns Description SCLK frequency Minimum SCLK period CS to SCLK falling edge setup time, VDRIVE above 3 V CS to SCLK falling edge setup time, VDRIVE above 2.3 V SCLK to CS rising edge hold time SCLK low pulse width SCLK high pulse width Data out access time after SCLK rising edge, VDRIVE above 3 V Data out access time after SCLK rising edge, VDRIVE above 2.3 V Data out hold time after SCLK rising edge Data in setup time before SCLK falling edge Data in hold time after SCLK falling edge CS rising edge to SDOx high impedance Dependent on VDRIVE and CLOAD (see Table 15). Rev. 0 | Page 8 of 51 16077-105 tDIN_HOLD Data Sheet AD7617 CONVST BUSY t SCLK_SETUP t DOUT_SETUP t SCLK tDOUT_HOLD t SCLK_HIGH t SCLK_LOW tSCLK_HOLD SCLK 1 2 SDOA DB15 DB14 SDOB DB15 DB14 SDI DB15 tDIN_SETUP DB14 3 14 15 16 DB13 DB2 DB1 DB0 DB13 DB2 DB1 DB0 DB13 DB2 tDIN_HOLD Figure 6. Serial Timing Diagram Rev. 0 | Page 9 of 51 DB1 DB0 t DOUT_3STATE 16077-106 CS AD7617 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 5. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Parameter VCC to AGND VDRIVE to AGND Analog Input Voltage to AGND1 Digital Input Voltage to AGND Digital Output Voltage to AGND REFINOUT to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature Soldering Reflow Pb/Sn Temperature (10 sec to 30 sec) Pb-Free Temperature ESD All Pins Except Analog Inputs Analog Input Pins Only 1 Rating −0.3 V to +7 V −0.3 V to VCC + 0.3 V ±21 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VCC + 0.3 V ±10 mA −40°C to +125°C −65°C to +150°C 150°C θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 6. Thermal Resistance Package Type ST-80-21 1 θJC 7.5 Unit °C/W Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board. See JEDEC JESD51. ESD CAUTION 240 (+0)°C 260 (+0)°C θJA 41 2 kV 8 kV Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) latch-up. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 10 of 51 Data Sheet AD7617 WR/BURST SCLK/RD CS CHSEL0 CHSEL1 CHSEL2 BUSY CONVST REGCAP REGGND AGND VCC V0BGND V0B V1BGND V1B V2BGND V2B V3BGND V3B PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 V4BGND 1 60 DB15/OS2 V4B 2 59 DB14/OS1 V5BGND 3 58 DB13/OS0 V5B 4 57 DB12/SDOA AGND 5 VCC 6 56 DB11/SDOB 55 DB10/SDI V6B 7 54 DB9 V6BGND 8 53 DB8 V7B 9 52 REGCAPD AD7617 V7BGND 10 51 REGGNDD TOP VIEW (Not to Scale) V7AGND 11 50 DGND 49 VDRIVE V7A 12 V6AGND 13 48 DB7 V6A 14 VCC 15 47 DB6 46 DB5/CRCEN AGND 16 45 DB4/SER1W V5A 17 44 DB3 V5AGND 18 43 DB2 V4A 19 42 DB1 V4AGND 20 41 DB0 DIGITAL INPUT DECOUPLING CAP PIN REFERENCE INPUT/OUTPUT POWER SUPPLY DIGITAL INPUT/OUTPUT GROUND PIN DIGITAL OUTPUT SER/PAR 16077-005 ANALOG INPUT HW_RNGSEL0 HW_RNGSEL1 SEQEN RESET REFSEL REFINOUT REFINOUTGND REFCAP REFGND VCC AGND V0A V0AGND V1A V1AGND V2A V2AGND V3A V3AGND 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 7. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5, 16, 29, 72 6, 15, 30, 71 Type 1 AI GND AI AI GND AI GND P Mnemonic 2 V4BGND V4B V5BGND V5B AGND VCC 7 8 9 10 11 12 13 14 17 18 19 20 AI AI GND AI AI GND AI GND AI AI GND AI AI AI GND AI AI GND V6B V6BGND V7B V7BGND V7AGND V7A V6AGND V6A V5A V5AGND V4A V4AGND Description Analog Input Ground Pin. This pin corresponds to Analog Input Pin V4B. Analog Input for Channel 4, ADC B. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V5B. Analog Input for Channel 5, ADC B. Analog Supply Ground Pin. Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal frontend amplifiers and to the ADC core. Decouple these pins to AGND using 0.1 µF and 10 µF capacitors in parallel. Analog Input for Channel 6, ADC B. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V6B. Analog Input for Channel 7, ADC B. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V7B. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V7A. Analog Input for Channel 7, ADC A. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V6A. Analog Input for Channel 6, ADC A. Analog Input for Channel 5, ADC A. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V5A. Analog Input for Channel 4, ADC A. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V4A. Rev. 0 | Page 11 of 51 AD7617 Data Sheet Pin No. 21 22 23 24 25 26 27 28 31 Type 1 AI GND AI AI GND AI AI GND AI AI GND AI CAP Mnemonic 2 V3AGND V3A V2AGND V2A V1AGND V1A V0AGND V0A REFCAP 32 33 CAP REF REFGND REFINOUT 34 35 CAP DI REFINOUTGND REFSEL 36 DI RESET 37 DI SEQEN 38, 39 DI HW_RNGSEL1, HW_RNGSEL0 40 DI SER/PAR 41, 42, 43, 44 DO/DI DB0, DB1, DB2, DB3 Description Analog Input Ground Pin. This pin corresponds to Analog Input Pin V3A. Analog Input for Channel 3, ADC A. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V2A. Analog Input for Channel 2, ADC A. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V1A. Analog Input for Channel 1, ADC A. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V0A. Analog Input for Channel 0, ADC A. Reference Buffer Output Force/Sense Pin. Decouple this pin to REFGND using a low effective series resistance (ESR), 10 µF, X5R ceramic capacitor, as close to the REFCAP pin as possible. The voltage on this pin is typically 4.096 V. Reference Ground Pin. Connect this pin to AGND. Reference Input/Reference Output. The on-chip reference of 2.5 V is available on this pin for external use when the REFSEL pin is set to logic high. Alternatively, the internal reference can be disabled by setting the REFSEL pin to logic low, and an external reference of 2.5 V can be applied to this input. Decoupling is required on this pin for both the internal and external reference options. Connect a 100 nF, X7R capacitor between the REFINOUT and REFINOUTGND pins, as close to the REFINOUT pin as possible. If using an external reference, connect a 10 kΩ series resistor to this pin to band limit the reference signal. Reference Input, Reference Output Ground Pin. Internal/External Reference Selection Input. REFSEL is a logic input. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled, and an external reference voltage must be applied to the REFINOUT pin. The signal state is latched on the release of a full reset and requires an additional full reset to reconfigure. Reset Input. Connect a 100 pF capacitor between RESET and ground. Full and partial reset options are available. The type of reset is determined by the length of the RESET pulse. Keeping RESET low places the device into shutdown mode. See the Reset Functionality section for further details. Channel Sequencer Enable Input (Hardware Mode Only). When SEQEN is tied low, the sequencer is disabled. When SEQEN is high, the sequencer is enabled (with restricted functionality in hardware mode). See the Sequencer section for further details. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. In software mode, this pin must be connected to DGND. Hardware/Software Mode Selection, Hardware Mode Range Select Inputs. Hardware/software mode selection is latched at full reset. Range selection in hardware mode is not latched. HW_RNGSELx = 00: software mode; the AD7617 is configured via the software registers. HW_RNGSELx = 01: hardware mode; analog input range is ±2.5 V. HW_RNGSELx = 10: hardware mode; analog input range is ±5 V. HW_RNGSELx = 11: hardware mode; analog input range is ±10 V. Serial/Parallel Interface Selection Input. Logic input. If this pin is tied to logic low, the parallel interface is selected. If this pin is tied to logic high, the serial interface is selected. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. Parallel Output/Input Data Bit 0 to Data Bit 3. In parallel mode, DB2 is the LSB of the 14-bit conversion result and DB0 and DB1output zero. In software parallel mode, DB0, DB1, DB2, and DB3 are the four LSBs of a register write/read operation. In hardware parallel mode, DB0 and DB1 can be left floating or pulled to DGND via a 10 kΩ pull-down resistor. Refer to the Parallel Interface section for further details. In serial mode, these pins must be tied to DGND. Rev. 0 | Page 12 of 51 Data Sheet AD7617 Pin No. 45 Type 1 DO/DI Mnemonic 2 DB4/SER1W 46 DO/DI DB5/CRCEN 47, 48 DO/DI DB6, DB7 49 P VDRIVE 50 GND DGND 51 52 CAP CAP REGGNDD REGCAPD 53, 54 DO/DI DB8, DB9 55 DO/DI DB10/SDI 56 DO/DI DB11/SDOB 57 DO/DI DB12/SDOA 58, 59, 60 DO/DI DB13/OS0, DB14/OS1, DB15/OS2 61 DI WR/BURST Description Parallel Output/Input Data Bit 4/Serial Output Selection. In parallel mode, this pin acts as a three-state parallel digital output/input pin. Refer to the Parallel Interface section for further details. In serial mode, this pin determines whether the serial output operates over SDOA and SDOB or just SDOA. When SER1W is low, the serial output operates over SDOA only. When SER1W is high, the serial output operates over both SDOA and SDOB. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. Parallel Output/Input Data Bit 5/Cyclic Redundancy Check (CRC) Enable Input. In parallel mode, this pin acts as a three-state parallel digital input/output. While in serial mode, this pin acts as a CRC enable input. The CRCEN signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. Refer to the Digital Interface section for further details. In serial mode, when CRCEN is low, there is no CRC word following the conversion results; when CRCEN is high, an extra CRC word follows the last conversion word configured by CHSELx. See the CRC section for further details. In software mode, this pin must be connected to DGND. Parallel Output/Input Data Bit 6 and Data Bit 7. When SER/PAR = 0, these pins act as threestate parallel digital input/outputs. Refer to the Parallel Interface section for further details. In serial mode, when SER/PAR = 1, these pins must be tied to DGND. Logic Power Supply Input. The voltage (2.3 V to 3.6 V) supplied at this pin determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface. Decouple this pin with 0.1 µF and 10 µF capacitors in parallel. Digital Ground. This pin is the ground reference point for all digital circuitry on the AD7617. The DGND pin must connect to the DGND plane of a system. Ground for the Digital Low Dropout (LDO) Regulator Connected to REGCAPD (Pin 52). Decoupling Capacitor Pin for Voltage Output from Internal Digital Regulator. Decouple this output pin separately to REGGNDD using a 10 μF capacitor. The voltage at this pin is 1.89 V typical. Parallel Output/Input Data Bit 9 and Data Bit 8. When SER/PAR = 0, these pins act as threestate parallel digital input/outputs. Refer to the Parallel Interface section for further details. In serial mode, when SER/PAR = 1, these pins must be tied to DGND. Parallel Output/Input Data Bit DB10/Serial Data Input. When SER/PAR = 0, this pin acts as a three-state parallel digital input/output. Refer to the Parallel Interface section for further details. In hardware serial mode, tie this pin to DGND. In serial mode, when SER/PAR = 1, this pin acts as the data input of the SPI interface. Parallel Output/Input Data Bit 11/Serial Data Output B. When SER/PAR = 0, this pin acts as a three-state parallel digital input/output. Refer to the Parallel Interface section for further details. In serial mode, when SER/PAR = 1 and DB4/SER1W = 1, this pin functions as SDOB and outputs serial conversion data. Parallel Output/Input Data Bit 12/Serial Data Output A. When SER/PAR = 0, this pin acts as a three-state parallel digital input/output. Refer to the Parallel Interface section for further details. In serial mode, when SER/PAR = 1, this pin functions as SDOA and outputs serial conversion data. Parallel Output/Input Data Bit 13, Data Bit 14, and Data Bit 15/Oversampling Ratio Selection. When SER/PAR = 0, these pins act as three-state parallel digital input/outputs. Refer to the Parallel Interface section for further details. In serial hardware mode, these pins control the oversampling settings. The signal state is latched on the release of a full reset and requires an additional full reset to reconfigure. See the Digital Filter section for further details. In software serial mode, these pins must be connected to DGND. Write/Burst Mode Enable. In software parallel mode, this pin acts as WR for a parallel interface. In hardware parallel or serial mode, this pin enables BURST mode. The signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. Refer to the Burst Sequencer section for further information. In software serial mode, connect this pin to DGND. Rev. 0 | Page 13 of 51 AD7617 Data Sheet Pin No. 62 Type 1 DI Mnemonic 2 SCLK/RD 63 DI CS 64, 65, 66 DI CHSEL0, CHSEL1, CHSEL2 67 DO BUSY 68 DI CONVST 69 70 CAP CAP REGGND REGCAP 73 74 75 76 77 78 79 80 AI AI GND AI AI GND AI AI GND AI AI GND V0B V0BGND V1B V1BGND V2B V2BGND V3B V3BGND 1 2 Description Serial Clock Input/Parallel Data Read Control Input. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the SDOA and SDOB data output lines out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the SDOA and SDOB serial data outputs. When both CS and RD are logic low in parallel mode, the output bus is enabled. Chip Select. This active low logic input frames the data transfer. In parallel mode, when both CS and RD are logic low, the DBx output bus is enabled, and the conversion result is output on the parallel data bus lines. In serial mode, CS frames the serial read transfer and clocks out the MSB of the serial output data. Channel Selection Input 0 to Input 2. In hardware mode, these inputs select the input channels for the next conversion in Channel Group A and Channel Group B. For example, CHSELx = 0x000 selects V0A and V0B for the next conversion; CHSELx = 0x001 selects V1A and V1B for the next conversion. In software mode, these pins must be connected to DGND. Busy Output. This pin transitions to a logic high after a CONVST rising edge and indicates that the conversion process started. The BUSY output remains high until the conversion process for the current selected channels completes. The falling edge of BUSY signals that the conversion data is being latched into the output data registers and is available to read. Data must be read after BUSY returns to low. Rising edges on CONVST have no effect while the BUSY signal is high. Conversion Start Input for Channel Group A and Channel Group B. This logic input initiates conversions on the analog input channels. A conversion initiates when CONVST transitions from low to high for the selected analog input pair. When burst mode and oversampling mode are disabled, every CONVST transition from low to high converts one channel pair. In sequencer mode, when burst mode or oversampling is enabled, a single CONVST transition from low to high is necessary to perform the required number of conversions. Internal Analog Regulator Ground. This pin must connect to the AGND plane of a system. Decoupling Capacitor Pin for Voltage Output from Internal Analog Regulator. Decouple this output pin separately to REGGND using a 10 μF capacitor. The voltage at this pin is 1.87 V typical. Analog Input for Channel 0, ADC B. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V0B. Analog Input for Channel 1, ADC B. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V1B. Analog Input for Channel 2, ADC B. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V2B. Analog Input for Channel 3, ADC B. Analog Input Ground Pin. This pin corresponds to Analog Input Pin V3B. AI is analog input, GND is ground, P is power supply, CAP is decoupling capacitor pin, REF is reference input/output, DI is digital input, and DO is digital output. Note that throughout this data sheet, multifunction pins, such as SER/PAR, are referred to either by the entire pin name or by a single function of the pin, for example, SER, when only that function is relevant. Rev. 0 | Page 14 of 51 Data Sheet AD7617 TYPICAL PERFORMANCE CHARACTERISTICS VREF = 2.5 V internal, VCC = 5 V, VDRIVE = 3.3 V, fSAMPLE = 1 MSPS, fIN = 1 kHz TA = 25°C, unless otherwise noted. 90 0 SNR = 85.1dB SINAD = 84.42dB THD = –103.41dB N SAMPLES = 8192 fSAMPLE = 1MSPS –20 –40 ±10V RANGE ±5V RANGE ±2.5V RANGE 89 88 SNR (dB) MAGNITUDE (dB) 87 –60 –80 –100 86 85 84 83 –120 82 –140 0 100 200 300 400 500 FREQUENCY (kHz) 80 –40 –25 –10 50 65 80 95 110 125 90 SNR = 84.47dB SINAD = 83.95dB THD = –103.41dB N SAMPLES = 8192 fSAMPLE = 1MSPS ±10V RANGE ±5V RANGE ±2.5V RANGE 89 88 87 –60 SINAD (dB) MAGNITUDE (dB) 35 Figure 11. SNR vs. Temperature 0 –40 20 TEMPERATURE (°C) Figure 8. Fast Fourier Transform (FFT), ±10 V Range –20 5 16077-311 81 16077-308 –160 –80 –100 86 85 84 83 –120 82 –140 0 100 200 300 400 500 FREQUENCY (kHz) 80 –40 –25 35 50 65 80 95 110 125 –60 RSOURCE MATCHED ON Vxx AND VxxGND INPUTS ±10V RANGE ±5V RANGE ±2.5V RANGE –70 –80 THD (dB) –60 –80 –90 –100 –100 –120 –110 –160 0 10 20 30 40 50 FREQUENCY (kHz) 60 Figure 10. FFT Burst Mode, ±10 V Range –120 –40 –25 –10 5 20 35 50 65 80 TEMPERATURE (°C) Figure 13. THD vs. Temperature Rev. 0 | Page 15 of 51 95 110 125 16077-313 –140 16077-310 MAGNITUDE (dB) –40 20 Figure 12. SINAD vs. Temperature SNR = 85dB SINAD = 84.43dB THD = –107.4dB N SAMPLES = 8192 fSAMPLE = 62.5kSPS –20 5 TEMPERATURE (°C) Figure 9. FFT, ±5 V Range 0 –10 16077-312 81 16077-309 –160 AD7617 Data Sheet 1.5 1.0 0.8 1.0 0.4 DNL ERROR (LSB) INL ERROR (LSB) 0.6 0.2 0 –0.2 –0.4 –0.6 0.5 0 –0.5 –1.0 0 5000 10000 15000 CODE –1.5 16077-314 –1.0 0 5000 15000 CODE Figure 14. Typical INL Error, ±10 V Range Figure 17. Typical DNL Error, ±5 V Range 1.0 70000 ±10V RANGE Vxx AND VxxGND SHORTED TOGETHER 65,537 SAMPLES 0.8 60000 0.6 57410 50000 0.4 NUMBER OF HITS INL ERROR (LSB) 10000 16077-317 –0.8 0.2 0 –0.2 –0.4 40000 30000 20000 –0.6 10000 8127 0 0 5000 10000 15000 CODE 0 16077-315 –1.0 0 8191 8192 8193 CODE Figure 18. DC Histogram of Codes at Code Center, ±10 V Range Figure 15. Typical INL Error, ±5 V Range 50000 1.5 1.0 NUMBER OF HITS 40000 0.5 0 –0.5 ±5V RANGE Vxx AND VxxGND SHORTED TOGETHER 65,537 SAMPLES 44759 30000 20776 20000 10000 –1.0 0 10000 5000 CODE 15000 0 8190 2 8191 8192 8193 CODE Figure 19. DC Histogram of Codes at Code Center, ±5 V Range Figure 16. Typical DNL Error, ±10 V Range Rev. 0 | Page 16 of 51 16077-319 0 –1.5 16077-316 DNL ERROR (LSB) 8190 16077-318 –0.8 Data Sheet AD7617 0.0030 50000 0.0025 30000 20776 20000 10000 0.0020 0.0015 0.0010 0 2 8191 8192 0 16077-320 8190 8193 CODE 5.0 ±10V RANGE ±5V RANGE ±2.5V RANGE NFS/PFS ERROR MATCHING (LSB) 4.5 4 2 0 –2 –4 –6 80 10 PFS ±10V RANGE NFS ±10V RANGE 4.0 3.5 3.0 2.5 2 1.5 1.0 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 0 –40 16077-321 –25 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 16077-324 0.5 –8 Figure 24. NFS/PFS Error Matching vs. Temperature Figure 21. NFS Error vs. Temperature 5 10 ±10V RANGE ±5V RANGE ±2.5V RANGE BIPOLAR ZERO CODE ERROR (LSB) 4 6 4 2 0 –2 –4 –6 ±10V RANGE ±5V RANGE ±2.5V RANGE 3 2 1 0 –1 –2 –3 –4 –8 –25 –10 5 20 35 50 65 80 95 TEMPERATURE (°C) 110 125 16077-322 PFS ERROR (LSB) 60 –5 –40 –25 –10 5 20 35 50 65 80 95 110 TEMPERATURE (°C) Figure 25. Bipolar Zero Code Error vs. Temperature Figure 22. PFS Error vs. Temperature Rev. 0 | Page 17 of 51 125 16077-325 NFS ERROR (LSB) 6 –10 –40 40 Figure 23. PFS/NFS Error vs. Source Resistance 10 8 20 SOURCE RESISTANCE (MΩ) Figure 20. DC Histogram of Codes at Code Center, ±2.5 V Range –10 –40 0 16077-323 0.0005 0 8 NFS ±10V NFS ±5V NFS ±2.5V PFS ±10V PFS ±5V PFS ±2.5V 44759 PFS/NFS ERROR (%FS) NUMBER OF HITS 40000 ±5V RANGE Vxx AND VxxGND SHORTED TOGETHER 65,537 SAMPLES AD7617 ±10V RANGE ±5V RANGE ±2.5V RANGE 3.5 87 DC INPUT 86 3.0 85 SNR (dB) 2.5 2.0 84 83 1.5 82 NO OS OSR ×2 OSR ×4 OSR ×8 OSR ×16 OSR ×32 81 0.5 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 80 100 Figure 26. Bipolar Zero Code Error Matching vs. Temperature 1k 10k 100k FREQUENCY (Hz) 16077-329 1.0 16077-326 BIPOLAR ZERO ERROR MATCHING (LSB) 4.0 Data Sheet Figure 29. SNR vs. Input Frequency for Different Oversampling Rates, ±10 V Range –60 87 –65 86 –70 85 SNR (dB) –85 –90 –95 0Ω 1.2kΩ 5.6kΩ 10kΩ 25kΩ 50kΩ 110kΩ –105 –110 1k 10k 100k INPUT FREQUENCY (Hz) –80 –85 –90 0Ω 1.2kΩ 5.6kΩ 10kΩ 25kΩ 50kΩ 110kΩ –110 1k 10k INPUT FREQUENCY (Hz) 100k 16077-328 THD (dB) –75 –105 10k 100k FREQUENCY (Hz) –50 –70 –95 1k Figure 30. SNR vs. Input Frequency for Different Oversampling Rates, ±5 V Range ±5V RANGE RSOURCE MATCHED ON Vxx AND VxxGND INPUTS –100 80 100 CHANNEL TO CHANNEL ISOLATION (dB) –65 NO OS OSR ×2 OSR ×4 OSR ×8 OSR ×16 OSR ×32 81 Figure 27. THD vs. Input Frequency for Various Source Impedances, ±10 V Range –60 83 82 16077-327 –100 84 Figure 28. THD vs. Input Frequency for Various Source Impedances, ±5 V Range ±10V RANGE ±5V RANGE ±2.5V RANGE –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 0 5000 10000 15000 20000 25000 30000 INTERFERER FREQUENCY (Hz) Figure 31. Channel to Channel Isolation vs. Interferer Frequency Rev. 0 | Page 18 of 51 16077-231 THD (dB) –80 16077-330 –75 Data Sheet AD7617 1.015 12 ±10V RANGE ±5V RANGE ±2.5V RANGE 1.010 INPUT IMPEDANCE (MΩ) 8 6 4 1.005 1.000 0.995 ±10V RANGE ±5V RANGE ±2.5V RANGE 0 –40 –25 –10 20 5 35 50 65 80 95 0.990 110 125 TEMPERATURE (°C) 0.985 –40 –10 5 20 35 50 65 80 110 125 Figure 35. Input Impedance vs. Temperature 0 2.510 ±10V RANGE ±5V RANGE ±2.5V RANGE 4.75V 5V 5.25V –20 2.505 CMRR (dB) –40 2.500 –60 –80 2.495 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) –120 16077-234 –25 10 100 1k 10k 100k 1M 10M RIPPLE FREQUENCY (Hz) 16077-237 –100 2.490 –40 Figure 36. CMRR vs. Ripple Frequency Figure 33. Internal Reference Voltage vs. Temperature for Various Supply Voltages 130 15 ±10V ±5V ±2.5V 120 10 110 +10V INPUT 100 5 0 PSRR (dB) +5V INPUT +2.5V INPUT –2.5V INPUT –5 90 80 70 –5V INPUT 60 –15 –40 –10V INPUT –25 –10 50 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 Figure 34. Analog Input Current vs. Temperature for Various Supply Voltages Rev. 0 | Page 19 of 51 40 100 1k 10k 100k RIPPLE FREQUENCY (Hz) Figure 37. PSRR vs. Ripple Frequency 1G 16077-337 –10 16077-235 ANALOG INPUT CURRENT (µA) 95 TEMPERATURE (°C) Figure 32. Phase Delay vs. Temperature INTERNAL REFERENCE VOLTAGE (V) –25 16077-335 2 16077-232 PHASE DELAY (µs) 10 AD7617 Data Sheet 0.7 90 0.6 STATIC VDRIVE CURRENT (mA) 80 70 60 50 DYNAMIC 40 STATIC 30 20 0.5 0.4 0.3 0.2 0.1 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 0 –40 5.0 47 4.5 46 4.0 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 45 IVCC CURRENT (mA) 3.5 3.0 2.5 2.0 1.5 44 43 42 41 1.0 40 0.5 39 –25 –10 5 20 35 50 65 80 95 110 TEMPERATURE (°C) 125 16077-239 DYNAMIC V DRIVE CURRENT (mA) –10 Figure 40. Static VDRIVE Current vs. Temperature Figure 38. Static/Dynamic IVCC Current vs. Temperature 0 –40 –25 Figure 39. Dynamic VDRIVE Current vs. Temperature 38 100 200 300 400 500 600 700 800 900 SAMPLING FREQUENCY (kSPS) Figure 41. IVCC Current vs. Sampling Frequency Rev. 0 | Page 20 of 51 1000 16077-241 0 –40 16077-240 10 16077-238 STATIC/DYNAMIC IVCC CURRENT (mA) 100 Data Sheet AD7617 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale at ½ LSB below the first code transition and full scale at ½ LSB above the last code transition. Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Bipolar Zero Code Error Bipolar zero code error is the deviation of the midscale transition (all 1s to all 0s) from the ideal, which is 0 V − ½ LSB. Bipolar Zero Code Error Matching Bipolar zero code error matching is the absolute difference in bipolar zero code error between any two input channels. Positive Full-Scale (PFS) Error Positive full-scale error is the deviation of the actual last code transition from the ideal last code transition (10 V − 1½ LSB (9.99954), 5 V − 1½ LSB (4.99977), and 2.5 V − 1½ LSB (2.49989)) after bipolar zero code error is adjusted out. The positive full-scale error includes the contribution from the internal reference buffer. Positive Full-Scale Error Matching Positive full-scale error matching is the absolute difference in positive full-scale error between any two input channels. Negative Full-Scale (NFS) Error Negative full-scale error is the deviation of the first code transition from the ideal first code transition (−10 V + ½ LSB (−9.99985), −5 V + ½ LSB (−4.99992) and −2.5 V + ½ LSB (−2.49996)) after the bipolar zero code error is adjusted out. The negative full-scale error includes the contribution from the internal reference buffer. Negative Full-Scale Error Matching Negative full-scale error matching is the absolute difference in negative full-scale error between any two input channels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the measured ratio of signal to noise and distortion at the output of the ADC. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), including harmonics, but excluding dc. Signal-to-Noise Ratio (SNR) SNR is the measured ratio of signal to noise at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the greater the number of levels, the smaller the quantization noise. The theoretical SNR for an ideal N-bit converter with a sine wave input is given by SNR = (6.02N + 1.76) dB Therefore, for a 14-bit converter, the SNR is 86 dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels (dB). Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the secondorder terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (dB). Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. The PSRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the VCC supply of the ADC of frequency, fS. PSRR (dB) = 10log(Pf/PfS) where: Pf is equal to the power at frequency, f, in the ADC output. PfS is equal to the power at frequency, fS, coupled onto the VCC supply. Rev. 0 | Page 21 of 51 AD7617 Data Sheet AC Common-Mode Rejection Ratio (AC CMRR) AC CMRR is defined as the ratio of the power in the ADC output at frequency, f, to the power of a sine wave applied to the common-mode voltage of Vxx and VxxGND at frequency, fS. AC CMRR (dB) = 10log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Channel to Channel Isolation Channel to channel isolation is a measure of the level of crosstalk between all input channels. It is measured by applying a full-scale sine wave signal, up to 160 kHz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 kHz sine wave signal applied. Phase Delay Phase delay is a measure of the absolute time delay between when an input is sampled by the converter and when the result associated with that sample is available to be read back from the ADC, including delay induced by the analog front end of the device. Phase Delay Drift Phase delay drift is the change in phase delay per unit temperature across the entire operating temperature of the device. Phase Delay Matching Phase delay matching is the maximum phase delay seen between any simultaneously sampled pair. Rev. 0 | Page 22 of 51 Data Sheet AD7617 THEORY OF OPERATION CONVERTER DETAILS The AD7617 is a data acquisition system that employs a high speed, low power, charge redistribution, SAR ADC, and allows dual simultaneous sampling of 16 analog input channels. The analog inputs on the AD7617 can accept true bipolar input signals. Analog input range options include ±10 V, ±5 V, and ±2.5 V. The AD7617 operates from a single 5 V supply. In hardware mode, a logic change on these pins has an immediate effect on the analog input range; however, there is typically a settling time of approximately 120 µs in addition to the normal acquisition time requirement. The recommended practice is to hardwire the range select pins according to the desired input range for the system signals. Analog Input Impedance The AD7617 contains input clamp protection, input signal scaling amplifiers, a first-order antialiasing filter, an on-chip reference, a reference buffer, a dual high speed ADC, a digital filter, a flexible sequencer, and high speed parallel and serial interfaces. The low drift analog input impedance of the AD7617 is 1 MΩ, a fixed input impedance that does not vary with the AD7617 sampling frequency. This high analog input impedance eliminates the need for a driver amplifier in front of the AD7617, allowing direct connection to the source or the sensor. The AD7617 can operate in hardware or software mode by controlling the HW_RNGSELx pins. In hardware mode, the AD7617 is configured by pin control. In software mode, the AD7617 is configured by the control registers accessed via the serial or parallel interface. Analog Input Clamp Protection ANALOG INPUT Figure 42 shows the analog input circuitry of the AD7617. Each analog input of the AD7617 contains clamp protection circuitry. Despite single +5 V supply operation, this analog input clamp protection allows an input overvoltage of between −20 V and +20 V. Analog Input Channel Selection RFB The AD7617 can handle true bipolar, single-ended input voltages. The logic levels on the range select pins, HW_RNGSEL0 and HW_RNGSEL1, determine the analog input range of all analog input channels. If both range select pins are tied to a logic low, the analog input range is determined in software mode via the input range registers (see the Register Summary section for more details). In software mode, it is possible to configure an individual analog input range per channel. FIRSTORDER LPF RFB Figure 42. Analog Input Circuitry Figure 43 shows the input clamp current vs. source voltage characteristic of the clamp circuit. For source voltages between −20 V and +20 V, no current flows in the clamp circuit. For input voltages that are greater than +20 V and less than −20 V, the AD7617 clamp circuitry turns on. 0.25 0.20 POWERED OFF POWERED ON 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 –0.25 –30 Table 8. Analog Input Range Selection Analog Input Range Configured via the Input Range Registers ±2.5 V ±5 V ±10 V CLAMP 1MΩ 1MΩ –20 –10 0 10 SOURCE VOLTAGE (V) HW_RNGSEL1 0 HW_RNGSEL0 0 0 1 1 1 0 1 16077-006 VxxGND CLAMP 20 30 16077-243 Analog Input Ranges Vxx INPUT CLAMP CURRENT (mA) The AD7617 contains dual, simultaneous sampling, 14-bit ADCs. Each ADC has eight analog input channels for a total of 16 analog inputs. Additionally, the AD7617 has on-chip diagnostic channels to monitor the VCC supply and an on-chip adjustable low dropout regulator. Channels can be selected for conversion by control of the CHSELx pins in hardware mode or via the channel register control in software mode. Software mode is required to sample the diagnostic channels. Channels can be selected dynamically or the AD7617 has an on-chip sequencer to allow the channels for conversion to be preprogrammed. In hardware mode, simultaneous sampling is limited to the corresponding A or B channel, that is, Channel V0A always samples with Channel V0B. In software mode, it is possible to select any A channel with any B channel for simultaneous sampling. Figure 43. Input Protection Clamp Profile, Input Clamp Current vs. Source Voltage Place a series resistor on the analog input channels to limit the current to ±10 mA for input voltages greater than +20 V and less than −20 V. In an application where there is a series resistance on an analog input channel, VxA or VxB, a corresponding resistance is required on the analog input ground channel, VxAGND or VxBGND (see Figure 44). Rev. 0 | Page 23 of 51 AD7617 Data Sheet If there is no corresponding resistor on the VxAGND or VxBGND channel, an offset error occurs on that channel. Use the input overvoltage clamp protection circuitry to protect the AD7617 against transient overvoltage events. It is not recommended to leave the AD7617 in a condition where the clamp protection circuitry is active in normal or power-down conditions for extended periods. R C VxxGND CLAMP 1MΩ 011...111 011...110 1MΩ RFB Figure 44. Input Resistance Matching on the Analog Input An analog antialiasing filter (a first-order Butterworth) is also provided on the AD7617. Figure 45 and Figure 46 show the frequency and phase response, respectively, of the analog antialiasing filter. The typical corner frequency in the ±10 V range is 39 kHz, and 33 kHz in the ±5 V range. ±10V RANGE ±5V RANGE ±2.5V RANGE ATTENUATION (dB) 0 –FS + 1/2LSB 0V – 1/2LSB +FS – 3/2LSB ANALOG INPUT *WHERE N IS THE NUMBER OF BITS OF THE CONVERTER Figure 47. Transfer Characteristics Table 9. Range ±10 V ±5 V ±2.5 V +FS +10 V +5 V +2.5 V Midscale 0V 0V 0V −FS −10 V −5 V −2.5 V LSB +1220 μV +610 μV +305 μV –5 INTERNAL/EXTERNAL REFERENCE –10 –15 –20 –30 100 1k 10k 100k INPUT FREQUENCY (Hz) 16077-244 –25 Figure 45. Analog Antialiasing Filter Frequency Response ±10V RANGE ±5V RANGE ±2.5V RANGE 5 The AD7617 can operate with either an internal or external reference. The device contains an on-chip 2.5 V band gap reference. The REFINOUT pin allows access to the 2.5 V reference that generates the on-chip 4.096 V reference internally, or it allows an external reference of 2.5 V to be applied to the AD7617. An externally applied reference of 2.5 V is also amplified to 4.096 V using the internal buffer. This 4.096 V buffered reference is the reference used by the SAR ADC. The REFSEL pin is a logic input pin that allows the user to select between the internal reference and an external reference. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled, and an external reference voltage must be applied to the REFINOUT pin. 6 4 The internal reference buffer is always enabled. After a full reset, the AD7617 operates in the reference mode selected by the REFSEL pin. Decoupling is required on the REFINOUT pin for both the internal and external reference options. A 100 nF, X7R ceramic capacitor is required on the REFINOUT pin to REFINOUTGND. 3 2 1 0 100 1k 10k 100k INPUT FREQUENCY (Hz) 16077-246 PHASE (µs) +FS – (–FS) 2N* 100...010 100...001 100...000 Analog Input Antialiasing Filter 5 LSB = 000...001 000...000 111...111 16077-009 CLAMP ADC CODE Vxx 16077-008 R The output coding of the AD7617 is twos complement. The code transitions occur midway between successive integer LSB values, that is, 1/2 LSB and 3/2 LSB. The LSB size is full-scale range ÷ 16,384 for the AD7617. The ideal transfer characteristics for the AD7617 are shown in Figure 47 and Figure 9. The LSB size is dependent on the analog input range selected. RFB AD7617 ANALOG INPUT SIGNAL ADC TRANSFER FUNCTION Figure 46. Analog Antialiasing Filter Phase Response Rev. 0 | Page 24 of 51 Data Sheet AD7617 The AD7617 contains a reference buffer configured to amplify the reference voltage to ~4.096 V. A 10 μF, X5R ceramic capacitor is required between REFCAP and REFGND. The reference voltage available at the REFINOUT pin is 2.5 V. When the AD7617 is configured in external reference mode, the REFINOUT pin is a high input impedance pin. If the internal reference is applied elsewhere within the system, it must first be buffered externally. REFINOUT REFCAP BUF REFSEL REFINOUTGND REFINOUTGND 16077-010 10µF 2.5V REF Figure 48. Reference Circuitry SHUTDOWN MODE The AD7617 enters shutdown mode by keeping the RESET pin low for greater than 1.2 µs. When the RESET pin is set from low to high, the device exits shutdown mode and enters normal mode. When the AD7617 is placed in shutdown mode, the current consumption is typically 48 µA, and the power-up time to perform a write to the device is approximately 240 µs. Power-up time to perform a conversion is 15 ms. In shutdown mode, all circuitry is powered down and all registers are cleared and reset to their default values. DIGITAL FILTER Table 10 provides the oversampling bit decoding to select the different oversample rates. In addition to the oversampling function, the output result is decimated to 14-bit resolution. If the OSx pins/OS bits are set to select an OS ratio of eight, the next CONVST rising edge takes the first sample for the selected channel, and the remaining seven samples for that channel are taken with an internally generated sampling signal. These samples are then averaged to yield an improvement in SNR performance. As the OS ratio increases, the −3 dB frequency is reduced, and the allowed sampling frequency is also reduced. The conversion time extends as the oversampling rate is increased, and the BUSY signal scales with oversampling rates. Acquisition and conversion time increase linearly with oversampling ratio. If oversampling is enabled with the sequencer, or in burst mode, the extra samples are gathered for a given channel before the sequencer moves on to the next channel. Table 10 shows the typical SNR performance of the device for each permissible oversampling ratio. The input tone used was a 1 kHz sine wave for the three input ranges of the device. A plot of SNR vs. OSR is shown in Figure 49. 87.0 fIN = 1kHz ±2.5V RANGE ±5V RANGE ±10V RANGE 86.5 86.0 85.5 85.0 84.5 84.0 The OSR of the digital filter is controlled in hardware using the oversampling pins, OS2 to OS0 (OSx), or in software via the OS bits within the configuration register. 83.5 83.0 0 10 20 30 40 50 60 OSR Figure 49. Typical SNR vs. OSR for all Analog Input Ranges Table 10. Oversampling Bit Decoding OSx Pins/OS Bits 000 001 010 011 100 101 110 111 OSR No oversampling 2 4 8 16 32 64 128 ±2.5 V Range 83.8 84.2 84.5 84.9 85.2 85.4 85.4 84.7 Typical SNR (dB) ±5 V Range 84.6 85.0 85.2 85.5 85.6 85.7 85.6 85.1 Rev. 0 | Page 25 of 51 ±10 V Range 84.9 85.3 85.5 85.7 85.8 85.8 85.6 85.2 −3 dB Bandwidth (kHz) All Ranges 37 36.5 35 30.5 22 13.2 7.2 3.6 16077-011 The AD7617 contains an optional digital first-order sinc filter for use in applications where slower throughput rates are in use or where higher SNR or dynamic range is desirable. SNR (dB) 100nF In software mode, oversampling is enabled for all channels after the OS bits are set in the configuration register. In hardware mode, the OSx signals at the time a full reset is released determine the OSR used. AD7617 Data Sheet APPLICATIONS INFORMATION FUNCTIONALITY OVERVIEW The AD7617 has two main modes of operation: hardware mode and software mode. Additionally, the communications interface for hardware or software mode can be serial or parallel. Depending on the mode of operation and interface chosen, certain functionality may not be available. Full functionality is available in both software serial and software parallel mode with restricted functionality in hardware serial mode and hardware parallel mode. Table 11 shows the functionality available in the different modes of operation. POWER SUPPLIES The AD7617 has two independent power supplies, VCC and VDRIVE, that supply the analog circuitry and digital interface, respectively. Decouple both the VCC supply and the VDRIVE supply with a 10 µF capacitor in parallel with a 100 nF capacitor. Additionally, these supplies are regulated by two internal LDO regulators. The analog LDO (ALDO) typically supplies 1.87 V. Decouple the ALDO with a 10 µF capacitor between the REGCAP and REGGND pins. The digital LDO (DLDO) typically supplies 1.89 V. Decouple the DLDO with a 10 µF capacitor between the REGCAPD and REGGNDD pins. The AD7617 is robust to power supply sequencing. The recommended sequence is to power up VDRIVE first, followed by VCC. Hold RESET low until both supplies are stabilized. TYPICAL CONNECTIONS Figure 50 shows the typical connections required for correct operation of the AD7617. Decouple the VCC and VDRIVE supplies as shown in Figure 50. Place the smaller, 0.1 µF capacitor as close to the supply pin as possible, with the larger 10 µF bulk capacitor in parallel. Decouple the reference and LDO regulators as shown in Figure 50 and as described in Table 7. The analog input pins require a matched resistance, R, on both the VxA and VxAGND (similarly, VxB and VxBGND) inputs to avoid a gain error on the analog input channels caused by an impedance mismatch. Table 11. Functionality Matrix Functionality Internal/External Reference Selectable Analog Input Ranges Individual Channel Configuration Common Channel Configuration Sequential Sequencer Fully Configurable Sequencer Burst Mode On-Chip Oversampling CRC Diagnostic Channel Conversion Hardware Reset Serial 1-Wire Mode Serial 2-Wire Mode Register Access 1 Operation Mode 1 Software Mode, HW_RNGSELx = 00 Hardware Mode, HW_RNGSELx ≠ 00 Serial, SER/PAR = 1 Parallel, SER/PAR = 0 Serial, SER/PAR = 1 Parallel, SER/PAR = 0 Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes No No Yes No Yes Yes No Yes Yes Yes No Yes Yes Yes No No Yes Yes No Yes No No No Yes No No No Yes means available; no means not available. Rev. 0 | Page 26 of 51 Data Sheet AD7617 5V 10µF 2.5V/3.3V 0.1µF 0.1µF VCC REGCAP ALDO DLDO 10µF 10µF VDRIVE REGCAPD 10µF AD7617 REGGND REGGNDD VxA R C VxAGND PGA MUX ADC PGA MUX ADC R VxB R C VxBGND R REFINOUT REFCAP BUF 0.1µF X7R 10µF X5R REFINOUTGND REFGND Figure 50. Typical External Connections Rev. 0 | Page 27 of 51 16077-300 2.5V REF AD7617 Data Sheet DEVICE CONFIGURATION OPERATIONAL MODE The mode of operation, hardware mode or software mode, is configured when the AD7617 is released from full reset. The logic level of the HW_RNGSELx pins when the RESET pin transitions from low to high determines the operational mode. The HW_RNGSELx pins are dual function. If HW_RNGSELx = 00, the AD7617 enters software mode. Any other combination of the HW_RNGSELx configures the AD7617 in hardware mode and the analog input range is configured as per Table 8. After software mode is configured, the logic level of the HW_RNGSELx signals is ignored. After an operational mode is configured, a full reset via the RESET pin is required to exit the operational mode and to set up an alternative mode. If hardware mode is selected, all further device configuration is via pin control. Access to the on-chip registers is prohibited in hardware mode. In software mode, the interface and reference configuration must be configured via pin control; however, all further device configuration is via register access only. INTERNAL/EXTERNAL REFERENCE The internal reference is enabled or disabled when the AD7617 is released from a full reset. The logic level of the REFSEL signal when the RESET pin transitions from low to high configures the reference. After the reference is configured, changes to the logic level of the REFSEL signal are ignored. If the REFSEL signal is set to Logic 1, the internal reference is enabled. If REFSEL is set to Logic 0, the internal reference is disabled and an external reference must be supplied to the REFINOUT pin for correct operation of the AD7617. A full reset via the RESET pin is required to exit the operational mode and set up an alternative mode. Connect a 100 nF capacitor between the REFINOUT and REFINOUTGND pins. If using an external reference, place a 10 kΩ band limiting resistor in series between the reference and the REFINOUT pin of the AD7617. DIGITAL INTERFACE The digital interface selection, parallel or serial, is configured when the AD7617 is released from a full reset. The logic level of the SER/PAR signal when the RESET pin transitions from low to high configures the interface. If the SER/PAR signal is set to 0, the parallel interface is enabled. If the SER/PAR signal is set to 1, the serial interface is selected. Additionally, if the serial interface is selected, the SER1W signal is monitored when the RESET pin is released to determine if serial 1-wire or 2-wire mode is selected. After the interface is configured, changes to the logic level of the SER/PAR signal or the SER1W signal (when the serial interface is enabled) are ignored. A full reset via the RESET pin is required to exit the operation mode and set up an alternative mode. HARDWARE MODE If hardware mode is selected, the available functionality is restricted and all functionality is configured via pin control. The logic level of the following signals is checked after a full reset to configure the functionality of the AD7617: CRC, BURST, SEQEN, and OSx. Table 12 provides a summary of the signals that are latched by the device on the release of a full reset, depending on the mode of operation chosen. After the device is configured, a full reset via the RESET pin is required to exit the configuration and set up an alternative configuration. Functionality availability is restricted depending on the interface type selected. See Table 11 for a full list of the functionality available in hardware parallel or serial mode. The CHSELx pins are queried at reset to determine the initial analog input channel pair to acquire for conversion or to configure the initial settings for the sequencer. The channel pair selected for conversion or the hardware sequencer can be reconfigured during normal operation by setting and maintaining the CHSELx signal level before the CONVST rising edge until the BUSY falling edge. The HW_RNGSELx signals control the analog input range for all 16 analog input channels. A logic change on these pins has an immediate effect on the analog input range; however, the typical settling time is approximately 120 µs, in addition to the normal acquisition time requirement. The recommended practice is to hardwire the range select pins according to the desired input range for the system signals. Access to the on-chip registers is prohibited in hardware mode. Rev. 0 | Page 28 of 51 Data Sheet AD7617 Table 12. Summary of Latched Hardware Signals1 Latched at Full Reset Signal REFSEL SEQEN HW_RNGSELx (Range Change) HW_RNGSELx (Hardware (HW) or Software (SW) Mode) SER/PAR CRCEN OSx BURST CHSELx SER1W 1 HW Mode SW Mode Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes No No No Yes Read at Reset HW Mode SW Mode Yes Yes Yes No Read During Busy HW Mode Yes SW Mode Edge Driven HW Mode SW Mode Yes No No Yes Blank cells in Table 12 mean not applicable. SOFTWARE MODE If software mode is selected and the reference and interface type is configured, all other configuration settings in the AD7617 are controlled via the on-chip registers. All functionality of the AD7617 is available when software mode is selected. Table 12 provides a summary of the signals that are latched by the device on the release of a full reset, depending on the mode of operation chosen. RESET FUNCTIONALITY The AD7617 has two reset modes: full or partial. The reset mode selected is dependent on the length of the reset low pulse. A partial reset requires the RESET pin to be held low between 40 ns and 500 ns. After 50 ns from release of RESET, the device is fully functional and a conversion can initiate. A full reset requires the RESET pin to be held low for a minimum of 1.2 µs. After 15 ms from release of RESET, the devices is completely reconfigured and a conversion can initiate. A partial reset reinitializes the following modules: • • • • If hardware mode is selected, the functionality determined by the CRC, BURSTEN, SEQEN, and OSx signals is also latched when the RESET pin transitions from low to high in full reset mode. After the functionality is configured, changes to these signals are ignored. In hardware mode, the analog input range (HW_RNGSELx signals) can be configured during either a full or partial reset or during normal operation; however, hardware/ software mode selection requires a full reset to reconfigure while this setting is latched. In hardware mode, the CHSELx and HW_RNGSELx pins are queried at release from both a full and a partial reset to perform the following actions: • Sequencer Digital filter SPI Both SAR ADCs • • The current conversion result is discarded on completion of a partial reset. The partial reset does not affect the register values programmed in software mode or the latches that store the user configuration in both hardware and software modes. A dummy conversion is required in software mode after a partial reset. A full reset returns the device to its default power-on state. The following features are configured when the AD7617 is released from full reset: • • • On power-up, the RESET signal can be released as soon as both the VCC and VDRIVE supplies are stable. The logic level of the HW_RNGSELx, REFSEL, SER/PAR and DB4/SER1W pins when the RESET pin is released after a full reset determines the configuration. Determine the initial analog input channel pair to acquire for conversion. Configure the initial settings for the sequencer. Select the analog input voltage range. The CHSELx and HW_RNGSELx signals are not latched. The channel pair selected for conversion, or the hardware sequencer, can be reconfigured during normal operation by setting and maintaining the CHSELx signal level before the CONVST rising edge, and ensuring the signal level remains constant until after BUSY transitions low again. See the Channel Selection section for further details. In software mode, all additional functionality is configured by controlling the on-chip registers. Hardware mode or software mode Internal/external reference Interface type Rev. 0 | Page 29 of 51 AD7617 Data Sheet PIN FUNCTION OVERVIEW Table 13 outlines the pin functionality in the different modes of operation and interface modes. There are several dual function pins on the AD7617. Their functionality is dependent on the mode of operation selected by the HW_RNGSELx pins. tRESET_WAIT tDEVICE_SETUP VCC VDRIVE RESET CONVST BUSY tRESET_SETUP tRESET_HOLD REFSEL SER/PAR, SER1W ALL MODES HW_RNGSEL0, HW_RNGSEL1 MODE RANGE SETTING IN HW MODE CRCEN, BURST SEQEN, OS0 TO OS2 CHx CHSEL0 TO CHSEL2 y ACQx ACTION z CONV x ACQy CONVy 16077-012 HARDWARE MODE ONLY Figure 51. AD7617 Configuration at Reset Table 13. Pin Functionality Overview Pins CHSELx SCLK/RD WR/BURST DB15/OS0 to DB13/OS2 DB12/SDOA DB11/SDOB DB10/SDI DB9 to DB6, DB3 to DB2 DB5/CRCEN DB4/SER1W DB1 to DB0 HW_RNGSELx SEQEN REFSEL Operation Mode Software, HW_RNGSELx = 00 Hardware, HW_RNGSELx ≠ 00 Serial, SER/PAR = 1 Parallel, SER/PAR = 0 Serial, SER/PAR = 1 Parallel, SER/PAR = 0 No function, connect to DGND SCLK Connect to DGND Connect to DGND No function, connect to DGND RD WR DB15 to DB13 CHSELx CHSELx SCLK BURST OSx RD BURST DB15 to DB13 SDOA SDOB, leave floating for serial 1-wire mode SDI Connect to DGND DB12 DB11 SDOA SDOB DB12 DB11 Connect to DGND Connect to DGND DB10 DB9 to DB6, DB3 to DB2 Connect to DGND SER1W Connect to DGND DB10 DB9 to DB6, DB3 to DB2 DB5 DB4 DB1 to DB0 CRCEN SER1W Connect to DGND HW_RNGSELx, connect to DGND No function, connect to DGND REFSEL HW_RNGSELx, connect to DGND No function, connect to DGND REFSEL HW_RNGSELx, configure analog input range SEQEN DB5 DB4 Float or pull to DGND via a 10 kΩ resistor HW_RNGSELx, configure analog input range SEQEN REFSEL REFSEL Rev. 0 | Page 30 of 51 Data Sheet AD7617 DIGITAL INTERFACE CHANNEL SELECTION Software Mode Hardware Mode In software mode, the channels for conversion are selected by control of the channel register. On power-up or after a reset, the default channels selected for conversion are Channel V0A and Channel V0B (see Figure 53). The logic level of the CHSELx signals determine the channel pair for conversion; see Table 14 for signal decoding information. The CHSELx signals at the time that either full or partial reset is released determine the initial channel pair to sample. After a reset, the logic levels of the CHSELx signals are examined during the BUSY high period to set the channel pair for the next conversion. The CHSELx signal level must be set before CONVST goes from low to high and be maintained until BUSY goes from high to low to indicate a conversion is complete. See Figure 52 for further details. Table 14. CHSELx Pin Decoding Channel Selection Input Pin CHSEL0 CHSEL1 CHSEL2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Analog Input Channels for Conversion V0A, V0B V1A, V1B V2A, V2B V3A, V3B V4A, V4B V5A, V5B V6A, V6B V7A, V7B RESET CONVST BUSY CHx CHy CHz A/Bx DATA BUS INITIAL SETUP CH... A/By CONFIGURE POINT CONFIGURE POINT A/Bz CONFIGURE POINT 16077-013 CHSEL2 TO CHSEL0 Figure 52. Hardware Mode Channel Conversion Setting RESET CONVST BUSY SDI SDOA, SDOB WRITE CHx WRITE CHy WRITE CHz WRITE CH... DO NOT CARE A/B0 A/Bx A/By CHx CONVERSION START Figure 53. Software Serial Mode Channel Conversion Setting Rev. 0 | Page 31 of 51 16077-014 CS AD7617 Data Sheet RESET CONVST BUSY CS WR DB0 TO DB15 CH x A0 B0 CHy Ax Ay Bx CHz 16077-153 RD By CH CHx CONVERSION START Figure 54. Software Parallel Mode Channel Conversion Setting The parallel interface reads the conversion results, and configures and reads back the on-chip registers. Data can be read from the AD7617 via the parallel data bus with standard CS, RD, and WR signals. To read the data over the parallel bus, tie the SER/PAR pin low. Reading Conversion Results The CONVST signal initiates the conversion process. A low to high transition on the CONVST signal initiates a conversion of the selected inputs. The BUSY signal goes high to indicate a conversion is in progress. When the BUSY signal transitions from high to low to indicate that a conversion is complete, it is possible to read back conversion results on the parallel interface. Data can be read from the AD7617 via the parallel data bus with standard CS and RD signals. The CS and RD input signals are internally gated to enable the conversion result onto the data bus. The data lines, DB15 to DB2, leave their high impedance state when both CS and RD are logic low. DB15 is the MSB of the conversion result and DB2 is the LSB of the 14-bit conversion result. The data lines DB1 and DB0 are only used for register write/read operations or for reading the CRC result. The rising edge of the CS input signal three-states the bus, and the falling edge of the CS input signal takes the bus out of the high impedance state. CS is the control signal that enables the data lines; it is the function that allows multiple AD7617 devices to share the same parallel data bus. The number of required read operations depends on the device configuration. A minimum of two reads are required to read the conversion result for the simultaneously sampled A and B channels. If additional functions such as CRC, status, and burst mode are enabled, the number of required readbacks increases accordingly. The RD pin reads data from the output conversion results register. Applying a sequence of RD pulses to the RD pin of the AD7617 clocks the conversion results out from each channel onto the parallel bus, DB15 to DB2. The first RD falling edge after BUSY goes low clocks out the conversion result from Channel AX. The next RD falling edge updates the bus with the Channel BX conversion result. Writing Register Data In software mode, all the read/write registers in the AD7617 may be written to over the parallel interface. A register write command is performed by a single 16-bit parallel access via the parallel bus (DB15 to DB0), CS, and WR signals. Provide data written to the AD7617 on the DB15 to DB0 inputs, with DB0 being the LSB of the data-word. The format for a write command is shown in Figure 55. Bit D15 must be set to 1 to select a write command. Bits[D14:D9] contain the register address. The subsequent nine bits (Bits[D8:D0]) contain the data to be written to the selected register. See the Register Summary section for the complete list of register addresses. Data is latched into the device on the rising edge of WR. CS WR DB15 TO DB0 WRITE REG 1 WRITE REG 2 16077-020 PARALLEL INTERFACE Figure 55. Parallel Interface Register Write Reading Register Data All the registers in the device can be read over the parallel interface. A register read is performed by first writing the address of the register to be read to the AD7617. The format for a register read command is shown in Figure 57. Bit D15 must be set to 0 to select a read command. Bits[D14:D9] contain the register address. The subsequent nine bits (Bits[D8:D0]) are ignored. The read command is latched into the AD7617 on the rising edge of WR. This latch transfers the relevant register data to the output register. The register data can then be read on the DB15 to DB0 pins by using a standard read command. See Figure 57 for additional information. Rev. 0 | Page 32 of 51 Data Sheet AD7617 CONVST BUSY CS DB15 TO DB0 CONV A CONV B 16077-016 RD Figure 56. Parallel Interface Conversion Readback CS WR DB15 TO DB0 READ REG 1 DATA REG 1 READ REG 2 DATA REG 2 16077-023 RD Figure 57. Parallel Interface Register Read SERIAL INTERFACE To interface to the AD7617 over the SPI, the SER/PAR pin must be tied high. The CS and SCLK signals transfer data from the AD7617. The AD7617 has two serial data output pins, SDOA and SDOB. Data is read back from the AD7617 using serial 1-wire or serial 2-wire mode. In serial 2-wire mode for the AD7617, conversion results from Channel V0A to Channel V7A appear on SDOA, and conversion results from Channel V0B to Channel V7B appear on SDOB. In serial 1-wire mode, conversion results from Channel V0B to Channel V7B are interlaced with conversion results from Channel V0A to Channel V7A. To achieve the maximum throughput, it is required to use 2-wire mode. To read back data over both SDOA and SDOB, the SER1W pin must be tied high. If data is read back over SDOA only, the tie SER1W pin low. Serial 1-wire or 2-wire mode is configured when the AD7617 is released from full reset. Reading Conversion Results The CONVST signal initiates the conversion process. A low to high transition on the CONVST signal initiates a conversion of the selected inputs. The BUSY signal goes high to indicate a conversion is in progress. When the BUSY signal transitions from high to low to indicate that a conversion is complete, it is possible to read back conversion results on the serial interface. The CS falling edge takes the data output lines, SDOA and SDOB, out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data outputs, SDOA and SDOB. Figure 58 shows a read of two simultaneous conversion results using two SDOx lines on the AD7617. If the status register is appended to the conversion results or operating in sequencer burst mode where multiples of 16 SCLK transfers access data from the AD7617, hold CS low to frame the entire data. Data can also be clocked out using just one SDOx line, in which case, use SDOA to access all conversion data. For the AD7617 to access both Channel VxA and Channel VxB conversion results on one SDOx line, a total of 32 SCLK cycles is required. Frame these 32 SCLK cycles using one CS signal, or individually frame each group of 16 SCLK cycles using the CS signal. The disadvantage of using just one SDOx line is that the throughput rate is reduced. In serial 2-wire, 16 SCLK cycles are required to read a conversion result. The first SCLK cycle reads the MSB of the conversion results. The 14th SCLK cycle reads the LSB. The last two SCLK cycles clock out zeros, as shown in Figure 58. In serial 1-wire, 32 SCLK cycles (or 2× 16 SCLK cycles) are required to read a conversion result. The first 16 SCLK cycles read the 14-bit Channel VxA result, followed by two zeros. The next 16 SCLK cycles read the 14-bit Channel VxB result, followed by two zeros, as shown in Figure 59. With CRC enabled, all 16 SCLK cycles read the status register. Refer to the CRC section for further information. Leave the unused SDOB line unconnected in serial 1-wire mode. If using SDOA as a single serial data output line, the channel results are output in the following order: VxA and VxB. Figure 59 shows a 1-wire, serial readback operation. The speed at which the data can be read back in serial interface mode is dependent on SPI frequency, VDRIVE supply, and the capacitance of the load on the SDO line, CLOAD. Table 15 shows a summary of the maximum speed achievable for various conditions. Table 15. SPI Frequency vs. Load Capacitance and VDRIVE VDRIVE (V) 2.3 to 3 3 to 3.6 Rev. 0 | Page 33 of 51 CLOAD (pF) 20 30 SPI Frequency (MHz) 40 50 AD7617 Data Sheet CONVST BUSY CS SCLK 1 2 3 SDOA 15(MSB) 14 SDOB 15(MSB) 14 14 13 15 16 2(LSB) 13 16077-017 CHANNEL VAx RESULT 2(LSB) CHANNEL VBx RESULT Figure 58. Serial Interface, 2-Wire Mode Reading Conversion Result CONVST BUSY SCLK SDOA 1 2 DB15(MSB) DB2(LSB) 15 16 ZERO ZERO CHANNEL VAx RESULT 17 DB 15(MSB) 18 DB2(LSB) 32 ZERO ZERO CHANNEL VBx RESULT Figure 59. Serial Interface, 1-Wire Mode Reading Conversion Result Rev. 0 | Page 34 of 51 31 16077-018 CS Data Sheet AD7617 Writing Register Data Reading Register Data All the read/write registers in the AD7617 can be written to over the serial interface. A register write command is performed by a single 16-bit SPI access. The format for a write command is shown in Table 16. Bit D15 must be set to 1 to select a write command. Bits[D14:D9] contain the register address. The subsequent nine bits (Bits[D8:D0]) contain the data to be written to the selected register. Figure 60 shows a typical serial interface register write command. All the registers in the device can be read over the serial interface. A register read is performed by issuing a register read command followed by an additional SPI command that can be either a valid command or no operation (NOP). The format for a read command is shown in Table 17. Bit D15 must be set to 0 to select a read command. Bits[D14:D9] contain the register address. The subsequent nine bits (Bits[D8:D0]) are ignored. See the Register Summary section for the complete list of register addresses. Figure 61 shows a typical serial interface register read command. CONVST WRITE REG 1 WRITE REG 2 WRITE REG 3 SDOA, SDOB CONV RESULT INVALID INVALID 16077-021 CS SDI Figure 60. Serial Interface Register Write CONVST SDI SDOA READ REG 1 READ REG 2 READ REG 3 CONV RESULT REG 1 DATA REG 2 DATA 16077-024 CS Figure 61. Serial Interface Register Read Table 16. Write Command Message Configuration MSB D15 W/R 1 D14 D13 D12 D11 D10 REGADDR[5:0] Register address D9 D8 D7 D6 D5 D4 D3 Data[8:0] Data to write D2 D1 LSB D0 D1 LSB D0 Table 17. Read Command Message Configuration MSB D15 W/R 0 D14 D13 D12 D11 D10 REGADDR[5:0] Register address D9 D8 D7 Rev. 0 | Page 35 of 51 D6 D5 D4 D3 Data[8:0] Do not care D2 AD7617 Data Sheet SEQUENCER When the sequencer is enabled, the logic levels of the CHSELx pins determine the channels selected for conversion in the sequence. The CHSELx pins at the time RESET is released determine the initial settings for the channels to convert in the sequence. To reconfigure the channels selected for conversion thereafter, set the CHSELx pins to the required setting for the duration of the final BUSY pulse before the current conversion sequence is complete. See Figure 62 for further details. The AD7617 features a highly configurable on-chip sequencer. The functionality and configuration of the sequencer is dependent on the mode of operation of the AD7617. In hardware mode, the sequencer is sequential only. The sequencer always starts converting at Channel V0A and Channel V0B and converts each subsequent channel up to the configured end channel. In software mode, the sequencer has additional functionality and configurability. The sequencer stack has 32 uniquely configurable sequence steps, allowing any channel order to be programmed. Additionally, any Channel VxA input can be paired with any Channel VxB input or diagnostic channel. Table 19. CHSELx Pin Decoding Sequencer Channel Selection Input Pin CHSEL0 CHSEL1 CHSEL2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 The sequencer can be operated with or without the burst function enabled. With the burst function enabled, only one CONVST pulse is required to convert every channel in a sequence. With burst mode disabled, one CONVST pulse is required for every conversion step in the sequence. See the Burst Sequencer section for additional details on operating in burst mode. HARDWARE MODE SEQUENCER In hardware mode, the sequencer is controlled by the SEQEN pin and the CHSELx pins. The sequencer is enabled or disabled when the AD7617 is released from full reset. The logic level of the SEQEN pin when the RESET pin is released determines whether the sequencer is enabled or disabled (see Table 18 for settings). After the RESET pin is released, the function is fixed and a full reset via the RESET pin is required to exit the function and set up an alternative configuration. SOFTWARE MODE SEQUENCER In software mode, the AD7617 contains a 32-layer fully configurable sequencer stack. Control of the sequencer is achieved by programming the configuration register and sequencer stack registers via the parallel or serial interface. Each stack step can be individually programmed to pair any input from Channel VxA to any input from Channel VxB, or any diagnostic channel can be selected for conversion. The sequencer depth can be set to any length from 1 to 32 layers. The sequencer depth is controlled via the SSRENx bit. Set the SSRENx bit in the sequencer stack register corresponding to the last step required. The channels to convert are selected by programming the ASELx and BSELx bits in each sequence stack register for the depth required. Table 18. Hardware Mode Sequencer Configuration Interface Mode Sequencer disabled Sequencer enabled The sequencer is activated by setting the SEQEN bit in the configuration register to 1. RESET SEQEN CONVST BUSY CHSEL2 TO CHSEL0 CHy CHx DATA A/B0 INITIAL SETUP A/Bx-1 CHz A/Bx A/B0 A/By-1 CONFIGURE POINT Figure 62. Hardware Mode Sequencer Configuration Rev. 0 | Page 36 of 51 A/By CONFIGURE POINT A/B0 16077-025 SEQEN 0 1 Analog Input Channels for Sequential Conversion V0x only V0x to V1x V0x to V2x V0x to V3x V0x to V4x V0x to V5x V0x to V6x V0x to V7x Data Sheet AD7617 To configure and enable the sequencer, it is recommended to complete the following procedure (see Figure 63): The conversion results are presented on the data bus (parallel or serial) in the same order as the programmed sequence. 1. The throughput rate of the AD7617 is limited in burst mode and dependent on the length of the sequence. Each channel pair requires an acquisition, conversion, and readback time. The time taken to complete a sequence with number of channel pairs, N, is estimated by 2. 3. 4. 5. 6. Configure the analog input range for the required analog input channels. Program the sequencer stack registers to select the channels for the sequence. Set the SSRENx bit in the last required sequence step. Set the SEQEN bit in the configuration register. Provide a dummy CONVST pulse. Cycle through CONVST pulses and conversion reads to step through each element of the sequencer stack. tBURST = (tCONV + 25 ns) + (N – 1)(tACQ + tCONV) + N(tRB) where: tCONV is the typical conversion time. tACQ is typical acquisition time. tRB is the time required to read back the conversion results in either serial 1-wire, serial 2-wire, or parallel mode. The sequence automatically restarts from the first element in the sequencer stack with the next CONVST pulse. Following a partial reset, the sequencer pointer is repositioned to the first layer of the stack, but the register programmed values remain unchanged. Hardware Mode Burst Burst mode is enabled in hardware mode by setting the BURST pin to 1. The SEQEN pin must also be set to 1 to enable the sequencer. BURST SEQUENCER In hardware mode, the burst sequencer is controlled by the BURST, SEQEN, and CHSELx pins. The burst sequencer is enabled or disabled when the AD7617 is released from full reset. The logic level of the SEQEN pin and the BURST pin when the RESET pin is released determines whether the burst sequencer is enabled or disabled. After the RESET pin is released, the function is fixed and a full reset via the RESET pin is required to exit the function and set up an alternative configuration. Burst mode avoids generating a CONVST pulse for each step in a sequence of conversions. One CONVST pulse converts every step in the sequence. The burst sequencer is an additional feature that works in conjunction with the sequencer. If the burst function is enabled, one CONVST pulse initiates a conversion of all the channels configured in the sequencer. The burst function avoids generating a CONVST pulse for each step in a sequence of conversions, as is the case when the burst function is disabled. When the burst sequencer is enabled, the logic levels of the CHSELx pins determine the channels selected for conversion in the burst sequence. The CHSELx pins at the time RESET is released determines the initial settings for the channels to convert in the burst sequence. To reconfigure the channels selected for conversion after a reset, set the CHSELx pins to the required setting for the duration of the next BUSY pulse (see Figure 64 for further details). Configuration of the burst function varies depending on the mode of operation: hardware or software mode. See the Hardware Mode Burst section and the Software Mode Burst section for specific details on configuring the burst function in the each mode. When configured, the burst sequence is initiated at the rising edge of CONVST. The BUSY pin goes high to indicate that a conversion is in progress. The BUSY pin remain highs until all conversions in the sequence are complete. The conversion results are available for readback after the BUSY pin goes low. Software Mode Burst In software mode, the burst function is enabled by setting the BURST bit in the configuration register to 1. This action must be performed when setting the SEQEN bit in the configuration register as outlined in the steps described in the Software Mode Sequencer section to configure the sequencer (see Figure 65 for additional information). The number of data reads required to read all the data in the burst sequence is dependent on the length of the sequence configured. RESET CONVST BUSY REGISTER SETUP INITIAL SETUP S0 1 Sn – 1 Sn 0 16077-026 A/B0 DATA SEQUENCE START DUMMY CONVERSION Figure 63. Software Mode Sequencer Configuration Rev. 0 | Page 37 of 51 AD7617 Data Sheet RESET SEQEN BURST CONVST BUSY CHx CHy CHz A/B0 DATA INITIAL SETUP A/B x–1 A/Bx CONFIGURE POINT CH z A/By–1 A/B0 CHz A/By CONFIGURE POINT A/B0 A/Bz–1 16077-027 CHSEL2 TO CHSEL0 A/B z CONFIGURE POINT Figure 64. BURST Sequencer, Hardware Mode RESET CONVST BUSY DATA A/B0 S0 S1 Sn–1 Sn DUMMY CONVERSION Figure 65. BURST Sequencer, Software Mode Rev. 0 | Page 38 of 51 S0 S1 Sn–1 Sn 16077-028 REGISTER SETUP AD7617 Data Sheet DIAGNOSTICS –7200 DIAGNOSTIC CHANNELS –7400 EXPECTED OUTPUT (Codes) –8200 –8400 –8600 4  VCC  – VREF  32,768 1.80 1.85 ALDO (V) 1.90 1.95 Figure 68. ALDO Diagnostic Transfer Function 5  VREF INTERFACE SELF TEST It is possible to test the integrity of the digital interface by selecting the communication self test channel in the channel register (see the Channel Register section). 10  VREF 750 Selecting the communication self test for conversion forces the conversion result register to a known fixed output. When conversion code is read, Code 0x2AAA is output as the conversion code of ADC A, and Code 0x1555 is output as the conversion code of ADC B. 500 250 VCC ERROR 0 CRC ALDO ERROR –250 –500 –750 0 100 200 300 400 500 600 SAMPLING FREQUENCY (kSPS) 16077-035 DEVIATION FROM EXPECTED VALUE (Codes) –8000 –9000 1.75 10  VALDO  – 7  VREF  32,768 LDO Code  Figure 66. Deviation from Expected Value vs. Sampling Frequency 29000 28000 27000 26000 25000 24500 23000 22000 4.50 4.75 5.00 5.25 VCC (V) Figure 67. VCC Diagnostic Transfer Function 5.50 16077-029 EXPECTED OUTPUT (Codes) –7800 –8800 The expected output for each channel is governed by the following transfer functions: VCC Code  –7600 16077-030 In addition to the 16 analog inputs, VxA and VxB, the AD7617 can also convert the following diagnostic channels: VCC and the ALDO voltage. The diagnostic channels are selected for conversion by programming the channel register (see the Channel Register section) to the corresponding channel identifier. Diagnostic channels can also be added to the sequencer stack in software mode but only provide an accurate reading at throughput rates 119 bits, the Hamming distance is 1, that is, 1-bit errors are always detected. crc_out[2] = data[15] ^ data[13] ^ data[12] ^ data[10] ^ data[8] ^ data[6] ^ data[2] ^ data[1] ^ data[0] ^ crc[0] ^ crc[2] ^ crc[4] ^ crc[5] ^ crc[7]; crc_out[3] = data[14] ^ data[13] ^ data[11] ^ data[9] ^ data[7] ^ data[3] ^ data[2] ^ data[1] ^ crc[1] ^ crc[3] ^ crc[5] ^ crc[6]; crc_out[4] = data[15] ^ data[14] ^ data[12] ^ data[10] ^ data[8] ^ data[4] ^ data[3] ^ data[2] ^ crc[0] ^ crc[2] ^ crc[4] ^ crc[6] ^ crc[7]; The CRC polynomial in use on the AD7617 is x8 + x2 + x + 1 crc_out[5] = data[15] ^ data[13] ^ data[11] ^ data[9] ^ data[5] ^ data[4] ^ data[3] ^ crc[1] ^ crc[3] ^ crc[5] ^ crc[7]; The following is a pseudocode description of how the CRC is implemented in the AD7617: crc_out[6] = data[14] ^ data[12] ^ data[10] ^ data[6] ^ data[5] ^ data[4] ^ crc[2] ^ crc[4] ^ crc[6]; crc = 8’b0; i = 0; x = number of conversion channel pairs; crc_out[7] = data[15] ^ data[13] ^ data[11] ^ data[7] ^ data[6] ^ data[5] ^ crc[3] ^ crc[5] ^ crc[7]; for (i=0, i