18-Bit, 670 kSPS, Differential
Programmable Input PulSAR® ADC
AD7634
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND VCC VEE DVDD
AGND
PDREF
GENERAL DESCRIPTION
The AD7634 is an 18-bit charge redistribution successive
approximation register (SAR), architecture analog-todigital converter (ADC) fabricated on Analog Devices, Inc.’s
iCMOS high voltage process. The device is configured through
hardware or via a dedicated write-only serial configuration port
for input range and operating mode. The AD7634 contains a
high speed 18-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. A falling edge on
CNVST samples the fully differential analog inputs on IN+ and
IN−. The AD7634 features four different analog input ranges and
three different sampling modes. Operation is specified from
−40°C to +85°C.
Rev. B
SERIAL
CONFIGURATION
18
PORT
PDBUF
IN+
SWITCHED
CAP DAC
IN–
OVDD
OGND
SERIAL DATA
PORT
REF
D[17:0]
BUSY
RD
PARALLEL
INTERFACE
CLOCK
CNVST
CS
D0/OB/2C
PD
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
RESET
D1/A0
D2/A1
WARP IMPULSE BIPOLAR TEN
MODE0
MODE1
Figure 1.
Table 1. 48-Lead PulSAR Selection
100 to
250
(kSPS)
500 to
570
(kSPS)
570 to
1000
(kSPS)
Input Type
Res
(Bits)
Bipolar
14
AD7951
Differential
Bipolar
14
AD7952
Unipolar
16
AD7651
AD7660
AD7661
AD7650
AD7652
AD7664
AD7666
AD7653
AD7667
Bipolar
16
AD7610
AD7663
AD7665
AD7612
AD7671
Differential
Unipolar
16
AD7675
AD7676
AD7677
AD7621
AD7622
AD7623
Simultaneous/
Multichannel
Unipolar
16
Differential
Unipolar
18
AD7678
AD7674
AD7641
AD7643
Differential
Bipolar
18
AD7631
APPLICATIONS
CT scanners
High dynamic data acquisition
Σ-Δ replacement
Spectrum analysis
Medical instruments
Instrumentation
Process controls
AD7634
REF
AMP
AVDD
DGND
06406-001
Multiple pins/software-programmable input ranges
5 V (10 V p-p), +10 V (20 V p-p), ±5 V (20 V p-p),
±10 V (40 V p-p)
Pins or serial SPI®-compatible input ranges/mode selection
Throughput
670 kSPS (warp mode)
570 kSPS (normal mode)
450 kSPS (impulse mode)
INL: ±1.5 LSB typical, ±2.5 LSB maximum (±9.5 ppm of FSR)
18-bit resolution with no missing codes
Dynamic range: 102.5 dB
SNR: 101 dB @ 2 kHz
THD: −112 dB @ 2kHz
iCMOS® process technology
5 V internal reference: typical drift 3 ppm/°C; TEMP output
No pipeline delay (SAR architecture)
Parallel (18-/16-/8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation
180 mW @ 670 kSPS, warp mode
28 mW @ 100 kSPS, impulse mode
10 mW @ 1 kSPS, impulse mode
Pb-free, 48-lead LQFP and 48-Lead LFCSP (7 mm × 7 mm)
>1000
(kSPS)
AD7654
AD7655
AD7679
AD7634
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AD7634
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Amplifier Choice ........................................................... 21
Applications ....................................................................................... 1
Voltage Reference Input/Output .............................................. 22
General Description ......................................................................... 1
Power Supplies ............................................................................ 22
Functional Block Diagram .............................................................. 1
Conversion Control ................................................................... 23
Revision History ............................................................................... 2
Interfaces.......................................................................................... 24
Specifications..................................................................................... 3
Digital Interface .......................................................................... 24
Timing Specifications .................................................................. 5
Parallel Interface ......................................................................... 24
Absolute Maximum Ratings............................................................ 7
Serial Interface ............................................................................ 25
ESD Caution .................................................................................. 7
Master Serial Interface ............................................................... 25
Pin Configuration and Function Descriptions ............................. 8
Slave Serial Interface .................................................................. 27
Typical Performance Characteristics ........................................... 12
Hardware Configuration ........................................................... 29
Terminology .................................................................................... 16
Software Configuration ............................................................. 29
Theory of Operation ...................................................................... 17
Microprocessor Interfacing ....................................................... 30
Overview...................................................................................... 17
Application Information ................................................................ 31
Converter Operation .................................................................. 17
Layout Guidelines....................................................................... 31
Modes of Operation ................................................................... 17
Evaluating Performance ............................................................ 31
Transfer Functions...................................................................... 18
Outline Dimensions ....................................................................... 32
Typical Connection Diagram ................................................... 19
Ordering Guide .......................................................................... 32
Analog Inputs .............................................................................. 20
REVISION HISTORY
12/12—Rev. A to Rev. B
Changes to Power Sequencing Section ........................................ 23
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
3/11—Rev. 0 to Rev. A
Changes to Resolution Parameter, Table 2 .................................... 3
Changes to Figure 4 and Table 6 ..................................................... 8
Added Exposed Pad Notation to Outline Dimensions ............. 32
1/07—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
AD7634
SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUTS
Differential Voltage Range, VIN
0 V to 5 V
0 V to 10 V
±5 V
±10 V
Operating Voltage Range
0 V to 5 V
0 V to 10 V
±5 V
±10 V
Common-Mode Voltage Range
5V
10 V
Bipolar Ranges
Analog Input CMRR
Input Current
Input Impedance
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
Time Between Conversions
Complete Cycle
Throughput Rate
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error2
Integral Linearity Error
No Missing Codes
Differential Linearity Error2
Transition Noise
Unipolar Zero Error
Bipolar Zero Error
Zero Error Temperature Drift
Bipolar Full-Scale Error
Unipolar Full-Scale Error
Full-Scale Error Temperature Drift
Power Supply Sensitivity
AC ACCURACY
Dynamic Range
Signal-to-Noise Ratio (SNR)
Signal-to-(Noise + Distortion), SINAD
Total Harmonic Distortion
Spurious-Free Dynamic Range
−3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Conditions/Comments
(VIN+) − (VIN−)
VIN = 10 V p-p
VIN = 20 V p-p
VIN = 20 V p-p
VIN = 40 V p-p
VIN+, VIN− to AGND
Min
18
Typ
Max
Unit
Bits
−VREF
−2 VREF
−2 VREF
−4 VREF
+VREF
+2 VREF
+2 VREF
+4 VREF
V
V
V
V
−0.1
−0.1
−5.1
−10.1
+5.1
+10.1
+5.1
+10.1
V
V
V
V
VREF/2 + 0.1
VREF + 0.2
+0.1
V
V
V
dB
μA
1.49
670
1
1.75
570
2.22
450
μs
kSPS
ms
μs
kSPS
μs
kSPS
+2.5
±0.5
3
LSB3
LSB
Bits
LSB
LSB
%FS
%FS
ppm/°C
%FS
%FS
ppm/°C
LSB
101.8
102.5
100.5
101
100
112
113
45
dB4
dB
dB
dB
dB
dB
dB
MHz
2
5
ns
ps rms
ns
VIN+, VIN−
VREF/2 − 0.1
VREF − 0.2
−0.1
fIN = 100 kHz
VIN = ±5 V, ±10 V @ 670 kSPS
See Analog Inputs section
In warp mode
In warp mode
In warp mode
In normal mode
In normal mode
In impulse mode
In impulse mode
VREF/2
VREF
0
75
2201
1
0
0
600 kSPS throughput
670 kSPS throughput
−2.5
±1.5
±1.5
18
−1
+ 2.5
0.75
−0.06
−0.03
+ 0.06
+ 0.03
±0.5
−0.09
−0.07
AVDD = 5 V ± 5%
VIN = 0 to 5 V, fIN = 2 kHz, −60 dB
VIN = all other input ranges, fIN = 2 kHz, −60 dB
VIN = 0 to 5 V, fIN = 2 kHz
VIN = all other input ranges, fIN = 2 kHz
fIN = 2 kHz
fIN = 2 kHz
fIN = 2 kHz
VIN = 0 V to 5 V
Full-scale step
100
100
98.5
98.5
+0.09
+0.07
500
Rev. B | Page 3 of 32
AD7634
Parameter
INTERNAL REFERENCE
Output Voltage
Temperature Drift
Line Regulation
Long-Term Drift
Turn-On Settling Time
REFERENCE BUFFER
REFBUFIN Input Voltage Range
EXTERNAL REFERENCE
Voltage Range
Current Drain
TEMPERATURE PIN
Voltage Output
Temperature Sensitivity
Output Resistance
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay5
VOL
VOH
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
VCC
VEE
Operating Current7, 8
AVDD
With Internal Reference
With Internal Reference Disabled
DVDD
OVDD
VCC
VEE
Power Dissipation
With Internal Reference
With Internal Reference Disabled
In Power-Down Mode9
TEMPERATURE RANGE10
Specified Performance
Data Sheet
Conditions/Comments
PDREF = PDBUF = low
REF @ 25°C
−40°C to +85°C
AVDD = 5 V ± 5%
1000 hours
CREF = 22 μF
PDREF = high
PDREF = PDBUF = high
REF
670 kSPS throughput
Min
Typ
Max
Unit
4.965
5.000
±3
±15
50
10
5.035
V
ppm/°C
ppm/V
ppm
ms
2.4
2.5
2.6
V
4.75
5
250
AVDD + 0.1
V
μA
@ 25°C
311
1
4.33
−0.3
2.1
−1
−1
mV
mV/°C
kΩ
+0.6
OVDD + 0.3
+1
+1
V
V
μA
μA
0.4
V
V
5.25
5.25
5.25
15.75
0
V
V
V
V
V
Parallel or serial 18-bit
ISINK = 500 μA
ISOURCE = –500 μA
OVDD − 0.6
4.756
4.75
2.7
7
−15.75
5
5
15
−15
@ 670 kSPS throughput
18.2
16.5
7.1
0.3
2.9
2
2
VCC = 15 V, with internal reference buffer
VCC = 15 V
VEE = −15 V
@ 670 kSPS throughput
PDREF = PDBUF = low
PDREF = PDBUF = high
PD = high
TMIN to TMAX
195
175
10
−40
1
mA
mA
mA
mA
mA
mA
mA
225
205
mW
mW
μW
+85
°C
With VIN = unipolar 5 V or unipolar 10 V ranges, the input current is typically 70 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section.
Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.
LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.
4
All specifications in decibels are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5
Conversion results are available immediately after completed conversion.
6
4.75 V or VREF – 0.1 V, whichever is larger.
7
Tested in parallel reading mode.
8
With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.
9
With all digital inputs forced to OVDD.
10
Consult sales for extended temperature range.
2
3
Rev. B | Page 4 of 32
Data Sheet
AD7634
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET (See Figure 35 and Figure 36)
Convert Pulse Width
Time Between Conversions
Warp Mode/Normal Mode/Impulse Mode1
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Warp Mode/Normal Mode/Impulse Mode
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Warp Mode/Normal Mode/Impulse Mode
Acquisition Time, All modes
RESET Pulse Width
PARALLEL INTERFACE MODES (See Figure 37 and Figure 39)
CNVST Low to Data Valid Delay
Warp Mode/Normal Mode/Impulse Mode
Data Valid to BUSY Low Delay
Bus Access Request to Data Valid
Bus Relinquish Time
MASTER SERIAL INTERFACE MODES2 (See Figure 41 and Figure 42)
CS Low to SYNC Valid Delay
CS Low to Internal SDCLK Valid Delay2
CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert
Warp Mode/Normal Mode/Impulse Mode
SYNC Asserted to SDCLK First Edge Delay
Internal SDCLK Period3
Internal SDCLK High3
Internal SDCLK Low3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SDCLK Last Edge to SYNC Delay3
CS High to SYNC High-Z
CS High to Internal SDCLK High-Z
CS High to SDOUT High-Z
BUSY High in Master Serial Read After Convert3
CNVST Low to SYNC Delay Read After Convert
Warp Mode/Normal Mode/Impulse Mode
SYNC Deasserted to BUSY Low Delay
Symbol
Min
t1
t2
10
Typ
Max
ns
1.49/1.75/2.22
t3
t4
35
t5
t6
t7
10
t8
t9
310
10
Unit
μs
ns
1.18/1.43/1.68
μs
ns
ns
1.18/1.43/1.68
μs
ns
ns
1.15/1.40/1.65
40
15
μs
ns
ns
ns
10
10
10
ns
ns
ns
2
t10
t11
t12
t13
20
2
t14
t15
t16
t17
50/290/530
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
Rev. B | Page 5 of 32
3
30
15
10
4
5
5
45
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Table 4
1.1/1.3/1.5
25
μs
ns
AD7634
Data Sheet
Parameter
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES2
(See Figure 44, Figure 45, and Figure 47)
External SDCLK, SCCLK Setup Time
External SDCLK Active Edge to SDOUT Delay
SDIN/SCIN Setup Time
SDIN/SCIN Hold Time
External SDCLK/SCCLK Period
External SDCLK/SCCLK High
External SDCLK/SCCLK Low
Symbol
Min
t31
t32
t33
t34
t35
t36
t37
5
2
5
5
25
10
10
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
18
1
In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
2
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
SYNC to SDCLK First Edge Delay Minimum
Internal SDCLK Period Minimum
Internal SDCLK Period Maximum
Internal SDCLK High Minimum
Internal SDCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SDCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum
Warp Mode
Normal Mode
Impulse Mode
1.6mA
0
0
3
30
45
15
10
4
5
5
0
1
20
60
90
30
25
20
8
7
1
0
20
120
180
60
55
20
35
35
1
1
20
240
360
120
115
20
90
90
Unit
ns
ns
ns
ns
ns
ns
ns
ns
1.98
2.23
2.48
2.78
3.03
3.28
4.34
4.59
4.84
7.46
7.71
7.96
μs
μs
μs
IOL
1.4V
CL
60pF
2V
0.8V
IOH
NOTES
1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK,
AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
tDELAY
tDELAY
2V
0.8V
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SDCLK Outputs, CL = 10 pF
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
Rev. B | Page 6 of 32
06406-003
500µA
06406-002
TO OUTPUT
PIN
Symbol
t18
t19
t19
t20
t21
t22
t23
t24
t28
Data Sheet
AD7634
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Analog Inputs/Outputs
IN+1, IN−1 to AGND
REF, REFBUFIN, TEMP,
REFGND to AGND
Ground Voltage Differences
AGND, DGND, OGND
Supply Voltages
AVDD, DVDD, OVDD
AVDD to DVDD, AVDD to OVDD
DVDD to OVDD
VCC to AGND, DGND
VEE to GND
Digital Inputs
PDREF, PDBUF
Internal Power Dissipation2
Internal Power Dissipation3
Junction Temperature
Storage Temperature Range
Rating
VEE − 0.3 V to VCC + 0.3 V
AVDD + 0.3 V to
AGND − 0.3 V
±0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−0.3 V to +7 V
±7 V
±7 V
–0.3 V to +16.5 V
+0.3 V to −16.5 V
−0.3 V to OVDD + 0 .3 V
±20 mA
700 mW
2.5 W
125°C
−65°C to +125°C
1
See the Analog Inputs section.
Specification is for the device in free air: 48-lead LFQP; θJA = 91°C/W,
θJC = 30°C/W.
3
Specification is for the device in free air: 48-lead LFCSP; θJA = 26°C/W.
2
Rev. B | Page 7 of 32
AD7634
Data Sheet
48 47 46 45 44 43 42
REF
IN–
REFGND
VCC
VEE
IN+
AGND
AVDD
TEMP
REFBUFIN
PDREF
PDBUF
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
41 40 39 38 37
36
BIPOLAR
35
CNVST
3
34
PD
4
33
RESET
D0/OB/2C 5
32
CS
31
RD
30
TEN
8
29
BUSY
D2/A1 9
28
D17/SCCS
D3 10
27
D16/SCCLK
D4/DIVSCLK[0] 11
26
D15/SCIN
D5/DIVSCLK[1] 12
25
D14/HW/SW
AGND 1
AVDD
2
MODE0
MODE1
WARP
PIN 1
AD7634
6
TOP VIEW
(Not to Scale)
IMPULSE 7
D1/A0
06406-004
D13/RDERROR
D12/SYNC
D11/SDCLK
DGND
D10/SDOUT
DVDD
OVDD
OGND
D9/RDC/SDIN
D8/INVSCLK
D6/EXT/INT
D7/INVSYNC
13 14 15 16 17 18 19 20 21 22 23 24
NOTES
1. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED PAD
SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT REQUIRED TO
MEET THE ELECTRICAL PERFORMANCES.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1, 42
Mnemonic
AGND
Type1
P
2, 44
3, 4
AVDD
MODE[0:1]
P
DI
5
D0/OB/2C
DI/O2
6
WARP
DI2
7
IMPULSE
DI2
Description
Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to AGND and should be connected to the analog ground plane of the system. In addition, the
AGND, DGND, and OGND voltages should be at the same potential.
Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors.
Data Input/Output Interface Mode Selection.
Interface Mode
MODE1
MODE0
Description
0
Low
Low
18-bit interface
1
Low
High
16-bit interface
2
High
Low
8-bit (byte) interface
3
High
High
Serial interface
In 18-bit parallel mode, this output is used as Bit 0 of the parallel port data output bus and the data
coding is straight binary. In all other modes, this pin allows the choice of straight binary or twos
complement.
When OB/2C = high, the digital output is straight binary
When OB/2C = low, the MSB is inverted resulting in a twos complement output from its internal shift
register.
Conversion Mode Selection. See the Modes of Operation section for a more detailed description. Used
in conjunction with the IMPULSE input per the following:
Conversion Mode
WARP
IMPULSE
Normal
Low
Low
Impulse
Low
High
Warp
High
Low
Normal
High
High
Conversion Mode Selection. See the WARP pin description in this table. See the Modes of Operation
section for a more detailed description.
Rev. B | Page 8 of 32
Data Sheet
AD7634
Pin No.
8
Mnemonic
D1/A0
Type1
DI/O
9
D2/A1
DI/O
10
D3
DO
11, 12
D[4:5] or
DIVSCLK[0:1]
DI/O
13
D6 or
EXT/INT
DO/I
14
D7 or
INVSYNC
DI/O
15
D8 or
INVSCLK
DI/O
16
D9 or
RDC or
DI/O
SDIN
17
OGND
P
18
OVDD
P
19
DVDD
P
20
DGND
P
21
D10 or
SDOUT
DI/O
Description
When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this
input pin controls the form in which data is output as shown in Table 7.
When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus.
When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus.
This pin is always an output, regardless of the interface mode.
When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
When MODE[1:0] = 3, serial data clock division selection. When using serial master read after convert
mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally
generated serial clock that clocks the data output. In other serial modes, these pins are high
impedance outputs.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Data Clock Source Select. In serial mode, this input is used to select
the internally generated (master) or external (slave) serial data clock for the AD7634 output data.
When EXT/INT = low (master mode), the internal serial data clock is selected on SDCLK output.
When EXT/INT = high (slave mode), the output data is synchronized to an external clock signal (gated by CS)
connected to the SDCLK input.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Data Invert Sync Select. In serial master mode (MODE[1:0] = 3,
EXT/INT = low), this input is used to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus.
When MODE[1:0] = 3, Invert SDCLK/SCCLK Select. This input is used to invert both SDCLK and SCCLK.
When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.
When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 9 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Data Read During Convert. In serial master mode (MODE[1:0] = 3,
EXT/INT = low), RDC is used to select the read mode. See the Master Serial Interface section.
When RDC = low, the current result is read after conversion. Note the maximum throughput is not
attainable in this mode.
When RDC = high, the previous conversion result is read during the current conversion.
When MODE[1:0] = 3, Serial Data In. In serial slave mode (MODE[1:0] = 3, EXT/INT = high), SDIN can be
used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT
line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation
of the read sequence.
Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be
connected to the system digital ground ideally at the same potential as AGND and DGND.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface
2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors.
Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be
supplied from AVDD.
Digital Power Ground. Ground reference point for digital outputs. Should be connected to system
digital ground ideally at the same potential as AGND and OGND.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Data Output. In all serial modes, this pin is used as the serial data output
synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7634 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C.
When EXT/INT = low (master mode), SDOUT is valid on both edges of SDCLK.
When EXT/INT = high (slave mode):
When INVSCLK = low, SDOUT is updated on SDCLK rising edge.
When INVSCLK = high, SDOUT is updated on SDCLK falling edge.
Rev. B | Page 9 of 32
AD7634
Data Sheet
Pin No.
22
Mnemonic
D11 or
SDCLK
Type1
DI/O
23
D12 or
SYNC
DO
24
D13 or
RDERROR
DO
25
D14 or
HW/SW
DI/O
26
D15 or
SCIN
DI/O
27
D16 or
SCCLK
DI/O
28
D17 or
SCCS
DI/O
29
BUSY
DO
30
TEN
DI2
31
32
RD
CS
DI
DI
33
RESET
DI
34
PD
DI2
35
CNVST
DI
Description
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Data Clock. In all serial modes, this pin is used as the serial data clock input
or output, dependent on the logic state of the EXT/INT pin. The active edge where the data SDOUT is
updated depends on the logic state of the INVSCLK pin.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Data Frame Synchronization. In serial master mode (MODE[1:0] = 3,
EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal
data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the
SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the
SDOUT output is valid.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Data Read Error. In serial slave mode (MODE[1:0] = 3, EXT/INT = high), this
output is used as an incomplete data read error flag. If a data read is started and not completed when
the current conversion is completed, the current data is lost and RDERROR is pulsed high.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 14 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Configuration Hardware/Software Select. In serial mode, this input is used
to configure the AD7634 by hardware or software. See the Hardware Configuration section and
Software Configuration section.
When HW/SW = low, the AD7634 is configured through software using the serial configuration register.
When HW/SW = high, the AD7634 is configured through dedicated hardware input pins.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 15 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Configuration Data Input. In serial software configuration mode (HW/SW =
low), this input is used to serially write in, MSB first, the configuration data into the serial configuration
register. The data on this input is latched with SCCLK. See the Software Configuration section.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 16 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Configuration Clock. In serial software configuration mode (HW/SW = low),
this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated
depends on the logic state of the INVSCLK pin. See the Software Configuration section.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 17 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Configuration Chip Select. In serial software configuration mode
(HW/SW = low), this input enables the serial configuration port. See the Software Configuration section.
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is completed and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal. Note that in master read after convert mode (MODE[1:0] = 3,
EXT/INT = low, RDC = low), the busy time changes according to Table 4.
Input Range Select. Used in conjunction with BIPOLAR per the following:
Input Range
BIPOLAR
TEN
0 V to 5 V
Low
Low
0 V to 10 V
Low
High
±5 V
High
Low
±10 V
High
High
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock in slave serial mode (not used for serial configurable port).
Reset Input. When high, reset the AD7634. Current conversion, if any, is aborted. The falling edge of
RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See
the Digital Interface section. If not used, this pin can be tied to OGND.
Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed. The digital interface remains active
during power down.
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
Rev. B | Page 10 of 32
Data Sheet
AD7634
Pin No.
36
37
Mnemonic
BIPOLAR
REF
Type1
DI2
AO/I
38
39
REFGND
IN−
AI
AI
40
41
43
VCC
VEE
IN+
P
P
AI
45
TEMP
AO
46
REFBUFIN
AI
47
PDREF
DI
48
PDBUF
DI
49
EPAD3
NC
Description
Input Range Select. See description for Pin 30.
Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing
an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF capacitor is
required with or without the internal reference and buffer. See the Voltage Reference Input/Output
section.
Reference Input Analog Ground. Connected to analog ground plane.
Analog Input. Referenced to IN+.
In the 0 V to 5 V input range, IN− is between 0 V and VREF V centered about VREF/2. In the 0 V to 10 V
range, IN− is between 0 V and 2 VREF V centered about VREF.
In the ±5 V and ±10 V ranges, IN− is true bipolar up to ±2 VREF V (±5 V range) or ±4 VREF V (±10 V range)
and centered about 0 V.
In all ranges, IN− must be driven 180° out of phase with IN+.
High Voltage Positive Supply. Normally 7 V to 15 V.
High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges).
Analog Input. Referenced to IN−.
In the 0 V to 5 V input range, IN+ is between 0 V and VREF V centered about VREF /2. In the 0 V to 10 V
range, IN+ is between 0 V and 2 VREF V centered about VREF.
In the ±5 V and ±10 V ranges, IN+ is true bipolar up to ±2 VREF V (±5 V range) or ±4 VREF V (±10 V range)
and centered about 0 V.
In all ranges, IN+ must be driven 180° out of phase with IN−
Temperature Sensor Analog Output. When the internal reference is enabled (PDREF = PDBUF = low),
this pin outputs a voltage proportional to the temperature of the AD7634. See the Voltage Reference
Input/Output section.
Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low,
PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference
Input/Output section.
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down, and an external reference must be used.
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be
soldered to VEE.
1
AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power, NC = no internal
connection.
2
In serial configuration mode (MODE[1:0] = 3, HW/SW = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the
Hardware Configuration section and the Software Configuration section.
3
LFCSP_VQ package only.
Table 7. Data Bus Interface Definition
MODE
MODE1
MODE0
D0/OB/2C
D1/A0
D2/A1
D[3]
D[4:9]
D[10:11]
D[12:15]
D[16:17]
Description
0
1
0
0
0
1
R[0]
OB/2C
R[1]
A0 = 0
R[2]
R[2]
R[3]
R[3]
R[4:9]
R[4:9]
R[10:11]
R[10:11]
R[12:15]
R[12:15]
R[16:17]
R[16:17]
18-bit parallel
16-bit high word
1
0
1
OB/2C
A0 = 1
R[0]
R[1]
2
1
0
OB/2C
A0 = 0
A1 = 0
All High-Z
R[10:11]
R[12:15]
R[16:17]
8-bit high byte
2
1
0
OB/2C
A0 = 0
A1 = 1
All High-Z
R[2:3]
R[4:7]
R[8:9]
8-bit midbyte
R[0:1]
2
1
0
OB/2C
A0 = 1
A1 = 0
All High-Z
2
1
0
OB/2C
A0 = 1
A1 = 1
All High-Z
3
1
1
OB/2C
All High-Z
Rev. B | Page 11 of 32
All zeros
16-bit low word
All zeros
All zeros
Serial interface
R[0:1]
8-bit low byte
8-bit low byte
Serial interface
AD7634
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C.
2.5
2.5
POSITIVE INL = 1.40LSB
NEGATIVE INL = –1.10LSB
2.0
POSITIVE DNL = 1.28LSB
NEGATIVE DNL = –0.63LSB
2.0
1.5
1.5
0.5
DNL (LSB)
INL (LSB)
1.0
0
–0.5
–1.0
1.0
0.5
0
–1.5
0
65536
131072
262144
196608
CODE
–1.0
06406-005
–2.5
0
65536
131072
262144
196608
CODE
06406-008
–0.5
–2.0
Figure 8. Differential Nonlinearity vs. Code, Bipolar 10 V Range
Figure 5. Integral Nonlinearity vs. Code, Bipolar 10 V Range
180
120
NEGATIVE INL
POSITIVE INL
NEGATIVE DNL
POSITIVE DNL
160
100
NUMBER OF UNITS
NUMBER OF UNITS
140
80
60
40
120
100
80
60
40
20
–1.6
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
2.0
1.6
INL DISTRIBUTION (LSB)
0
–2.0
06406-006
0
–2.0
–1.6
–1.2
–0.8
–0.4
60000
70000
54874
σ = 0.80
59925
60000
0.4
0.8
1.2
2.0
1.6
Figure 9. Differential Nonlinearity Distribution, Bipolar 5 V Range
(288 Devices)
Figure 6. Integral Nonlinearity Distribution, Unipolar 10 V Range
(288 Devices)
56811
σ = 0.75
50000
50000
40000
32769
COUNTS
40000
34164
30000
30000
20000
20000
11838
10000
0
0
1FFFE
0
25
20000
2172
1997
20002
20004
20
20006
0
0
20008
CODE IN HEX
0
6901
0
1FFFC
0
5
1FFFE
349
294
20000
20002
20004
0
0
20006
CODE IN HEX
Figure 10. Histogram of 261,120 Conversions of a DC Input
at the Code Transition, Bipolar 5 V Range
Figure 7. Histogram of 261,120 Conversions of a DC Input
at the Code Center, Bipolar 5 V Range
Rev. B | Page 12 of 32
06406-010
10000
06406-007
COUNTS
0
DNL DISTRIBUTION (LSB)
06406-009
20
Data Sheet
AD7634
SNR, SINAD REFERRED TO FULL SCALE (dB)
–20
SNR = 98.3dB
THD = –116.8dB
SFDR = 121dB
SINAD = 97.8dB
–40
–60
–80
–100
–120
–140
–160
0
50
100
150
200
250
300
FREQUENCY (kHz)
100.5
–50
–40
–30
–20
–10
0
140
–80
120
–90
100
15.5
88
15.0
86
14.5
84
14.0
82
13.5
–100
80
–110
60
–120
40
10
–140
13.0
1000
100
06406-012
1
FREQUENCY (kHz)
20
THIRD
HARMONIC
1
10
0
1000
100
FREQUENCY (kHz)
Figure 15. THD, Harmonics, and SFDR vs. Frequency, Unipolar 5 V Range
Figure 12. SNR, SINAD, and ENOB vs. Frequency, Unipolar 5 V Range
103
103
102
0V TO 10V
102
±10V
0V TO 10V
±10V
101
SINAD (dB)
101
0V TO 5V
100
±5V
100
0V TO 5V
99
98
98
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
06406-013
99
97
–55
SECOND
HARMONIC
THD
SFDR (dB)
16.0
90
06406-015
92
THD, HARMONICS (dB)
16.5
SINAD
ENOB
–130
SNR (dB)
0V TO 5V
17.0
ENOB (Bits)
SNR, SINAD (dB)
101.0
SFDR
17.5
94
80
0V TO 10V
101.5
–70
SNR
96
102.0
Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale)
18.0
98
±10V
±5V
INPUT LEVEL (dB)
Figure 11. FFT 20 kHz, Bipolar 5 V Range, Internal Reference
100
102.5
100.0
–60
06406-011
–180
SNR
SINAD
97
–55
±5V
–35
–15
5
25
45
65
85
TEMPERATURE (°C)
Figure 16. SINAD vs. Temperature
Figure 13. SNR vs. Temperature
Rev. B | Page 13 of 32
105
125
06406-016
AMPLITUDE (dB OF FULL SCALE)
103.0
fS = 670kSPS
fIN = 20.1kHz
06406-014
0
Data Sheet
–100
128
–104
124
–108
120
±5V
–112
SFDR (dB)
THD (dB)
AD7634
±10V
–116
0V TO 5V
0V TO 10V
116
±10V
±5V
112
0V TO 5V
108
–120
0V TO 10V
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
100
–55
06406-017
–128
–55
–15
5
25
45
65
85
125
105
TEMPERATURE (°C)
Figure 20. SFDR vs. Temperature (Excludes Harmonics)
Figure 17. THD vs. Temperature
5.0080
20
16
5.0060
ZERO/OFFSET ERROR
12
5.0040
8
4
5.0020
0
VREF (V)
POSITIVE
FULL-SCALE ERROR
–4
5.0000
4.9980
–8
4.9960
NEGATIVE
FULL-SCALE ERROR
–12
–20
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
4.9920
–55
Figure 18. Zero/Offset Error, Positive and Negative Full-Scale Error vs.
Temperature, All Normalized to 25°C
60
–35
–15
5
25
45
65
85
125
105
TEMPERATURE (°C)
06406-021
4.9940
–16
06406-018
ZERO/OFFSET ERROR, FULL-SCALE ERROR (LSB)
–35
06406-020
104
–124
Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices)
100000
AVDD, WARP/NORMAL
10000
DVDD, ALL MODES
OPERATING CURRENTS (µA)
NUMBER OF UNITS
50
40
30
20
10
1000
100
10
AVDD, IMPULSE
VCC +15V
VEE –15V
ALL MODES
1
0.1
OVDD, ALL MODES
0
1
2
3
4
5
6
REFERENCE DRIFT (ppm/°C)
7
8
Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices)
Rev. B | Page 14 of 32
0.001
10
PDREF = PDBUF = HIGH
100
1000
10000
100000
SAMPLING RATE (SPS)
Figure 22. Operating Currents vs. Sample Rate
1000000
06406-022
0
06406-049
0.01
Data Sheet
50
PD = PDBUF = PDREF = HIGH
OVDD = 2.7V @ 85°C
45
600
OVDD = 2.7V @ 25°C
40
500
400
t12 DELAY (ns)
35
VEE, –15V
VCC, +15V
DVDD
OVDD
AVDD
300
30
25
OVDD = 5V @ 85°C
20
OVDD = 5V @ 25°C
15
200
10
100
0
–35
–15
5
25
45
65
85
105
TEMPERATURE (°C)
0
50
100
150
CL (pF)
Figure 24. Typical Delay vs. Load Capacitance CL
Figure 23. Power-Down Operating Currents vs. Temperature
Rev. B | Page 15 of 32
200
06406-024
0
–55
5
06406-023
POWER-DOWN OPERATING CURRENTS (nA)
700
AD7634
AD7634
Data Sheet
TERMINOLOGY
Least Significant Bit (LSB)
Total Harmonic Distortion (THD)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For a fully differential input
ADC with N bits of resolution, the LSB expressed in volts is
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
LSB (V )
Signal-to-(Noise + Distortion) Ratio (SINAD)
V INp-p
2N
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive fullscale. The point used as negative full scale occurs a ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSBs beyond the last code transition. The deviation is measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Bipolar Zero Error
The difference between the ideal midscale input voltage (0 V)
and the actual voltage producing the midscale output code.
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
ENOB = [(SINADdB − 1.76)/6.02]
Aperture Delay
Aperture delay is a measure of the acquisition performance
measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
Unipolar Offset Error
The first transition should occur at a level ½ LSB above analog
ground. The unipolar offset error is the deviation of the actual
transition from that point.
Full-Scale Error
The last transition (from 111…10 to 111…11 in straight binary
format) should occur for an analog voltage 1½ LSB below the
nominal full-scale. The full-scale error is the deviation in LSB
(or % of full-scale range) of the actual level of the last transition
from the ideal level and includes the effect of the offset error.
Closely related is the gain error (also in LSB or % of full-scale
range), which does not include the effects of the offset error.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured for an input typically at −60 dB. The
value for dynamic range is expressed in decibels.
The time required for the AD7634 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at
the maximum and minimum reference output voltage (VREF)
measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as
TCVREF ( ppm/C )
VREF ( Max ) – VREF ( Min )
VREF ( 25C ) ( TMAX – TMIN )
10 6
where:
VREF (Max) = maximum VREF at TMIN, T(25°C), or TMAX.
VREF (Min) = minimum VREF at TMIN, T(25°C), or TMAX.
VREF (25°C) = VREF at 25°C.
TMAX = +85°C.
TMIN = –40°C.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Rev. B | Page 16 of 32
Data Sheet
AD7634
THEORY OF OPERATION
IN+
AGND
LSB
MSB
131,072C
65,536C
4C
2C
C
SW+
SWITCHES
CONTROL
C
BUSY
REF
COMP
REFGND
4C
2C
MSB
C
OUTPUT
CODE
C
SW–
LSB
CNVST
AGND
IN–
06406-025
131,072C 65,536C
CONTROL
LOGIC
Figure 25. ADC Simplified Schematic
OVERVIEW
CONVERTER OPERATION
The AD7634 is a very fast, low power, precise, 18-bit ADC using
successive approximation capacitive digital-to-analog (CDAC)
architecture.
The AD7634 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The CDAC consists of two identical
arrays of 18 binary weighted capacitors, which are connected
to the two comparator inputs.
The AD7634 can be configured at any time for one of four input
ranges and conversion mode with inputs in parallel and serial
hardware modes or by a dedicated write-only, SPI-compatible
interface via a configuration register in serial software mode.
The AD7634 uses Analog Devices’ patented iCMOS high voltage process to accommodate 0 V to +5 V (10 V p-p), 0 V to
+10 V (20 V p-p), ±5 V (20 V p-p), and ±10 V (40 V p-p) input
ranges on the fully differential IN+ and IN− inputs without the
use of conventional thin films. Only one acquisition cycle, t8, is
required for the inputs to latch to the correct configuration. Resetting or power cycling is not required for reconfiguring the ADC.
The AD7634 features different modes to optimize performance
according to the applications. It is capable of converting 670,000
samples per second (670 kSPS) in warp mode, 570 kSPS in normal
mode, and 450 kSPS in impulse mode.
The AD7634 provides the user with an on-chip, track-and-hold,
successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple, multiplexed channel
applications.
For unipolar input ranges, the AD7634 typically requires three
supplies: VCC, AVDD (which can supply DVDD), and OVDD
(which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic).
For bipolar input ranges, the AD7634 requires the use of the
additional VEE supply.
The device is housed in a Pb-free, 48-lead LQFP or a 48-lead
tiny LFCSP (7 mm × 7 mm) that combine space savings with
flexibility. In addition, the AD7634 can be configured as either
a parallel or serial SPI-compatible interface.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW−.
All independent switches are connected to the analog inputs. Thus,
the capacitor arrays are used as sampling capacitors and acquire
the analog signal on IN+ and IN− inputs. A conversion phase is
initiated once the acquisition phase is completed and the CNVST
input goes low. When the conversion phase begins, SW+ and SW−
are opened first. The two capacitor arrays are then disconnected
from the inputs and connected to the REFGND input. Therefore,
the differential voltage between the inputs (IN+ and IN−) captured
at the end of the acquisition phase is applied to the comparator
inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and
REF, the comparator input varies by binary weighted voltage
steps (VREF/2, VREF/4 through VREF/ 262,144). The control logic
toggles these switches, starting with the MSB first, to bring the
comparator back into a balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings the BUSY output low.
MODES OF OPERATION
The AD7634 features three modes of operation: warp, normal,
and impulse. Each of these modes is more suitable to specific
applications. The mode is configured with the input pins, WARP
and IMPULSE, or via the configuration register. See Table 6 for
the pin details; see the Hardware Configuration section and the
Software Configuration section for programming the mode
selection with either pins or configuration register. Note that
when using the configuration register, the WARP and IMPULSE
inputs are don’t cares and should be tied to either high or low.
Rev. B | Page 17 of 32
AD7634
Data Sheet
Warp Mode
TRANSFER FUNCTIONS
Except in 18-bit parallel interface mode, using the D0/OB/2C
digital input or via the configuration register, the AD7634 offers
two output codings: straight binary and twos complement. See
Figure 26 and Table 8 for the ideal transfer characteristic and
digital output codes for the different analog input ranges, VIN.
Note that when using the configuration register, the D0/OB/2C
input is a don’t care and should be tied to either high or low.
Setting WARP = IMPULSE = low or WARP = IMPULSE = high
allows the fastest mode (570 kSPS) without any limitation on
time between conversions. This mode makes the AD7634 ideal
for asynchronous applications such as data acquisition systems,
where both high accuracy and fast sample rate are required.
Impulse Mode
Setting WARP = low and IMPULSE = high uses the lowest power
dissipation mode and allows power savings between conversions. The maximum throughput in this mode is 450 kSPS, and
in this mode, the ADC powers down circuits after conversion,
making the AD7634 ideal for battery-powered applications.
111...111
111...110
111...101
000...010
000...001
000...000
–FSR
–FSR + 1 LSB
–FSR + 0.5 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
06406-026
Normal Mode
ADC CODE (Straight Binary)
Setting WARP = high and IMPULSE = low allows the fastest
conversion rate of up to 670 kSPS. However, in this mode, the
full-specified accuracy is guaranteed only when the time between
conversions does not exceed 1 ms. If the time between two
consecutive conversions is longer than 1 ms (after power-up),
the first conversion result should be ignored because in warp mode,
the ADC performs a background calibration during the SAR
conversion process. This calibration can drift if the time between
conversions exceeds 1 ms thus causing the first conversion to
appear offset. This mode makes the AD7634 ideal for applications
where both high accuracy and fast sample rate are required.
Figure 26. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description
FSR − 1 LSB
FSR − 2 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
1
2
VIN = 0 V to +5 V
(10 V p-p)
+4.999962 V
+4.999924 V
+38.15 μV
0V
−38.15 μV
−4.999962 V
−5 V
VREF = 5 V
VIN = 0 V to +10 V
VIN = ±5 V
(20 V p-p)
(20 V p-p)
+9.999924 V
+9.999924 V
+9.999847 V
+9.999847 V
−76.29 μV
−76.29 μV
0V
0V
−76.29 μV
−76.29 μV
−9.999924 V
−9.999924 V
−10 V
−10 V
This is also the code for overrange analog input.
This is also the code for underrange analog input.
Rev. B | Page 18 of 32
Digital Output Code
VIN = ±10 V
(40 V p-p)
+19.999847 V
+19.999695 V
+152.59 μV
0V
−152.59 μV
−19.999847 V
−20 V
Straight Binary
0x3FFFF1
0x3FFFE
0x20001
0x20000
0x1FFFF
0x00001
0x000002
Twos Complement
0x1FFFF1
0x1FFFE
0x00001
0x00000
0x3FFFF
0x20001
0x200002
Data Sheet
AD7634
TYPICAL CONNECTION DIAGRAM
Figure 27 shows a typical connection diagram for the AD7634 using the internal reference, serial data interface, and serial configuration
port. Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections.
DIGITAL
SUPPLY (5V)
NOTE 5
DIGITAL
INTERFACE
SUPPLY
(2.5V, 3.3V, OR 5V)
10Ω
ANALOG
SUPPLY (5V)
10µF
100nF
10µF
AVDD
+7V TO +15.75V
SUPPLY
10µF
100nF
10µF
100nF
AGND
100nF
10µF
100nF
DGND
DVDD
OVDD
VCC
OGND
MicroConverter ®/
MICROPROCESSOR/
DSP
BUSY
SDCLK
–7V TO –15.75V
SUPPLY
SERIAL
PORT 1
SDOUT
SCCLK
VEE
SERIAL
PORT 2
SCIN
NOTE 6
REF
NOTE 4
CREF
22µF
100nF
NOTE 3
SCCS
REFBUFIN
REFGND
33Ω
NOTE 7
CNVST
AD7634
D
D0/OB/2C
NOTE 2
ANALOG
INPUT+
U1
15Ω
MODE[1:0]
IN+
OVDD
HW/SW
BIPOLAR
CC
2.7nF
TEN
WARP
IN–
CLOCK
IMPULSE
NOTE 3
NOTE 2
ANALOG
INPUT–
U1
CC
NOTE 1
15Ω
PDREF PDBUF
PD
RD
CS RESET
2.7nF
AGND
DGND
NOTES
1. ANALOG INPUTS ARE DIFFERENTIAL (ANTIPHASE). SEE ANALOG INPUTS SECTION.
2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT/OUTPUT SECTION.
4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M).
SEE VOLTAGE REFERENCE INPUT/OUTPUT SECTION.
5. OPTIONAL, SEE POWER SUPPLIES SECTION.
6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) + 2V] AND VEE = [VIN(MIN) – 2V] FOR BIPOLAR INPUT RANGES.
FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLIES SECTION.
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
8. A SEPARATE ANALOG AND DIGITAL GROUND PLANE IS RECOMMENDED, CONNECTED TOGETHER DIRECTLY UNDER THE ADC.
SEE LAYOUT GUIDELINES SECTION.
Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port
Rev. B | Page 19 of 32
06406-027
NOTE 8
AD7634
Data Sheet
120
ANALOG INPUTS
0V TO 10V
Input Range Selection
100
±5V
0V TO 5V
80
±10V
CMRR (dB)
In parallel mode and serial hardware mode, the input range is
selected by using the BIPOLAR (bipolar) and TEN (10 V range)
inputs. See Table 6 for pin details; see the Hardware Configuration
section and the Software Configuration section for programming the mode selection with either pins or configuration
register. Note that when using the configuration register, the
BIPOLAR and TEN inputs are don’t cares and should be tied
to either high or low.
60
40
20
0
Figure 28 shows an equivalent circuit for the input structure of
the AD7634.
1
10
0V TO 5V
RANGE ONLY
CPIN
D2
D4
RIN
10000
CIN
VEE
AGND
Figure 28. AD7634 Simplified Analog Input
The four diodes, D1 to D4, provide ESD protection for the analog
inputs, IN+ and IN−. Care must be taken to ensure that the analog
input signal never exceeds the supply rails by more than 0.3 V,
because this causes the diodes to become forward-biased and
to start conducting current. These diodes can handle a forwardbiased current of 120 mA maximum. For instance, these conditions
could eventually occur when the input buffer’s U1 supplies are
different from AVDD, VCC, and VEE. In such a case, an input
buffer with a short-circuit current limitation can be used to protect
the part although most op amps’ short-circuit current is
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