Low Cost, 4-Channel, 16-Bit 1 MSPS
PulSAR ADC
AD7655-EP
Enhanced Product
FEATURES
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
AC motor control
3-phase power control
4-channel data acquisition
Uninterrupted power supplies
Communications
INA1
INAN
INA2
A0
INB1
INBN
INB2
PD
REFGND REFx
DVDD DGND
TRACK/HOLD
×2
OVDD
SERIAL
PORT 16
MUX
MUX
SWITCHED
CAP DAC
OGND
D[15:0]
SER/PAR
EOC
MUX
BUSY
CLOCK
PARALLEL
INTERFACE
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
RESET
CS
RD
A/B
AD7655-EP
IMPULSE
BYTESWAP
CNVST
Figure 1.
Table 1. PulSAR® Selection
Type/kSPS
Pseudo
Differential
100 to 250
AD7660/
AD7661
True Bipolar
True
Differential
18 Bit
Multichannel/
Simultaneous
AD7663
AD7675
AD7678
500 to 570
AD7650/
AD7652
AD7664/
AD7666
AD7665
AD7676
AD7679
AD7654
800 to
1000
AD7653
AD7667
AD7671
AD7677
AD7674
AD7655
>1000
AD7621
AD7623
AD7641
power applications, a reduced power mode (impulse) where the
power is scaled with the throughput. Operation is specified
from −55°C to +125°C.
GENERAL DESCRIPTION
The AD7655-EP is a low cost, simultaneous sampling, dualchannel, 16-bit, charge redistribution SAR, analog-to-digital
converter that operates from a single 5 V power supply. It
contains two low noise, wide bandwidth, track-and-hold
amplifiers that allow simultaneous sampling, a high speed
16-bit sampling ADC, an internal conversion clock, error
correction circuits, and both serial and parallel system interface
ports. Each track-and-hold has a multiplexer in front to provide
a 4-channel input ADC. The A0 multiplexer control input
allows the choice of simultaneously sampling input pairs
INA1/INB1 (A0 = low) or INA2/ INB2 (A0 = high). The part
features a very high sampling rate mode (normal) and, for low
Rev. B
AVDD AGND
09230-001
4-channel, 16-bit resolution ADC
2 track-and-hold amplifiers
Throughput
1 MSPS (normal mode)
888 kSPS (impulse mode)
Analog input voltage range: 0 V to 5 V
No pipeline delay
Parallel and serial 5 V/3 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 5 V supply operation
Power dissipation
120 mW typical
2.6 mW at 10 kSPS
48-lead frame chip scale package (LFCSP)
Pin-to-pin compatible with the AD7654
Low cost
Supports defense and aerospace applications (AQEC
standard)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
Product change notification
Qualification data available on request
Full details about this enhanced product are available in the
AD7655 data sheet, which should be consulted in conjunction
with this data sheet.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
Multichannel ADC.
The AD7655-EP features 4-channel inputs with two sampleand-hold circuits that allow simultaneous sampling.
Fast Throughput.
The AD7655-EP is a 1 MSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
Single-Supply Operation.
The AD7655-EP operates from a single 5 V supply. In impulse
mode, its power dissipation decreases with throughput.
Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangements
are compatible with both 3 V and 5 V logic.
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2010–2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD7655-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Timing Specifications ...................................................................5
Applications ....................................................................................... 1
Absolute Maximum Ratings ............................................................7
General Description ......................................................................... 1
ESD Caution...................................................................................7
Functional Block Diagram .............................................................. 1
Pin Configurations and Function Descriptions ............................8
Product Highlights ........................................................................... 1
Outline Dimensions ....................................................................... 11
Revision History ............................................................................... 2
Ordering Guide .......................................................................... 12
Specifications..................................................................................... 3
REVISION HISTORY
1/2018—Rev. A to Rev. B
Added CP-48-4 Package .................................................... Universal
Change to General Description Section ........................................ 1
Added Figure 5; Renumbered Sequentially .................................. 8
Changes to Figure 4 and Table 6 ..................................................... 8
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
2/2011—Rev. 0 to Rev. A
Removed LQFP from Features Section ......................................... 1
Removed Internal Power Dissipation (700 mW) from Table 5..... 7
7/2010—Revision 0: Initial Version
Rev. B | Page 2 of 12
Enhanced Product
AD7655-EP
SPECIFICATIONS
AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Common-Mode Input Voltage
Analog Input CMRR
Input Current
Input Impedance
THROUGHPUT SPEED
Complete Cycle (2 Channels)
Throughput Rate
Complete Cycle (2 Channels)
Throughput Rate
DC ACCURACY
Integral Linearity Error 1
No Missing Codes
Transition Noise
Full-Scale Error
Full-Scale Error Drift
Unipolar Zero Error
Unipolar Zero Error Drift
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-Noise and Distortion
Channel-to-Channel Isolation
−3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Aperture Delay Matching
Aperture Jitter
Transient Response
REFERENCE
External Reference Voltage Range
External Reference Current Drain
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format 4
Pipeline Delay 5
VOL
VOH
Conditions
Min
16
VINx – VINxN
VINxN
fIN = 100 kHz
1 MSPS throughput
0
−0.1
Normal mode
Normal mode
Impulse mode
Impulse mode
Typ
Max
Unit
Bits
2 VREF
+0.5
V
V
dB
µA
2
1
2.25
888
µs
MSPS
µs
kSPS
+6
±0.8
±0.8
LSB 2
Bits
LSB
% of FSR
ppm/°C
% of FSR
ppm/°C
LSB
86
98
−96
86
30
−92
10
dB 3
dB
dB
dB
dB
dB
MHz
2
30
5
ns
ps
ps rms
ns
55
45
0
0
−6
15
0.8
±0.25
±2
TMIN to TMAX
TMIN to TMAX
±0.5
±0.25
AVDD = 5 V ± 5%
fIN = 100 kHz
fIN = 100 kHz
fIN = 100 kHz
fIN = 100 kHz
fIN = 100 kHz, −60 dB input
fIN = 100 kHz
Full-scale step
250
2.3
1 MSPS throughput
−0.3
+2.0
−1
−1
ISINK = 1.6 mA
ISOURCE = −500 µA
Rev. B | Page 3 of 12
OVDD − 0.2
2.5
180
AVDD/2
V
µA
+0.8
DVDD + 0.3
+1
+1
V
V
µA
µA
0.4
V
V
AD7655-EP
Parameter
POWER SUPPLIES
Specified Performance
AVDD
Enhanced Product
Conditions
DVDD
OVDD
Operating Current 7
AVDD
DVDD
OVDD
Power Dissipation
TEMPERATURE RANGE 9
Specified Performance
Min
Typ
Max
Unit
4.75
4.75
5
5
5.25
5.25
V
V
5.25 6
V
2.7
1 MSPS throughput
15.5
8.5
100
120
2.6
114
1 MSPS throughput7
20 kSPS throughput 8
888 kSPS throughput8
TMIN to TMAX
−55
125
mA
mA
µA
mW
mW
mW
+125
°C
135
Linearity is tested using endpoints, not best fit.
LSB means least significant bit. With the 0 V to 5 V input range, 1 LSB is 76.294 µV.
All specifications in dB are referred to as full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.
4
Parallel or serial 16 bit.
5
Conversion results are available immediately after completed conversion.
6
The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.
7
In normal mode; tested in parallel reading mode.
8
In impulse mode; tested in parallel reading mode.
9
Consult sales for extended temperature range.
1
2
3
Rev. B | Page 4 of 12
Enhanced Product
AD7655-EP
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET
Convert Pulse Width
Time Between Conversions
(Normal Mode/Impulse Mode)
CNVST Low to BUSY High Delay
BUSY High All Modes Except in Master Serial Read After Convert Mode
(Normal Mode/Impulse Mode)
Aperture Delay
End of Conversions to BUSY Low Delay
Conversion Time
(Normal Mode/Impulse Mode)
Acquisition Time
RESET Pulse Width
CNVST Low to EOC High Delay
EOC High for Channel A Conversion
(Normal Mode/Impulse Mode)
EOC Low after Channel A Conversion
EOC High for Channel B Conversion
Channel Selection Setup Time
Channel Selection Hold Time
PARALLEL INTERFACE MODES
CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
A/B Low to Data Valid Delay
Symbol
Min
t1
5
t2
t3
2/2.25
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
MASTER SERIAL INTERFACE MODES
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay 1
CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert
(Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
Internal SCK Period 2
Internal SCLK High2
Internal SCLK Low2
SDOUT Valid Setup Time2
SDOUT Valid Hold Time2
SCLK Last Edge to SYNC Delay2
CS High to SYNC High-Z
CS High to Internal SCLK High-Z
CS High to SDOUT High-Z
BUSY High in Master Serial Read after Convert2
CNVST Low to SYNC Asserted Delay
(Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY Low Delay
Typ
t36
t37
Rev. B | Page 5 of 12
Unit
ns
32
µs
ns
ns
1.75/2
µs
ns
ns
ns
10
250
10
30
1/1.25
45
0.75
250
30
1.75/2
40
15
40
10
10
10
ns
ns
ns
250/500
3
23
12
7
4
2
1
µs
ns
µs
ns
ns
µs
ns
ns
ns
ns
14
5
µs
ns
1.75/2
2
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
t35
Max
40
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Table 4
0.75/1
25
µs
ns
AD7655-EP
Enhanced Product
Parameter
SLAVE SERIAL INTERFACE MODES
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
1
2
Symbol
Min
t38
t39
t40
t41
t42
t43
t44
5
3
5
5
25
10
10
Typ
Max
18
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise CL is 60 pF maximum.
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Table 4. Serial Clock Timings in Master Read After Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Typical
Internal SCLK High Minimum
Internal SCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum (Normal)
Busy High Width Maximum (Impulse)
Symbol
t25
t26
t26
t27
t28
t29
t30
t31
t35
t35
0
0
3
25
40
12
7
4
2
1
3.25
3.5
Rev. B | Page 6 of 12
0
1
17
50
70
22
21
18
4
3
4.25
4.5
1
0
17
100
140
50
49
18
30
30
6.25
6.5
1
1
17
200
280
100
99
18
80
80
10.75
11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Unit
ns
ns
ns
ns
ns
ns
ns
Enhanced Product
AD7655-EP
ABSOLUTE MAXIMUM RATINGS
1.6mA
Table 5.
1
TO OUTPUT
PIN C
L
60pF*
AVDD + 0.3 V to
AGND − 0.3 V
1.4V
500mA
±0.3 V
IOH
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
–0.3 V to +7 V
±7 V
−0.3 V to +7 V
−0.3 V to DVDD + 0.3 V
2.5 W
150°C
−65°C to +150°C
Figure 2. Load Circuit for Digital Interface Timing
2V
0.8V
tDELAY
tDELAY
2V
0.8V
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
300°C
Specification is for device in free air: 48-lead LFCSP, θJA = 26°C/W.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. B | Page 7 of 12
09230-003
Ground Voltage Differences
AGND, DGND, OGND
Supply Voltages
AVDD, DVDD, OVDD
AVDD to DVDD, AVDD to OVDD
DVDD to OVDD
Digital Inputs
Internal Power Dissipation
Junction Temperature
Storage Temperature Range1
Lead Temperature Range
(Soldering 10 sec)
Values
09230-002
Parameter
Analog Input
INAx, INBx, REFx, INxN, REFGND
IOL
AD7655-EP
Enhanced Product
24
18
19
20
21
22
23
AGND 1
AVDD 2
A0 3
BYTESWAP 4
A/B 5
DGND 6
IMPULSE 7
SER/PAR 8
D0 9
D1 10
D2/DIVSCLK[0] 11
D3/DIVSCLK[1] 12
AD7655-EP
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
DVDD
CNVST
PD
RESET
CS
RD
EOC
BUSY
D15
D14
D13
D12
NOTES
1. EXPOSED PAD. THE EPAD IS CONNECTED TO GROUND; HOWEVER, THIS CONNECTION
IS NOT REQUIRED TO MEET SPECIFIED PERFORMANCE.
09230-004
D4/EXT/INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OVDD
DVDD
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERROR
D4/EXT/INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OVDD
DVDD
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERROR
13
14
15
16
17
TOP VIEW
(Not to Scale)
PD
RESET
CS
RD
EOC
BUSY
D15
D14
D13
D12
NOTES
1. EXPOSED PAD. THE EPAD IS CONNECTED TO GROUND; HOWEVER, THIS CONNECTION
IS NOT REQUIRED TO MEET SPECIFIED PERFORMANCE.
Figure 4. 48-Lead LFCSP (CP-48-1)
09230-005
AD7655-EP
DVDD
CNVST
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
AGND 1
AVDD 2
A0 3
BYTESWAP 4
A/B 5
DGND 6
IMPULSE 7
SER/PAR 8
D0 9
D1 10
D2/DIVSCLK[0] 11
D3/DIVSCLK[1] 12
AGND
AGND
INA1
INAN
INA2
REFA
REFB
INB2
INBN
INB1
REFGND
REF
48
47
46
45
44
43
42
41
40
39
38
37
AGND
AGND
INA1
INAN
INA2
REFA
REFB
INB2
INBN
INB1
REFGND
REF
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. 48-Lead LFCSP (CP-48-4)
Table 6. Pin Function Descriptions
Pin No.
1, 47, 48
2
3
Mnemonic
AGND
AVDD
A0
Type1
P
P
DI
4
BYTESWAP
DI
5
A/B
DI
6, 20
7
DGND
IMPULSE
P
DI
8
SER/PAR
DI
9, 10
D[0:1]
DO
11, 12
D[2:3] or
DIVSCLK[0:1]
DI/O
13
D[4]
DI/O
or EXT/INT
Description
Analog Power Ground Pin.
Input Analog Power Pin. Nominally 5 V.
Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously, then
converted. When HIGH, the analog inputs INA2 and INB2 are sampled simultaneously, then converted.
Parallel Mode Selection (8 Bit, 16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
Data Channel Selection. In parallel mode, when LOW, the data from Channel B is read. When HIGH,
the data from Channel A is read. In serial mode, when HIGH, Channel A is output first followed by
Channel B. When LOW, Channel B is output first followed by Channel A.
Digital Power Ground.
Mode Selection. When HIGH, this input selects a reduced power mode. In this mode, the power
dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface
mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high
impedance.
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW, which is the serial master read after
convert mode. These inputs, part of the serial port, are used to slow down the internal serial clock that
clocks the data output. In the other serial modes, these inputs are not used.
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing
the internal or an external data clock called, respectively, master and slave mode. With EXT/INT tied
LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is
synchronized to an external clock signal connected to the SCLK input.
Rev. B | Page 8 of 12
Enhanced Product
AD7655-EP
Pin No.
14
Mnemonic
D[5]
or INVSYNC
Type1
DI/O
Description
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal in Master modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
15
D[6]
or INVSCLK
DI/O
16
D[7]
or RDC/SDIN
DI/O
17
18
OGND
OVDD
P
P
19, 36
21
DVDD
D[8]
or SDOUT
P
DO
22
D[9]
or SCLK
DI/O
23
D[10]
or SYNC
DO
24
D[11]
or RDERROR
DO
25 to 28
D[12:15]
DO
29
BUSY
DO
30
31
32
EOC
RD
CS
DO
DI
DI
33
RESET
DI
34
PD
DI
When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in
both master and slave modes.
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a
read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN can be used as a data input to daisy-chain the conversion results
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT
with a delay of 32 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the
previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output
on SDOUT only when the conversion is complete.
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface
(5 V or 3 V).
Digital Power. Nominally at 5 V.
When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized
to SCLK. Conversion results are stored in a 32-bit on-chip register. The AD7655-EP provides the two
conversion results, MSB first, from its internal shift register. The order of channel outputs is controlled
by A/B. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK.
In serial mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge.
When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,
depends upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated
depends on the logic state of the INVSCLK pin.
When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW).
When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and frames SDOUT. After
the first channel is output, SYNC is pulsed LOW. When a read sequence is initiated and INVSYNC is
HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. After the first channel is
output, SYNC is pulsed HIGH.
When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as an
incomplete read error flag. In slave mode, when a data read is started but not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
Bit 12 to Bit 15 of the parallel port data output bus. When SER/PAR is HIGH, these outputs are in high
impedance.
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the two
conversions are complete and the data is latched into the on-chip shift register. The falling edge of
BUSY can be used as a data ready clock signal.
End of Convert Output. Goes LOW at each channel conversion.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external serial clock.
Reset Input. When set to a logic HIGH, reset the AD7655-EP. Current conversion, if any, is aborted. If not
used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current conversion is completed.
Rev. B | Page 9 of 12
AD7655-EP
Enhanced Product
Pin No.
Mnemonic
Type 1
Description
35
CNVST
DI
37
38
39, 41
40, 45
42, 43
44, 46
REF
REFGND
INB1, INB2
INBN, INAN
REFB, REFA
INA2, INA1
EPAD
AI
AI
AI
AI
AI
AI
Start Conversion. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion. In impulse mode (IMPULSE = HIGH), if CNVST is held LOW when the acquisition
phase (t8) is complete, the internal sample-and-hold is put into the hold state and a conversion is
immediately started.
This input pin is used to provide a reference to the converter.
Reference Input Analog Ground.
Channel B Analog Inputs.
Analog Inputs Ground Senses. Allow to sense each channel ground independently.
These inputs are the references applied to Channel A and Channel B, respectively.
Channel A Analog Inputs.
Exposed Pad. The exposed pad is connected to ground; however, this connection is not required to
meet specified performance.
1
Al = input; DI = digital input; DO = digital output; DI/O = bidirectional digital; P = power.
Rev. B | Page 10 of 12
Enhanced Product
AD7655-EP
OUTLINE DIMENSIONS
7.10
7.00 SQ
6.90
0.30
0.23
0.18
0.60 MAX
0.60 MAX
37
48
1
36
PIN 1
INDICATOR
6.85
6.75 SQ
6.65
0.50
REF
5.25
5.10 SQ
4.95
EXPOSED
PAD
12
25
1.00
0.85
0.80
12° MAX
SIDE VIEW
5.50 REF
0.80 MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PKG-001049
SEATING
PLANE
0.20 MIN
BOTTOM VIEW
11-13-2017-B
TOP VIEW
13
24
0.50
0.40
0.30
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 6. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.85 mm Package Height
(CP-48-1)
Dimensions shown in millimeters
7.10
7.00 SQ
6.90
DETAIL A
(JEDEC 95)
0.30
0.23
0.18
PIN 1
INDICATOR
37
36
48
1
0.50
BSC
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
5.20
5.10 SQ
5.00
EXPOSED
PAD
12
0.80
0.75
0.70
PKG-004509
SEATING
PLANE
END VIEW
24
13
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4
Figure 7. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters
Rev. B | Page 11 of 12
0.20 MIN
5.50 REF
10-26-2017-C
TOP VIEW
0.45
0.40
0.35
AD7655-EP
Enhanced Product
ORDERING GUIDE
Model 1
AD7655SCP-EP-RL
AD7655SCPZ-EP-RL
1
Temperature Range
−55°C to +125°C
−55°C to +125°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09230-0-1/18(B)
Rev. B | Page 12 of 12
Package Option
CP-48-1
CP-48-4
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