AD7667

16-Bit, 750 kSPS, Unipolar/Bipolar Programmable Input PulSAR® ADC AD7612 FEATURES Multiple pins/software programmable input ranges: 5 V, 10 V, ±5 V, ±10 V Pins or serial SPI®-compatible input ranges/mode selection Throughput 750 kSPS (warp mode) 600 kSPS (normal mode) 500 kSPS (impulse mode) INL: ±0.75 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR) 16-bit resolution with no missing codes SNR: 92 minimum (5 V) @ 2 kHz, 94 dB typical (±10 V) @ 2 kHz THD: −107 dB typical iCMOS™ process technology 5 V internal reference: typical drift 3 ppm/°C; TEMP output No pipeline delay (SAR architecture) Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Power dissipation: 190 mW @ 750 kSPS Pb-free, 48-lead LQFP and LFCSP (7 mm × 7 mm) packages AGND AVDD PDREF PDBUF IN+ IN– SWITCHED CAP DAC REF FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND OVDD OGND REF AMP AD7612 SERIAL DATA PORT SERIAL CONFIGURATION 16 PORT D[15:0] SER/PAR BYTESWAP CNVST PD RESET CLOCK CONTROL LOGIC AND CALIBRATION CIRCUITRY PARALLEL INTERFACE OB/2C BUSY RD CS 06265-001 WARP IMPULSE BIPOLAR TEN Figure 1. Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection Type Pseudo Differential 100 kSPS to 250 kSPS AD7651 AD7660 AD7661 AD7663 AD7675 500 kSPS to 570 kSPS AD7650 AD7652 AD7664 AD7666 AD7665 AD7676 800 kSPS to 1000 kSPS AD7653 AD7667 >1000 kSPS APPLICATIONS Process control Medical instruments High speed data acquisition Digital signal processing Instrumentation Spectrum analysis ATE True Bipolar True Differential 18-Bit, True Differential Multichannel/ Simultaneous AD7612 AD7671 AD7677 AD7678 AD7679 AD7654 AD7655 AD7674 AD7621 AD7622 AD7623 AD7641 AD7643 GENERAL DESCRIPTION The AD7612 is a 16-bit charge redistribution successive approximation register (SAR), architecture analog-to-digital converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS high voltage process. The device is configured through hardware or via a dedicated write only serial configuration port for input range and operating mode. The AD7612 contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. A falling edge on CNVST samples the analog input on IN+ with respect to a ground sense, IN−. The AD7612 features four different analog input ranges and three different sampling modes: warp mode for the fastest throughput, normal mode for the fastest asynchronous throughput, and impulse mode where power consumption is scaled linearly with throughput. Operation is specified from −40°C to +85°C. PRODUCT HIGHLIGHTS 1. 2. 3. 4. Programmable input range and mode selection. Pins or serial port for selecting input range/mode select. Fast throughput. In warp mode, the AD7612 is 750 kSPS. Superior Linearity. No missing 16-bit code. ±1.5 LSB max INL. Internal Reference. 5 V internal reference with a typical drift of ±3 ppm/°C and an on-chip temperature sensor. Serial or Parallel Interface. Versatile parallel (16- or 8-bit bus) or 2-wire serial interface arrangement compatible with 3.3 V or 5 V logic. 5. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD7612 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 12 Terminology .................................................................................... 16 Theory of Operation ...................................................................... 17 Overview...................................................................................... 17 Converter Operation.................................................................. 17 Modes of Operation ................................................................... 18 Transfer Functions...................................................................... 18 Typical Connection Diagram ................................................... 19 Analog Inputs ............................................................................. 20 Driver Amplifier Choice ........................................................... 21 Voltage Reference Input/Output .............................................. 21 Power Supplies ............................................................................ 22 Conversion Control ................................................................... 23 Interfaces.......................................................................................... 24 Digital Interface.......................................................................... 24 Parallel Interface......................................................................... 24 Serial Interface ............................................................................ 25 Master Serial Interface............................................................... 25 Slave Serial Interface .................................................................. 27 Hardware Configuration ........................................................... 29 Software Configuration ............................................................. 29 Microprocessor Interfacing....................................................... 30 Application Information................................................................ 31 Layout Guidelines....................................................................... 31 Evaluating Performance ............................................................ 31 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7612 SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range, VIN Conditions/Comments Min 16 −0.1 −0.1 −5.1 −10.1 −0.1 75 220 1 Typ Max Unit Bits V V V V V dB μA Analog Input CMRR Input Current Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time Between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error 3 No Missing Codes3 Differential Linearity Error3 Transition Noise Zero Error (Unipolar or Bipolar) Zero Error Temperature Drift Bipolar Full-Scale Error Unipolar Full-Scale Error Full-Scale Error Temperature Drift Power Supply Sensitivity AC ACCURACY Dynamic Range VIN+ − VIN− = 0 V to 5 V VIN+ − VIN− = 0V to 10 V VIN+ − VIN− = ±5 V VIN+ − VIN− = ±10 V VIN− to AGND fIN = 100 kHz VIN = ±5 V, ±10 V @ 750 kSPS See Analog Inputs section In warp mode In warp mode In warp mode In normal mode In normal mode In impulse mode In impulse mode +5.1 +10.1 +5.1 +10.1 +0.1 1 0 0 −1.5 16 −1 −35 ±1 −50 −70 ±0.75 1.33 750 2 1 1.67 600 2 500 +1.5 +1.5 0.55 +35 +50 +70 ±1 3 μs kSPS ms μs kSPS μs kSPS LSB 4 Bits LSB LSB LSB ppm/°C LSB LSB ppm/°C LSB dB 5 dB dB dB dB dB dB dB dB dB MHz ns ps rms ns V ppm/°C ppm/V ppm ms AVDD = 5 V ± 5% VIN = 0 V to 5 V, fIN = 2 kHz, −60 dB VIN = 0 V to 10 V, ±5 V, fIN = 2 kHz, −60 dB VIN = ±10 V, fIN = 2 kHz, −60 dB VIN = 0 V to 5 V, 0 V to 10 V, fIN = 2 kHz VIN = ±5 V, ±10 V, fIN = 2 kHz VIN = ±5 V, fIN = 2 kHz VIN = 0 V to 10 V, ±5 V, fIN = 2 kHz VIN = ±10 V, fIN = 2 kHz fIN = 2 kHz fIN = 2 kHz VIN = 0 V to 5 V 92.5 Signal-to-Noise Ratio Signal-to-(Noise + Distortion) (SINAD) 92 Total Harmonic Distortion Spurious-Free Dynamic Range –3 dB Input Bandwidth Aperture Delay Aperture Jitter Transient Response INTERNAL REFERENCE Output Voltage Temperature Drift Line Regulation Long-Term Drift Turn-On Settling Time 93.5 94 94.5 93 94 92.5 93 93.5 −107 107 45 2 5 500 Full-scale step PDREF = PDBUF = low REF @ 25°C –40°C to +85°C AVDD = 5 V ± 5% 1000 hours CREF = 22 μF 4.965 5.000 ±3 ±15 50 10 5.035 Rev. 0 | Page 3 of 32 AD7612 Parameter REFERENCE BUFFER REFBUFIN Input Voltage Range EXTERNAL REFERENCE Voltage Range Current Drain TEMPERATURE PIN Voltage Output Temperature Sensitivity Output Resistance DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay 6 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD VCC VEE Operating Current 8 , 9 AVDD With Internal Reference With Internal Reference Disabled DVDD OVDD VCC VEE Power Dissipation With Internal Reference With Internal Reference Disabled In Power-Down Mode 10 TEMPERATURE RANGE 11 Specified Performance 1 2 3 Conditions/Comments PDREF = high PDREF = PDBUF = high REF 750 kSPS throughput @ 25°C Min 2.4 4.75 Typ 2.5 5 250 311 1 4.33 Max 2.6 AVDD + 0.1 Unit V V μA mV mV/°C kΩ −0.3 2.1 −1 −1 Parallel or serial 16-bit ISINK = 500 μA ISOURCE = –500 μA +0.6 OVDD + 0.3 +1 +1 V V μA μA 0.4 OVDD − 0.6 V V 4.75 7 4.75 2.7 7 −15.75 @ 750 kSPS throughput 5 5 15 −15 5.25 5.25 5.25 15.75 0 V V V V V VCC = 15 V, with internal reference buffer VCC = 15 V VEE = −15 V @ 750 kSPS throughput PDREF = PDBUF = low PDREF = PDBUF = high PD = high TMIN to TMAX −40 19.5 18 6.5 0.5 3 2.3 2 205 190 10 230 210 mA mA mA mA mA mA mA mW mW μW °C +85 With VIN = 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 70 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section. All specified performance is guaranteed up to 750 kSPS throughout, however throughputs up to 900 kSPS can be used with some linearity performance degradation. Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference. 4 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference. 5 All specifications in decibels are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 6 Conversion results are available immediately after completed conversion. 7 4.75 V or VREF – 0.1 V, whichever is larger. 8 Tested in parallel reading mode. 9 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low. 10 With all digital inputs forced to OVDD. 11 Consult sales for extended temperature range. Rev. 0 | Page 4 of 32 AD7612 TIMING SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter CONVERSION AND RESET (See Figure 33 and Figure 34) Convert Pulse Width Time Between Conversions Warp Mode/Normal Mode/Impulse Mode1 CNVST Low to BUSY High Delay BUSY High All Modes (Except Master Serial Read After Convert) Warp Mode/Normal Mode/Impulse Mode Aperture Delay End of Conversion to BUSY Low Delay Conversion Time Warp Mode/Normal Mode/Impulse Mode Acquisition Time Warp Mode/Normal Mode/Impulse Mode RESET Pulse Width PARALLEL INTERFACE MODES (See Figure 35 and Figure 37) CNVST Low to DATA Valid Delay Warp Mode/Normal Mode/Impulse Mode DATA Valid to BUSY Low Delay Bus Access Request to DATA Valid Bus Relinquish Time MASTER SERIAL INTERFACE MODES2 (See Figure 39 and Figure 40) CS Low to SYNC Valid Delay CS Low to Internal SDCLK Valid Delay2 CS Low to SDOUT Delay CNVST Low to SYNC Delay, Read During Convert Warp Mode/Normal Mode/Impulse Mode SYNC Asserted to SDCLK First Edge Delay Internal SDCLK Period3 Internal SDCLK High3 Internal SDCLK Low3 SDOUT Valid Setup Time3 SDOUT Valid Hold Time3 SDCLK Last Edge to SYNC Delay3 CS High to SYNC HI-Z CS High to Internal SDCLK HI-Z CS High to SDOUT HI-Z BUSY High in Master Serial Read After Convert3 CNVST Low to SYNC Delay, Read After Convert Warp Mode/Normal Mode/Impulse Mode SYNC Deasserted to BUSY Low Delay Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 910/1160/1410 t11 t12 t13 t14 t15 t16 t17 65/315/560 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 3 30 15 10 4 5 5 45 20 2 40 15 10 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 380 10 ns ns 2 10 950/1250/1450 Min 10 1.33/1.67/2 35 950/1250/1450 Typ Max Unit ns μs ns ns ns ns ns 10 10 10 See Table 4 830/1070/1310 25 ns ns Rev. 0 | Page 5 of 32 AD7612 Parameter SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES2 (See Figure 42, Figure 43, and Figure 45) External SDCLK, SCCLK Setup Time External SDCLK Active Edge to SDOUT Delay SDIN/SCIN Setup Time SDIN/SCIN Hold Time External SDCLK/SCCLK Period External SDCLK/SCCLK High External SDCLK/SCCLK Low 1 2 Symbol Min Typ Max Unit t31 t32 t33 t34 t35 t36 t37 5 2 5 5 25 10 10 18 ns ns ns ns ns ns ns In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 3 In serial master read during convert mode. See Table 4 for serial master read after convert mode. Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] DIVSCLK[0] SYNC to SDCLK First Edge Delay Minimum Internal SDCLK Period Minimum Internal SDCLK Period Maximum Internal SDCLK High Minimum Internal SDCLK Low Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SDCLK Last Edge to SYNC Delay Minimum BUSY High Width Maximum Warp Mode Normal Mode Impulse Mode Symbol t18 t19 t19 t20 t21 t22 t23 t24 t28 0 0 3 30 45 15 10 4 5 5 1.65 1.9 2.15 0 1 20 60 90 30 25 20 8 7 2.35 2.6 2.85 1 0 20 120 180 60 55 20 35 35 3.75 4.00 4.25 1 1 20 240 360 120 115 20 90 90 6.53 6.78 7.03 Unit ns ns ns ns ns ns ns ns μs μs μs 1.6mA IOL TO OUTPUT PIN 1.4V CL 60pF 2V 0.8V 06265-003 500µA IOH tDELAY 2V 0.8V 06265-002 tDELAY 2V 0.8V NOTES 1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Figure 3. Voltage Reference Levels for Timing Rev. 0 | Page 6 of 32 AD7612 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs/Outputs IN+1, IN−1 to AGND REF, REFBUFIN, TEMP, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD, OVDD AVDD to DVDD, AVDD to OVDD DVDD to OVDD VCC to AGND, DGND VEE to GND Digital Inputs PDREF, PDBUF2 Internal Power Dissipation3 Internal Power Dissipation4 Junction Temperature Storage Temperature Range 1 2 3 Rating VEE − 0.3 V to VCC + 0.3 V AVDD + 0.3 V to AGND − 0.3 V ±0.3 V −0.3 V to +7 V ±7 V ±7 V –0.3 V to +16.5 +0.3 V to −16.5 −0.3 V to OVDD + 0 .3 V ±20 mA 700 mW 2.5 W 125°C −65°C to +125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION See the Analog Inputs section. See the Voltage Reference Input section. Specification is for the device in free air: 48-Lead LFQP; θJA = 91°C/W, θJC = 30°C/W. 4 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. Rev. 0 | Page 7 of 32 AD7612 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REFBUFIN REFGND PDBUF PDREF AGND AVDD TEMP VCC VEE 48 47 46 45 44 43 42 41 40 39 38 37 36 PIN 1 35 34 33 AGND 1 AVDD 2 AGND 3 REF IN+ IN– BIPOLAR CNVST PD RESET CS RD TEN BUSY D15/SCCS D14/SCCLK D13/SCIN D12/HW/SW BYTESWAP 4 OB/2C 5 WARP 6 IMPULSE 7 SER/PAR 8 D0 9 AD7612 TOP VIEW (Not to Scale) 32 31 30 29 28 27 26 25 D1 10 D2/DIVSCLK[0] 11 D3/DIVSCLK[1] 12 13 14 15 16 17 18 19 20 21 22 23 24 D4/EXT/INT OGND OVDD D6/INVSCLK D5/INVSYNC DGND DVDD D8/SDOUT D7/RDC/SDIN D10/SYNC D11/RDERROR D9/SDCLK Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 3, 42 Mnemonic AGND Type1 P Description Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and OGND voltages should be at the same potential. Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low, the MSB is inverted resulting in a twos complement output from its internal shift register. Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following: Conversion Mode WARP IMPULSE Normal Low Low Impulse Low High Warp High Low Normal High High See the Modes of Operation section for a more detailed description. Conversion Mode Selection. See the WARP pin description in the previous row of this table. See the Modes of Operation section for a more detailed description. Serial/Parallel Selection Input. When SER/PAR = low, the parallel mode is selected. When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port and the remaining data bits are high impedance outputs. Bit 0 and Bit 1 of the parallel port data output bus. These pins are always outputs regardless of the state of SER/PAR. In parallel mode, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high, EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial data clock that clocks the data output. In other serial modes, these pins are high impedance outputs. 2, 44 4 5 6 AVDD BYTESWAP OB/2C WARP P DI DI2 DI2 7 8 IMPULSE SER/PAR DI2 DI 9, 10 11, 12 D[0:1] D[2:3] or DIVSCLK[0:1] DO DI/O Rev. 0 | Page 8 of 32 06265-004 AD7612 Pin No. 13 Mnemonic D4 or EXT/INT Type1 DI/O Description In parallel mode, this output is used as Bit 4 of the parallel port data output bus. Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or external (slave) serial data clock for the AD7612 output data. When EXT/INT = low, master mode; the internal serial data clock is selected on SDCLK output. When EXT/INT = high, slave mode; the output data is synchronized to an external clock signal (gated by CS) connected to the SDCLK input. DI/O In parallel mode, this output is used as Bit 5 of the parallel port data output bus. Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low). This input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. In parallel mode, this output is used as Bit 6 of the parallel port data output bus. In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK. When INVSCLK = low, the rising edge of SDCLK/SCCLK are used. When INVSCLK = high, the falling edge of SDCLK/SCCLK are used. In parallel mode, this output is used as Bit 7 of the parallel port data output bus. Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low) RDC is used to select the read mode. Refer to the Master Serial Interface section. When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable in this mode. When RDC = high, the previous conversion result is read during the current conversion. Serial Data In. In serial slave mode (SER/PAR = high EXT/INT = high) SDIN can be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence. Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be connected to the system digital ground ideally at the same potential as AGND and DGND. Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors. Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied from AVDD. Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital ground ideally at the same potential as AGND and OGND. In parallel mode, this output is used as Bit 8 of the parallel port data output bus. Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7612 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. When EXT/INT = low, (master mode) SDOUT is valid on both edges of SDCLK. When EXT/INT = high, (slave mode). When INVSCLK = low, SDOUT is updated on SDCLK rising edge. When INVSCLK = high, SDOUT is updated on SDCLK falling edge. In parallel mode, this output is used as Bit 9 of the parallel port data output bus. Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. In parallel mode, this output is used as Bit 10 of the parallel port data output bus. Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT output is valid. 14 D5 or INVSYNC 15 D6 or INVSCLK DI/O 16 D7 or RDC or DI/O SDIN 17 18 19 20 21 OGND OVDD DVDD DGND D8 or SDOUT P P P P DO 22 D9 or SDCLK DI/O 23 D10 or SYNC DO Rev. 0 | Page 9 of 32 AD7612 Pin No. 24 Mnemonic D11 or RDERROR Type1 DO Description In parallel mode, this output is used as Bit 11 of the parallel port data output bus. Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an incomplete data read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. In parallel mode, this output is used as Bit 12 of the parallel port data output bus. Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7612 by hardware or software. See the Hardware Configuration section and Software Configuration section. When HW/SW = low, the AD7612 is configured through software using the serial configuration register. When HW/SW = high, the AD7612 is configured through dedicated hardware input pins. In parallel mode, this output is used as Bit 13 of the parallel port data output bus. Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input is used to serially write in, MSB first, the configuration data into the serial configuration register. The data on this input is latched with SCCLK. See the Software Configuration section. In parallel mode, this output is used as Bit 14 of the parallel port data output bus. Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state of the INVSCLK pin. See the Software Configuration section. In parallel mode, this output is used as Bit 15 of the parallel port data output bus. Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input enables the serial configuration port. See the Software Configuration section. Busy Output. Transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data ready clock signal. Note that in master read after convert mode (SER/PAR = high, EXT/INT = low, RDC = low) the busy time changes according to Table 4. Input Range Select. Used in conjunction with BIPOLAR per the following: Input Range BIPOLAR TEN 0 V to 5 V Low Low 0 V to 10 V Low High ±5 V High Low ±10 V High High Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode (not used for serial programmable port). Reset Input. When high, reset the AD7612. Current conversion, if any, is aborted. The falling edge of RESET resets the data outputs to all zero’s (with OB/2C = high) and clears the configuration register. See the Digital Interface section. If not used, this pin can be tied to OGND. Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. The digital interface remains active during power down. Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. Input Range Select. See description for Pin 30. Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is required with or without the internal reference and buffer. See the Reference Decoupling section. Reference Input Analog Ground. Connected to analog ground plane. Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground. High Voltage Positive Supply. Normally +7 V to +15 V. High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges). 25 D12 or HW/SW DI/O 26 D13 or SCIN DI/O 27 D14 or SCCLK DI/O 28 D15 or SCCS BUSY DI/O 29 DO 30 TEN DI2 31 32 33 RD CS RESET DI DI DI 34 PD DI2 35 36 37 CNVST BIPOLAR REF DI DI2 AI/O 38 39 40 41 REFGND IN− VCC VEE AI AI P P Rev. 0 | Page 10 of 32 AD7612 Pin No. 43 45 46 Mnemonic IN+ TEMP REFBUFIN Type1 AI AO AI Description Analog Input. Referenced to IN−. Temperature Sensor Analog Output. Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference Input section. Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down, and an external reference must be used. Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. 47 PDREF DI 48 PDBUF DI AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. In serial configuration mode (SER/PAR = high, HW/SW = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the Hardware Configuration section and Software Configuration section. 2 1 Rev. 0 | Page 11 of 32 AD7612 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C. 1.5 1.5 1.0 1.0 0.5 0 DNL (LSB) 06265-005 INL (LSB) 0.5 0 –0.5 –0.5 –1.0 0 16384 32768 CODE 49152 65536 0 16384 32768 CODE 49152 65536 Figure 5. Integral Nonlinearity vs. Code 180 160 140 NUMBER OF UNITS 180 Figure 8. Differential Nonlinearity vs. Code NEGATIVE DNL POSITIVE DNL NEGATIVE INL POSITIVE INL 160 140 120 100 80 60 40 20 06265-006 NUMBER OF UNITS 120 100 80 60 40 20 06265-009 06265-010 0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 INL DISTRIBUTION (LSB) DNL DISTRIBUTION (LSB) Figure 6. Integral Nonlinearity Distribution (239 Devices) 200k 180k 160k 140k 181942 σ = 0.55 Figure 9. Differential Nonlinearity Distribution (239 Devices) 140k 120k 100k 128400 130570 σ = 0.52 COUNTS 100k 80k 60k 40k 20k 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 06265-007 COUNTS 120k 80k 60k 40k 47749 31321 0 0 15 93 0 0 20k 0 0 0 0 917 1232 1 0 0 0 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 8007 CODE IN HEX CODE IN HEX Figure 7. Histogram of 261,120 Conversions of a DC Input at the Code Center Figure 10. Histogram of 261,120 Conversions of a DC Input at the Code Transition Rev. 0 | Page 12 of 32 06265-008 –1.5 –1.0 AD7612 0 –20 AMPLITUDE (dB of Full Scale) fS = 750kSPS fIN = 19.99kHz 95.0 SNR SINAD –40 –60 –80 –100 –120 –140 –160 SNR = 93.23dB THD = –107.5dB SFDR = 113.9dB SINAD = 93.1dB SNR, SINAD (dB) ±10V ±5V 0V TO +10V 0V TO +5V 94.5 94.0 93.5 06265-011 0 125 250 375 –50 –40 –30 –20 –10 0 FREQUENCY (kHz) INPUT LEVEL (dB) Figure 11. FFT 20 kHz 96 SNR 94 SINAD 92 SNR, SINAD (dB) Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale) 16.0 15.8 15.6 THD, HARMONICS (dB) –70 SFDR 120 110 100 90 –80 88 86 84 82 80 15.2 15.0 14.8 14.6 14.4 100 –100 THD THIRD HARMONIC 70 60 50 40 –110 –120 SECOND HARMONIC 1 10 FREQUENCY (kHz) 30 06265-015 06265-016 1 10 FREQUENCY (kHz) 06265-012 –130 20 100 Figure 12. SNR, SINAD, and ENOB vs. Frequency 96 ±10V ±5V 0V TO +10V 0V TO +5V Figure 15. THD, Harmonics, and SFDR vs. Frequency 96 ±10V ±5V 0V TO +10V 0V TO +5V 95 95 94 SINAD (dB) SNR (dB) 94 93 93 92 92 91 91 –35 –15 5 25 45 65 85 105 125 06265-013 90 –55 90 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. SNR vs. Temperature Figure 16. SINAD vs. Temperature Rev. 0 | Page 13 of 32 SFDR (dB) ENOB ENOB (Bits) 90 15.4 –90 80 06265-014 –180 93.0 –60 AD7612 –96 –98 –100 –102 –104 ±10V ±5V 0V TO +10V 0V TO +5V 124 122 120 118 SFDR (dB) 0V TO +10V ±5V ±10V 0V TO +5V THD (dB) –106 –108 –110 –112 –114 –116 –118 –35 –15 5 25 45 65 85 105 125 06265-017 116 114 112 110 108 06265-020 06265-022 06265-021 –120 –55 106 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. THD vs. Temperature 5 5.002 5.001 POSITIVE FULL SCALE ERROR ZERO ERROR NEGATIVE FULL SCALE ERROR 5.000 Figure 20. SFDR vs. Temperature (Excludes Harmonics) ZERO ERROR, FULL SCALE ERROR (LSB) 4 3 2 1 0 –1 –2 –3 –4 –35 –15 5 25 45 65 85 105 125 06265-018 VREF (V) 4.999 4.998 4.997 4.996 4.995 –55 –5 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Zero Error, Positive and Negative Full Scale vs. Temperature 60 Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices) 100000 10000 50 OPERATING CURRENTS (µA) 1000 100 10 1 0.1 0.01 0.001 10 PDREF = PDBUF = HIGH 100 1000 10000 100000 1000000 AVDD, WARP/NORMAL DVDD, ALL MODES AVDD, IMPULSE VCC +15V, VEE –15V, ALL MODES OVDD, ALL MODES NUMBER OF UNITS 40 30 20 10 0 1 2 3 4 5 6 7 8 06265-019 0 REFERENCE DRIFT (ppm/°C) SAMPLING RATE (SPS) Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices) Figure 22. Operating Currents vs. Sample Rate Rev. 0 | Page 14 of 32 AD7612 700 50 POWER-DOWN OPERATING CURRENTS (nA) PD = PDBUF = PDREF = HIGH 45 40 35 OVDD = 2.7V @ 85°C OVDD = 2.7V @ 25°C 600 500 t12 DELAY (ns) 400 300 200 100 0 –55 30 25 20 OVDD = 5V @ 25°C 15 10 5 0 OVDD = 5V @ 85°C VEE, –15V VCC, +15V DVDD OVDD AVDD TEMPERATURE (°C) CL (pF) Figure 23. Power-Down Operating Currents vs. Temperature Figure 24. Typical Delay vs. Load Capacitance CL Rev. 0 | Page 15 of 32 06265-024 –35 –15 5 25 45 65 85 105 06265-023 0 50 100 150 200 AD7612 TERMINOLOGY Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For an analog-to-digital converter with N bits of resolution, the LSB expressed in volts is LSB(V ) = VINp-p 2N Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by ENOB = [(SINADdB − 1.76)/6.02] Aperture Delay Aperture delay is a measure of the acquisition performance measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response The time required for the AD7612 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as TCVREF ( ppm/°C ) = VREF ( Max ) – VREF ( Min) VREF ( 25°C ) × ( TMAX – TMIN ) ×106 Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full-scale through positive fullscale. The point used as negative full-scale occurs a ½ LSB before the first code transition. Positive full-scale is defined as a level 1½ LSBs beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Bipolar Zero Error The difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Unipolar Offset Error The first transition should occur at a level ½ LSB above analog ground. The unipolar offset error is the deviation of the actual transition from that point. Full-Scale Error The last transition (from 111…10 to 111…11) should occur for an analog voltage 1½ LSB below the nominal full-scale. The fullscale error is the deviation in LSB (or % of full-scale range) of the actual level of the last transition from the ideal level and includes the effect of the offset error. Closely related is the gain error (also in LSB or % of full-scale range), which does not include the effects of the offset error. Dynamic Range Dynamic range is the ratio of the rms value of the full-scale to the rms noise measured for an input typically at −60 dB. The value for dynamic range is expressed in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. where: VREF (Max) = maximum VREF at TMIN, T(25°C), or TMAX. VREF (Min) = minimum VREF at TMIN, T(25°C), or TMAX. VREF (25°C) = VREF at 25°C. TMAX = +85°C. TMIN = –40°C. Rev. 0 | Page 16 of 32 AD7612 THEORY OF OPERATION IN+ REF REFGND MSB 32,768C 16,384C 4C 2C C C BUSY COMP IN– 65,536C SWB CNVST CONTROL LOGIC OUTPUT CODE 06265-025 LSB SWA SWITCHES CONTROL Figure 25. ADC Simplified Schematic OVERVIEW The AD7612 is a very fast, low power, precise, 16-bit analog-todigital converter (ADC) using successive approximation capacitive digital-to-analog (CDAC) architecture. The AD7612 can be configured at any time for one of four input ranges and conversion mode with inputs in parallel and serial hardware modes or by a dedicated write only, SPI-compatible interface via a configuration register in serial software mode. The AD7612 uses Analog Device’s patented iCMOS high voltage process to accommodate 0 to 5 V, 0 to 10 V, ±5 V, and ±10 V input ranges without the use of conventional thin films. Only one acquisition cycle, t8, is required for the inputs to latch to the correct configuration. Resetting or power cycling is not required for reconfiguring the ADC. The AD7612 features different modes to optimize performance according to the applications. It is capable of converting 750,000 samples per second (750 kSPS) in warp mode, 600 kSPS in normal mode, and 500 kSPS in impulse mode. The AD7612 provides the user with an on-chip track-and-hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. For unipolar input ranges, the AD7612 typically requires three supplies; VCC, AVDD (which can supply DVDD), and OVDD which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic. For bipolar input ranges, the AD7612 requires the use of the additional VEE supply. The device is housed in Pb-free, 48-lead LQFP or tiny LFCSP 7 mm × 7 mm packages that combine space savings with flexibility. In addition, the AD7612 can be configured as either a parallel or serial SPI-compatible interface. CONVERTER OPERATION The AD7612 is a successive approximation ADC based on a charge redistribution DAC. Figure 25 shows the simplified schematic of the ADC. The CDAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to AGND via SW+ and SW−. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on IN+ and IN− inputs. A conversion phase is initiated once the acquisition phase is complete and the CNVST input goes low. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the inputs (IN+ and IN−) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 through VREF/ 65536). The control logic toggles these switches, starting with the MSB first, in order to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings the BUSY output low. Rev. 0 | Page 17 of 32 AD7612 MODES OF OPERATION The AD7612 features three modes of operation: warp, normal, and impulse. Each of these modes is more suitable to specific applications. The mode is configured with the input pins, WARP and IMPULSE, or via the configuration register. See Table 6 for the pin details and the Hardware Configuration section and Software Configuration section for programming the mode selection with either pins or configuration register. Note that when using the configuration register, the WARP and IMPULSE inputs are don’t cares and should be tied to either high or low. Warp Mode Setting WARP = high and IMPULSE = low allow the fastest conversion rate up to 750 kSPS. However, in this mode, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms (after power-up), the first conversion result should be ignored since in warp mode, the ADC performs a background calibration during the SAR conversion process. This calibration can drift if the time between conversions exceeds 1 ms thus causing the first conversion to appear offset. This mode makes the AD7612 ideal for applications where both high accuracy and fast sample rate are required. In addition, the AD7612 can run up to 900 kSPS throughput with some performance degradation, mainly dc linearity. Impulse Mode Setting WARP = low and IMPULSE = high uses the lowest power dissipation mode and allows power saving between conversions. The maximum throughput in this mode is 500 kSPS and in this mode, the ADC powers down circuits after conversion making the AD7612 ideal for battery-powered applications. TRANSFER FUNCTIONS Using the OB/2C digital input or via the configuration register, the AD7612 offers two output codings: straight binary and twos complement. See Figure 26 and Table 7 for the ideal transfer characteristic and digital output codes for the different analog input ranges, VIN. Note that when using the configuration register, the OB/2C input is a don’t care and should be tied to either high or low. ADC CODE (Straight Binary) 111...111 111...110 111...101 –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Setting WARP = IMPULSE = low or WARP = IMPULSE = high allows the fastest mode (600 kSPS) without any limitation on time between conversions. This mode makes the AD7612 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. Figure 26. ADC Ideal Transfer Function Table 7. Output Codes and Ideal Input Voltages Description FSR − 1 LSB FSR − 2 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 1 2 VIN = 5 V 4.999924 V 4.999847 V 2.500076 V 2.5 V 2.499924 V 76.3 μV 0V VIN = 10 V 9.999847 V 9.999695 V 5.000153 V 5.000000 V 4.999847 V 152.6 μV 0V VREF = 5 V VIN = ±5 V +4.999847 V +4.999695 V +152.6 μV 0V −152.6 μV −4.999847 V −5 V VIN = ±10 V +9.999695 V +9.999390 V +305.2 μV 0V −305.2 μV −9.999695 V −10 V Digital Output Code Straight Binary Twos Complement 0xFFFF 1 0x7FFF1 0xFFFE 0x7FFE 0x8001 0x0001 0x8000 0x0000 0x7FFF 0xFFFF 0x0001 0x8001 0x0000 2 0x80002 This is also the code for overrange analog input (VIN+ − VIN− above VREF − VREFGND). This is also the code for overrange analog input (VIN+ − VIN− below VREF − VREFGND). Rev. 0 | Page 18 of 32 06265-026 Normal Mode 000...010 000...001 000...000 –FSR –FSR + 1 LSB +FSR – 1 LSB AD7612 TYPICAL CONNECTION DIAGRAM Figure 27 shows a typical connection diagram for the AD7612 using the internal reference, serial data interface, and serial configuration port. Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections. DIGITAL SUPPLY (5V) NOTE 5 ANALOG SUPPLY (5V) 10µF 100nF 10µF 100nF 100nF 10µF DIGITAL INTERFACE SUPPLY (2.5V, 3.3V, or 5V) AVDD +7V TO +15.75V SUPPLY 10µF 100nF VCC AGND DGND DVDD OVDD OGND BUSY SDCLK MICROCONVERTER/ MICROPROCESSOR/ DSP SERIAL PORT 1 SERIAL PORT 2 10µF –7V TO –15.75V SUPPLY NOTE 6 100nF VEE REF NOTE 3 SDOUT SCCLK SCIN SCCS NOTE 7 NOTE 4 CREF 22µF 100nF REFBUFIN REFGND CNVST D AD7612 NOTE 2 OB/2C SER/PAR OVDD ANALOG INPUT + U1 CC 2.7nF IN+ HW/SW BIPOLAR TEN WARP CLOCK ANALOG INPUT– NOTE 1 IN– NOTE 3 IMPULSE PD RD CS RESET PDREF PDBUF Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port Rev. 0 | Page 19 of 32 06265-027 NOTES 1. SEE ANALOG INPUT SECTION. ANALOG INPUT(–) IS REFERENCED TO AGND ±0.1V. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION. 4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M). SEE VOLTAGE REFERENCE INPUT SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) +2V] and VEE = [VIN(MIN) –2V] FOR BIPOLAR INPUT RANGES. FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLY SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. AD7612 ANALOG INPUTS Input Range Selection In parallel mode and serial hardware mode, the input range is selected by using the BIPOLAR (bipolar) and TEN (10 Volt range) inputs. See Table 6 for pin details and the Hardware Configuration section and Software Configuration section for programming the mode selection with either pins or configuration register. Note that when using the configuration register, the BIPOLAR and TEN inputs are don’t cares and should be tied to either high or low. For instance, by using IN− to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated. 100 90 80 70 CMRR (dB) 60 50 40 30 20 10 1 10 100 FREQUENCY (kHz) 1000 10000 06265-029 Input Structure Figure 28 shows an equivalent circuit for the input structure of the AD7612. 0 TO 5V RANGE ONLY VCC D1 IN+ OR IN– CPIN VEE AGND D2 D4 AVDD D3 CIN 0 RIN Figure 29. Analog Input CMRR vs. Frequency Figure 28. AD7612 Simplified Analog Input The four diodes, D1 to D4, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V, because this causes the diodes to become forward-biased and to start conducting current. These diodes can handle a forwardbiased current of 120 mA maximum. For instance, these conditions could eventually occur when the input buffer’s U1 supplies are different from AVDD, VCC, and VEE. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part although most op amps’ short circuit current is