AD7675ACPZRL

a FEATURES Throughput: 100 kSPS INL:
1.5 LSB Max (
0.0015% of Full Scale) 16 Bits Resolution with No Missing Codes S/(N+D): 94 dB Typ @ 45 kHz THD: –110 dB Typ @ 45 kHz Differential Input Range:
2.5 V Both AC and DC Specifications No Pipeline Delay Parallel (8 Bits/16 Bits) and Serial 5 V/3 V Interface SPI™/QSPI™/MICROWIRE™/DSP Compatible Single 5 V Supply Operation 15 mW Typical Power Dissipation, 15 W @ 100 SPS Power-Down Mode: 7 W Max Packages: 48-Lead Quad Flatpack (LQFP), 46-Lead Frame Chip Scale (LFCSP) Pin-to-Pin Compatible with the AD7660 Replacement of AD676, AD677 APPLICATIONS CT Scanners Data Acquisition Instrumentation Spectrum Analysis Medical Instruments Battery-Powered Systems Process Control 16-Bit, 100 kSPS, Differential ADC AD7675 FUNCTIONAL BLOCK DIAGRAM AVDD AGND REF REFGND DVDD DGND OVDD AD7675 OGND SERIAL PORT IN+ SWITCHED CAP DAC IN– SER/PAR BUSY 16 DATA[15:0] CLOCK PD RESET PARALLEL INTERFACE CS CONTROL LOGIC AND CALIBRATION CIRCUITRY RD OB/2C BYTESWAP CNVST PulSAR Selection Type/kSPS 100–250 500–570 1000 Pseudo Differential AD7660 AD7650 AD7664 True Bipolar AD7663 AD7665 AD7671 True Differential AD7675 AD7676 AD7677 GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7675 is a 16-bit, 100 kSPS, charge redistribution SAR, fully differential analog-to-digital converter that operates from a single 5 V power supply. The part contains a high speed 16-bit sampling ADC, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. 1. Excellent INL The AD7675 has a maximum integral nonlinearity of 1.5 LSB with no missing 16-bit code. The AD7675 is hardware factory calibrated and is comprehensively tested to ensure such ac parameters as signal-to-noise ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional dc parameters of gain, offset, and linearity. 3. Fast Throughput The AD7675 is a 100 kSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry. It is fabricated using Analog Devices’ high performance, 0.6 micron CMOS process and is available in a 48-lead LQFP or a tiny 48-lead LFCSP with operation specified from –40°C to +85°C. 2. Superior AC Performances The AD7675 has a minimum dynamic of 92 dB, 94 dB typical. 4. Single-Supply Operation The AD7675 operates from a single 5 V supply and typically dissipates only 17 mW. Its power dissipation decreases with the throughput to, for instance, only 15 µW at a 100 SPS throughput. It consumes 7 µW maximum when in power-down. 5. Serial or Parallel Interface Versatile parallel (8 bits or 16 bits) or 2-wire serial interface arrangement compatible with either 3 V or 5 V logic. SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD7675–SPECIFICATIONS (–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Conditions Min RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Max 16 VIN+ – VIN– VIN+, VIN– to AGND fIN = 10 kHz 100 kSPS Throughput Unit Bits –VREF –0.1 +VREF +3 V V dB µA 10 100 µs kSPS +1.5 LSB1 Bits LSB LSB LSB LSB LSB 79 1 See Analog Input Section THROUGHPUT SPEED Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise +Full-Scale Error2 –Full-Scale Error2 Zero Error2 Power Supply Sensitivity Typ 0 –1.5 16 0.35 –22 –22 –8 AVDD = 5 V ± 5% fIN = 20 kHz fIN = 45 kHz fIN = 20 kHz fIN = 45 kHz fIN = 20 kHz fIN = 45 kHz fIN = 20 kHz fIN = 45 kHz fIN = 45 kHz, –60 dB Input 92 104.5 92 –3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Full-Scale Step REFERENCE External Reference Voltage Range External Reference Current Drain 100 kSPS Throughput ± 0.5 94 94 110 110 –110 –110 94 94 34 3.9 +22 +22 +8 –103.5 2 5 8.75 2.3 2.5 35 dB3 dB3 dB3 dB3 dB3 dB3 dB3 dB3 dB3 MHz ns ps rms µs AVDD – 1.85 V µA +0.8 DVDD + 0.3 +1 +1 V V µA µA DIGITAL INPUTS Logic Levels VIL VIH IIL IIH –0.3 2.0 –1 –1 DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH Parallel or Serial 16-Bit Conversion Results Available Immediately After Completed Conversion 0.4 OVDD – 0.6 V V 4.75 4.75 2.7 5.25 5.25 5.254 V V V 25 7 mA µA µA mW µW µW +85 °C POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current AVDD DVDD5 OVDD5 Power Dissipation5 In Power-Down Mode5 TEMPERATURE RANGE7 Specified Performance ISINK = 1.6 mA ISOURCE = –100 µA 5 5 300 kSPS Throughput 3 750 7.5 17 15 100 kSPS Throughput 100 SPS Throughput TMIN to TMAX –40 NOTES 1 LSB means Least Significant Bit. With the ± 2.5 V input range, one LSB is 76.3 µV. 2 See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. 4 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 5 Tested in Parallel Reading Mode. 6 With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively. 7 Contact factory for extended temperature range. Specifications subject to change without notice. –2– REV. A AD7675 TIMING SPECIFICATIONS (–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Refer to Figures 11 and 12 Convert Pulsewidth Time Between Conversions CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except in Master Serial Read After Convert Mode Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time Acquisition Time RESET Pulsewidth Symbol Min t1 t2 t3 t4 5 10 Typ Max Unit 30 1.25 ns µs ns µs 2 t5 t6 t7 t8 t9 10 1.25 8.75 10 Refer to Figures 13, 14, and 15 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid Bus Relinquish Time t10 t11 t12 t13 Refer to Figures 16 and 17 (Master Serial Interface Modes)1 CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay CS LOW to SDOUT Delay CNVST LOW to SYNC Delay SYNC Asserted to SCLK First Edge Delay2 Internal SCLK Period2 Internal SCLK HIGH2 Internal SCLK LOW2 SDOUT Valid Setup Time2 SDOUT Valid Hold Time2 SCLK Last Edge to SYNC Delay2 CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read After Convert2 CNVST LOW to SYNC Asserted Delay SYNC Deasserted to BUSY LOW Delay t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 Refer to Figures 18 and 19 (Slave Serial Interface Modes) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW t31 t32 t33 t34 t35 t36 t37 1.25 45 40 15 5 10 10 10 525 3 25 12 7 4 2 3 40 10 10 10 See Table I 1.25 25 5 3 5 5 25 10 10 18 NOTES 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 2 In serial master read during convert mode. See Table I for serial master read after convert mode. Specifications subject to change without notice. REV. A –3– ns ns µs µs ns µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs ns ns ns ns ns ns ns ns AD7675 Table I. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Typical Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum Busy High Width Maximum t18 t19 t19 t20 t21 t22 t23 t24 t28 0 0 0 1 1 0 1 1 Unit 3 25 40 12 7 4 2 3 2 17 50 70 22 21 18 4 60 2.5 17 100 140 50 49 18 30 140 3.5 17 200 280 100 99 18 89 300 5.75 ns ns ns ns ns ns ns ns µs ABSOLUTE MAXIMUM RATINGS 1 1.6mA Analog Inputs IN+2, IN–2, REF, REFGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V Ground Voltage Differences AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ± 0.3 V Supply Voltages AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ± 7 V DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . . 700 mW Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . . . . . 2.5 W Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150° C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C IOL TO OUTPUT PIN 1.4V CL 60pF1 500A IOH NOTE 1 IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF 2V 0.8V tDELAY NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 Specification is for device in free air: 48-Lead LQFP: ␪JA = 91°C/W, ␪JC = 30°C/W. 4 Specification is for device in free air: LFCSP: ␪JA = 26°C/W tDELAY 2V 0.8V 2V 0.8V Figure 2. Voltage Reference Levels for Timing ORDERING GUIDE Model Temperature Range Package Description AD7675AST AD7675ASTRL AD7675ACP AD7675ACPRL EVAL-AD7675CB1 EVAL-CONTROL BRD22 –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Quad Flatpack (LQFP) Quad Flatpack (LQFP) Chip Scale (LFCSP) Chip Scale (LFCSP) Evaluation Board Controller Board Package Option ST-48 ST-48 CP-48 CP-48 NOTES 1 This board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/ demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7675 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. A AD7675 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description 1 2 3, 6, 7, 40–42, 44–48 4 AGND AVDD NC P P Analog Power Ground Pin Input Analog Power Pins. Nominally 5 V. No Connect BYTESWAP DI 5 OB/2C DI 8 SER/PAR DI 9, 10 DATA[0:1] DO 11, 12 DATA[2:3] or DI/O Parallel Mode Selection (8-Bit/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted resulting in a two’s complement output from its internal shift register. Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the serial master read after convert mode. These inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In the other serial modes, these pins are high impedance outputs. When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. When SER/PAR is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. When SER/PAR is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. When SER/PAR is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/ SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data is output on SDOUT only when the conversion is complete. Input/Output Interface Digital Power Ground Input/Output Interface Digital Power. Nominally at the same supply than the supply of the host interface (5 V or 3 V). Digital Power. Nominally at 5 V. Digital Power Ground DIVSCLK[0:1] 13 DATA[4] or EXT/INT DI/O 14 DATA[5] or INVSYNC DI/O 15 DATA[6] or INVSCLK DI/O 16 DATA[7] or RDC/SDIN DI/O 17 18 OGND OVDD P P 19 20 DVDD DGND P P REV. A –5– AD7675 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Type Description 21 DATA[8] or SDOUT DO 22 DATA[9] or SCLK DI/O 23 DATA[10] or SYNC DO 24 DATA[11] or RDERROR DO 25–28 DATA[12:15] DO 29 BUSY DO 30 31 32 DGND RD CS P DI DI 33 34 RESET PD DI DI 35 CNVST DI 36 37 38 39 43 AGND REF REFGND IN– IN+ P AI AI AI AI When SER/PAR is LOW, this output is used as the Bit 8 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7675 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge. When SER/PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT Pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK Pin. When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus. When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regardless of the state of SER/PAR. Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. Must Be Tied to Digital Ground Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external serial clock. Reset Input. When set to a logic HIGH, reset the AD7675. Current conversion if any is aborted. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. Start Conversion. If CNVST is HIGH when the acquisition phase (t8) is complete, the next falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. This mode is the most appropriate if low sampling jitter is desired. If CNVST is LOW when the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. Must Be Tied to Analog Ground Reference Input Voltage Reference Input Analog Ground Differential Negative Analog Input Differential Positive Analog Input NOTES AI = Analog Input DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power –6– REV. A AD7675 PIN CONFIGURATION REF REFGND IN– NC NC NC IN+ NC NC NC NC NC 48-Lead LQFP (ST-48) 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 AVDD 2 PIN 1 IDENTIFIER 36 AGND 35 NC 3 34 CNVST PD BYTESWAP 4 33 RESET OB/2C 5 NC 6 32 CS 31 30 RD DGND SER/PAR 8 D0 9 29 BUSY 28 D15 D1 10 27 D14 D2/DIVSCLK[0] 11 26 D13 D3/DIVSCLK[1] 12 25 D12 AD7675 TOP VIEW (Not to Scale) NC 7 D11/RDERROR D10/SYNC D9/SCLK D8/SDOUT DGND DVDD OVDD OGND D7/RDC/SDIN D6/INVSCLK 13 14 15 16 17 18 19 20 21 22 23 24 D4/EXT/INT D5/INVSYNC NC = NO CONNECT DEFINITION OF SPECIFICATIONS EFFECTIVE NUMBER OF BITS (ENOB) INTEGRAL NONLINEARITY ERROR (INL) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula: Integral Nonlinearity is the maximum deviation of a straight line drawn through the transfer function of the actual ADC. The deviation is measured from the middle of each code. DIFFERENTIAL NONLINEARITY ERROR (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. ( [ ENOB = S / N + D ] dB ) – 1.76 / 6.02 and is expressed in bits. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. +FULL-SCALE ERROR The last transition (from 011 . . . 10 to 011 . . . 11 in two’s complement coding) should occur for an analog voltage 1 1/2 LSB below the nominal +full scale (+2.499886 V for the ± 2.5 V range). The +full-scale error is the deviation of the actual level of the last transition from the ideal level. SIGNAL-TO-NOISE RATIO (SNR) –FULL-SCALE ERROR SIGNAL-TO-(NOISE + DISTORTION) RATIO (S/[N+D]) The first transition (from 100 . . . 00 to 100 . . . 01 in two’s complement coding) should occur for an analog voltage 1/2 LSB above the nominal –full scale (–2.499962 V for the ± 2.5 V range). The –full-scale error is the deviation of the actual level of the last transition from the ideal level. S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels. SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. APERTURE DELAY BIPOLAR ZERO ERROR The bipolar zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. TRANSIENT RESPONSE SPURIOUS FREE DYNAMIC RANGE (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. REV. A The time required for the AD7675 to achieve its rated accuracy after a full-scale step function is applied to its input. –7– AD7675 –Typical Performance Characteristics 1.00 16000 0.75 14000 0.50 12000 0.25 10000 COUNTS INL – LSB 14687 0.00 8000 –0.25 6000 –0.50 4000 –0.75 2000 –1.00 0000 0 16384 32768 CODE 49152 65536 8246 8118 8000 810 0 0 0 0 0 7FF8 7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 CODE IN HEXA 16 14 NUMBER OF UNITS 7000 6000 COUNTS 0 18 9000 5000 4000 3000 12 10 8 6 4 2000 2 1000 0 0000 0 0 6 14 0 0 0 0 –1.0 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 CODE IN HEXA –0.8 –0.6 –0.4 NEGATIVE INL – LSB –0.2 0.0 TPC 5. Typical Negative INL Distribution (40 Units) TPC 2. Histogram of 16,384 Conversions of a DC Input at the Code Transition 0 16 –20 AMPLITUDE – dB of Full Scale 18 14 NUMBER OF UNITS 0 TPC 4. Histogram of 16,384 Conversions of a DC Input at the Code Center TPC 1. Integral Nonlinearity vs. Code 12 10 8 6 4 fS = 100 kSPS fIN = 45.01kHz SNR = 94dB THD = –110dB SFDR = 110dB SINAD = 93.9dB –40 –60 –80 –100 –120 –140 –160 2 0 887 0 –180 0 0.2 0.4 0.6 POSITIVE INL – LSB 0.8 1.0 TPC 3. Typical Positive INL Distribution (40 Units) 0 10 20 30 FREQUENCY – kHz 40 50 TPC 6. FFT Plot –8– REV. A AD7675 100 16.0 50 OVDD = 2.7V @ 85C 15.5 15.0 SNR 14.5 85 SINAD 80 t12 DELAY – ns 90 40 ENOB – Bits SNR AND S/[N+D] – dB 95 ENOB OVDD = 5.0V @ 85C 20 OVDD = 5.0V @ 25C 10 13.5 70 1 13.0 1000 10 100 FREQUENCY – kHz 0 0 50 100 CL – pF 200 150 TPC 7. SNR, S/(N+D), and ENOB vs. Frequency TPC 10. Typical Delay vs. Load Capacitance CL 96 100k SNR 10k SINAD OPERATING CURRENTS – A SNR (REFERRED TO FULL SCALE) – dB 30 14.0 75 94 92 90 1k AVDD 100 DVDD 10 1 OVDD 0.1 0.01 88 –60 –50 –40 –30 –20 INPUT LEVEL – dB –10 0.001 10 0 TPC 8. SNR and S/(N+D) vs. Input Level 96 –104 POWER-DOWN OPERATING CURRENTS – nA –106 90 –108 84 –55 –110 THD –35 –15 0 25 45 65 TEMPERATURE – C 85 105 TPC 9. SNR, THD vs. Temperature REV. A 1k 10k SAMPLING RATE – SPS 100k 250 THD – dB 93 87 100 TPC 11. Operating Currents vs. Sample Rate SNR SNR – dB OVDD = 2.7V @ 25C –112 125 DVDD 200 150 100 50 0 –55 AVDD OVDD –35 –15 5 25 45 65 85 105 TEMPERATURE – C TPC 12. Power-Down Operating Currents vs. Temperature –9– AD7675 During the acquisition phase, terminals of the array tied to the comparator’s input are connected to AGND via SW+ and SW–. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire both analog signals. 5 4 3 2 –FS When the acquisition phase is complete and the CNVST input goes or is low, a conversion phase is initiated. When the conversion phase begins, SW+ and SW– are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the output of IN+ and IN– captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. LSB 1 0 –1 OFFSET –2 +FS –3 –4 –5 –55 –35 –15 –5 15 35 55 75 TEMPERATURE – C 95 115 135 By switching each element of the capacitor array between REFGND or REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536). The control logic toggles these switches, starting with the MSB first, in order to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings BUSY output low. TPC 13. Drift vs. Temperature CIRCUIT INFORMATION The AD7675 is a fast, low power, single-supply, precise 16-bit analog-to-digital converter (ADC). The AD7675 is capable of converting 100,000 samples per second (100 kSPS) and allows power saving between conversions. When operating at 100 SPS, for example, it consumes typically only 15 µW. This feature makes the AD7675 ideal for battery-powered applications. Transfer Functions Using the OB/2C digital input, the AD7675 offers two output codings: straight binary and two’s complement. The ideal transfer characteristic for the AD7675 is shown in Figure 4. ADC CODE – Straight Binary The AD7675 provides the user with an on-chip track/hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7675 can be operated from a single 5 V supply and be interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead LQFP package that combines space savings and allows flexible configurations as either serial or parallel interface. The AD7675 is pin-to-pin compatible with the AD7660. 111...111 111...110 111...101 000...010 CONVERTER OPERATION 000...001 The AD7675 is a successive approximation analog-to-digital converter based on a charge redistribution DAC. Figure 3 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary-weighted capacitors that are connected to the two comparator inputs. 000...000 –FS –FS + 1 LSB +FS – 1 LSB –FS + 0.5 LSB +FS – 1.5 LSB ANALOG INPUT Figure 4. ADC Ideal Transfer Function IN+ SWITCHES CONTROL MSB 32,768C 16,384C LSB 4C 2C C C SW+ BUSY REF COMP CONTROL LOGIC OUTPUT CODE REFGND 32,768C 16,384C 4C 2C C C LSB MSB SW– CNVST IN– Figure 3. ADC Simplified Schematic –10– REV. A AD7675 DVDD ANALOG SUPPLY (5V) 100 DIGITAL SUPPLY (3.3V OR 5V) NOTE 6 + + 100nF 10F ADR421 AVDD 10F AGND 100nF DGND 100nF DVDD REF 2.5V REF 1M C 50k + REF NOTE 1 100nF OVDD + 10F OGND SERIAL PORT SCLK 1F NOTE 2 SDOUT REFGND NOTE 3 50 NOTE 4 ANALOG INPUT+ BUSY – U1 + AD8021 15 CC CNVST IN+ C/P/DSP 50 D NOTE 7 2.7nF AD7675 NOTE 5 OB/2C SER/PAR DVDD 50 NOTE 4 ANALOG INPUT– – U2 + AD8021 CS 15 CC IN– CLOCK RD BYTESWAP 2.7nF RESET NOTE 5 PD NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION. 2. WITH THE RECOMMENDED VOLTAGE REFERENCES, CREF IS 47F. SEE CHAPTER VOLTAGE REFERENCE INPUT SECTION 3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION. 4. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 5. SEE ANALOG INPUT SECTION. 6. OPTION, SEE POWER SUPPLY SECTION 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 5. Typical Connection Diagram. (± 2.5 V Range Shown) the input buffer’s (U1) or (U2) supplies are different from TYPICAL CONNECTION DIAGRAM AVDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. Figure 5 shows a typical connection diagram for the AD7675. Different circuitry shown on this diagram is optional and is discussed below. Analog Inputs Figure 6 shows a simplified analog input section of the AD7675. This analog input structure is a true differential structure. By using these differential inputs, signals common to both inputs are rejected, as shown in Figure 7, which represents the typical CMRR over frequency. AVDD 85 80 R+ = 684 75 IN+ CS 70 IN– CMRR – dB CS R– = 684 65 60 55 AGND 50 Figure 6. Simplified Analog Input The diodes shown in Figure 6 provide ESD protection for the inputs. Care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs. This will cause these diodes to become forward-biased and start conducting current. These diodes can handle a forward-biased current of 120 mA maximum. This condition could eventually occur when REV. A –11– 45 40 1k 10k 100k 1M 10M FREQUENCY – Hz Figure 7. Analog Input CMRR vs. Frequency AD7675 one-pole, low-pass filter made by R+, R–, and CS. The SNR degradation due to the amplifier is: During the acquisition phase for ac signals, the AD7675 behaves like a one-pole RC filter consisting of the equivalent resistance R+, R–, and CS. The resistors R+ and R– are typically 684 Ω and are lumped components made up of some serial resistors and the on resistance of the switches. The capacitor CS is typically 60 pF and is mainly the ADC sampling capacitor. This one pole filter with a typical –3 dB cutoff frequency of 3.9 MHz reduces undesirable aliasing effect and limits the noise coming from the inputs. SNR LOSS f –3 dB is the –3 dB input bandwidth of the AD7675 (3.9 MHz) or the cutoff frequency of the input filter if any is used. N is the noise factor of the amplifier (1 if in buffer configuration) eN is the equivalent input noise voltage of the op amp in nV/(Hz)1/2. For instance, in the case of a driver with an equivalent input noise of 2 nV/√Hz like the AD8021 and configured as a buffer, thus with a noise gain of +1, the SNR degrades by only 0.04 dB with the filter in Figure 5, and 0.07 dB without. • The driver needs to have a THD performance suitable to that of the AD7675. Single to Differential Driver For applications using unipolar analog signals, a single-ended to differential driver will allow for a differential input into the part. The schematic is shown in Figure 8. AD8021 CC The AD8132 or the AD8138 could also be used to generate a differential signal from a single-ended signal. When using the AD8138 with the filter in Figure 5, the SNR degrades by only 0.9 dB. IN+ 590 590 590 AD8021 CC The AD829 is another alternative where high frequency (above 100 kHz) performances are not required. In gain of 1, it requires an 82 pF compensation capacitor. AD7675 IN– U2 The AD8021 meets these requirements and is usually appropriate for almost all applications. The AD8021 needs an external compensation capacitor of 10 pF. This capacitor should have good linearity as an NPO ceramic or mica type. The AD8022 could also be used where dual version is needed and gain of 1 is used. U1 590 2.5V REF      where Because the input impedance of the AD7675 is very high, the AD7675 can be driven directly by a low impedance source without gain error. That allows users to put, as shown in Figure 5, an external one-pole RC filter between the output of the amplifier output and the ADC analog inputs to even further improve the noise filtering done by the AD7675 analog input circuit. However, the source impedance has to be kept low because it affects the ac performances, especially the total harmonic distortion. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD degrades proportionally to the source impedance. ANALOG INPUT (UNIPOLAR)   28 = 20LOG  π  784 + f –3 dB ( N e N )2  4 REF The AD8610 is also another option where low bias current is needed in low frequency applications. 2.5V REF Figure 8. Single-Ended-to-Differential Driver Circuit The AD8519, OP162, or the OP184 could also be used. This configuration, when provided an input signal of 0 to VREF, will produce a differential ± 2.5 V with a common mode at 1.25 V. Voltage Reference Input If the application can tolerate more noise, the AD8138 can be used. The voltage reference input REF of the AD7675 has a dynamic input impedance. Therefore, it should be driven by a low impedance source with an efficient decoupling between REF and REFGND inputs. This decoupling depends on the choice of the voltage reference but usually consists of a 1 µF ceramic capacitor and a low ESR tantalum capacitor connected to the REF and REFGND inputs with minimum parasitic inductance. 47 µF is an appropriate value for the tantalum capacitor when used with one of the recommended reference voltages: Driver Amplifier Choice Although the AD7675 is easy to drive, the driver amplifier needs to meet at least the following requirements: • The driver amplifier and the AD7675 analog input circuit have to be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier’s data sheet, the settling at 0.1% or 0.01% is more commonly specified. It could significantly differ from the settling time at 16-bit level and, therefore, it should be verified prior to the driver selection. The tiny op amp AD8021, which combines ultra low noise and a high gain bandwidth, meets this settling time requirement even when used with a high gain up to 13. • The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7675. The noise coming from the driver is filtered by the AD7675 analog input circuit The AD7675 uses an external 2.5 V voltage reference. • The low noise, low temperature drift ADR421 and AD780 voltage references • The low power ADR291 voltage reference • The low cost AD1582 voltage reference For applications using multiple AD7675s, it is more effective to buffer the reference voltage with a low noise, very stable op amp like the AD8031. –12– REV. A AD7675 Care should also be taken with the reference temperature coefficient of the voltage reference which directly affects the full-scale accuracy if this parameter matters. For instance, a ± 15 ppm/°C tempco of the reference changes the full scale by ± 1 LSB/°C. 100k POWER DISSIPATION – W 10k VREF , as mentioned in the specification table, could be increased to AVDD – 1.85 V. The benefit here is the increased SNR obtained as a result of this increase. Since the input range is defined in terms of VREF, this would essentially increase the range to make it a ± 3 V input range with an AVDD above 4.85 V. The theoretical improvement as a result of this increase in reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical quantization noise, however, the observed improvement is approximately 1 dB. The AD780 can be selected with a 3 V reference voltage. 1k 100 10 1 0.1 10 100 1k 10k 100k 1M SAMPLING RATE – SPS Power Supply The AD7675 uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and DVDD + 0.3 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply as shown in Figure 5. The AD7675 is independent of power supply sequencing once OVDD does not exceed DVDD by more than 0.3 V, and thus free from supply voltage induced latchup. Additionally, it is very insensitive to power supply variations over a wide frequency range as shown in Figure 9. Figure 10. Power Dissipation vs. Sample Rate CONVERSION CONTROL Figure 11 shows the detailed timing diagrams of the conversion process. The AD7675 is controlled by the signal CNVST, which initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until the conversion is complete. The CNVST signal operates independently of CS and RD signals. t2 t1 CNVST 75 70 BUSY t4 PSRR – dB 65 t3 MODE ACQUIRE CONVERT ACQUIRE t7 t8 CONVERT 55 50 Figure 11. Basic Conversion Timing 45 For true sampling applications, the recommended operation of the CNVST signal is as follows: 40 35 1k 10k 100k 1M 10M FREQUENCY – Hz Figure 9. PSRR vs. Frequency POWER DISSIPATION The AD7675 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows a significant power saving when the conversion rate is reduced as shown in Figure 10. This feature makes the AD7675 ideal for very low power battery applications. CNVST must be held high from the previous falling edge of BUSY, and during a minimum delay corresponding to the acquisition time t8; then, when CNVST is brought low, a conversion is initiated and BUSY signal goes high until the completion of the conversion. Although CNVST is a digital signal, it should be designed with this special care with fast, clean edges and levels, with minimum overshoot and undershoot or ringing. For applications where the SNR is critical, the CNVST signal should have a very low jitter. Some solutions to achieve that are to use a dedicated oscillator for CNVST generation or, at least, to clock it with a high frequency low jitter clock, as shown in Figure 5. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., DVDD and DGND) and OVDD should not exceed DVDD by more than 0.3 V. REV. A t6 t5 60 –13– AD7675 PARALLEL INTERFACE t9 The AD7675 is configured to use the parallel interface (Figure 13) when the SER/PAR is held low. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in Figure 14 and Figure 15. When the data is read during the conversion, however, it is recommended that it be read-only during the first half of the conversion phase. That avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. RESET BUSY DATA t8 CS CNVST RD Figure 12. RESET Timing For other applications, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the AD7675 controls the acquisition phase and then automatically initiates a new conversion. By keeping CNVST low, the AD7675 keeps the conversion process running by itself. It should be noted that the analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should be brought low once to initiate the conversion process. In this mode, the AD7675 could sometimes run slightly faster than the guaranteed limit of 100 kSPS. BUSY DATA BUS t12 CS = 0 t1 CNVST t1 CNVST, RD The AD7675 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7675 digital interface also accommodates both 3 V or 5 V logic by simply connecting the OVDD supply pin of the AD7675 to the host system interface digital supply. Finally, by using the OB/2C input pin, either two’s complement or straight binary coding can be used. CS = RD = 0 t13 Figure 14. Slave Parallel Data Timing for Reading (Read after Convert) DIGITAL INTERFACE The two signals CS and RD control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7675 in multicircuits applications and is held low in a single AD7675 design. RD is generally used to enable the conversion result on the data bus. CURRENT CONVERSION t4 BUSY t3 PREVIOUS CONVERSION DATA BUS t12 t13 Figure 15. Slave Parallel Data Timing for Reading (Read During Convert) The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in Figure 16, the LSB byte is output on D[7:0] and the MSB is output on D[15:8] when BYTESWAP is low. When BYTESWAP is high, the LSB and MSB bytes are swapped and the LSB is output on D[15:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16-bit data can be read in two bytes on either D[15:8] or D[7:0]. t10 t3 DATA BUS CS t4 BUSY t11 PREVIOUS CONVERSION DATA RD NEW DATA BYTE Figure 13. Master Parallel Data Timing for Reading (Continuous Read) PINS D[15:8] HI-Z HIGH BYTE t12 PINS D[7:0] HI-Z LOW BYTE LOW BYTE t12 HIGH BYTE HI-Z t13 HI-Z Figure 16. 8-Bit Parallel Interface –14– REV. A AD7675 serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. The output data is valid on both the rising and falling edge of the data clock. Depending on RDC/ SDIN input, the data can be read after each conversion, or during the following conversion. Figure 17 and Figure 18 show the detailed timing diagrams of these two modes. SERIAL INTERFACE The AD7675 is configured to use the serial interface when the SER/PAR is held high. The AD7675 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. MASTER SERIAL INTERFACE Internal Clock Usually, because the AD7675 has a longer acquisition phase than the conversion phase, the data is read immediately after conversion. That makes the mode master, read after conversion, the most recommended serial mode when it can be used. The AD7675 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7675 also generates a SYNC signal to indicate to the host when the RDC/SDIN = 0 EXT/INT = 0 CS, RD INVSCLK = INVSYNC = 0 t3 CNVST t28 BUSY t30 t29 t25 SYNC t18 t19 t14 t20 t24 t21 t26 1 SCLK 2 3 14 15 16 t15 t27 X SDOUT t16 D15 D14 D2 D1 D0 t23 t22 Figure 17. Master Serial Data Timing for Reading (Read after Convert) RDC/SDIN = 1 EXT/INT = 0 CS, RD INVSCLK = INVSYNC = 0 t1 CNVST t3 BUSY t17 t25 SYNC t14 t19 t20 t21 t15 SCLK 1 t24 2 3 14 15 t18 X SDOUT t16 t27 D15 t22 t26 16 D14 D2 D1 D0 t23 Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) REV. A –15– AD7675 In read-after-conversion mode, unlike in other modes, it should be noted that the signal BUSY returns low after the 16 data bits are pulsed out and not at the end of the conversion phase, which results in a longer BUSY width. the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when BUSY is low or, more importantly, that it does not transition during the latter half of BUSY high. In read-during-conversion mode, the serial clock and data toggle at appropriate instances, which minimizes potential feedthrough between digital activity and the critical conversion decisions. External Discontinuous Clock Data Read after Conversion To accommodate slow digital hosts, the serial clock can be slowed down by using DIVSCLK. SLAVE SERIAL INTERFACE External Clock The AD7675 is configured to accept an externally supplied serial data clock on the SCLK Pin when the EXT/INT Pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS and the data are output when both CS and RD are low. Thus, depending on CS, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 19 and Figure 20 show the detailed timing diagrams of these methods. Usually, because the AD7675 has a longer acquisition phase than the conversion phase, the data are read immediately after conversion. While the AD7675 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7675 provides error-correction circuitry that can correct for an improper bit decision made during the first half of This mode is the most recommended of the serial slave modes. Figure 19 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the result of this conversion can be read while both CS and RD are low. The data is shifted out, MSB first, with 16 clock pulses and is valid on both the rising and falling edge of the clock. One of the advantages of this method is that the conversion performance is not degraded because there are no voltage transient on the digital interface during the conversion process. Another advantage is the ability to read the data at any speed up to 40 MHz, which accommodates both slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7675 provides a “daisy chain” feature using the RDC/SDIN input pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when it is desired as it is, for instance, in isolated multiconverters applications. An example of the concatenation of two devices is shown in Figure 21. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the opposite edge of SCLK of the one used to shift out the data on SDOUT. Hence, the MSB of the “upstream” converter just follows the LSB of the “downstream” converter on the next SCLK cycle. RD = 0 INVSCLK = 0 EXT/INT = 1 CS BUSY t36 SCLK t35 t37 1 2 t31 3 14 15 16 17 18 t32 SDOUT X t16 D15 D14 D13 D1 D0 X15 X14 X14 X13 X1 X0 Y15 Y14 t34 SDIN X15 t33 Figure 19. Slave Serial Data Timing for Reading (Read after Convert) –16– REV. A AD7675 16-bit wide interface or with a general purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7675 to prevent digital noise from coupling into the ADC. The following sections illustrate the use of the AD7675 with an SPI-equipped microcontroller, and the ADSP-21065L and ADSP-218x signal processors. External Clock Data Read During Conversion Figure 20 shows the detailed timing diagrams of this method. During a conversion, while both CS and RD are low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 16 clock pulses, and is valid on both rising and falling edges of the clock. The 16 bits have to be read before the current conversion is complete. If that is not done, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. There is no “daisy chain” feature in this mode, and RDC/SDIN input should always be tied either high or low. SPI Interface (MC68HC11) To reduce performance degradation due to digital activity, a fast discontinuous clock of 18 MHz at least is recommended to ensure that all the bits are read during the first half of the conversion phase. For this reason, this mode is more difficult to use. MICROPROCESSOR INTERFACING The AD7675 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The AD7675 is designed to interface either with a parallel 8-bit or Figure 22 shows an interface diagram between the AD7675 and an SPI-equipped microcontroller like the MC68HC11. To accommodate the slower speed of the microcontroller, the AD7675 acts as a slave device and data must be read after conversion. This mode also allows the “daisy chain” feature. The convert command could be initiated in response to an internal timer interrupt. The reading of output data, one byte at a time if necessary, could be initiated in response to the end-of-conversion signal (BUSY going low) using an interrupt line of the microcontroller. The Serial Peripheral Interface (SPI) on the MC68HC11 is configured for master mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and SPI interrupt enable (SPIE) = 1 by writing to the SPI Control Register (SPCR). The IRQ is configured for edge-sensitive-only operation (IRQE = 1 in OPTION register). RD = 0 INVSCLK = 0 EXT/INT = 1 CS CNVST BUSY t3 t35 t36 SCLK t37 1 2 t31 SDOUT 3 14 15 16 t32 X D15 D14 D13 D1 D0 t16 Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) BUSY OUT BUSY BUSY AD7675 #2 AD7675 #1 (DOWNSTREAM) (UPSTREAM) RDC/SDIN SDOUT RDC/SDIN CNVST SDOUT DATA OUT CNVST CS CS SCLK SCLK SCLK IN CS IN CNVST IN Figure 21. Two AD7675s in a “Daisy Chain” Configuration REV. A –17– AD7675 ground planes should be joined in only one place, preferably underneath the AD7675, or, at least, as close as possible to the AD7675. If the AD7675 is in a system where multiple devices require analog to digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7675. DVDD MC68HC11* AD7675* SER/PAR EXT/INT CS BUSY RD SDOUT INVSCLK CNVST SCLK IRQ MISO/SDI SCK I/O PORT *ADDITIONAL PINS OMITTED FOR CLARITY Figure 22. Interfacing the AD7675 to SPI Interface ADSP-21065L in Master Serial Interface As shown in Figure 23, the AD7675 can be interfaced to the ADSP-21065L using the serial interface in master mode without any glue logic required. This mode combines the advantages of reducing the wire connections and the ability to read the data during or after conversion maximum speed transfer (DIVSCLK[0:1] both low). The AD7675 is configured for the internal clock mode (EXT/ INT low) and acts, therefore, as the master device. The convert command can be generated by either an external low jitter oscillator or, as shown, by a FLAG output of the ADSP-21065L or by a frame output TFS of one serial port of the ADSP-21065L that can be used like a timer. The serial port on the ADSP21065L is configured for external clock (IRFS = 0), rising edge active (CKRE = 1), external late framed sync signals (IRFS = 0, LAFS = 1, RFSR = 1) and active high (LRFS = 0). The serial port of the ADSP-21065L is configured by writing to its receive control register (SRCTL)—see ADSP-2106x SHARC User’s Manual. Because the serial port within the ADSP-21065L will be seeing a discontinuous clock, an initial word reading has to be done after the ADSP-21065L has been reset to ensure that the serial port is properly synchronized to this clock during each following data read operation. DVDD ADSP-21065L* AD7675* SHARC RDC/SDIN EXT/INT CS INVSYNC SYNC SDOUT SCLK CNVST The power supply lines to the AD7675 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply’s impedance presented to the AD7675 and reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each power supply’s pins, AVDD, DVDD, and OVDD, close to and ideally right up against these pins and their corresponding ground pins. Additionally, low ESR 10 µF capacitors should be located in the vicinity of the ADC to further reduce low-frequency ripple. The DVDD supply of the AD7675 can be either a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, it is recommended if no separate supply is available, to connect the DVDD digital supply to the analog supply AVDD through an RC filter as shown in Figure 5, and connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7675 has four different ground pins: REFGND, AGND, DGND, and OGND. REFGND senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. AGND is the ground to which most internal ADC analog signals are referenced. This ground must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. SER/PAR RD It is recommended that running digital lines under the device should be avoided as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7675 to avoid noise coupling. Fast switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of feedthrough through the board. RFS DR RCLK FLAG OR TFS INVSCLK *ADDITIONAL PINS OMITTED FOR CLARITY Figure 23. Interfacing to the ADSP-21065L Using the Serial Master Mode The layout of the decoupling of the reference voltage is important. The decoupling capacitor should be close to the ADC and connected with short and large traces to minimize parasitic inductances. APPLICATION HINTS Layout Evaluating the AD7675 Performance The AD7675 has very good immunity to noise on the power supplies as can be seen in Figure 21. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD7675 should be designed so the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. Digital and analog A recommended layout for the AD7675 is outlined in the evaluation board for the AD7675. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the Eval-Control BRD2. –18– REV. A AD7675 OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] 1.4 mm Thick (ST-48) Dimensions shown in millimeters 1.60 MAX 0.75 0.60 0.45 PIN 1 INDICATOR 9.00 BSC SQ 37 48 36 1 1.45 1.40 1.35 SEATING PLANE 0.20 0.09 VIEW A 7 3.5 0 0.08 MAX COPLANARITY 0.15 0.05 7.00 BSC SQ TOP VIEW (PINS DOWN) 25 12 24 13 0.27 0.22 0.17 0.50 BSC VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC 48-Lead Frame Chip Scale Package [LFCSP] 7 mm  7 mm Body (CP-48) Dimensions shown in millimeters 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 6.75 BSC SQ TOP VIEW 0.25 REF 48 0.70 MAX 0.65 NOM 1 12 25 24 13 5.50 REF COPLANARITY 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 REV. A 5.25 4.70 2.25 BOTTOM VIEW 0.50 0.40 0.30 12 MAX PIN 1 INDICATOR 36 PIN 1 INDICATOR 1.00 0.90 0.80 0.30 0.23 0.18 –19– PADDLE CONNECTED TO AGND Revision History Location Page 7/02—Data Sheet changed from REV. 0 to REV. A. Added PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Edits to NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Additions to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 C02689–0–7/02(A) Added 48-Lead LFCSP to FEATURES and GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to Power Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 PRINTED IN U.S.A. Added 48-Lead Frame Chip Scale Package (LFCSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 –20– REV. A