AD7689CCPZRL7

16-Bit, 4-Channel/8-Channel, 250 kSPS PulSAR ADCs AD7682/AD7689 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS 0.5V TO VDD 10µF REFIN REF BAND GAP REF 2.3V TO 5.5V VDD AD7682/AD7689 1.8V VIO TO VDD TEMP SENSOR IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 CNV 16-BIT SAR ADC MUX SPI SERIAL INTERFACE ONE-POLE LPF SCK SDO DIN SEQUENCER COM GND Figure 1. GENERAL DESCRIPTION The AD7682/AD7689 are 4-channel/8-channel, 16-bit, charge redistribution successive approximation register (SAR) analogto-digital converters (ADCs) that operate from a single power supply, VDD. The AD7682/AD7689 contain all components for use in a multichannel, low power data acquisition system, including a true 16-bit SAR ADC with no missing codes; a 4-channel (AD7682) or 8-channel (AD7689) low crosstalk multiplexer that is useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order. The AD7682/AD7689 use a simple serial port interface (SPI) for writing to the configuration register and receiving conversion results. The SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput. Multichannel system monitoring Battery-powered equipment Medical instruments: ECG/EKG Mobile communications: GPS Power line monitoring Data acquisition Seismic data acquisition systems Instrumentation Process control Rev. J 0.5V TO VDD – 0.5V 0.1µF 07353-001 16-bit resolution with no missing codes 4-channel (AD7682)/8-channel (AD7689) multiplexer with choice of inputs Unipolar single-ended Differential (GND sense) Pseudobipolar Throughput: 250 kSPS INL: ±0.4 LSB typical, ±1.5 LSB maximum (±23 ppm or FSR) Dynamic range: 93.8 dB SINAD: 92.5 dB at 20 kHz THD: −100 dB at 20 kHz Analog input range: 0 V to VREF with VREF up to VDD Multiple reference types Internal selectable 2.5 V or 4.096 V External buffered (up to 4.096 V) External (up to VDD) Internal temperature sensor (TEMP) Channel sequencer, selectable 1-pole filter, busy indicator No pipeline delay, SAR architecture Single-supply 2.3 V to 5.5 V operation with 1.8 V to 5.5 V logic interface Serial interface compatible with SPI, MICROWIRE, QSPI, and DSP Power dissipation 3.5 mW at 2.5 V/200 kSPS 12.5 mW at 5 V/250 kSPS Standby current: 50 nA Low cost grade available 20-lead 4 mm × 4 mm LFCSP package 20-lead 2.4 mm × 2.4 mm WLCSP package Continued on Page 4 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7682/AD7689 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference Output/Input .............................................. 26 Applications ....................................................................................... 1 Power Supply............................................................................... 28 Functional Block Diagram .............................................................. 1 Supplying the ADC from the Reference.................................. 28 General Description ......................................................................... 1 Digital Interface .............................................................................. 29 Revision History ............................................................................... 2 Reading/Writing During Conversion, Fast Hosts.................. 29 Specifications..................................................................................... 5 Reading/Writing After Conversion, Any Speed Hosts.......... 29 Timing Specifications .................................................................. 9 Reading/Writing Spanning Conversion, Any Speed Host .... 29 Absolute Maximum Ratings .......................................................... 12 Configuration Register, CFG .................................................... 29 ESD Caution ................................................................................ 12 General Timing Without a Busy Indicator ............................. 31 Pin Configurations and Function Descriptions ......................... 13 General Timing with a Busy Indicator .................................... 32 Typical Performance Characteristics ........................................... 17 Channel Sequencer .................................................................... 33 Terminology .................................................................................... 20 Theory of Operation ...................................................................... 21 Read/Write Spanning Conversion Without a Busy Indicator ...................................................................................... 34 Overview...................................................................................... 21 Read/Write Spanning Conversion with a Busy Indicator ..... 35 Converter Operation .................................................................. 21 Applications Information .............................................................. 36 Transfer Functions...................................................................... 22 Layout .......................................................................................... 36 Typical Connection Diagrams .................................................. 23 Evaluating the AD7682/AD7689 Performance ........................ 36 Analog Inputs .............................................................................. 24 Outline Dimensions ....................................................................... 37 Driver Amplifier Choice ............................................................ 26 Ordering Guide .......................................................................... 38 REVISION HISTORY 11/2019—Rev. I to Rev. J Updated Outline Dimensions ....................................................... 37 11/2019—Rev. H to Rev. I Changes to General Description Section ...................................... 4 Changes to Table 2 ............................................................................ 5 Added Table 3; Renumbered Sequentially .................................... 7 Changes to Table 4 ............................................................................ 8 Changes to Timing Specifications Section .................................... 9 Changes to Table 6 .......................................................................... 10 Changes to Pin 1, Pin 20 Description, Table 8............................ 13 Changes to Pin B6, Pin B8 Description, Table 9......................... 15 Changes to Figure 38 ...................................................................... 28 Updated Outline Dimensions ....................................................... 37 Changes to Ordering Guide .......................................................... 38 8/2017—Rev. G to Rev. H Changed CP-20-8 to CP-20-10 .................................... Throughout Change to Product Title................................................................... 1 Updated Outline Dimensions ....................................................... 34 Changes to Ordering Guide .......................................................... 35 6/2017—Rev. F to Rev. G Changed CP-20-10 to CP-20-8 .................................... Throughout Changes to Table 11 ........................................................................ 27 Updated Outline Dimensions ....................................................... 34 Changes to Ordering Guide .......................................................... 35 4/2016—Rev. E to Rev. F Changed ADA4841-x to ADA4805-1/ADA4807-1, Table 1........1 Added Endnote 6, Table 3; Renumbered Sequentially .................6 Changes to Figure 28 and Figure 29 ............................................ 20 Changes to Table 10 ....................................................................... 23 Changes to External Reference Section and the Reference Decoupling Section ........................................................................ 24 Changes to the Supplying the ADC from the Reference Section .. 25 Changes to Ordering Guide .......................................................... 35 1/2015—Rev. D to Rev. E Added WLCSP (Throughout) .........................................................1 Added WLCSP Signal-to-Noise and SINAD Parameters; Table 2 .................................................................................................3 Changed θJA Thermal Impedance (LFCSP) from 47.6°C/W to 48°C/W ...............................................................................................9 Added Figure 6, Figure 7, and Table 8 ......................................... 12 Changes to Layout Section ............................................................ 33 Added Figure 47; Outline Dimensions ........................................ 34 Changes to Ordering Guide .......................................................... 35 Rev. J | Page 2 of 38 Data Sheet AD7682/AD7689 4/2012—Rev. C to Rev. D Changes to Figure 27 ......................................................................18 Changed Internal Reference Section to Internal Reference/Temperature Sensor Section .......................................21 Changes to Internal Reference/Temperature Sensor Section ....21 Changed External Reference/Temperature Sensor Section to External Reference Section ............................................................22 Changes to External Reference and Internal Buffer Section and External Reference Section ............................................................22 Changes to REF Bit, Function Column, Table 10 .......................25 Updated Outline Dimensions ........................................................32 9/2011—Rev. B to Rev. C Changes to Internal Reference Section ........................................21 Changes to the External Reference and Internal Buffer Section ..............................................................................................22 Changes to the External Reference/Temperature Sensor Section ..............................................................................................22 Changes to Table 10, REF Bit Description ...................................25 6/2009—Rev. A to Rev. B Changes Table 6 ................................................................................. 8 Changes to Figure 37 ......................................................................25 Changes to Figure 38 ......................................................................26 3/2009—Rev. 0 to Rev. A Changes to Features Section, Applications Section, and Figure 1 ............................................................................................... 1 Added Table 2; Renumbered Sequentially ..................................... 3 Changed VREF to VREF ..................................................................... 4 Changes to Table 3 ............................................................................ 5 Changes to Table 4 ............................................................................ 6 Changes to Table 5 ............................................................................ 7 Deleted Endnote 2 in Table 6 ........................................................... 8 Changes to Figure 4, Figure 5, and Table 7 .................................... 9 Changes to Figure 6, Figure 9, and Figure 10 .............................. 11 Changes to Figure 22 ...................................................................... 13 Changes to Overview Section and Converter Operation Section .............................................................................................. 15 Changes to Table 8 .......................................................................... 16 Changes to Figure 26 and Figure 27 ............................................. 17 Changes to Bipolar Single Supply Section and Analog Inputs Section .............................................................................................. 18 Changes to Internal Reference/Temperature Sensor Section .... 20 Added Figure 31; Renumbered Sequentially ............................... 20 Changes to External Reference and Internal Buffer Section and External Reference Section ............................................................ 21 Added Figure 32 and Figure 33 ..................................................... 21 Changes to Power Supply Section ................................................. 22 Changes to Digital Interface Section, Reading/Writing After Conversion, Any Speed Hosts Section, and Configuration Register, CFG Section ..................................................................... 23 Changes to Table 10 ........................................................................ 24 Added General Timing Without a Busy Indicator Section and Figure 37 ........................................................................................... 25 Added General Timing With a Busy Indicator Section and Figure 38 ........................................................................................... 26 Added Channel Sequencer Section and Figure 39 ..................... 27 Changes to Read/Write Spanning Conversion Without a Busy Indicator Section and Figure 41 .................................................... 28 Changes to Read/Write Spanning Conversion with a Busy Indicator and Figure 43 .................................................................. 29 Changes to Evaluating AD7682/AD7689 Performance Section .............................................................................................. 30 Added Exposed Pad Notation to Outline Dimensions .............. 31 Changes to Ordering Guide ........................................................... 31 5/2008—Revision 0: Initial Version Rev. J | Page 3 of 38 AD7682/AD7689 Data Sheet The AD7682/AD7689 are housed in a tiny 20-lead lead frame chip scale package (LFCSP) and 20-lead wafer level chip scale package (WLCSP) with operation specified from −40°C to +85°C. The AD7689 includes an extended temperature range model with specifications guaranteed to a maximum temperature (TMAX) of +125°C. Table 1. Multichannel 14-Bit/16-Bit PulSAR® ADCs Type 14-Bit Channels 8 250 kSPS AD7949 16-Bit 4 AD7682 16-Bit 8 AD7689 Rev. J | Page 4 of 38 500 kSPS AD7699 ADC Driver ADA4805-1/ ADA4807-1 ADA4805-1/ ADA4807-1 ADA4805-1/ ADA4807-1 Data Sheet AD7682/AD7689 SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, reference voltage (VREF) = VDD, all specifications, TA = −40°C to +85°C, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR 1 Leakage Current at 25°C Input Impedance 2 THROUGHPUT Conversion Rate Full Bandwidth 3 ¼ Bandwidth3 Transient Response ACCURACY No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Gain Error 5 Gain Error Match Gain Error Temperature Drift Offset Error5 Offset Error Match Offset Error Temperature Drift Power Supply Sensitivity AC ACCURACY 6 Dynamic Range Signal-to-Noise (SNR) LFCSP Test Conditions/ Comments AD7689A Typ Max Min 16 Min 16 AD7682B/AD7689B Typ Max Unit Bits Unipolar mode Bipolar mode Positive input, unipolar and bipolar modes Negative or COM input, unipolar mode Negative or COM input, bipolar mode Input frequency (fIN) = 250 kHz Acquisition phase 0 −VREF/2 −0.1 +VREF +VREF/2 VREF + 0.1 0 −VREF/2 −0.1 +VREF +VREF/2 VREF + 0.1 V V V −0.1 +0.1 −0.1 +0.1 V VREF/2 + 0.1 VREF/2 − 0.1 VREF/2 + 0.1 V VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V Full-scale step, full bandwidth Full-scale step, ¼ bandwidth 0 0 0 0 VREF/2 − 0.1 VREF/2 68 68 dB 1 1 nA 250 200 62.5 50 1.8 REF = VDD = 5 V +4 +32 −8 −4 +32 −8 ±2 ±1 fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 4.096 V, internal REF fIN = 20 kHz, VREF = 2.5 V, internal REF 16 −1.5 −1 0.6 −32 VDD = 5 V ± 5% 0 0 0 0 14.5 15 −4 VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V VREF/2 −32 ±32 ±2 ±1 −4 250 200 62.5 50 1.8 kSPS kSPS kSPS kSPS µs 14.5 µs ±0.4 ±0.25 0.5 ±1 ±0.5 ±1 +1.5 +1.5 ±1 ±5 ±0.5 ±1 +8 +8 +4 +4 Bits LSB 4 LSB LSB LSB LSB ppm/°C LSB LSB LSB ppm/°C ±1.5 ±1.5 LSB 90.5 93.8 dB 7 90 89 92.5 91 93.5 92.3 dB dB 86 87.5 88.8 dB Rev. J | Page 5 of 38 AD7682/AD7689 Parameter WLFCSP SINAD 8 LFCSP WLFCSP Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Channel to Channel Crosstalk SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay TEMPERATURE RANGE Specified Performance Data Sheet Test Conditions/ Comments fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 4.096 V, internal REF fIN = 20 kHz, VREF = 2.5 V, internal REF Min AD7689A Typ Max Min 91 89.5 AD7682B/AD7689B Typ Max 92 91 Unit dB dB 86 87.5 dB fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 5 V, −60 dB input fIN = 20 kHz, VREF = 4.096 V, internal REF fIN = 20 kHz, VREF = 2.5 V, internal REF fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 5 V, −60 dB input fIN = 20 kHz, VREF = 4.096 V, internal REF fIN = 20 kHz, VREF = 2.5 V, internal REF fIN = 20 kHz 89 30.5 91 92.5 33.5 dB dB 88 90 91 dB 86 87 88.4 dB 89.5 91 32 dB dB 88.5 89.5 dB 85.5 87 dB −97 −100 dB fIN = 20 kHz 105 110 dB fIN = 100 kHz on adjacent channel(s) −120 −125 dB Full bandwidth ¼ bandwidth VDD = 5 V 1.7 0.425 2.5 1.7 0.425 2.5 MHz MHz ns Minimum temperature (TMIN) to TMAX −40 +85 −40 +85 °C CMRR means common mode rejection ratio. See the Analog Inputs section. 3 The bandwidth is set in the configuration register. 4 With the 5 V input range, one LSB is 76.3 µV. 5 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 6 With VDD = 5 V, unless otherwise noted. 7 All specifications expressed in decibels are referred to a full-scale input range (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 8 See the Terminology section. 1 2 Rev. J | Page 6 of 38 Data Sheet AD7682/AD7689 VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, VREF = VDD, all specifications, TA = −40°C to +125°C, unless otherwise noted. Table 3. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current at 25°C Input Impedance 1 THROUGHPUT Conversion Rate Full Bandwidth 2 ¼ Bandwidth3 Transient Response ACCURACY No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Gain Error 4 Gain Error Match Gain Error Temperature Drift Offset Error5 Offset Error Match Offset Error Temperature Drift Power Supply Sensitivity AC ACCURACY 5 Dynamic Range Signal-to-Noise Total Harmonic Distortion (THD) Spurious-Free Dynamic Range Channel-to-Channel Crosstalk SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay TEMPERATURE RANGE Specified Performance Test Conditions/Comments Min 16 Unipolar mode Bipolar mode Positive input, unipolar and bipolar modes Negative or COM input, unipolar mode Negative or COM input, bipolar mode fIN = 250 kHz Acquisition phase 0 −VREF/2 −0.1 −0.1 VREF/2 − 0.1 VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V Full-scale step, full bandwidth Full-scale step, ¼ bandwidth 0 0 0 0 16 −2.0 −1 REF = VDD = 5 V −8 −4 VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V −8 −6 VDD = 5 V ± 5% fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 4.096 V, internal REF fIN = 20 kHz, VREF = 2.5 V, internal REF fIN = 20 kHz fIN = 20 kHz fIN = 100 kHz on adjacent channel(s) 92 89.5 86.5 Full bandwidth ¼ bandwidth VDD = 5 V TMIN to TMAX −40 AD7689C Typ Max VREF/2 68 1 ±0.4 ±0.25 0.5 ±1 ±0.5 ±1 ±1 ±5 ±0.5 ±1 ±1.5 +VREF +VREF/2 VREF + 0.1 +0.1 VREF/2 + 0.1 V V V V V dB nA 250 200 62.5 50 1.8 14.5 kSPS kSPS kSPS kSPS µs µs +2.0 +1.8 +8 +4 +8 +6 2 Rev. J | Page 7 of 38 Bits LSB 3 LSB LSB LSB LSB ppm/°C LSB LSB LSB ppm/°C LSB 93.8 dB 6 93.5 92.3 88.8 −100 110 −125 dB dB dB dB dB dB 1.7 0.425 2.5 MHz MHz ns +125 See the Analog Inputs section. The bandwidth is set in the configuration register. 3 With the 5 V input range, one LSB is 76.3 µV. 4 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 5 With VDD = 5 V, unless otherwise noted. 6 All specifications expressed in decibels are referred to an FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 1 Unit Bits °C AD7682/AD7689 Data Sheet VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, VREF = VDD, all specifications, TA = −40°C to +85°C or TA = −40°C to +125°C (AD7689C), unless otherwise noted. Table 4. Parameter INTERNAL REFERENCE REF Output Voltage REFIN Output Voltage 1 REF Output Current Temperature Drift Line Regulation Long-Term Drift Turn-On Settling Time EXTERNAL REFERENCE Voltage Range Current Drain 2 TEMPERATURE SENSOR Output Voltage 3 Temperature Sensitivity DIGITAL INPUTS Logic Levels Input Voltage Low (VIL) High (VIH) Input Current Low (IIL) High (IIH) DIGITAL OUTPUTS Data Format 4 Pipeline Delay 5 Output Voltage Low (VOL) High (VOH) POWER SUPPLIES VDD 6 VIO Standby Current 7, 8 Power Dissipation Energy per Conversion TEMPERATURE RANGE 9 Specified Performance Test Conditions/Comments Min Typ Max Unit 2.5 V at 25°C 4.096 V at 25°C 2.5 V at 25°C 4.096 V at 25°C 2.490 4.086 2.500 4.096 1.2 2.3 ±300 ±10 ±15 50 5 2.510 4.106 V V V V µA ppm/°C ppm/V ppm ms VDD + 0.3 VDD − 0.5 50 V V µA 283 1 mV mV/°C VDD = 5 V ± 5% 1000 hours Reference capacitor (CREF) = 10 µF REF input REFIN input (buffered) 250 kSPS, REF = 5 V 0.5 0.5 25°C Sink current (ISINK) = 500 µA Source current (ISOURCE) = −500 µA −0.3 0.7 × VIO +0.3 × VIO VIO + 0.3 V V −1 −1 +1 +1 µA µA 0.4 V V 5.5 VDD + 0.3 V V nA µW mW mW mW nJ VIO − 0.3 Specified performance Specified performance VDD and VIO = 5 V at 25°C VDD = 2.5 V, 100 kSPS throughput VDD = 2.5 V, 200 kSPS throughput VDD = 5 V, 250 kSPS throughput VDD = 5 V, 250 kSPS throughput with internal reference VDD = 5 V 2.3 1.8 TMIN to TMAX, AD7682B/AD7689B, AD7689A TMIN to TMAX, AD7689C −40 −40 50 1.7 3.5 12.5 15.5 60 18 21 +85 +125 °C °C This is the output from the internal band gap. This is an average current and scales with throughput. The output voltage is internal and present on a dedicated multiplexer input. 4 Unipolar mode is serial 16-bit straight binary. Bipolar mode is serial, 16-bit twos complement. 5 Conversion results available immediately after completed conversion. 6 The minimum VDD supply must be 3 V when the 2.5 V internal reference is enabled, and 4.5 V when the 4.096 V internal reference is enabled. See Figure 23 for more information. 7 With all digital inputs forced to VIO or GND as required. 8 During acquisition phase. 9 Contact an Analog Devices, Inc., sales representative for the extended temperature range. 1 2 3 Rev. J | Page 8 of 38 Data Sheet AD7682/AD7689 TIMING SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications, TA = −40°C to +85°C or TA = −40°C to +125°C (AD7689C), unless otherwise noted. See Figure 2 and Figure 3 for load conditions. Table 5. Parameter CONVERSION TIME CNV Rising Edge to Data Available ACQUISITION TIME TIME BETWEEN CONVERSIONS DATA WRITE/READ DURING CONVERSION SCK Period Low Time High Time Falling Edge to Data Remains Valid Falling Edge to Data Valid Delay VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.8 V CNV Pulse Width Low to SDO D15 MSB Valid VIO Above 2.7 V VIO Above 2.3 V VIO Above 1.8 V High or Last SCK Falling Edge to SDO High Impedance Low to SCK Rising Edge DIN Valid Setup Time from SCK Rising Edge Valid Hold Time from SCK Rising Edge Symbol Min tCONV tACQ tCYC tDATA 1.8 4.0 tSCK tSCKL tSCKH tHSDO tDSDO Typ Max Unit 2.2 µs µs µs µs 1.2 tDSDO + 2 11 11 4 ns ns ns ns 18 23 28 tCNVH tEN Rev. J | Page 9 of 38 10 ns ns ns ns 18 22 25 32 tDIS tCLSCK 10 ns ns ns ns ns tSDIN tHDIN 5 5 ns ns AD7682/AD7689 Data Sheet VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications, TA = −40°C to +85°C or TA = −40°C to +125°C (AD7689C), unless otherwise noted. See Figure 2 and Figure 3 for load conditions. Table 6. Parameter CONVERSION TIME CNV Rising Edge to Data Available, TA ≤ 85°C CNV Rising Edge to Data Available, TA ≤ 125°C (AD7689C Only) ACQUISITION TIME TA ≤ 85°C TA ≤ 125°C (AD7689C Only) TIME BETWEEN CONVERSIONS DATA WRITE/READ DURING CONVERSION SCK Period Low Time High Time Falling Edge to Data Remains Valid Falling Edge to Data Valid Delay VIO Above 3 V, TA ≤ 85°C VIO Above 3 V, TA ≤ 125°C, (AD7689C Only) VIO Above 2.7 V, TA ≤ 85°C VIO Above 2.7 V, TA ≤ 125°C, (AD7689C Only) VIO Above 2.3 V, TA ≤ 85°C VIO Above 2.3 V, TA ≤ 125°C, (AD7689C Only) VIO Above 1.8 V, TA ≤ 85°C VIO Above 1.8 V, TA ≤ 125°C, (AD7689C Only) CNV Pulse Width Low to SDO D15 MSB Valid VIO Above 3 V, TA ≤ 85°C VIO Above 3 V, TA ≤ 125°C, (AD7689C Only) VIO Above 2.7 V, TA ≤ 85°C VIO Above 2.7 V, TA ≤ 125°C, (AD7689C Only) VIO Above 2.3 V, TA ≤ 85°C VIO Above 2.3 V, TA ≤ 125°C, (AD7689C Only) VIO Above 1.8 V, TA ≤ 85°C VIO Above 1.8 V, TA ≤ 125°C, (AD7689C Only) High or Last SCK Falling Edge to SDO High Impedance Low to SCK Rising Edge DIN Valid Setup Time from SCK Rising Edge Valid Hold Time from SCK Rising Edge Rev. J | Page 10 of 38 Symbol Min tCONV tCONV tACQ tACQ tCYC tDATA 1.8 1.7 5 tSCK tSCKL tSCKH tHSDO tDSDO tDSDO + 2 12 12 5 Typ Max Unit 3.2 3.3 µs µs 1.2 µs µs µs µs ns ns ns ns 24 30 30 36 38 44 48 54 tEN tCNVH 10 ns ns ns ns ns ns ns ns ns 21 27 27 33 35 41 45 51 50 tDIS tCLSCK 10 ns ns ns ns ns ns ns ns ns ns tSDIN tHDIN 5 5 ns ns Data Sheet AD7682/AD7689 IOL 500µA 1.4V TO SDO 500µA 07353-002 CL 50pF IOH Figure 2. Load Circuit for Digital Interface Timing 70% VIO 30% VIO tDELAY tDELAY 0.8V OR 0.5V2 12V IF VIO ABOVE 2.5V, VIO – 0.5V IF 20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO 2V OR VIO – 0.5V1 0.8V OR 0.5V2 VIO BELOW 2.5V. BELOW 2.5V. Figure 3. Voltage Levels for Timing Rev. J | Page 11 of 38 07353-003 2V OR VIO – 0.5V1 AD7682/AD7689 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Analog Inputs INx,1 COM REF, REFIN Supply Voltages VDD, VIO to GND VIO to VDD DIN, CNV, SCK to GND SDO to GND Storage Temperature Range Junction Temperature Thermal Impedance (LFCSP) θJA θJC 1 Rating GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA GND − 0.3 V to VDD + 0.3 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 48°C/W 4.4°C/W See the Analog Inputs section. Rev. J | Page 12 of 38 Data Sheet AD7682/AD7689 TOP VIEW (Not to Scale) 15 14 13 12 11 VIO SDO SCK DIN CNV VDD REF REFIN GND GND 1 2 3 4 5 AD7689 TOP VIEW (Not to Scale) 15 14 13 12 11 VIO SDO SCK DIN CNV NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. 07353-004 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. 07353-005 AD7682 IN4 6 IN5 7 IN6 8 IN7 9 COM 10 1 2 3 4 5 NC 6 IN2 7 NC 8 IN3 9 COM 10 VDD REF REFIN GND GND 20 19 18 17 16 20 19 18 17 16 VDD IN3 IN2 IN1 IN0 VDD NC IN1 NC IN0 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 5. AD7689 LFCSP Pin Configuration Figure 4. AD7682 LFCSP Pin Configuration Table 8. AD7682 LFCSP and AD7689 LFCSP Pin Function Descriptions Pin No. 1, 20 LFCSP Mnemonic AD7682 AD7689 VDD VDD Type 1 P 2 REF REF AI/O 3 REFIN REFIN AI/O 4, 5 6 GND NC GND IN4 P AI 7 IN2 IN5 AI 8 NC IN6 AI 9 IN3 IN7 AI 10 COM COM AI 11 CNV CNV DI 12 DIN DIN DI 13 SCK SCK DI Description Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and 100 nF capacitors. When using the internal reference for a 2.5 V output, the minimum must be 3.0 V. When using the internal reference for 4.096 V output, the minimum must be 4.5 V. Reference Input/Output. See the Voltage Reference Output/Input section. When the internal reference is enabled, this pin produces a selectable system reference of 2.5 V or 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (VDD − 0.5 V, maximum), which is useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as close to REF as possible. See the Reference Decoupling section. Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section. When using the internal reference, the internal unbuffered reference voltage is present and requires decoupling with a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and (VDD − 0.5 V) that is buffered to the REF pin, as described in the REF pin description. Power Supply Ground. No Connection (AD7682). Analog Input Channel 4 (AD7689). Analog Input Channel 2 (AD7682). Analog Input Channel 5 (AD7689). No Connection (AD7682). Analog Input Channel 6 (AD7689). Analog Input Channel 3 (AD7682). Analog Input Channel 7 (AD7689). Common Channel Input. All input channels, IN[7:0], can be referenced to a commonmode point of 0 V or VREF/2 V. Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held low, the busy indictor is enabled. Data Input. Use this input for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion. Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion. Rev. J | Page 13 of 38 AD7682/AD7689 Data Sheet Pin No. 14 LFCSP Mnemonic AD7682 AD7689 SDO SDO Type 1 DO 15 VIO VIO P 16 17 IN0 NC IN0 IN1 AI AI 18 IN1 IN2 AI 19 NC IN3 AI 21 EPAD EPAD NC Description Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary. In bipolar modes, conversion results are twos complement. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Analog Input Channel 0. No Connection (AD7682). Analog Input Channel 1 (AD7689). Analog Input Channel 1 (AD7682). Analog Input Channel 2 (AD7689). No Connection (AD7682). Analog Input Channel 3 (AD7689). Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. AI means analog input, AI/O means analog input/output, DI means digital input, DO means digital output, P means power, and NC means no internal connection. 1 Rev. J | Page 14 of 38 Data Sheet AD7682/AD7689 AD7682 A 6 5 NC VDD B C 7 REF D REFIN E 3 IN1 VDD GND AD7689 4 IN0 NC DIN GND NC 2 1 9 VIO A SDO C CNV IN2 NC D COM E 7 6 IN3 VDD B SCK IN3 8 REF 5 IN2 VDD REFIN GND 3 DIN 1 VIO SDO SCK IN7 IN5 2 IN0 IN1 GND IN4 4 CNV IN6 COM 07353-106 8 07353-105 9 Figure 7. AD7689 WLCSP Pin Configuration Figure 6. AD7682 WLCSP Pin Configuration Table 9. AD7682 WLCSP and AD7689 WLCSP Pin Function Descriptions Pin No. B6, B8 WLCSP Mnemonic AD7682 AD7689 VDD VDD Type 1 P C9 REF REF AI/O C7 REFIN REFIN AI/O D6, D8 A7 GND NC GND IN3 P AI E5 IN2 IN5 AI E3 NC IN6 AI D4 IN3 IN7 AI E1 COM COM AI D2 CNV CNV DI Description Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and 100 nF capacitors. When using the internal reference for a 2.5 V output, the minimum must be 3.0 V. When using the internal reference for 4.096 V output, the minimum must be 4.5 V. Reference Input/Output. See the Voltage Reference Output/Input section. When the internal reference is enabled, this pin produces a selectable system reference of 2.5 V or 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (VDD − 0.5 V, maximum), which is useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as close to REF as possible. See the Reference Decoupling section. Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section. When using the internal reference, the internal unbuffered reference voltage is present and requires decoupling with a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and (VDD − 0.5 V) that is buffered to the REF pin, as described in the REF pin description. Power Supply Ground. No Connection (AD7682). Analog Input Channel 3 (AD7689). Analog Input Channel 2 (AD7682). Analog Input Channel 5 (AD7689). No Connection (AD7682). Analog Input Channel 6 (AD7689). Analog Input Channel 3 (AD7682). Analog Input Channel 7 (AD7689). Common Channel Input. All input channels, IN[7:0], can be referenced to a commonmode point of 0 V or VREF/2 V. Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held low, the busy indictor is enabled. Rev. J | Page 15 of 38 AD7682/AD7689 Data Sheet Pin No. C5 WLCSP Mnemonic AD7682 AD7689 DIN DIN Type 1 DI C3 SCK SCK DI B2 SDO SDO DO A1 VIO VIO P A3 B4 IN0 NC IN0 IN1 AI AI A5 IN1 IN2 AI E7 NC IN4 AI Description Data Input. Use this input for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion. Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion. Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary. In bipolar modes, conversion results are twos complement. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Analog Input Channel 0. No connection (AD7682). Analog Input Channel 1 (AD7689). Analog Input Channel 1 (AD7682). Analog Input Channel 2 (AD7689). No Connection (AD7682). Analog Input Channel 4 (AD7689). AI means analog input, AI/O means analog input/output, DI means digital input, DO means digital output, P means power, and NC means no internal connection. 1 Rev. J | Page 16 of 38 Data Sheet AD7682/AD7689 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V to 5.5 V, VREF = 2.5 V to 5 V, VIO = 2.3 V to VDD, unless otherwise noted. 1.5 1.5 INL MAX = +0.34 LSB INL MIN = –0.44 LSB DNL MAX = +0.20 LSB DNL MIN = –0.22 LSB 1.0 1.0 0.5 DNL (LSB) INL (LSB) 0.5 0 0 –0.5 0 16,384 32,768 49,152 65,536 CODES –1.0 07353-009 –1.5 32,768 49,152 65,536 Figure 11. Differential Nonlinearity vs. Code, VREF = VDD = 5 V 160k σ = 0.50 VREF = VDD = 5V 180k 16,384 CODES Figure 8. Integral Nonlinearity vs. Code, VREF = VDD = 5 V 200k 0 07353-006 –0.5 –1.0 σ = 0.78 VREF = VDD = 2.5V 135,207 140k 160k 120k 135,326 124,689 100k 120k COUNTS COUNTS 140k 100k 80k 80k 63,257 60k 51,778 60k 40k 40k 20k 0 0 487 619 0 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 0 0 8001 8002 CODE IN HEX 6649 1 0 07353-007 0 7FFB 7FFC 7FFD 7FFE 7FFF 8000 60 1 8002 8003 Figure 12. Histogram of a DC Input at Code Center 0 0 VREF = VDD = 5V fS= 250kSPS fIN = 19.9kHz SNR = 92.9dB SINAD = 92.4dB THD = –102dB SFDR = 103dB SECOND HARMONIC = –111dB THIRD HARMONIC = –104dB –40 –60 –80 VREF = VDD = 2.5V fs= 200kSPS fIN = 19.9kHz SNR = 88.0dB SINAD = 87.0dB THD = –89dB SFDR = 89dB SECOND HARMONIC = –105dB THIRD HARMONIC = –90dB –20 AMPLITUDE (dB of Full-Scale) –20 –100 –120 –140 –40 –60 –80 –100 –120 –140 0 25 50 75 100 125 FREQUENCY (kHz) –180 0 25 50 75 FREQUENCY (kHz) Figure 13. 20 kHz FFT, VREF = VDD = 2.5 V Figure 10. 20 kHz Fast Fourier Transform (FFT), VREF = VDD = 5 V Rev. J | Page 17 of 38 100 07353-011 –160 –160 07353-008 AMPLITUDE (dB of Full-Scale) 4090 8001 CODE IN HEX Figure 9. Histogram of a DC Input at Code Center –180 78 07353-010 20k AD7682/AD7689 Data Sheet 95 95 90 90 85 85 SINAD (dB) 100 80 75 75 60 0 50 VREF VREF VREF VREF 70 65 100 150 200 60 FREQUENCY (kHz) 0 50 17.0 SNR AT 2kHz SINAD AT 2kHz SNR AT 20kHz SINAD AT 20kHz ENOB AT 2kHz ENOB AT 20kHz 16.5 200 130 –60 125 –65 –70 120 16.0 SFDR = 2kHz 115 –75 –80 110 15.5 88 15.0 86 14.5 SFDR (dB) 90 ENOB (Bits) –85 105 100 95 SFDR = 20kHz –90 THD = 20kHz –95 –100 90 84 14.0 –105 85 THD = 2kHz 80 82 –110 13.5 –115 75 1.5 2.0 2.5 3.0 3.5 4.0 4.5 13.0 5.5 5.0 70 1.0 07353-013 80 1.0 REFERENCE VOLTAGE (V) Figure 15. SNR, SINAD, and Effective Number of Bits (ENOB) vs. Reference Voltage 1.5 2.0 2.5 3.5 3.0 4.0 4.5 5.0 –120 5.5 REFERENCE VOLTAGE (V) Figure 18. Spurious-Free Dynamic Range (SFDR) and THD vs. Reference Voltage 96 –90 fIN = 20kHz fIN = 20kHz 94 VREF = VDD = 5V –95 THD (dB) VREF = VDD = 5V 90 –100 VREF = VDD = 2.5V VREF = VDD = 2.5V 88 –105 86 84 –55 –35 –15 5 25 45 65 85 TEMPERATURE (°C) 105 125 –110 –55 07353-014 SNR (dB) 92 –35 –15 5 25 45 65 TEMPERATURE (°C) Figure 16. SNR vs. Temperature Figure 19. THD vs. Temperature Rev. J | Page 18 of 38 85 105 125 07353-017 SNR, SINAD (dB) 150 Figure 17. SINAD vs. Frequency 96 92 100 FREQUENCY (kHz) Figure 14. SNR vs. Frequency 94 = VDD = 5V, –0.5dB = VDD = 5V, –10dB = VDD = 2.5V, –0.5dB = VDD = 2.5V, –10dB THD (dB) 65 = VDD = 5V, –0.5dB = VDD = 5V, –10dB = VDD = 2.5V, –0.5dB = VDD = 2.5V, –10dB 07353-041 VREF VREF VREF VREF 70 07353-012 80 07353-016 SNR (dB) 100 Data Sheet AD7682/AD7689 3000 100 2.5V INTERNAL REF 4.096V INTERNAL REF INTERNAL BUFFER, TEMP ON INTERNAL BUFFER, TEMP OFF EXTERNAL REF, TEMP ON EXTERNAL REF, TEMP OFF VIO VDD CURRENT (µA) 2500 –90 –100 0 50 100 150 200 FREQUENCY (kHz) 2000 60 1750 50 1500 40 1250 30 1000 2.5 3.0 94 91 90 89 VREF = VDD = 2.5V 140 2250 120 VDD = 5V, EXTERNAL REF 2000 100 80 1750 1500 87 160 VDD = 5V, INTERNAL 4.096V REF 2500 VDD CURRENT (µA) SNR (dB) 180 fS = 200kSPS 2750 VREF = VDD = 5V 88 60 VDD = 2.5, EXTERNAL REF 1250 86 40 –8 –6 –4 –2 0 INPUT LEVEL (dB) 07353-018 VIO 85 –10 1000 –55 –35 –15 5 25 45 65 85 105 20 125 TEMPERATURE (°C) Figure 24. Operating Currents vs. Temperature Figure 21. SNR vs. Input Level 25 3 2 VDD = 2.5V, 85°C 20 tDSDO DELAY (ns) 1 0 –1 UNIPOLAR ZERO UNIPOLAR GAIN BIPOLAR ZERO BIPOLAR GAIN –35 –15 5 15 VDD = 2.5V, 25°C 10 VDD = 5V, 85°C VDD = 5V, 25°C 5 VDD = 3.3V, 85°C VDD = 3.3V, 25°C 25 45 65 85 105 TEMPERATURE (°C) 125 07353-020 OFFSET ERROR AND GAIN ERROR (LSB) 20 5.5 5.0 3000 92 –3 –55 4.5 Figure 23. Operating Currents vs. Supply fIN = 20kHz 93 –2 4.0 VDD SUPPLY (V) Figure 20. THD vs. Frequency 95 3.5 07353-022 –120 70 VIO CURRENT (µA) –110 = VDD = 5V, –0.5dB = VDD = 2.5V, –0.5dB = VDD = 2.5V, –10dB = VDD = 5V, –10dB 07353-015 VREF VREF VREF VREF 2250 80 0 0 20 40 60 80 SDO CAPACITIVE LOAD (pF) 100 120 Figure 25. tDSDO Delay vs. SDO Capacitance Load and Supply Figure 22. Offset and Gain Error vs. Temperature Rev. J | Page 19 of 38 07353-023 THD (dB) –80 90 VIO CURRENT (µA) 2750 –70 fS = 200kSPS 07353-021 –60 AD7682/AD7689 Data Sheet TERMINOLOGY Least Significant Bit (LSB) The LSB is the smallest increment represented by a converter. For an ADC with N bits of resolution, the LSB expressed in volts is LSB (V) = VREF/2N Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 27). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition must occur at a level ½ LSB above analog ground. The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111…10 to 111…11) must occur for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation in LSB (or percentage of full-scale range) of the actual level of the last transition from the ideal level after the offset error is adjusted out. Closely related is the full-scale error (also in LSB or percentage of full-scale range), which includes the effects of the offset error. Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and the point at which the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the formula ENOB = (SINADdB − 1.76)/6.02 and is expressed in bits. Channel-to-Channel Crosstalk Channel-to-channel crosstalk is a measure of the level of crosstalk between any two adjacent channels. It is measured by applying a dc to the channel under test and applying a full-scale, 100 kHz sine wave signal to the adjacent channel(s). The crosstalk is the amount of signal that leaks into the test channel, and is expressed in decibels. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (VREF) measured at TMIN, T (25°C), and TMAX. It is expressed in ppm/°C as TCV REF (ppm/°C) = V REF ( Max ) – V REF ( Min) V REF (25°C ) × (T MAX – T MIN ) × 10 6 where: VREF (Max) = maximum VREF at TMIN, T (25°C), or TMAX. VREF (Min) = minimum VREF at TMIN, T (25°C), or TMAX. VREF (25°C) = VREF at 25°C. TMAX = 85°C. TMIN = –40°C. Rev. J | Page 20 of 38 Data Sheet AD7682/AD7689 THEORY OF OPERATION INx+ SWITCHES CONTROL MSB 32,768C 16,384C LSB 4C 2C C SW+ C BUSY REF COMP GND 32,768C 16,384C 4C 2C C CONTROL LOGIC OUTPUT CODE C MSB LSB SW– 07353-026 CNV INx– OR COM Figure 26. ADC Simplified Schematic OVERVIEW CONVERTER OPERATION The AD7682/AD7689 are 4-channel/8-channel, 16-bit, charge redistribution SAR ADCs. These devices are capable of converting 250,000 samples per second (250 kSPS) and power down between conversions. For example, when operating with an external reference at 1 kSPS, they consume 17 µW typically, ideal for battery-powered applications. The AD7682/AD7689 are successive approximation ADCs based on a charge redistribution DAC. Figure 26 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. The AD7682/AD7689 contain all of the components for use in a multichannel, low power data acquisition system, including the following: • • • • • • 16-bit SAR ADC with no missing codes 4-channel/8-channel, low crosstalk multiplexer Internal low drift reference and buffer Temperature sensor Selectable one-pole filter Channel sequencer These components are configured through an SPI-compatible, 14-bit register. Conversion results, also SPI compatible, can be read after or during conversions with the option for reading back the configuration associated with the conversion. The AD7682/AD7689 provide the user with an on-chip trackand-hold and do not exhibit pipeline delay or latency. The AD7682/AD7689 are specified from 2.3 V to 5.5 V and can be interfaced to any 1.8 V to 5 V digital logic family. They are housed in a 20-lead, 4 mm × 4 mm LFCSP and a 20-lead, 2.4 mm × 2.4 mm WLCSP that combine space savings and allow flexible configurations. They are pin-for-pin compatible with the 16-bit AD7699 and 14-bit AD7949. During the acquisition phase, terminals of the array tied to the comparator input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. The capacitor arrays are used as sampling capacitors and acquire the analog signal on the INx+ and INx− (or COM) inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− open first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the INx+ and INx− (or COM) inputs captured at the end of the acquisition phase applies to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4...VREF/32,768). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the device returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. Because the AD7682/AD7689 have an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev. J | Page 21 of 38 AD7682/AD7689 Data Sheet With the inputs configured for bipolar range (COM = VREF/2 or paired differentially with INx− = VREF/2), the data outputs are twos complement. TWOS STRAIGHT COMPLEMENT BINARY 011...111 111...111 011...110 011...101 111...110 111...101 The ideal transfer characteristic for the AD7682/AD7689 is shown in Figure 27 and for both unipolar and bipolar ranges with the internal 4.096 V reference. 100...010 000...010 100...001 000...001 100...000 000...000 –FSR –FSR + 1LSB –FSR + 0.5LSB +FSR – 1LSB +FSR – 1.5LSB ANALOG INPUT 07353-027 With the inputs configured for unipolar range (single-ended, COM with ground sense, or paired differentially with INx− as ground sense), the data output is straight binary. ADC CODE TRANSFER FUNCTIONS Figure 27. ADC Ideal Transfer Function Table 10. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR Unipolar Analog Input 1 VREF = 4.096 V 4.095938 V 2.048063 V 2.048 V 2.047938 V 62.5 μV 0V Digital Output Code (Straight Binary Hex) 0xFFFF 3 0x8001 0x8000 0x7FFF 0x0001 0x0000 4 With COM or INx− = 0 V or all INx referenced to GND. With COM or INx− = VREF/2. 3 This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above VREF − GND). 4 This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below GND). 1 2 Rev. J | Page 22 of 38 Bipolar Analog Input 2 VREF = 4.096 V 2.047938 V 62.5 μV 0V −62.5 μV −2.047938 V −2.048 V Digital Output Code (Twos Complement Hex) 0x7FFF3 0x0001 0x0000 0xFFFF 0x8001 0x80004 Data Sheet AD7682/AD7689 TYPICAL CONNECTION DIAGRAMS 5V REFIN VDD REF 0V TO VREF 100nF 100nF 10µF2 V+ 1.8V TO VDD 100nF VIO ADA4805-1/ ADA4807-1 3 IN0 V– AD7689 V+ DIN MOSI SCK SCK SDO MISO CNV SS IN[7:1] 0V TO VREF ADA4805-1/ ADA4807-1 3 V– 0V OR VREF /2 COM NOTES 1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION. 2. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). 3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA. 07353-028 GND Figure 28. Typical Application Diagram with Multiple Supplies 1.8V TO VDD +5V 10µF2 100nF 100nF 100nF V+ REF REFIN VDD VIO ADA4805-1/ V– ADA4807-1 3 IN0 AD7689 DIN MOSI SCK SCK SDO MISO CNV SS IN[7:1] V+ ADA4805-1/ V– ADA4807-1 3 VREF /2 COM GND NOTES 1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION. 2. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). 3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA. Figure 29. Typical Application Diagram Using Bipolar Input Rev. J | Page 23 of 38 07353-029 VREF p-p AD7682/AD7689 Data Sheet Unipolar or Bipolar 70 Figure 28 shows an example of the recommended connection diagram for the AD7682/AD7689 when multiple supplies are available. 65 60 55 CMRR (dB) Bipolar Single Supply Figure 29 shows an example of a system with a bipolar input using single supplies with the internal reference (optional different VIO supply). This circuit is also useful when the amplifier/signal conditioning circuit is remotely located with some common mode present. Note that for any input configuration, the INx inputs are unipolar and are always referenced to GND (no negative voltages even in bipolar range). ANALOG INPUTS 40 35 30 Figure 30 shows an equivalent circuit of the input structure of the AD7682/AD7689. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN[7:0] and COM. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this causes the diodes to become forward biased and to start conducting current. These diodes can handle a maximum forward-biased current of 130 mA. For instance, these conditions may eventually occur when the input buffer supplies are different from VDD. In such a case, for example, an input buffer with a short circuit, the current limitation can be used to protect the device. 10 100 FREQUENCY (kHz) 1k 10k Figure 31. Analog Input CMRR vs. Frequency During the acquisition phase, the impedance of the analog inputs can be modeled as a parallel combination of the capacitor, CPIN, and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 2.2 kΩ and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 27 pF and is mainly the ADC sampling capacitor. During the conversion phase, when the switches are opened, the input impedance is limited to CPIN. While the AD7682/AD7689 are acquiring, RIN and CIN make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise from the driving circuitry. The low-pass filter can be programmed for the full bandwidth or ¼ of the bandwidth with CFG[6], as shown in Table 12. This setting changes RIN to 19 kΩ. Note that the converter throughput must also be reduced by ¼ when using the filter. If the maximum throughput is used with the bandwidth (BW) set to ¼, the converter acquisition time, tACQ, is violated, resulting in increased THD. VDD D1 RIN CIN D2 07353-030 CPIN 1 Selectable Low-Pass Filter Input Structure INx+ OR INx– OR COM 45 07353-031 For this circuit, a rail-to-rail input/output amplifier can be used. However, take the offset voltage vs. input common-mode range into consideration (1 LSB = 62.5 μV with VREF = 4.096 V). Note that the conversion results are in twos complement format when using the bipolar input configuration. Refer to the AN-581 Application Note, Biasing and Decoupling Op Amps in Single Supply Applications, for additional details about using single-supply amplifiers. 50 GND Figure 30. Equivalent Analog Input Circuit This analog input structure allows the sampling of the true differential signal between INx+ and COM or INx+ and INx−. (COM or INx− = GND ± 0.1 V or VREF ± 0.1 V). By using these differential inputs, signals common to both inputs are rejected, as shown in Figure 31. Rev. J | Page 24 of 38 Data Sheet AD7682/AD7689 Figure 32 shows the different methods for configuring the analog inputs with the configuration register, CFG[12:10]. Refer to the Configuration Register, CFG section for more details. CH0+ IN0 CH0+ CH1+ IN1 CH1+ IN1 CH2+ IN2 CH2+ IN2 IN3 IN0 CH3+ IN3 CH3+ The analog inputs can be configured as shown in the following figures: CH4+ IN4 CH4+ IN4 CH5+ IN5 CH5+ IN5 • CH6+ IN6 CH6+ IN6 CH7+ IN7 CH7+ IN7 COM COM– COM • • • Figure 32 (A), single-ended referenced to system ground, CFG[12:10] = 1112. In this configuration, all inputs (IN[7:0]) have a range of GND to VREF. Figure 32 (B), bipolar differential with a common reference point, COM = VREF/2, CFG[12:10] = 0102. Unipolar differential with COM connected to a ground sense; CFG[12:10] = 1102. In this configuration, all inputs IN[7:0] have a range of GND to VREF. Figure 32 (C), bipolar differential pairs with the negative input channel referenced to VREF/2, CFG[12:10] = 00X2. Unipolar differential pairs with the negative input channel referenced to a ground sense, CFG[12:10] = 10X2. In these configurations, the positive input channels have the range of GND to VREF. The negative input channels are a sense referred to VREF/2 for bipolar pairs, or GND for unipolar pairs. The positive channel is configured with CFG[9:7]. If CFG[9:7] is even, then IN0, IN2, IN4, and IN6 are used. If CFG[9:7] is odd, then IN1, IN3, IN5, and IN7 are used, as indicated by the channels with parentheses in Figure 32 (C). For example, for IN0/IN1 pairs with the positive channel on IN0, CFG[9:7] = 0002. For IN4/IN5 pairs with the positive channel on IN5, CFG[9:7] = 1012. Note that for the sequencer, detailed in the Channel Sequencer section, the positive channels are always IN0, IN2, IN4, and IN6. Figure 32 (D), inputs configured in any of the preceding combinations (showing that the AD7682/AD7689 can be configured dynamically). GND A—8 CHANNELS, SINGLE ENDED GND B—8 CHANNELS, COMMON REFERNCE CH0+ (–) IN0 CH0+ (–) IN0 CH0– (+) IN1 CH0– (+) IN1 CH1+ (–) IN2 CH1+ (–) IN2 CH1– (+) IN3 CH1– (+) IN3 CH2+ (–) IN4 CH2+ IN4 CH2– (+) IN5 CH3+ IN5 CH3+ (–) IN6 CH4+ IN6 CH3– (+) IN7 CH5+ IN7 COM GND C—4 CHANNELS, DIFFERENTIAL COM– COM GND D—COMBINATION 07353-032 Input Configurations Figure 32. Multiplexed Analog Input Configurations Sequencer The AD7682/AD7689 include a channel sequencer useful for scanning channels in a repeated fashion. Refer to the Channel Sequencer section for further details on the sequencer operation. Source Resistance When the source impedance of the driving circuit is low, the AD7682/AD7689 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. Rev. J | Page 25 of 38 AD7682/AD7689 Data Sheet DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE OUTPUT/INPUT Although the AD7682/AD7689 are easy to drive, the driver amplifier must meet the following requirements: The AD7682/AD7689 allow the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference. The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7682/AD7689. Note that the AD7682/AD7689 have a noise much lower than most other 16-bit ADCs and, therefore, can be driven by a noisier amplifier to meet a given system noise spec-ification. The noise from the amplifier is filtered by the AD7682/AD7689 analog input circuit low-pass filter made by RIN and CIN, or by an external filter, if one is used. Because the typical noise of the AD7682/AD7689 is 35 µV rms (with VREF = 5 V), the SNR degradation due to the amplifier is SNRLOSS   35 = 20 log   π 2 2  35 + f − 3dB (Ne N ) 2        where: f–3dB is the input bandwidth in megahertz of the AD7682/ AD7689 (1.7 MHz in full BW or 425 kHz in ¼ BW), or the cutoff frequency of an input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/√Hz. • • For ac applications, the driver must have a THD performance commensurate with the AD7682/AD7689. Figure 20 shows THD vs. frequency for the AD7682/ AD7689. For multichannel, multiplexed applications on each input or input pair, the driver amplifier and the AD7682/ AD7689 analog input circuit must settle a full-scale step onto the capacitor array at a 16-bit level (0.0015%). In amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at a 16-bit level and must be verified prior to driver selection. The internal reference of the AD7682/AD7689 provide excellent performance and can be used in almost all applications. There are six possible choices of voltage reference schemes, briefly described in Table 12, with more details in each of the following sections. Internal Reference/Temperature Sensor The precision internal reference, suitable for most applications, can be set for either a 2.5 V or a 4.096 V output, as detailed in Table 12. With the internal reference enabled, the band gap voltage is also present on the REFIN pin, which requires an external 0.1 μF capacitor. Because the current output of REFIN is limited, it can be used as a source if followed by a suitable buffer, such as the AD8605. Note that the voltage of REFIN changes depending on the 2.5 V or 4.096 V internal reference. Enabling the reference also enables the internal temperature sensor, which measures the internal temperature of the AD7682/ AD7689, and is therefore useful for performing a system calibration. For applications requiring the use of the temperature sensor, the internal reference must be active (internal buffer can be disabled in this case). Note that, when using the temperature sensor, the output is straight binary referenced from the AD7682/AD7689 GND pin. The internal reference is temperature compensated to within 10 mV. The reference is trimmed to provide a typical drift of ±10 ppm/°C. Connect the AD7682/AD7689 as shown in Figure 33 for either a 2.5 V or 4.096 V internal reference. Table 11. Recommended Driver Amplifiers Amplifier ADA4805-1 ADA4807-1 ADA4627-1 ADA4522-1 ADA4500-2 Typical Application Low noise, small size, and low power Very low noise and high frequency Precision, low noise, and low input bias Precision, zero drift, and electromagnetic interference (EMI) enhanced Precision, rail-to-rail input/output, and zero input crossover distortion Rev. J | Page 26 of 38 10µF 100nF REF AD7682/ AD7689 REFIN TEMP GND 07353-049 • Figure 33. 2.5 V or 4.096 V Internal Reference Connection Data Sheet AD7682/AD7689 External Reference and Internal Buffer For improved drift performance, an external reference can be used with the internal buffer, as shown in Figure 34. The external source is connected to REFIN, the input to the on-chip unity-gain buffer, and the output is produced on the REF pin. An external reference can be used with the internal buffer with or without the temperature sensor enabled. Refer to Table 12 for register details. With the buffer enabled, the gain is unity and is limited to an input/output of VDD = −0.2 V. However, the maximum voltage allowable must be ≤VDD − 0.5 V. The internal reference buffer is useful in multiconverter applications because a buffer is typically required in these applications. In addition, a low power reference can be used because the internal buffer provides the necessary performance to drive the SAR architecture of the AD7682/AD7689. REF SOURCE ≤ (VDD – 0.5V) 10µF 100nF AD7682/ AD7689 REFIN TEMP GND 07353-132 REF Figure 34. External Reference Using Internal Buffer External Reference In any of the six voltage reference schemes, an external reference can be connected directly on the REF pin as shown in Figure 35 because the output impedance of REF is >5 kΩ. To reduce power consumption, power down the reference and buffer. Refer to Table 12 for register details. For improved drift performance, an external reference from the family of devices that includes the ADR430, ADR431, ADR433, ADR434, and ADR435, or the family of devices that includes the ADR440, ADR441, ADR443, ADR444, and ADR445 is recommended. REF SOURCE 0.5V < REF < (VDD + 0.3V) 10µF REF TEMP GND Figure 35. External Reference 07353-047 AD7682/ AD7689 NO CONNECTION REQUIRED REFIN Note that the best SNR is achieved with a 5 V external reference as the internal reference is limited to 4.096 V. The SNR degradation is as follows: SNRLOSS = 20log 4.096 5 Reference Decoupling Whether using an internal or external reference, the AD7682/ AD7689 voltage reference output/input, REF, has a dynamic input impedance and must be driven by a low impedance source with efficient decoupling between the REF and GND pins. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF and GND with minimum parasitic inductance. A 10 µF (X5R, 1206 size) ceramic chip capacitor is appropriate when using the internal reference, a member of the ADR430, ADR431, ADR433, ADR434, and ADR435 family of external references, a member of the ADR440, ADR441, ADR443, ADR444, and ADR445 family of external references, or a low impedance buffer such as the AD8031 or the AD8605. The placement of the reference decoupling capacitor is also important to the performance of the AD7682/AD7689, as explained in the Layout section. Mount the decoupling capacitor with a thick PCB trace on the same side as the ADC at the REF pin. The GND must also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias. If desired, smaller reference decoupling capacitor values down to 2.2 µF can be used with a minimal impact on performance, especially on DNL. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins. For applications that use multiple AD7682/AD7689 devices or other PulSAR devices, it is more effective to use the internal reference buffer to buffer the external reference voltage, thus reducing SAR conversion crosstalk. The voltage reference temperature coefficient directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the temperature coefficient. For instance, a ±10 ppm/°C temperature coefficient of the reference changes full scale by ±1 LSB/°C. Rev. J | Page 27 of 38 AD7682/AD7689 Data Sheet POWER SUPPLY SUPPLYING THE ADC FROM THE REFERENCE The AD7682/AD7689 use two power supply pins: an analog and digital core supply (VDD), and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD pins can be tied together. The AD7682/AD7689 are independent of power supply sequencing between VIO and VDD. Additionally, they are very insensitive to power supply variations over a wide frequency range, as shown in Figure 36. For simplified applications, the AD7682/AD7689, with their low operating current, can be supplied directly using an external reference circuit like the one shown in Figure 38. The reference line can be driven by the following: 75 • • • 70 The system power supply directly. A reference voltage with enough current output capability, such as the ADR430, ADR431, ADR433, ADR434, ADR435, ADR440, ADR441, ADR443, ADR444, or ADR445. A reference buffer, such as the AD8605, which can also filter the system power supply, as shown in Figure 38. 65 5V 5V 60 55 5V 50 10Ω 10kΩ 1µF AD8605 1µF 10µF REF 40 VDD VIO 10 1k 100 FREQUENCY (kHz) 10k 07353-034 1 1OPTIONAL Figure 38. Example of an Application Circuit Figure 36. Power Supply Rejection Ratio (PSRR) vs. Frequency The AD7682/AD7689 power down automatically at the end of each conversion phase. Therefore, the operating currents and power scale linearly with the sampling rate. This makes the device ideal for low sampling rates (even of a few hertz), and low battery-powered applications. 10,000 VDD = 5V, INTERNAL REF 1000 100 VDD = 5V, EXTERNAL REF 10 VDD = 2.5V, EXTERNAL REF 1 VIO 0.1 10 100 1k 10k SAMPLING RATE (SPS) 100k 1M 07353-040 0.010 0.001 REFERENCE BUFFER AND FILTER. Figure 37. Operating Currents vs. Sampling Rate Rev. J | Page 28 of 38 07353-035 AD7682/AD7689 35 OPERATING CURRENT (µA) 0.1µF 1 45 30 0.1µF Data Sheet AD7682/AD7689 DIGITAL INTERFACE The AD7682/AD7689 use a simple 4-wire interface and are compatible with SPI, MICROWIRE™, QSPI™, digital hosts, and DSPs (for example, Blackfin® ADSP-BF53x, SHARC®, ADSP-219x, and ADSP-218x). The SCK frequency required is calculated by The interface uses the CNV, DIN, SCK, and SDO signals and allows CNV, which initiates the conversion, to be independent of the readback timing. This is useful in low jitter sampling or simultaneous sampling applications. The time between tDATA and tCONV is a safe time when digital activity must not occur, or sensitive bit decisions may be corrupt. A 14-bit register, CFG[13:0], is used to configure the ADC for the channel to be converted, the reference selection, and other components, which are detailed in the Configuration Register, CFG section. When CNV is low, reading/writing can occur during conversion, acquisition, and spanning conversion (acquisition plus conversion). The CFG word is updated on the first 14 SCK rising edges, and conversion results are output on the first 15 (or 16, if busy mode is selected) SCK falling edges. If the CFG readback is enabled, an additional 14 SCK falling edges are required to output the CFG word associated with the conversion results with the CFG MSB following the LSB of the conversion result. A discontinuous SCK is recommended because the device is selected with CNV low, and SCK activity begins to write a new configuration word and clock out data. The timing diagrams indicate digital activity (SCK, CNV, DIN, and SDO) during the conversion. However, due to the possibility of performance degradation, digital activity occurs only prior to the safe data reading/writing time, tDATA, because the AD7682/AD7689 provide error correction circuitry that can correct for an incorrect bit during this time. From tDATA to tCONV, there is no error correction, and conversion results may be corrupted. Configure the AD7682/AD7689 and initiate the busy indicator (if desired) prior to tDATA. It is also possible to corrupt the sample by having SCK or DIN transitions near the sampling instant. Therefore, it is recommended to keep the digital pins quiet for approximately 20 ns before and 10 ns after the rising edge of CNV, using a discontinuous SCK whenever possible to avoid any potential performance degradation. READING/WRITING DURING CONVERSION, FAST HOSTS f SCK ≥ Number _ SCK _ Edges t DATA READING/WRITING AFTER CONVERSION, ANY SPEED HOSTS When reading/writing after conversion, or during acquisition (n), conversion results are for the previous (n − 1) conversion, and writing is for the (n + 1) acquisition. For the maximum throughput, the only time restriction is that the reading/writing take place during the tACQ (minimum) time. For slow throughputs, the time restriction is dictated by the throughput required by the user, and the host is free to run at any speed. Thus for slow hosts, data access must take place during the acquisition phase. READING/WRITING SPANNING CONVERSION, ANY SPEED HOST When reading/writing spanning conversion, the data access starts at the current acquisition (n) and spans into the conversion (n). Conversion results are for the previous (n − 1) conversion, and writing the CFG register is for the next (n + 1) acquisition and conversion. Similar to reading/writing during conversion, reading/writing must only occur up to tDATA. For the maximum throughput, the only time restriction is that reading/writing take place during the tACQ + tDATA time. For slow throughputs, the time restriction is dictated by the required throughput, and the host is free to run at any speed. Similar to reading/writing during acquisition, for slow hosts, the data access must take place during the acquisition phase with additional time into the conversion. Data access spanning conversion requires the CNV to be driven high to initiate a new conversion, and data access is not allowed when CNV is high. Therefore, the host must perform two bursts of data access when using this method. CONFIGURATION REGISTER, CFG When reading/writing during conversion (n), conversion results are for the previous (n − 1) conversion, and writing the CFG register is for the next (n + 1) acquisition and conversion. After the CNV is brought high to initiate conversion, it must be brought low again to allow reading/writing during conversion. Reading/writing must only occur up to tDATA and, because this time is limited, the host must use a fast SCK. The AD7682/AD7689 use a 14-bit configuration register (CFG[13:0]), as detailed in Table 12, to configure the inputs, the channel to be converted, the one-pole filter bandwidth, the reference, and the channel sequencer. The CFG register is latched (MSB first) on DIN with 14 SCK rising edges. The CFG update is edge dependent, allowing for asynchronous or synchronous hosts. The register can be written to during conversion, during acquisition, or spanning acquisition/conversion, and is updated at the end of conversion, tCONV (maximum). There is always a one deep delay when writing the CFG register. Rev. J | Page 29 of 38 AD7682/AD7689 Data Sheet • • • At power-up, the CFG register is undefined and two dummy conversions are required to update the register. To preload the CFG register with a factory setting, hold DIN high for two conversions (CFG[13:0] = 0x3FFF). This sets the AD7682/ AD7689 for the following: • • IN[7:0] unipolar referenced to GND, sequenced in order. Full bandwidth for a one-pole filter. Internal reference/temperature sensor disabled, buffer enabled. Enables the internal sequencer. No readback of the CFG register. Table 12 summarizes the configuration register bit details. See the Theory of Operation section for more details. 13 CFG 12 INCC 11 INCC 10 INCC 9 INx 8 INx 7 INx 6 BW 5 REF 4 REF 3 REF 2 SEQ 1 SEQ 0 RB Table 12. Configuration Register Description Bit(s) [13] Name CFG [12:10] INCC [9:7] INx [6] BW [5:3] REF [2:1] SEQ [0] RB 1 Description Configuration update. 0 = keep current configuration settings. 1 = overwrite contents of register. Input channel configuration. Selection of pseudo bipolar, pseudo differential, pairs, single-ended, or temperature sensor. Refer to the Input Configurations section. Bit 12 Bit 11 Bit 10 Function 0 0 X1 Bipolar differential pairs; INx− referenced to VREF/2 ± 0.1 V. 0 1 0 Bipolar; INx referenced to COM = VREF/2 ± 0.1 V. 0 1 1 Temperature sensor. 1 0 Unipolar differential pairs; INx− referenced to GND ± 0.1 V. X1 1 1 0 Unipolar, INx referenced to COM = GND ± 0.1 V. Unipolar, INx referenced to GND. 1 1 1 Input channel selection in binary fashion. AD7682 AD7689 Bit 9 X1 Bit 8 0 Bit 7 0 Channel IN0 Bit 9 0 Bit 8 0 Bit 7 0 Channel IN0 X1 0 1 IN1 0 0 1 IN1 X1 1 0 IN2 … … … … 1 1 IN3 1 1 1 IN7 X1 Select bandwidth for low-pass filter. Refer to the Selectable Low-Pass Filter section. 0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must be reduced to ¼. 1 = full BW. Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor. Refer to the Voltage Reference Output/Input section. Bit 5 Bit 4 Bit 3 Function 0 0 0 Internal reference and temperature sensor enabled. REF = 2.5 V buffered output. 0 0 1 Internal reference and temperature sensor enabled. REF = 4.096 V buffered output. 0 1 0 Use external reference. Temperature sensor enabled. Internal buffer disabled. 0 1 1 Use external reference. Internal buffer and temperature sensor enabled. 1 0 0 Do not use. 1 0 1 Do not use. 1 1 0 Use external reference. Internal reference, internal buffer, and temperature sensor disabled. Use external reference. Internal buffer enabled. Internal reference and temperature 1 1 1 sensor disabled. Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the Channel Sequencer section. Bit 2 Bit 1 Function 0 0 Disable sequencer. 0 1 Update configuration during sequence. 1 0 Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature. 1 1 Scan IN0 to IN[7:0] (set in CFG[9:7]). Read back the CFG register. 0 = read back current configuration at end of data. 1 = do not read back contents of configuration. X means don’t care. Rev. J | Page 30 of 38 Data Sheet AD7682/AD7689 GENERAL TIMING WITHOUT A BUSY INDICATOR When CNV is brought low after EOC, SDO is driven from high impedance to the MSB. Falling SCK edges clock out bits starting with MSB − 1. Figure 39 details the timing for all three modes: read/write during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC). Note that the gating item for both CFG and data readback is at the end of conversion (EOC). At EOC, if CNV is high, the busy indicator is disabled. The SCK can idle high or low depending on the clock polarity (CPOL) and clock phase (CPHA) settings if SPI is used. A simple solution is to use CPOL = CPHA = 0 as shown in Figure 39 with SCK idling low. As detailed in the Digital Interface section, the data access must occur up to safe data reading/writing time, tDATA. If the full CFG word is not written to prior to EOC, it is discarded and the current configuration remains. If the conversion result is not read out fully prior to EOC, it is lost as the ADC updates SDO with the MSB of the current conversion. For detailed timing, refer to Figure 42 and Figure 43, which depict reading/writing spanning conversion with all timing details, including setup, hold, and SCK. SOC tCYC POWER UP tCONV CONVERSION (n – 2) UNDEFINED PHASE From power-up, in any read/write mode, the first three conversion results are undefined because a valid CFG does not take place until the second EOC; therefore, two dummy conversions are required. If the state machine writes the CFG during the power-up state (RDC shown), the CFG register must be rewritten at the next phase. The first valid data occurs in phase (n + 1) when the CFG register is written during phase (n − 1). EOC EOC EOC EOC tDATA ACQUISITION (n – 1) UNDEFINED CONVERSION (n – 1) UNDEFINED ACQUISITION (n) CONVERSION (n) ACQUISITION (n + 1) CONVERSION (n + 1) ACQUISITION (n + 2) NOTE 1 CNV DIN CFG (n + 1) CFG (n) XXX CFG (n + 2) RDC SDO SCK DATA (n – 3) XXX MSB XXX 1 MSB XXX DATA (n – 2) XXX 1 16 DATA (n – 1) XXX 16 DATA (n) 16 1 16 1 NOTE 2 NOTE 1 CNV CFG (n) DIN RAC DATA (n – 2) XXX SDO SCK CFG (n + 1) CFG (n + 3) DATA (n) DATA (n + 1) DATA (n – 1) XXX 16 1 CFG (n + 2) 1 16 1 1 16 NOTE 2 NOTE 1 CNV RSC DIN CFG (n) SDO DATA (n – 2) XXX SCK 1 n CFG (n) DATA (n – 2) XXX n+1 16 1 CFG (n + 1) CFG (n + 1) DATA (n – 1) XXX DATA (n – 1) XXX n n+1 16 CFG (n + 2) CFG (n + 2) DATA (n) DATA (n) 1 n n+1 16 CFG (n + 3) DATA (n + 1) 1 n NOTES 1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR. 2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 39. General Interface Timing for the AD7682/AD7689 a Busy Indicator Rev. J | Page 31 of 38 07353-043 NOTE 2 AD7682/AD7689 Data Sheet GENERAL TIMING WITH A BUSY INDICATOR usually limited to 8-bit or 16-bit bursts. Therefore, the LSB remains. Because the transition noise of the AD7682/ AD7689 is 4 LSBs peak-to-peak (or greater), the LSB is low 50% of the time. For this interface, the SPI host needs to burst 24 SCKs, or a QSPI interface can be used and programmed for 17 SCKs. Figure 40 details the timing for all three modes: RDC, RAC, and RSC. Note that the gating item for both CFG and data readback is at EOC. The data access must occur up to safe data reading/writing time, tDATA. If the full CFG word is not written to prior to EOC, it is discarded and the current configuration remains. The SCK can idle high or low depending on the CPOL and CPHA settings if SPI is used. A simple solution is to use CPOL = CPHA = 1 (not shown) with SCK idling high. At the EOC, if CNV is low, the busy indicator enables. In addition, to generate the busy indicator properly, the host must assert a minimum of 17 SCK falling edges to return SDO to high impedance because the last bit on SDO remains active. Unlike the case detailed in the Read/Write Spanning Conversion Without a Busy Indicator section, if the conversion result is not read out fully prior to EOC, the last bit clocked out remains. If this bit is low, the busy signal indicator cannot be generated because the busy generation requires either a high impedance or a remaining bit high-to-low transition. A good example of this occurs when an SPI host sends 16 SCKs because these are START OF CONVERSION (SOC) tCYC POWER UP PHASE tCONV CONVERSION (n – 2) UNDEFINED From power-up, in any read/write mode, the first three conversion results are undefined because a valid CFG does not take place until the second EOC. Thus, two dummy conversions are required. Also, if the state machine writes the CFG during the power-up state (RDC shown), the CFG register needs to be rewritten again at the next phase. The first valid data occurs in phase (n + 1) when the CFG register is written during phase (n − 1). EOC EOC EOC EOC tDATA ACQUISITION (n – 1) UNDEFINED CONVERSION (n – 1) UNDEFINED CONVERSION (n) ACQUISITION (n) CONVERSION (n + 1) ACQUISITION (n + 1) ACQUISITION (n + 2) NOTE 1 CNV DIN CFG (n) XXX CFG (n + 1) CFG (n + 2) RDC SDO SCK 1 1 17 1 17 1 17 17 NOTE 2 CNV NOTE 1 DIN CFG (n) CFG (n + 1) CFG (n + 2) CFG (n + 3) RAC SDO SCK DATA (n) 1 17 1 1 17 DATA (n + 1) 1 17 NOTE 2 CNV NOTE 1 DIN CFG (n + 2) CFG (n + 1) CFG (n) CFG (n + 3) RSC SDO SCK DATA (n) DATA (n) 1 n n+1 17 1 n n+1 17 1 n n+1 17 DATA (n + 1) 1 NOTES 1. CNV MUST BE LOW PRIOR TO THE END OF CONVERSION (EOC) TO GENERATE THE BUSY INDICATOR. 2. A TOTAL OF 17 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 31 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 40. General Interface Timing for the AD7682/AD7689 With a Busy Indicator Rev. J | Page 32 of 38 07353-044 NOTE 2 Data Sheet AD7682/AD7689 CHANNEL SEQUENCER Conversion Without a Busy Indicator section for more details. The sequencer can also be used with the busy indicator and details for these timings can be found in the General Timing with a Busy Indicator section and the Read/Write Spanning Conversion with a Busy Indicator section. The AD7682/AD7689 include a channel sequencer useful for scanning channels in a repeated fashion. Channels are scanned as singles or pairs, with or without the temperature sensor, after the last channel is sequenced. For sequencer operation, the CFG register must be set during the (n − 1) phase after power-up. On phase (n), the sequencer setting takes place and acquires IN0. The first valid conversion result is available at phase (n + 1). After the last channel set in CFG[9:7] is converted, the internal temperature sensor data is output (if enabled), followed by acquisition of IN0. The sequencer starts with IN0 and finishes with IN[7:0] set in CFG[9:7]. For paired channels, the channels are paired depending on the last channel set in CFG[9:7]. Note that in sequencer mode, the channels are always paired with the positive input on the even channels (IN0, IN2, IN4, and IN6), and with the negative input on the odd channels (IN1, IN3, IN5, and IN7). For example, setting CFG[9:7] = 110 or 111 scans all pairs with the positive inputs dedicated to IN0, IN2, IN4, and IN6. Examples With all channels configured for unipolar mode to GND, including the internal temperature sensor, the sequence scans in the following order: CFG[2:1] are used to enable the sequencer. After the CFG register is updated, DIN must be held low while reading data out for Bit 13, or the CFG register begins updating again. IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7, TEMP, IN0, IN1, IN2… Note that while operating in a sequence, some bits of the CFG register can be changed. However, if changing CFG[11] (paired or single channel) or CFG[9:7] (last channel in sequence), the sequence reinitializes and converts IN0 (or IN0/IN1 pairs) after the CFG register is updated. For paired channels with the internal temperature sensor enabled, the sequencer scans in the following order: IN0, IN2, IN4, IN6, TEMP, IN0… Note that IN1, IN3, IN5, and IN7 are referenced to a GND sense or VREF/2, as detailed in the Input Configurations section. Figure 41 details the timing for all three modes without a busy indicator. Refer to the Read/Write Spanning Conversion Without a Busy Indicator section and the Read/Write Spanning SOC tCYC POWER UP CONVERSION (n – 2) UNDEFINED PHASE EOC EOC EOC tCONV EOC tDATA ACQUISITION (n – 1) UNDEFINED CONVERSION (n – 1) UNDEFINED ACQUISITION (n), IN0 CONVERSION (n), IN0 ACQUISITION (n + 1), IN1 CONVERSION (n + 1), IN1 ACQUISITION (n + 2), IN2 NOTE 1 CNV DIN CFG (n) XXX RDC SDO SCK DATA (n – 3) XXX MSB XXX 1 MSB XXX DATA (n – 2) XXX 1 16 2 DATA (n – 1) XXX 16 DATA IN0 16 1 16 1 NOTE 2 CNV CFG (n) DIN RAC DATA (n – 2) XXX SDO SCK 1 DATA (n – 1) XXX 16 1 DATA IN0 16 1 DATA IN1 1 16 NOTE 2 CNV DIN CFG (n) SDO DATA (n – 2) XXX SCK 1 n CFG (n) DATA (n – 2) XXX n+1 16 DATA (n – 1) XXX 1 n DATA (n – 1) XXX n+1 16 DATA IN0 DATA IN0 1 n n+1 16 DATA IN1 1 n NOTE 2 NOTES 1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR. 2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 41. General Channel Sequencer Timing Without a Busy Indicator Rev. J | Page 33 of 38 07353-046 RSC AD7682/AD7689 Data Sheet READ/WRITE SPANNING CONVERSION WITHOUT A BUSY INDICATOR host also must enable the MSB of the CFG register at this time (if necessary) to begin the CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG, and the first 15 SCK falling edges clock out the conversion results starting with MSB − 1. The restriction for both configuring and reading is that they both must occur before the tDATA time of the next conversion elapses. All 14 bits of CFG[13:0] must be written or they are ignored. In addition, if the 16-bit conversion result is not read back before tDATA elapses, it is lost. This mode is used when the AD7682/AD7689 are connected to any host using an SPI, serial port, or FPGA. The connection diagram is shown in Figure 42, and the corresponding timing is given in Figure 43. For the SPI, the host must use CPHA = CPOL = 0. Reading/writing spanning conversion is shown, which covers all three modes detailed in the Digital Interface section. For this mode, the host must generate the data transfer based on the conversion time. For an interrupt driven transfer that uses a busy indicator, refer to the Read/Write Spanning Conversion with a Busy Indicator section. The SDO data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th (or 30th) SCK falling edge, or when CNV goes high (whichever occurs first), SDO returns to high impedance. A rising edge on CNV initiates a conversion, forces SDO to high impedance, and ignores data present on DIN. After a conversion initiates, it continues until completion, irrespective of the state of CNV. CNV must be returned high before the safe data transfer time (tDATA), and held high beyond the conversion time (tCONV) to avoid generation of the busy signal indicator. If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 30 SCK falling edges is required to return SDO to high impedance if this is enabled. After the conversion is complete, the AD7682/AD7689 enter the acquisition phase and power-down. When the host brings CNV low after tCONV (maximum), the MSB enables on SDO. The CNV SS SDO MISO DIN MOSI SCK SCK FOR SPI USE CPHA = 0, CPOL = 0. 07353-036 DIGITAL HOST AD7682/ AD7689 Figure 42. Connection Diagram for the AD7682/AD7689 Without a Busy Indicator tCYC > tCONV tCONV tCONV tDATA tDATA tCNVH EOC EOC RETURN CNV HIGH FOR NO BUSY RETURN CNV HIGH FOR NO BUSY CNV tACQ (QUIET TIME) CONVERSION (n – 1) tSCK tSCKH SCK 14 UPDATE (n) CFG/SDO 16/ 30 15 CFG LSB DIN 1 tEN END CFG (n) SDO END DATA (n – 2) tSDIN tEN 14 15 16/ 30 X X tHDIN CFG LSB BEGIN CFG (n + 1) tHSDO tDSDO tEN END CFG (n + 1) SEE NOTE MSB LSB tDIS 2 CFG MSB X X tDIS UPDATE (n + 1) CFG/SDO SEE NOTE tCLSCK tSCKL (QUIET TIME) CONVERSION (n) ACQUISITION (n) LSB BEGIN DATA (n – 1) tDIS END DATA (n – 1) NOTES 1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF 15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS. 29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE. Figure 43. Serial Interface Timing for the AD7682/AD7689 Without a Busy Indicator Rev. J | Page 34 of 38 tDIS 07353-037 ACQUISITION (n - 1) Data Sheet AD7682/AD7689 READ/WRITE SPANNING CONVERSION WITH A BUSY INDICATOR the CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG register, and the first 16 SCK falling edges clock out the conversion results starting with the MSB. The restriction for both configuring and reading is that they both occur before the tDATA time elapses for the next conversion. All 14 bits of CFG[13:0] must be written or they are ignored. If the 16-bit conversion result is not read back before tDATA elapses, it is lost. This mode is used when the AD7682/AD7689 are connected to any host using an SPI, serial port, or FPGA with an interrupt input. The connection diagram is shown in Figure 44, and the corresponding timing is given in Figure 45. For the SPI, the host must use CPHA = CPOL = 1. Reading/writing spanning conversion is shown, which covers all three modes detailed in the Digital Interface section. The SDO data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 17th (or 31st) SCK falling edge, SDO returns to high impedance. If the optional SCK falling edge is not used, the busy feature cannot be detected, as described in the General Timing with a Busy Indicator section. A rising edge on CNV initiates a conversion, ignores data present on DIN, and forces SDO to high impedance. After the conversion initiates, it continues until completion, irrespective of the state of CNV. CNV must be returned low before the safe data transfer time (tDATA), and then held low beyond the conversion time (tCONV) to generate the busy signal indicator. When the conversion is complete, SDO transitions from high impedance to low (data ready), and with a pull-up to VIO, SDO can be used to interrupt the host to begin data transfer. If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 31 SCK falling edges is required to return SDO to high impedance if this is enabled. After the conversion is complete, the AD7682/AD7689 enter the acquisition phase and power-down. The host must enable the MSB of the CFG register at this time (if necessary) to begin VIO AD7682/ AD7689 DIGITAL HOST SDO MISO IRQ DIN MOSI SCK SCK 07353-038 SS CNV FOR SPI USE CPHA = 1, CPOL = 1. Figure 44. Connection Diagram for the AD7682/AD7689 with a Busy Indicator tCYC tCONV tDATA tACQ tDATA tCNVH CNV (QUIET TIME) CONVERSION (n – 1) tSCK tSCKH 15 SCK 16 UPDATE (n + 1) CFG/SDO SEE NOTE 1 2 15 16 17/ 31 X X X ACQUISITION (n + 1) tHDIN tSDIN X X LSB +1 END DATA (n – 2) CFG CFG MSB MSB –1 X tDIS END CFG (n) SDO (QUIET TIME) CONVERSION (n) UPDATE (n) CFG/SDO 17/ 31 tSCKL DIN ACQUISITION (n) BEIGN CFG (n + 1) MSB LSB tEN tHSDO tDSDO tEN MSB –1 BEGIN DATA (n – 1) LSB +1 tDIS LSB END DATA (n – 1) SEE NOTE NOTES: 1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF 16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS. 30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE. OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW. Figure 45. Serial Interface Timing for the AD7682/AD7689 with a Busy Indicator Rev. J | Page 35 of 38 tDIS END CFG (n + 1) tEN 07353-039 CONVERSION (n – 1) AD7682/AD7689 Data Sheet APPLICATIONS INFORMATION LAYOUT The printed circuit board (PCB) that houses the AD7682/ AD7689 must be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pin configuration of the AD7682/AD7689, with all its analog signals on the left side and all its digital signals on the right side, eases this task. the REF and GND pins and connecting them with wide, low impedance traces. Finally, the power supplies of the AD7682/AD7689 (VDD and VIO) must be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7682/AD7689, and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7682/AD7689 is used as a shield. Fast switching signals, such as CNV or clocks, must not run near analog signal paths. Avoid crossover of digital and analog signals. The AN-617 Application Note has information on PCB layout and assembly. This information is particularly important for guiding customers who do not have experience with WLCSP. Use at least one ground plane. It can be common or split between the digital and analog sections. In the latter case, join the planes underneath the AD7682/AD7689. Other recommended layouts for the AD7682/AD7689 are outlined in the documentation of the evaluation board for the AD7682/AD7689 (EVAL-AD7682EDZ/EVAL-AD7689EDZ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the converter and evaluation development data capture board, EVAL-CED1Z. EVALUATING THE AD7682/AD7689 PERFORMANCE The AD7682/AD7689 voltage reference input, REF, has a dynamic input impedance and must be decoupled with minimal parasitic inductances. This is achieved by placing the reference decoupling ceramic capacitor close to (ideally, right up against) Rev. J | Page 36 of 38 Data Sheet AD7682/AD7689 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.20 0.50 BSC 16 P IN 1 IN D IC AT O R AR E A OP T IO N S (SEE DETAIL A) 20 1 15 2.65 2.50 SQ 2.35 EXPOSED PAD 5 11 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-003578 SEATING PLANE 0.50 0.40 0.30 10 0.20 MIN 6 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 09-04-2018-C PIN 1 INDICATOR AREA 4.10 4.00 SQ 3.90 COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-11. Figure 46. 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-20-10) Dimensions shown in millimeters 2.430 2.390 SQ 2.350 9 8 BOTTOM VIEW (BALL SIDE UP) 7 6 5 4 3 2 1 A BALL A1 IDENTIFIER B C 0.433 REF D 0.50 REF E TOP VIEW (BALL SIDE DOWN) PKG-004466 SEATING PLANE SIDE VIEW 0.300 0.260 0.220 0.25 REF 0.50 REF COPLANARITY 0.05 0.230 0.200 0.170 Figure 47. 20-Ball Wafer Level Chip Scale Package [WLCSP] (CB-20-12) Dimensions shown in millimeters Rev. J | Page 37 of 38 05-13-2014-A 0.560 0.500 0.440 0.330 0.300 0.270 AD7682/AD7689 Data Sheet ORDERING GUIDE Model 1, 2 AD7682BCPZ AD7682BCPZRL7 AD7682BCBZ-RL7 AD7689ACPZ AD7689ACPZRL7 AD7689BCPZ AD7689BCPZRL7 AD7689BCBZ-RL7 AD7689CCPZ AD7689CCPZRL7 EVAL-AD7682EDZ EVAL-AD7689EDZ EVAL-CED1Z 1 2 Integral Nonlinearity ±1.5 LSB maximum ±1.5 LSB maximum ±1.5 LSB maximum ±4 LSB maximum ±4 LSB maximum ±1.5 LSB maximum ±1.5 LSB maximum ±1.5 LSB maximum ±2 LSB maximum ±2 LSB maximum No Missing Code 16 bits 16 bits 16 bits 15 bits 15 bits 16 bits 16 bits 16 bits 16 bits 16 bits Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C Package Description 20-Lead LFCSP 20-Lead LFCSP 20-Ball WLCSP 20-Lead LFCSP 20-Lead LFCSP 20-Lead LFCSP 20-Lead LFCSP 20-Ball WLCSP 20-Lead LFCSP 20-Lead LFCSP Evaluation Board Evaluation Board Converter Evaluation and Development Board Package Option CP-20-10 CP-20-10 CB-20-12 CP-20-10 CP-20-10 CP-20-10 CP-20-10 CB-20-12 CP-20-10 CP-20-10 Z = RoHS Complaint Part. The EVAL-CED1Z controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in EDZ. ©2008–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07353-0-11/19(J) Rev. J | Page 38 of 38 Ordering Quantity Tray, 490 Reel, 1,500 Reel, 1,500 Tray, 490 Reel, 1,500 Tray, 490 Reel, 1,500 Reel, 1,500 Tray, 490 Reel, 1,500