LC2MOS
20-Bit A/D Converter
AD7703
FEATURES
Monolithic 16-Bit ADC
0.0015% Linearity Error
On-Chip Self-Calibration Circuitry
Programmable Low-Pass Filter
0.1 Hz to 10 Hz Corner Frequency
0 V to +2.5 V or ⴞ2.5 V Analog Input Range
4 kSPS Output Data Rate
Flexible Serial Interface
Ultralow Power
APPLICATIONS
Industrial Process Control
Weigh Scales
Portable Instrumentation
Remote Data Acquisition
FUNCTIONAL BLOCK DIAGRAM
AVSS
DVSS
SC1
SC2
7
6
4
17
AD7703
DVDD 15
AVDD 14
AIN
ANALOG
MODULATOR
GENERAL DESCRIPTION
The AD7703 is a 20-bit ADC that uses a S-D conversion technique. The analog input is continuously sampled by an analog
modulator whose mean output duty cycle is proportional to the
input signal. The modulator output is processed by an on-chip
digital filter with a six-pole Gaussian response, which updates the
output data register with 16-bit binary words at word rates up to
4 kHz. The sampling rate, filter corner frequency, and output
word rate are set by a master clock input that may be supplied
externally, or by a crystal controlled on-chip clock oscillator.
The inherent linearity of the ADC is excellent and endpoint accuracy is ensured by self-calibration of zero and full scale, which
may be initiated at any time. The self-calibration scheme can
also be extended to null system offset and gain errors in the input
channel.
The output data is accessed through a flexible serial port, which
has an asynchronous mode compatible with UARTs and two
synchronous modes suitable for interfacing to shift registers or
the serial ports of industry-standard microcontrollers.
13 CAL
12 BP/UP
6-POLE GAUSSIAN
LOW-PASS
DIGITAL FILTER
11 SLEEP
8
CLOCK
GENERATOR
DGND
CALIBRATION
MICROCONTROLLER
20-BIT CHARGE BALANCE A/D
CONVERTER
9
VREF 10
AGND
CALIBRATION
SRAM
SERIAL INTERFACE
LOGIC
5
3
2
1
16
18
CLKIN
CLKOUT
MODE
CS
DRDY
20 SDATA
19 SCLK
PRODUCT HIGHLIGHTS
1. The AD7703 offers 20-bit resolution coupled with outstanding
0.0003% accuracy.
2. No missing codes ensures true, usable, 20-bit dynamic range,
removing the need for programmable gain and level-setting
circuitry.
3. The effects of temperature drift are eliminated by on-chip
self-calibration, which removes zero and gain error. External
circuits can also be included in the calibration loop to remove
system offsets and gain errors.
4. Flexible synchronous/asynchronous interface allows the
AD7703 to interface directly to the serial ports of industrystandard microcontrollers and DSP processors.
5. Low operating power consumption and an ultralow power
standby mode make the AD7703 ideal for loop-powered
remote sensing applications, or battery-powered portable
instruments.
CMOS construction ensures low power dissipation, and a powerdown mode reduces the idle power consumption to only 10 µW.
Rev. F
Document Feedback
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Technical Support
www.analog.com
AD7703–SPECIFICATIONS
(TA = 25ⴗC; AVDD = DVDD = +5 V; AVSS = DVSS = –5 V; VREF = +2.5 V; fCLKIN = 4.096 MHz;
BP/UP = +5 V; MODE = +5 V; AIN Source Resistance = 1 k⍀1 with 1 nF to AGND at AIN; unless otherwise noted.)
Parameter
STATIC PERFORMANCE
Resolution
Integral Nonlinearity, T MIN to TMAX
25°C
TMIN to TMAX
Differential Nonlinearity, TMIN to TMAX
Positive Full-Scale Error 3
Full-Scale Drift 4
Unipolar Offset Error 3
Unipolar Offset Drift 4
Bipolar Zero Error 3
Bipolar Zero Drift 4
Bipolar Negative Full-Scale Errors 3
Bipolar Negative Full-Scale Drift 4
Noise (Referred to Output)
DYNAMIC PERFORMANCE
Sampling Frequency, f S
Output Update Rate, f OUT
Filter Corner Frequency, f –3 dB
Settling Time to ±0.0007% FS
SYSTEM CALIBRATION
Positive Full-Scale Calibration Range
Positive Full-Scale Overrange
Negative Full-Scale Overrange
Maximum Offset Calibration Ranges 5, 6
Unipolar Input Range
Bipolar Input Range
Input Span7
ANALOG INPUT
Unipolar Input Range
Bipolar Input Range
Input Capacitance
Input Bias Current 1
LOGIC INPUTS
All Inputs Except CLKIN
VINL, Input Low Voltage
VINH, Input High Voltage
CLKIN
VINL, Input Low Voltage
VINH, Input High Voltage
IIN, Input Current
LOGIC OUTPUTS
VOL, Output Low Voltage
VOH, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
POWER REQUIREMENTS
Power Supply Voltages
Analog Positive Supply (AV DD)
Digital Positive Supply (DV DD)
Analog Negative Supply (AV SS)
Digital Negative Supply (DV SS)
Calibration Memory Retention
Power Supply Voltage
A/S Version2
B Version2
C Version2
Unit
20
±0.0015
±0.003
±0.003
±0.5
±4
±16
±19/±37
±4
±16
±26
±67 +48/–400
±4
±16
±13
±34 +24/–200
±8
±32
±10/±20
1.6
20
±0.0007
±0.0015
±0.0015
±0.5
±4
±16
±19
±4
±16
±26
±67
±4
±16
±13
±34
±8
±32
±10
1.6
20
±0.0003
±0.0008
±0.0012
±0.5
±4
±16
±19
±4
±16
±26
±67
±4
±16
±13
±34
±8
±32
±10
1.6
Bits
% FSR typ
% FSR max
% FSR max
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
LSB typ
LSB max
LSB typ
LSB rms typ
fCLKIN/256
fCLKIN/1024
fCLKIN/409,600
507904/f CLKIN
fCLKIN/256
fCLKIN/1024
fCLKIN/409,600
507904/fCLKIN
fCLKIN/256
fCLKIN/1024
fCLKIN/409,600
507904/fCLKIN
Hz
Hz
Hz
sec
VREF + 0.1
VREF + 0.1
–(VREF + 0.1)
VREF + 0.1
VREF + 0.1
–(VREF + 0.1)
VREF + 0.1
VREF + 0.1
–(VREF + 0.1)
V max
V max
V max
–(VREF + 0.1)
–0.4 VREF to +0.4 VREF
0.8 VREF
2 VREF + 0.2
–(VREF + 0.1)
–0.4 VREF to +0.4 VREF
0.8 VREF
2 VREF + 0.2
–(VREF + 0.1)
–0.4 VREF to +0.4 VREF
0.8 VREF
2 VREF + 0.2
V max
V max
V min
V max
0 to 2.5
±2.5
20
1
0 to 2.5
±2.5
20
1
0 to 2.5
±2.5
20
1
V
V
pF typ
nA typ
0.8
2.0
0.8
2.0
0.8
2.0
V max
V min
0.8
3.5
10
0.8
3.5
10
0.8
3.5
10
V max
V min
µA max
0.4
DVDD – 1
±10
9
0.4
DVDD – 1
±10
9
0.4
DVDD – 1
±10
9
V max
V min
µA max
pF typ
4.5/5.5
4.5/AVDD
–4.5/–5.5
–4.5/–5.5
4.5/5.5
4.5/AVDD
–4.5/–5.5
–4.5/–5.5
4.5/5.5
4.5/AVDD
–4.5/–5.5
–4.5/–5.5
V min/V max For Specified Performance
V min/V max
V min/V max
V min/V max
2.0
2.0
2.0
V min
–2–
Test Conditions/Comments
Guaranteed No Missing Codes
Temp Range: 0°C to +70°C
Specified Temp Range
Temp Range: 0°C to +70°C
Specified Temp Range
For Full-Scale Input Step
System calibration applies to
unipolar and bipolar ranges.
After calibration, if A IN > VREF,
the device will output all 1s.
If AIN < 0 (unipolar) or –V REF
(bipolar), the device will
output all 0s.
ISINK = 1.6 mA
ISOURCE = 100 µA
REV. F
AD7703
Parameter
POWER REQUIREMENTS
DC Power Supply Currents 8
Analog Positive Supply (AI DD)
Digital Positive Supply (DI DD)
Analog Negative Supply (AI SS)
Digital Negative Supply (DI SS)
Power Supply Rejection 9
Positive Supplies
Negative Supplies
Power Dissipation
Normal Operation
Standby Operations 10
A, B, C
S
A/S Version2
B Version2
C Version2
Unit
Test Conditions/Comments
2.7
2
2.7
0.1
2.7
2
2.7
0.1
2.7
2
2.7
0.1
mA max
mA max
mA max
mA max
Typically 2 mA
Typically 1 mA
Typically 2 mA
Typically 0.03 mA
70
75
70
75
70
75
dB typ
dB typ
37
37
37
mW max
20
40
20
40
20
40
µW max
µW max
SLEEP = Logic 1,
Typically 25 mW
SLEEP = Logic 0,
Typically 10 µW
NOTES
1
The AIN pin presents a very high impedance dynamic load that varies with clock frequency. A ceramic 1 nF capacitor from the AIN pin to AGND is necessary.
Source resistance should be 750 or less.
2
Temperature ranges are as follows: A, B, C Versions: –40°C to +85°C; S Version: –55°C to +125°C.
3
Applies after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.
4
Total drift over the specified temperature range after calibration at power-up at 25 °C. This is guaranteed by design and/or characterization. Recalibration at any
temperature will remove these errors.
5
In Unipolar mode, the offset can have a negative value (–V REF) such that the Unipolar mode can mimic Bipolar mode operation.
6
The specifications for input overrange and for input span apply additional constraints on the offset calibration range.
7
For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and negative full-scale
points. When using less than the maximum input span, the span range may be placed anywhere within the range of ± (VREF + 0.1).
8
All digital outputs unloaded. All digital inputs at 5 V CMOS levels.
9
Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.
10
CLKIN is stopped. All digital inputs are grounded.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
(TA = 25°C, unless otherwise noted.)
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Analog Input Voltage to AGND . . . AVSS – 0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ± 10 mA
Operating Temperature Range
Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C
Power Dissipation (DIP Package) to 75°C . . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
Power Dissipation (SOIC Package) to 75°C . . . . . . . 250 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . . 15 mW/°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7703 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. F
–3–
AD7703
(AVDD = DVDD = +5 V ⴞ 10%; AVSS = DVSS = –5 V ⴞ 10%; AGND = DGND = O V;
CLKIN = 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DVDD; unless otherwise noted.)
TIMING CHARACTERISTICS1, 2 f
Parameter
fCLKIN
3, 4
tr5
tf5
t1
t2
t3 6
SSC MODE
t4 7
t5
t6
7
t8
t98
t108, 9
SEC MODE
fSCLK
t11
t12
t137, 10
t1411
t158
t168
Limit at TMIN, TMAX
(A, B Versions)
Limit at TMIN, TMAX
(S, T Versions)
Unit
200
5
200
5
50
50
0
50
1000
200
5
200
5
50
50
0
50
1000
kHz min
MHz max
kHz min
MHz max
ns max
ns max
ns min
ns min
ns min
Master Clock Frequency: Internal Gate Oscillator
Typically 4.096 MHz
Master Clock Frequency: Externally Supplied
3/fCLKIN
100
250
300
790
l/fCLKIN + 200
4/fCLKIN + 200
3/fCLKIN
100
250
300
790
l/fCLKIN + 200
4/fCLKIN + 200
ns max
ns max
ns min
ns max
ns max
ns max
ns max
Data Access Time (CS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay (25 ns typ)
MSB Data Setup Time. Typically 380 ns.
SCLK High Pulsewidth. Typically 240 ns.
SCLK Low Pulsewidth. Typically 730 ns.
SCLK Rising Edge to Hi-Z Delay (l/fCLKIN + 100 ns typ)
CS High to Hi-Z Delay
5
35
160
160
150
250
200
5
35
160
160
150
250
200
MHz max
ns min
ns min
ns max
ns max
ns max
ns max
Serial Clock Input Frequency
SCLK Input High Pulsewidth
SCLK Low Pulsewidth
Data Access Time (CS Low to Data Valid). Typically 80 ns.
SCLK Falling Edge to Data Valid Delay. Typically 75 ns.
CS High to Hi-Z Delay
SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
Conditions/Comments
Digital Output Rise Time. Typically 20 ns.
Digital Output Fall Time. Typically 20 ns.
SC1, SC2 to CAL High Setup Time
SC1, SC2 Hold Time after CAL Goes High
SLEEP High to CLKIN High Setup Time
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with t r = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 1 to 6.
3
CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
4
The AD7703 is production tested with f CLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
5
Specified using 10% and 90% points on waveform of interest.
6
In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met.
7
t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
8
t9, t10, t15, and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is
the true bus relinquish time of the part and as such is independent of external bus loading capacitance.
9
If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
10
If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be
as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high
sooner than four CLKIN cycles plus 160 ns after CS goes low.
11
SDATA is clocked out on the falling edge of the SCLK input.
Specifications subject to change without notice.
CAL
IOL
1.6mA
t1
SC1, SC2
TO
OUTPUT
PIN
t2
SC1, SC2 VALID
+ 2.1V
CL
Figure 2. Calibration Control Timing
100pF
IOH
200A
CLKIN
Figure 1. Load Circuit for Access Time
and Bus Relinquish Time
t3
SLEEP
Figure 3. Sleep Mode Timing
–4–
REV. F
AD7703
CS
CS
t15
t10
DATA
VALID
SDATA
HI-Z
DATA
VALID
SDATA
Figure 4. SSC Mode Data Hold Time
HI-Z
Figure 5b. SEC Mode Data Hold Time
CLKIN
DRDY
CS
t7
CS
t12
SCLK
t11
t9
t8
t13
HI-Z
DB19
DB18
t5
t16
t14
DB1
DB0
HI-Z
SDATA
HI-Z
Figure 5a. SEC Mode Timing Diagram
DB19
DB18
HI-Z
DB1
DB0
Figure 6. SSC Mode Timing Diagram
DEFINITION OF TERMS
Linearity Error
Positive Full-Scale Overrange
Positive full-scale overrange is the amount of overhead available
to handle input voltages greater than +VREF (for example, noise
peaks or excess voltages due to system gain errors in system
calibration routines) without introducing errors due to overloading
the analog modulator or overflowing the digital filter.
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero-scale (not to be
confused with bipolar zero), a point 0.5 LSB below the first code
transition (000 . . . 000 to 000 . . . 001) and full-scale, a point
1.5 LSB above the last code transition (111 . . . 110 to 111 . . .
111). The error is expressed as a percentage of full scale.
Negative Full-Scale Overrange
This is the amount of overhead available to handle voltages below
–VREF without overloading the analog modulator or overflowing
the digital filter. Note that the analog input will accept negative
voltage peaks even in the Unipolar mode.
Differential Linearity Error
This is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential linearity error is expressed in
LSB. A differential linearity specification of ± 1 LSB or less
guarantees monotonicity.
Offset Calibration Range
In the system calibration modes (SC2 low), the AD7703 calibrates
its offset with respect to the AIN pin. The offset calibration range
specification defines the range of voltages, expressed as a
percentage of VREF, that the AD7703 can accept and still accurately
calibrate offset.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 111) from the ideal (VREF ± 3/2 LSB).
It applies to both positive and negative analog input ranges and
is expressed in microvolts.
Full-Scale Calibration Range
This is the range of voltages that the AD7703 can accept in the
system calibration mode and still correctly calibrate full scale.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal (AGND + 0.5 LSB) when operating in the
Unipolar mode.
Input Span
In system calibration schemes, two voltages applied in sequence
to the AD7703’s analog input define the analog input range. The
input span specification defines the minimum and maximum
input voltages from zero to full scale that the AD7703 can accept
and still accurately calibrate gain. The input span is expressed
as a percentage of VREF.
Bipolar Zero Error
This is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operating
in the Bipolar mode. It is expressed in microvolts.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal
(–VREF + 0.5 LSB) when operating in the Bipolar mode.
REV. F
HI-Z
t4
SCLK
SDATA
t8
HI-Z
–5–
AD7703
Table I. Bit Weight Table (2.5 V Reference Voltage)
PIN CONFIGURATION
DIP, SOIC
MODE
1
20 SDATA
CLKOUT
2
19 SCLK
CLKIN
3
18 DRDY
SC1
4
AD7703
17 SC2
DVSS
16 CS
5
TOP VIEW
6 (Not to Scale) 15 DVDD
DGND
AVSS
7
14 AVDD
AGND
8
13 CAL
AIN
9
12 BP/UP
VREF 10
V
LSB
Unipolar Mode
ppm
% FS
FS
0.596
1.192
2.384
4.768
9.537
0.25
0.5
1.00
2.00
4.00
0.0000238
0.0000477
0.0000954
0.0001907
0.0003814
0.24
0.48
0.95
1.91
3.81
LSB
Bipolar Mode
ppm
% FS
FS
0.13
0.26
0.5
1.00
2.00
0.0000119
0.0000238
0.0000477
0.0000954
0.0001907
0.12
0.24
0.48
0.95
1.91
11 SLEEP
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1
MODE
Selects the Serial Interface Mode. If MODE is tied to DGND, the Synchronous External Clocking (SEC)
mode is selected. SCLK is configured as an input, and the output appears without formatting, the MSB
coming first. If MODE is tied to +5 V, the AD7703 operates in the Synchronous Self-Clocking (SSC) mode.
SCLK is configured as an output, with a clock frequency for fCLKIN/4 and 25% duty cycle.
2
CLKOUT
Clock Output to Generate an Internal Master Clock by Connecting a Crystal between CLKOUT and CLKIN.
If an external clock is used, CLKOUT is not connected.
3
CLKIN
Clock Input for External Clock.
4, 17
SC1, SC2
System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration
performed.
5
DGND
Digital Ground. Ground reference for all digital signals.
6
DVSS
Digital Negative Supply, –5 V Nominal.
7
AVSS
Analog Negative Supply, –5 V Nominal.
8
AGND
Analog Ground. Ground reference for all analog signals.
9
AIN
Analog Input.
10
VREF
Voltage Reference Input, 2.5 V Nominal. This determines the value of positive full scale in the Unipolar
mode and the value of both positive and negative full scale in the Bipolar mode.
11
SLEEP
Sleep Mode Pin. When this pin is taken low, the AD7703 goes into a low power mode with typically 10 µW
power consumption.
12
BP/UP
Bipolar/Unipolar Mode Pin. When this pin is low, the AD7703 is configured for a unipolar input range going
from AGND to VREF. When Pin 12 is high, the AD7703 is configured for a bipolar input range, ±VREF.
13
CAL
Calibration Mode Pin. When CAL is taken high for more than four cycles, the AD7703 is reset and performs
a calibration cycle when CAL is brought low again. The CAL pin can also be used as a strobe to synchronize
the operation of several AD7703s.
14
AVDD
Analog Positive Supply, 5 V Nominal.
15
DVDD
Digital Positive Supply, 5 V Nominal.
16
CS
Chip Select Input. When CS is brought low, the AD7703 will begin to transmit serial data in a format determined
by the state of the MODE pin.
18
DRDY
Data Ready Output. DRDY is low when valid data is available in the output register. It goes high after transmission of a word is completed. It also goes high for four clock cycles when a new data-word is being loaded
into the output register, to indicate that valid data is not available, irrespective of whether data transmission
is complete or not.
19
SCLK
Serial Clock Input/Output. The SCLK pin is configured as an input or output, dependent on the type of
serial data transmission that has been selected by the MODE pin. When configured as an output in the
Synchronous Self-Clocking mode, it has a frequency of fCLKIN/4 and a duty cycle of 25%.
20
SDATA
Serial Data Output. The AD7703’s output data is available at this pin as a 20-bit serial word.
–6–
REV. F
AD7703
GENERAL DESCRIPTION
4. A 1-bit A/D converter (comparator)
The AD7703 is a 20-bit A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those representing chemical,
physical, or biological processes. It contains a charge-balancing
(⌺-⌬) ADC, calibration microcontroller with on-chip static
RAM, clock oscillator, and serial communications port.
5. A 1-bit DAC
6. A digital low-pass filter
S/H AMP
ANALOG
LOW-PASS
FILTER
The analog input signal to the AD7703 is continuously sampled
at a rate determined by the frequency of the master clock, CLKIN.
A charge-balancing A/D converter (⌺-⌬ modulator) converts
the sampled signal into a digital pulse train whose duty cycle
contains the digital information. A six-pole Gaussian digital
low-pass filter processes the output of the ⌺-⌬ modulator and
updates the 20-bit output register at a 4 kHz rate. The output
data can be read from the serial port randomly or periodically at
any rate up to 4 kHz.
+5V
ANALOG
SUPPLY
AVDD
DAC
SLEEP
2.5V
VREF
Oversampling is fundamental to the operation of ⌺-⌬ ADCs.
Using the quantization noise formula for an ADC
0.1F
DRDY
DATA READY
CS
READ
(TRANSMIT)
AD7703
RANGE
SELECT
BP/UP
CAL
CALIBRATE
ANALOG
INPUT
AIN
ANALOG
GROUND
AGND
SCLK
SERIAL CLOCK
SDATA
SERIAL DATA
SNR = (6.02 ¥ number of bits + 1.76) dB
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
The AD7703 samples the input signal at 16 kHz, which spreads
the quantization noise from 0 kHz to 8 kHz. Since the specified
analog input bandwidth of the AD7703 is only 0 Hz to 10 Hz, the
noise energy in this bandwidth would be only 1/800 of the total
quantization noise, even if the noise energy were spread evenly
throughout the spectrum. It is reduced still further by analog
filtering in the modulator loop, which shapes the quantization
noise spectrum to move most of the noise energy to frequencies
above 10 Hz. The SNR performance in the 0 Hz to 10 Hz range
is conditioned to the 20-bit level in this fashion.
CLKIN
CLKOUT
SC1
AVSS
–5V
ANALOG
SUPPLY
SC2
DGND
0.1F
0.1F
DVSS
10F
The output of the comparator provides the digital input for the
1-bit DAC, so the system functions as a negative feedback loop
that minimizes the difference signal. The digital data that represents the analog input voltage is in the duty cycle of the pulse train
appearing at the output of the comparator. It can be retrieved as
a parallel binary data-word using a digital filter.
Figure 7. Typical System Connection Diagram
The AD7703 can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. A calibration cycle may be initiated at any time
using the CAL control input.
⌺-⌬ ADCs are generally described by the order of the analog
low-pass filter. A simple example of a first-order, ⌺-⌬ ADC is
shown in Figure 8. This contains only a first-order, low-pass
filter or integrator. It also illustrates the derivation of the alternative name for these devices: charge-balancing ADCs.
Other system components may also be included in the calibration loop to remove offset and gain errors in the input channel.
For battery operation, the AD7703 also offers a standby mode
that reduces idle power consumption to typically 10 µW.
The AD7703 uses a second-order, ⌺-⌬ modulator and a sophisticated digital filter that provides a rolling average of the sampled
output. After power-up or if there is a step change in the input
voltage, there is a settling time that must elapse before valid
data is obtained.
THEORY OF OPERATION
The general block diagram of a ⌺-⌬ ADC is shown in Figure 8.
It contains the following elements:
1. A sample-hold amplifier
2. A differential amplifier or subtracter
3. An analog low-pass filter
REV. F
DIGITAL DATA
Figure 8. General ⌺-⌬ ADC
MODE
VOLTAGE
REFERENCE
DIGITAL
FILTER
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the difference signal at a frequency many times that of the analog signal
sampling frequency (oversampling).
DVDD
0.1F
10F
COMPARATOR
–7–
AD7703
The output settling of the AD7703 in response to a step input
change is shown in Figure 10. The Gaussian response has fast
settling with no overshoot, and the worst-case settling time to
±0.0007% is 125 ms with a 4.096 MHz master clock frequency.
DIGITAL FILTERING
The AD7703’s digital filter behaves like an analog filter, with a
few minor differences.
First, since digital filtering occurs after the analog-to-digital
conversion, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
On the other hand, analog filtering can remove noise superimposed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator and
digital filter, even though the average value of the signal is within
limits. To alleviate this problem, the AD7703 has overrange
headroom built into the ⌺-⌬ modulator and digital filter that
allows overrange excursions of 100 mV. If noise signals are larger
than this, consideration should be given to analog input filtering,
or to reducing the gain in the input channel so that a full-scale
input (2.5 V) gives only a half-scale input to the AD7703 (1.25 V).
This will provide an overrange capability greater than 100% at
the expense of reducing the dynamic range by one bit (50%).
PERCENT OF FINAL VALUE
100
80
60
40
20
0
0
The cutoff frequency of the digital filter is fCLK/409600. At the
maximum clock frequency of 4.096 MHz, the cutoff frequency
of the filter is 10 Hz and the data update rate is 4 kHz.
120
160
USING THE AD7703
SYSTEM DESIGN CONSIDERATIONS
The AD7703 operates differently from successive approximation
ADCs or integrating ADCs. Since it samples the signal continuously, like a tracking ADC, there is no need for a start convert
command. The 20-bit output register is updated at a 4 kHz rate,
and the output can be read at any time, either synchronously or
asynchronously.
Figure 9 shows the filter frequency response. This is a six-pole
Gaussian response that provides 55 dB of 60 Hz rejection for a
10 Hz cutoff frequency. If the clock frequency is halved to give a
5 Hz cutoff, 60 Hz rejection is better than 90 dB.
20
CLOCKING
0
fCLK = 4MHz
The AD7703 requires a master clock input, which may be an external TTL/CMOS compatible clock signal applied to the CLKIN
pin (CLKOUT not used). Alternatively, a crystal of the correct
frequency can be connected between CLKIN and CLKOUT,
when the clock circuit will function as a crystal controlled oscillator.
–40
GAIN – dB
80
TIME – ms
Figure 10. AD7703 Step Response
FILTER CHARACTERISTICS
–20
40
–60
fCLK = 2MHz
–80
Figure 11 shows a simple model of the on-chip gate oscillator
and Table II gives some typical capacitor values to be used with
various resonators.
–100
–120
fCLK = 1MHz
–140
–160
R1
5M⍀
1
10
FREQUENCY – Hz
100
2
Figure 9. Frequency Response of AD7703 Filter
gm = 1500MHO
Since the AD7703 contains this low-pass filtering, there is a
settling time associated with step function inputs, and data will
be invalid after a step change until the settling time has elapsed.
The AD7703 is, therefore, unsuitable for high speed multiplexing, where channels are switched and converted sequentially at
high rates, as switching between channels can cause a step change
in the input. However, slow multiplexing of the AD7703 is
possible, provided that the settling time is allowed to elapse
before data for the new channel is accessed.
10pF
C2*
X1
3
C1*
10pF
AD7703
*SEE TABLE II
Figure 11. On-Chip Gate Oscillator
–8–
REV. F
AD7703
low capacitance/voltage coefficient. The device also achieves low
input drift through the use of chopper-stabilized techniques in
its input stage. To ensure excellent performance over time and
temperature, the AD7703 uses digital calibration techniques
that minimize offset and gain error to typically ±4 LSB.
Table II. Resonator Loading Capacitors
Resonators
Ceramic
200 kHz
455 kHz
1.0 MHz
2.0 MHz
Crystal
2.000 MHz
3.579 MHz
4.096 MHz
C1 (pF)
C2 (pF)
330
100
50
20
470
100
50
20
30
20
None
30
20
None
AUTOCALIBRATION
The AD7703 offers both self-calibration and system-calibration
facilities. For calibration to occur, the on-chip microcontroller
must record the modulator output for two different input conditions. These are the zero-scale and full-scale points. In Unipolar
self-calibration mode, the zero-scale point is VAGND and the
full-scale point is VREF. With these readings, the microcontroller
can calculate the gain slope for the input to output transfer
function of the converter. In Unipolar mode, the slope factor is
determined by dividing the span between zero and full scale by
220. In Bipolar mode, it is determined by dividing the span by
219 since the inputs applied represent only half the total codes.
In both Unipolar and Bipolar modes, the slope factor is saved
and used to calculate the binary output code when an analog
input is applied to the device. Table IV gives the output code
size after calibration.
The input sampling frequency, output data rate, filter characteristics, and calibration time are all directly related to the master
clock frequency, fCLKIN, by the ratios given in the Specification
table under Dynamic Performance. Therefore, the first step in
system design with the AD7703 is to select a master clock frequency suitable for the bandwidth and output data rate required
by the application.
ANALOG INPUT RANGES
System calibration allows the AD7703 to compensate for system
gain and offset errors. A typical circuit where this might be used
is shown in Figure 12.
The AD7703 performs conversion relative to an externally
supplied reference voltage that allows easy interfacing to ratiometric systems. In addition, either unipolar or bipolar input
voltage ranges may be selected using the BP/UP input. With
BP/UP tied low, the input range is unipolar and the span is
(VREF to VAGND), where VAGND is the voltage at the device AGND
pin. With BP/UP tied high, the input range is bipolar and the
span is 2VREF. In the Bipolar mode, both positive and negative
full scale are directly determined by VREF. This offers superior
tracking of positive and negative full scale and better midscale
(bipolar zero) stability than bipolar schemes that simply scale
and offset the input range.
System calibration performs the same slope factor calculations
as self-calibration but uses voltage values presented by the system
to the AIN pin for the zero- and full-scale points. There are two
system calibration modes.
The first mode offers system level calibration for system offset
and system gain. This is a two step operation. The zero-scale
point must be presented to the converter first. It must be applied
to the converter before the calibration step is initiated and remain
stable until the step is complete. The DRDY output from the
device will signal when the step is complete by going low. After
the zero-scale point is calibrated, the full-scale point is applied
and the second calibration step is initiated. Again, the voltage
must remain stable throughout the calibration step.
The digital output coding for the unipolar range is unipolar binary;
for the bipolar range it is offset binary. Bit weights for the Unipolar
and Bipolar modes are shown in Table I.
ACCURACY
The two step calibration mode offers another feature. After the
sequence has been completed, additional offset calibrations can be
performed by themselves to adjust the zero reference point to a
new system zero reference value. This second system calibration
mode uses an input voltage for the zero-scale calibration point
but uses the VREF value for the full-scale point.
S-D ADCs, like VFCs and other integrating ADCs, do not
contain any source of nonmonotonicity and inherently offer
no-missing-codes performance.
The AD7703 achieves excellent linearity by the use of high
quality, on-chip silicon dioxide capacitors, which have a very
SCLK
SYSTEM
REF HI
AIN
SYSTEM
REF LO
ANALOG
MUX
A0
SIGNAL
CONDITIONING
SDATA
AIN
SC1
AD7703
A1
CAL
MICROCOMPUTER
SC2
Figure 12. Typical Connections for System Calibration
REV. F
–9–
AD7703
Initiating Calibration
Table III illustrates the calibration modes available in the AD7703.
Not shown in the table is the function of the BP/UP pin, which
determines whether the converter has been calibrated to measure bipolar or unipolar signals. A calibration step is initiated by
bringing the CAL pin high for at least four CLKIN cycles and
then bringing it low again. The states of SC1 and SC2 along
with the BP/UP pin will determine the type of calibration to be
performed. All three signals should be stable before the CAL
pin is taken positive. The SC1 and SC2 inputs are latched when
CAL goes high. The BP/UP input is not latched and, therefore,
must remain in a fixed state throughout the calibration and
measurement cycles. Any time the state of the BP/UP is changed,
a new calibration cycle must be performed to enable the AD7703
to function properly in the new mode.
When a calibration step is initiated, the DRDY signal will go high
and remain high until the step is finished. Table III shows the
number of clock cycles each calibration requires. Once a calibration step is initiated, it must finish before a new calibration step
can be executed. In the two step system calibration mode, the
offset calibration step must be initiated before initiating the gain
calibration step.
When self-calibration is completed, DRDY falls and the output
port is updated with a data-word that represents the analog input
signal. When a system calibration step is completed, DRDY will
fall and the output port will be updated with the appropriate data
value (all 0s for the zero-scale point and all 1s for the full-scale
point). In the system calibration mode, the digital filter must
settle before the output code will represent the value of the
analog input signal. Tables IV and V indicate the output code
size and output coding of the AD7703 in its various modes. In
these tables, SOFF is the measured system offset in volts and
SGAIN is the measured system gain at the full-scale point in volts.
Span and Offset Limits
Whenever a system calibration mode is used, there are limits
on the amount of offset and span that can be accommodated.
The range of input span in both the Unipolar and Bipolar
modes has a minimum value of 0.8 VREF and a maximum
value of 2(VREF + 0.1 V).
The amount of offset that can be accommodated depends on
whether the Unipolar or Bipolar mode is being used. In Unipolar
mode, the system calibration modes can handle a maximum
offset of 0.2 VREF and a minimum offset of –(VREF + 0.1 V).
Therefore the AD7703 in the Unipolar mode can be calibrated
to mimic bipolar operation.
Table III. Calibration Truth Table*
CAL
SC1
SC2
Calibration
Type
Zero-Scale
Calibration
Full-Scale
Calibration
0
1
0
1
0
1
1
0
Self-Calibration
System Offset
System Gain
System Offset
VAGND
AIN
VREF
AIN
VREF
AIN
Sequence
Calibration
Time
One Step
First Step
Second Step
One Step
3,145,655 Clock Cycles
1,052,599 Clock Cycles
1,068,813 Clock Cycles
2,117,389 Clock Cycles
*DRDY remains high throughout the calibration sequence. In the Self-Calibration mode, DRDY falls once the AD7703 has settled to the analog input. In all other
modes, DRDY falls as the device begins to settle.
Table IV. Output Code Size After Calibration
Calibration Mode
Zero Scale
Gain Factor
Unipolar
1 LSB
Bipolar
Self-Calibration
VAGND
VREF
(V REF –V AGND )
1048576
2(V REF –V AGND )
1048576
System Calibration
SOFF
SGAIN
(SGAIN – SOFF )
1048576
2(SGAIN – SOFF )
1048576
–10–
REV. F
AD7703
Table V. Output Coding
Input Voltage, Unipolar Mode
Input Voltage, Bipolar Mode
System Calibration
Self-Calibration
Output Codes
Self-Calibration
System Calibration
>(SGAIN –1.5 LSB)
>(VREF – 1.5 LSB)
FFFFF
>(VREF –1.5 LSB)
>(SGAIN – 1.5 LSB)
SGAIN – 1.5 LSB
VREF – 1.5 LSB
FFFFF
FFFFE
VREF – 1.5 LSB
SGAIN – 1.5 LSB
(SGAIN – SOFF)/2 – 0.5 LSB
(VREF – VAGND)/2 – 0.5 LSB
80000
7FFFF
VAGND – 0.5 LSB
SOFF – 0.5 LSB
SOFF + 0.5 LSB
VAGND + 0.5 LSB
–VREF + 0.5 LSB
–SGAIN + 2 SOFF + 0.5 LSB
