AD7703CQ

a FEATURES Monolithic 20-Bit ADC 0.0003% Linearity Error 20-Bit No Missed Codes On-Chip Self-Calibration Circuitry Programmable Low-Pass Filter 0.1 Hz to 10 Hz Corner Frequency 0 to +2.5 V or +2.5 V Analog Input Range 4 kSPS Output Data Rate Flexible Serial Interface Ultralow Power APPLICATIONS Industrial Process Control Weigh Scales Portable Instrumentation Remote Data Acquisition DVDD 15 AVDD 14 LC2MOS 20-Bit A/D Converter AD7703 FUNCTIONAL BLOCK DIAGRAM AVSS 7 DVSS 6 SC1 4 SC2 17 AD7703 CALIBRATION SRAM CALIBRATION MICROCONTROLLER 13 CAL AIN 9 20-BIT CHARGE BALANCE A/D CONVERTER ANALOG MODULATOR 6-POLE GAUSSIAN LOW-PASS DIGITAL FILTER 12 BP/UP VREF 10 11 SLEEP AGND 8 CLOCK GENERATOR SERIAL INTERFACE LOGIC 20 SDATA 19 SCLK DGND 5 3 CLKIN 2 CLKOUT 1 MODE 16 CS 18 DRDY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7703 is a 20-bit ADC which uses a sigma delta conversion technique. The analog input is continuously sampled by an analog modulator whose mean output duty cycle is proportional to the input signal. The modulator output is processed by an on-chip digital filter with a six-pole Gaussian response, which updates the output data register with 20-bit binary words at word rates up to 4 kHz. The sampling rate, filter corner frequency and output word rate are set by a master clock input that may be supplied externally, or by an on-chip gate oscillator. The inherent linearity of the ADC is excellent, and endpoint accuracy is ensured by self-calibration of zero and full scale which may be initiated at any time. The self-calibration scheme can also be extended to null system offset and gain errors in the input channel. The output data is accessed through a serial port, which has two synchronous modes suitable for interfacing to shift registers or the serial ports of industry standard microcontrollers. CMOS construction ensures low power dissipation, and a power down mode reduces the idle power consumption to only 10 W. 1. The AD7703 offers 20-bit resolution coupled with outstanding 0.0003% accuracy. 2. No missing codes ensures true, usable, 20-bit dynamic range, removing the need for programmable gain and level-setting circuitry. 3. The effects of temperature drift are eliminated by on-chip self-calibration, which removes zero and gain error. External circuits can also be included in the calibration loop to remove system offsets and gain errors. 4. A flexible synchronization allows the AD7703 to interface directly to the serial ports of industry standard microcontrollers and DSP processors. 5. Low operating power consumption and an ultralow power standby mode make the AD7703 ideal for loop powered remote sensing applications, or battery-powered portable instruments. R EV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AV = DV V; AV = DV = –5 V; AD7703–SPECIFICATIONS1(Tk = +25 1C;nF to AGND at=A+5unless otherwise noted.)V BP/UP = +5 V; MODE = +5 V; A Source Resistance = with A DD DD SS SS IN 1 IN REF = +2.5 V; fCLKIN = 4.096 MHz; Test Conditions/Comments Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity, T MIN to TMAX +25 °C TMIN to TMAX Differential Nonlinearity, TMIN to TMAX Positive Full-Scale Error 3 Full-Scale Drift 4 Unipolar Offset Error 3 Unipolar Offset Drift 4 Bipolar Zero Error 3 Bipolar Zero Drift 4 Bipolar Negative Full-Scale Errors 3 Bipolar Negative Full-Scale Drift 4 Noise (Referred to Output) DYNAMIC PERFORMANCE Sampling Frequency, f S Output Update Rate, f OUT Filter Corner Frequency, f –3 dB Settling Time to ± 0.0007% FS SYSTEM CALIBRATION Positive Full-Scale Calibration Range Positive Full-Scale Overrange Negative Full-Scale Overrange Maximum Offset Calibration Ranges 5, 6 Unipolar Input Range Bipolar Input Range Input Span 7 ANALOG INPUT Unipolar Input Range Bipolar Input Range Input Capacitance Input Bias Current 1 LOGIC INPUTS All Inputs except CLKIN VINL, Input Low Voltage VINH, Input High Voltage CLKIN VINL, Input Low Voltage VINH, Input High Voltage IIN, Input Current LOGIC OUTPUTS VOL, Output Low Voltage VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance POWER REQUIREMENTS Power Supply Voltages Analog Positive Supply (AV DD) Digital Positive Supply (DV DD) Analog Negative Supply (AV SS) Digital Negative Supply (DV SS) Calibration Memory Retention Power Supply Voltage A/S Versions 2 B Version 2 C Version2 Units 20 ± 0.0015 ± 0.003 ± 0.003 ± 0.5 ±4 ± 16 ± 19/± 37 ±4 ± 16 ± 26 ± 67 +48/–400 ±4 ± 16 ± 13 ± 34 +24/–200 ±8 ± 32 ± 10/± 20 1.6 fCLKIN/256 fCLKIN/1024 fCLKIN/409,600 507904/fCLKIN VREF + 0.1 VREF + 0.1 –(VREF + 0.1) –(VREF + 0.1) –0.4 VREF to +0.4 VREF 0.8 VREF 2 VREF + 0.2 0 to +2.5 ± 2.5 20 1 20 ± 0.0007 ± 0.0015 ± 0.0015 ± 0.5 ±4 ± 16 ± 19 ±4 ± 16 ± 26 ± 67 ±4 ± 16 ± 13 ± 34 ±8 ± 32 ± 10 1.6 fCLKIN/256 fCLKIN/1024 fCLKIN/409,600 507904/fCLKIN VREF + 0.1 VREF + 0.1 –(VREF + 0.1) –(VREF + 0.1) –0.4 VREF to +0.4 VREF 0.8 VREF 2 VREF + 0.2 0 to +2.5 ± 2.5 20 1 20 ± 0.0003 ± 0.0008 ± 0.0012 ± 0.5 ±4 ± 16 ± 19 ±4 ± 16 ± 26 ± 67 ±4 ± 16 ± 13 ± 34 ±8 ± 32 ± 10 1.6 fCLKIN/256 fCLKIN/1024 fCLKIN/409,600 507904/fCLKIN VREF + 0.1 VREF + 0.1 –(VREF + 0.1) –(VREF + 0.1) –0.4 VREF to +0.4 VREF 0.8 VREF 2 VREF + 0.2 0 to +2.5 ± 2.5 20 1 Bits % FSR typ % FSR max % FSR max LSB typ LSB typ LSB max LSB typ LSB typ LSB max LSB typ LSB typ LSB typ LSB max LSB typ LSB typ LSB typ LSB max LSB typ LSB rms typ Hz Hz Hz sec V max V max V max V max V max V min V max Volts Volts pF typ nA typ Guaranteed No Missing Codes Temp Range: 0 °C to +70°C Specified Temp Range Temp Range: 0 °C to +70°C Specified Temp Range For Full-Scale Input Step System Calibration Applies to Unipolar and Bipolar Ranges. After Calibration, if A IN > VREF, the Device Will Output All 1s. If AIN < 0 (Unipolar) or –V REF (Bipolar), the Device Will Output all 0s 0.8 2.0 0.8 3.5 10 0.4 DVDD –1 ± 10 9 0.8 2.0 0.8 3.5 10 0.4 DVDD –1 ± 10 9 0.8 2.0 0.8 3.5 10 0.4 DVDD –1 ± 10 9 V max V min V max V min µA max V max V min µA max pF typ ISINK = 1.6 mA ISOURCE = 100 µA 4.5/5.5 4.5/AVDD –4.5/–5.5 –4.5/–5.5 2.0 4.5/5.5 4.5/AVDD –4.5/–5.5 –4.5/–5.5 2.0 4.5/5.5 4.5/AVDD –4.5/–5.5 –4.5/–5.5 2.0 V min/V max For Specified Performance V min/V max V min/V max V min/V max V min –2– REV. D AD7703 Parameter STATIC PERFORMANCE DC Power Supply Currents 8 Analog Positive Supply (AI DD) Digital Positive Supply (DI DD) Analog Negative Supply (AI SS) Digital Negative Supply (DI SS) Power Supply Rejection 9 Positive Supplies Negative Supplies Power Dissipation Normal Operation Standby Operations 10 A, B, C S A/S Versions2 B Version2 C Version2 Units Test Conditions/Comments 3.2 1.5 3.2 0.1 70 75 40 3.2 1.5 3.2 0.1 70 75 40 3.2 1.5 3.2 0.1 70 75 40 mA max mA max mA max mA max dB typ dB typ mW rnax µW max µW max Typically 2 mA Typically 1 mA Typically 2 mA Typically 0.03 mA 20 40 20 40 20 40 SLEEP = Logic 1, Typically 25 mW SLEEP = Logic 0, Typically 10 µW NOTES 1 The AIN pin presents a very high impedance dynamic load which varies with clock frequency. A ceramic 1 nF capacitor from the A IN to AGND is necessary. Source resistance should be 750 Ω or less. 2 Temperature Ranges are as follows: A, B, C Versions: –40 °C to +85°C; S Version: –55 °C to +125°C. 3 Applies after calibration at the temperature of interest. Full-Scale Error applies for both unipolar and bipolar input ranges. 4 Total drift over the specified temperature range after calibration at power-up at +25 °C. This is guaranteed by design and/or characterization. Recalibration at any temperature will remove these errors. 5 In unipolar mode the offset can have a negative value (–VREF) such that the unipolar mode can mimic bipolar mode operation. 6 The specifications for input overrange and for input span apply additional constraints on the offset calibration range. 7 For unipolar mode, input span is the difference between full scale and zero scale. For bipolar mode, input span is the difference between positive and negative full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ± (VREF + 0.1). 8 All digital outputs unloaded. All digital inputs at 5 V CMOS levels. 9 Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter. 10 CLKIN is stopped. All digital inputs are grounded. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) ORDERING GUIDE DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V DVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V Analog Input Voltage to AGND . . . . . . . . . . .AVSS – 0.3 V to . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V Input Current to Any Pin Except Supplies1 . . . . . . . . ± 10 mA Operating Temperature Range Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C Power Dissipation (DIP Package) to +75°C . . . . . . . 450 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C Power Dissipation (SOIC Package) to +75°C . . . . . . 250 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 15 mW/°C NOTES *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Transient currents of up to 100 mA will not cause SCR latch-up. Model AD7703AN AD7703BN AD7703CN AD7703AR AD7703BR AD7703CR AD7703AQ AD7703BQ AD7703CQ AD7703SQ Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C Linearity Error (% FSR) 0.003 0.0015 0.0012 0.003 0.0015 0.0012 0.003 0.0015 0.0012 0.003 Package Options* N-20 N-20 N-20 R-20 R-20 R-20 Q-20 Q-20 Q-20 Q-20 *N = Plastic DIP; R = SOIC; Q = Cerdip. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. D –3– AD7703 TIMING CHARACTERISTICS1, 2 Parameter fCLKIN3, 4 200 5 200 5 50 50 0 50 1000 3/fCLKIN 100 250 300 790 l/fCLKIN + 200 4/fCLKIN + 200 5 35 160 160 150 250 200 200 5 200 5 50 50 0 50 1000 3/fCLKIN 100 250 300 790 l/fCLKIN + 200 4/fCLKIN + 200 5 35 160 160 150 250 200 (AVDD = DVDD = +5 V 10%; AVSS = DVSS = –5 V 10%; AGND = DGND = 0 V; fCLKIN = 4.096 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted.) Conditions/Comment6 Master Clock Frequency: Internal Gate Oscillator Typically 4096 kHz Master Clock Frequency: Externally Supplied Digital Output Rise Time. Typically 20 ns Digital Output Fall Time. Typically 20 ns SC1, SC2 to CAL High Setup Time SC1, SC2 Hold Time After CAL Goes High SLEEP High to CLKIN High Setup Time Data Access Time (CS Low to Data Valid) SCLK Falling Edge to Data Valid Delay (25 ns typ) MSB Data Setup Time. Typically 380 ns SCLK High Pulse Width. Typically 240 ns SCLK Low Pulse Width. Typically 730 ns SCLK Rising Edge to Hi-Z Delay (1/fCLKIN + 100 ns typ) CS High to Hi-Z Delay Serial Clock Input Frequency SCLK High Pulse Width SCLK Low Pulse Width Data Access Time (CS Low to Data Valid). Typically 80 ns SCLK Falling Edge to Data Valid Delay. Typically 75 ns CS High to Hi-Z Delay SCLK Falling Edge to Hi-Z Delay. Typically 100 ns Limit at TMIN, TMAX Limit at TMIN, TMAX (A, B, C Versions) (S Version) Units kHz min MHz max kHz min MHz max ns max ns max ns min ns min ns min ns max ns max ns min ns max ns max ns max ns max MHz max ns min ns min ns max ns max ns max ns max tr5 tf5 t1 t2 t3 6 SSC MODE t4 7 t5 t6 t7 t8 t9 t108, 9 SEC MODE fSCLK t11 t12 t137, 10 t1411 t158 t168 NOTES 1 Sample tested at +25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figures 1 to 6. 3 CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 The AD7703 is production tested with f CLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz. 5 Specified using 10% and 90% points on waveform of interest. 6 In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met. 7 t4 and t 13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 8 t9, t10, t15 and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the tune quoted in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. 9 If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance. 10 If CS is activated asynchronously to DRDY , CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be as great as 4 CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than 4 CLKIN cycles plus 160 ns after CS goes low. 11 SDATA is clocked out on the falling edge of the SCLK input. CAL IOL 1.6mA TO OUTPUT PIN t1 +2.1V t2 SC1, SC2 SC1,SC2 VALID CL 100pF IOH 200µA Figure 2. Calibration Control Timing CLKIN Figure 1. Load Circuit for Access Time and Bus Relinquish Time t3 SLEEP Figure 3. Sleep Mode Timing –4– REV. D AD7703 CS CS t10 SDATA DATA VALID HI-Z SDATA DATA VALID t15 HI-Z Figure 4. SSC Mode Data Hold Time Figure 5a. SEC Mode Data Hold Time CLKIN DRDY CS CS t12 t11 SCLK SCLK HI-Z t7 t8 t9 t8 HI-Z SDATA HI-Z DB19 HI-Z t13 SDATA HI-Z DB19 t4 t14 DB18 DB1 t16 DB0 t5 DB18 DB1 DB0 HI-Z Figure 5b. SEC Mode Timing Diagram Figure 6. SSC Mode Timing Diagram TERMINOLOGY LINEARITY ERROR POSITIVE FULL-SCALE OVERRANGE This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero-scale (not to be confused with bipolar zero), a point 0.5 LSB below the first code transition (000 . . . 000 to 000 . . . 001) and full scale, a point 1.5 LSB above the last code transition (111 . . . 110 to 111 . . . 111). The error is expressed as a percentage of full scale. DIFFERENTIAL LINEARITY ERROR Positive full-scale overrange is the amount of overhead available to handle input voltages greater than +VREF (for example, noise peaks or excess voltages due to system gain errors in system calibration routines) without introducing errors due to overloading the analog modulator or overflowing the digital filter. NEGATIVE FULL-SCALE OVERRANGE This is the difference between any code’s actual width and the ideal (1 LSB) width. Differential linearity error is expressed in LSBs. A differential linearity specification of ± 1 LSB or less guarantees monotonicity. POSITIVE FULL-SCALE ERROR This is the amount of overhead available to handle voltages below –VREF without overloading the analog modulator or overflowing the digital filter. Note that the analog input will accept negative voltage peaks even in the unipolar mode. OFFSET CALIBRATION RANGE Positive full-scale error is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal (VREF –3/2 LSBs). It applies to both positive and negative analog input ranges. UNIPOLAR OFFSET ERROR In the system calibration modes (SC2 Low) the AD7703 calibrates its offset with respect to the AIN pin. The offset calibration range specification defines the range of voltages that the AD7701 can accept and still calibrate offset accurately. FULL-SCALE CALIBRATION RANGE This is the range of voltages that the AD7703 can accept in the system calibration mode and still calibrate full scale correctly. INPUT SPAN Unipolar offset error is the deviation of the first code transition from the ideal (AGND + 0.5 LSB) when operating in the unipolar mode. BIPOLAR ZERO ERROR This is the deviation of the midscale transition (0111 . . . 111 to 1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operating in the bipolar mode. BIPOLAR NEGATIVE FULL-SCALE ERROR In system calibration schemes, two voltages applied in sequence to the AD7703’s analog input define the analog input range. The input span specification defines the minimum and maximum input voltages from zero to full scale that the AD7703 can accept and still calibrate gain accurately. This is the deviation of the first code transition from the ideal (–VREF + 0.5 LSB), when operating in the bipolar mode. REV. D –5– AD7703 PIN FUNCTION DESCRIPTION Pin 1 Mnemonic MODE Description Selects the Serial Interface Mode. If MODE is tied to DGND, the Synchronous External Clocking (SEC) mode is selected. SCLK is configured as an input, and the output appears without formatting, the MSB coming first. If MODE is tied to +5 V, the AD7703 operates in the Synchronous Self-Clocking (SSC) mode. SCLK is configured as an output, with a clock frequency for fCLKIN/4 and 25% duty cycle. Clock Output to generate an Internal Master Clock by connecting a crystal between CLKOUT and CLKIN. If an external clock is used, CLKOUT is not connected. Clock Input for External Clock. System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration performed. Digital Ground. Ground reference for all digital signals. Digital Negative Supply, –5 V nominal. Analog Negative Supply, –5 V nominal. Analog Ground. Ground reference for all analog signals. Analog Input. Voltage Reference Input, +2.5 V nominal. This determines the value of positive full-scale in the unipolar mode and of both positive and negative full-scale in the Bipolar Mode. Sleep mode pin. When this pin is taken low, the AD7703 goes into a low-power mode with typically 10 µW power consumption. Bipolar/Unipolar mode pin. When this pin is Low, the AD7703 is configured for a unipolar input range going from AGND to VREF. When Pin 12 is High, the AD7703 is configured for a bipolar input range, ± VREF. Calibration mode pin. When CAL is taken High for more than 4 cycles, the AD7703 is reset and performs a calibration cycle when CAL is brought Low again. The CAL pin can also be used as a strobe to synchronize the operation of several AD7703s. Analog Positive Supply, +5 V nominal. Digital Positive Supply, +5 V nominal. Chip Select Input. When CS is brought low, the AD7703 will begin to transmit serial data in a format determined by the state of the MODE pin. Data Ready Output. DRDY is low when valid data is available in the output register. It goes high after transmission of a word is completed. It also goes high for four clock cycles when a new data word is being loaded into the output register, to indicate that valid data is not available, irrespective of whether data transmission is complete or not. Serial Clock Input/Output. The SCLK pin in configured as an input or output, dependent on the type of serial data transmission that has been selected by the MODE pin. When configured as an output in the Synchronous Self-Clocking mode, it has a frequency of fCLKIN/4 and a duty cycle of 25%. Serial Data Output. The AD7703’s output data is available at this pin as a 20-bit serial word. 2 3 4, 17 5 6 7 8 9 10 11 12 13 CLKOUT CLKIN SC1, SC2 DGND DVSS AVSS AGND AIN VREF SLEEP BP/UP CAL 14 15 16 18 AVDD DVDD CS DRDY 19 SCLK 20 SDATA Table I. Bit Weight Table (2.5 V Reference Voltage) V 0.596 1.192 2.384 4.768 9.537 UNIPOLAR MODE BIPOLAR MODE LSBs % FS ppm FS LSBs % FS ppm FS 0.25 0.5 1.00 2.00 4.00 0.0000238 0.0000477 0.0000954 0.0001907 0.0003814 0.24 0.48 0.95 1.91 3.81 0.13 0.26 0.5 1.00 2.00 0.0000119 0.0000238 0.0000477 0.0000954 0.0001907 0.12 0.24 0.48 0.95 1.91 PIN CONFIGURATION DIP, Cerdip, SOIC MODE CLKOUT CLKIN SC1 DGND DVSS AVSS AGND AIN 1 2 3 4 5 20 SDATA 19 SCLK 18 DRDY 16 CS TOP VIEW 6 (Not to Scale) 15 DVDD 7 8 9 14 AVDD 13 CAL 12 BP/UP 11 SLEEP AD7703 17 SC2 VREF 10 –6– REV. D AD7703 GENERAL DESCRIPTION The AD7703 is a 20-bit A/D converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those representing chemical, physical or biological processes. It contains a charge-balancing (sigma-delta) ADC, calibration microcontroller with on-chip static RAM, a clock oscillator and a serial communications port. The analog input signal to the AD7703 is continuously sampled at a rate determined by the frequency of the master clock, CLKIN. A charge-balancing A/D converter (sigma-delta modulator) converts the sampled signal into a digital pulse train whose duty cycle contains the digital information. A six-pole Gaussian digital low-pass filter processes the output of the sigma-delta modulator and updates the 20-bit output register at a 4 kHz rate. The output data can be read from the serial port randomly or periodically at any rate up to 4 kHz. +5V ANALOG SUPPLY THEORY OF OPERATION The general block diagram of a sigma-delta ADC is shown in Figure 8. It contains the following elements: 1. A sample-hold amplifier 2. A differential amplifier or subtracter 3. An analog low-pass filter 4. A 1-bit A/D converter (comparator) 5. A 1-bit DAC 6. A digital low-pass filter S/H AMP ANALOG LOW-PASS FILTER COMPARATOR DIGITAL FILTER DAC 10µF 0.1µF AVDD DVDD SLEEP MODE VOLTAGE REFERENCE 2.5V VREF DRDY CS SCLK RANGE SELECT BP/UP CAL AIN SDATA CLKIN CLKOUT SC1 DATA READY READ (TRANSMIT) SERIAL CLOCK SERIAL DATA 0.1µF DIGITAL DATA Figure 8. General Sigma-Delta ADC AD7703 CALIBRATE ANALOG INPUT ANALOG GROUND 0.1µF –5V ANALOG SUPPLY In operation, the sampled analog signal is fed to the subtracter, along with the output of the 1-bit DAC. The filtered difference signal is fed to the comparator, whose output samples the difference signal at a frequency many times that of the analog signal frequency (oversampling). Oversampling is fundamental to the operation of sigma-delta ADCs. Using the quantization noise formula for an ADC: AGND AVSS 10µF SC2 DGND 0.1µF DVSS SNR = (6.02 × number of bits + 1.76) dB, a 1-bit ADC or comparator yields an SNR of 7.78 dB. The AD7703 samples the input signal at 16 kHz, which spreads the quantization noise from 0 kHz to 8 kHz. Since the specified analog input bandwidth of the AD7703 is only 0 Hz to 10 Hz, the noise energy in this bandwidth would be only 1/800 of the total quantization noise, assuming that the noise energy was spread evenly throughout the spectrum. It is reduced still further by analog filtering in the modulator loop, which shapes the quantization noise spectrum to move most of the noise energy to frequencies above 10 Hz. The SNR performance in the 0 Hz to 10 Hz range is conditioned to the 20-bit level in this fashion. The output of the comparator provides the digital input for the 1-bit DAC, so the system functions as a negative feedback loop which minimizes the difference signal. The digital data that represents the analog input voltage is in the duty cycle of the pulse train appearing at the output of the comparator. It can be retrieved as a parallel binary data word using a digital filter. Sigma-delta ADCs are generally described by the order of the analog low-pass filter. A simple example of a first order sigmadelta ADC is shown in Figure 8. This contains only a first-order low-pass filter or integrator. The AD7703 uses a second-order sigma-delta modulator and a digital filter that provides a rolling average of the sampled output. After power-up or if there is a step change in the input voltage, there is a settling time before valid data is obtained. Figure 7. Typical System Connection Diagram The AD7703 can perform self-calibration using the on-chip calibration microcontroller and SRAM to store calibration parameters. A calibration cycle may be initiated at any time using the CAL control input. Other system components may also be included in the calibration loop to remove offset and gain errors in the input channel. For battery operation, the AD7703 also offers a standby mode that reduces idle power consumption to typically 10 µW. REV. D –7– AD7703 DIGITAL FILTERING The AD7703’s digital filter behaves like an analog filter, with a few minor differences. First, since digital filtering occurs after the A to D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. On the other hand, analog filtering can remove noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. To alleviate this problem, the AD7703 has overrange headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 100 mV. If noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the gain in the input channel so that a full-scale input (2.5 V) gives only a half-scale input to the AD7703 (1.25 V). This will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%). FILTER CHARACTERISTICS The output settling of the AD7703 in response to a step input change is shown in Figure 10. The Gaussian response has fast settling with no overshoot, and the worst-case settling time to ± 0.0007% is 125 ms with a 4.096 MHz master clock frequency. 100 PERCENT OF FINAL VALUE 80 60 40 20 0 0 40 80 TIME – ms 120 160 Figure 10. AD7703 Step Response USING THE AD7703 SYSTEM DESIGN CONSIDERATIONS The cutoff frequency of the digital filter is fCLK/409600. At the maximum clock frequency of 4.096 MHz, the cutoff frequency of the filter is 10 Hz and the data update rate is 4 kHz. Figure 9 shows the filter frequency response. This is a 6-pole Gaussian response that provides 55 dB of 60 Hz rejection for a 10 Hz cutoff frequency. If the clock frequency is halved to give a 5 Hz cutoff, 60 Hz rejection is better than 90 dB. 20 0 fCLK = 4MHz –20 –40 GAIN – dB The AD7703 operates differently from successive approximation ADCs or integrating ADCs. Since it samples the signal continuously, like a tracking ADC, there is no need for a start convert command. The 20-bit output register is updated at a 4 kHz rate, and the output can be read at any time, either synchronously or asynchronously. CLOCKING –60 fCLK = 2MHz –80 The AD7703 requires a master clock input, which may be an external TTL/CMOS compatible clock signal applied to the CLKIN pin (CLKOUT not used). Alternatively, a crystal of the correct frequency can be connected between CLKIN and CLKOUT, when the clock circuit will function as a crystal controlled oscillator. Figure 11 shows a simple model of the on-chip gate oscillator and Table II gives some typical capacitor values to be used with various resonators. R1 5MΩ –100 –120 fCLK = 1MHz –140 –160 1 10 FREQUENCY – Hz 100 Figure 9. Frequency Response of AD7703 Filter 2 gm = 1500µMHO 10pF 3 10pF C1* X1 C2* Since the AD7703 contains this low-pass filtering, there is a settling time associated with step function inputs, and data will be invalid after a step change until the settling time has elapsed. The AD7703 is, therefore, unsuitable for high speed multiplexing, where channels are switched and converted sequentially at high rates, as switching between channels can cause a step change in the input. However, slow multiplexing of the AD7703 is possible, provided that the settling time is allowed to elapse before data for the new channel is accessed. AD7703 *SEE TABLE II Figure 11. On-Chip Gate Oscillator –8– REV. D AD7703 Table II. Resonator Loading Capacitors Resonators Ceramic 200 kHz 455 kHz 1.0 MHz 2.0 MHz Crystals 2.000 MHz 3.579 MHz 4.096 MHz C1 330 pF 100 pF 50 pF 20 pF 30 pF 20 pF None C2 470 pF 100 pF 50 pF 20 pF 30 pF 20 pF None low capacitance/voltage coefficient. The device also achieves low input drift through the use of chopper-stabilized techniques in its input stage. To ensure excellent performance over time and temperature, the AD7703 uses digital calibration techniques which minimize offset and gain error to typically ± 4 LSBs. AUTOCALIBRATION The input sampling frequency, output data rate, filter characteristics and calibration time are all directly related to the master clock frequency fCLKIN by the ratios given in the specification table under Dynamic Performance. Therefore, the first step in system design with the AD7703 is to select a master clock frequency suitable for the bandwidth and output data rate required by the application. ANALOG INPUT RANGES The AD7703 offers both self-calibration and system-calibration facilities. For calibration to occur, the on-chip microcontroller must record the modulator output for two different input conditions. These are the “zero scale” and “full scale” points. In unipolar self-calibration mode, the zero scale point is VAGND and the full-scale point is VREF. With these readings the microcontroller can calculate the gain slope for the input to output transfer function of the converter. In unipolar mode the slope factor is determined by dividing the span between zero and full scale by 220. In bipolar mode it is determined by dividing the span by 219 since the inputs applied represent only half the total codes. In both unipolar and bipolar modes the slope factor is saved and used to calculate the binary output code when an analog input is applied to the device. Table IV gives the output code size after calibration. System calibration allows the AD7703 to compensate for system gain and offset errors. A typical circuit where this might be used is shown in Figure 12. System calibration performs the same slope factor calculations as self-calibration but uses voltage values presented by the system to the AIN pin for the zero and full-scale points. There are two system calibration modes. The first mode offers system level calibration for system offset and system gain. This is a two step operation. The zero-scale point must be presented to the converter first. It must be applied to the converter before the calibration step is initiated and remain stable until the step is complete. The DRDY output from the device will signal when the step is complete by going low. After the zero-scale point is calibrated the full-scale point is applied and the second calibration step is initiated. Again the voltage must remain stable throughout the calibration step. The two step calibration mode offers another feature. After the sequence has been completed, additional offset calibrations can be performed by themselves to adjust the zero reference point to a new system zero reference value. This second system calibration mode uses an input voltage for the zero-scale calibration point but uses the VREF value for the full-scale point. The AD7703 performs conversion relative to an externally supplied reference voltage, which allows easy interfacing to ratiometric systems. In addition, either unipolar or bipolar input voltage ranges may be selected using the BP/UP input. With BP/UP tied low, the input range is unipolar and the span is (VREF–VAGND), where VAGND is the voltage at the device AGND pin. With BP/UP tied high, the input range is bipolar and the span is 2 VREF. In the bipolar mode both positive and negative full scale are directly determined by VREF. This offers superior tracking of positive and negative full scale and better midscale (bipolar zero) stability than bipolar schemes that simply scale and offset the input range. The digital output coding for the unipolar range is unipolar binary and for the bipolar range it is offset binary. Bit weights for the unipolar and bipolar modes are shown in Table I. ACCURACY Sigma-delta ADCs, like VFCs and other integrating ADCs, do not contain any source of nonmonotonicity and inherently offer no missing codes performance. The AD7703 achieves excellent linearity by the use of high quality, on-chip silicon dioxide capacitors, which have a very SYSTEM REF HI AIN SYSTEM REF LO ANALOG MUX A0 A1 SIGNAL CONDITIONING AIN SCLK SDATA CAL SC1 SC2 MICRO COMPUTER AD7703 Figure 12. Typical Connections for System Calibration REV. D –9– AD7703 Initiating Calibration Table III illustrates the calibration modes available in the AD7703. Not shown in the table is the function of the BP/UP pin which determines whether the converter has been calibrated to measure bipolar or unipolar signals. A calibration step is initiated by bringing the CAL pin high for at least 4 CLKIN cycles and then bringing it low again. The states of SC1 and SC2 along with the BP/UP pin will determine the type of calibration to be performed. All three signals should be stable before the CAL pin is taken positive. The SC1 and SC2 inputs are latched when CAL goes high. The BP/UP input is not latched and therefore must remain in a fixed state throughout the calibration and measurement cycles. Any time the state of the BP/UP is changed, a new calibration cycle must be performed to enable the AD7703 to function properly in the new mode. When a calibration step is initiated, the DRDY signal will go high and remain high until the step is finished. Table III shows the number of clock cycles each calibration requires. Once a calibration step is initiated it must finish before a new calibration step can be executed. In the two step system calibration mode, the offset calibration step must be initiated before initiating the gain calibration step. When self-calibration is completed, DRDY falls and the output port is updated with a data word that represents the analog input signal. When a system calibration step is completed, DRDY will fall and the output port will be updated with the appropriate data value (all 0s for the zero-scale point and all 1s for the full-scale point). In the system calibration mode, the digital filter must settle before the output code will represent the value of the analog input signal. Tables IV and V indicate the output code size and output coding of the AD7703 in its various modes. In these tables, SOFF is the measured system offset in volts and SGAIN is the measured system gain at the full-scale point in volts. Span and Offset Limits Whenever a system calibration mode is used, there are limits on the amount of offset and span which can be accommodated. The range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 VREF and a maximum value of 2 (VREF + 0.1 V). The amount of offset which can be accommodated depends on whether the unipolar or bipolar mode is being used. In unipolar mode, the system calibration modes can handle a maximum offset of 0.2 VREF and a minimum offset of –(VREF + 0.1 V). Thus the AD7703 in the unipolar mode can be calibrated to mimic bipolar operation. Table III. Calibration Truth Table CAL SC1 0 1 0 1 SC2 0 1 1 0 CAL TYPE Self-Cal System Offset System Gain System Offset ZERO-SCALE CAL FULL-SCALE CAL SEQUENCE VAGND AIN _ AIN VREF _ AIN VREF One Step 1st Step 2nd Step One Step CALIBRATION TIME 3,145,655 Clock Cycles 1,052,599 Clock Cycles 1,068,813 Clock Cycles 2,117,389 Clock Cycles NOTE DRDY remains high throughout the calibration sequence. In the Self-Cal mode, DRDY falls once the AD7703 has settled to the analog input. In all other modes DRDY falls as the device begins to settle. Table IV. Output Code Size After Calibration 1 LSB CAL MODE Self-Cal ZERO-SCALE VAGND GAIN FACTOR VREF UNIPOLAR (V REF – V AGND ) 1048576 (SGAIN – SOFF ) 1048576 BIPOLAR 2(V REF – V AGND ) 1048576 2(SGAIN – SOFF ) 1048576 System Cal SOFF SGAIN –10– REV. D AD7703 Table V. AD7703 Output Coding INPUT VOLTAGE, UNIPOLAR MODE System Cal >(SGAIN –1.5 LSB) SGAIN – 1.5 LSB Self Cal >(VREF – 1.5 LSB) VREF – 1.5 LSB Output Codes FFFFF FFFFF FFFFE 80000 7FFFF 00001 00000 INPUT VOLTAGE, BIPOLAR MODE Self-Cal >(VREF –1.5 LSB) VREF – 1.5 LSB System Cal >(SGAIN – 1.5 LSB) SGAIN – 1.5 LSB (SGAIN – SOFF)/2 – 0.5 LSB (VREF – VAGND)/2 – 0.5 LSB VAGND – 0.5 LSB SOFF – 0.5 LSB SOFF + 0.5 LSB