AD7707BRZ-REEL7

3 V/5 V, ±10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC AD7707 FEATURES FUNCTIONAL BLOCK DIAGRAM DVDD REF IN(–) REF IN(+) AD7707 CHARGE BALANCING A/D CONVERTER AIN1 AIN2 MUX LOCOM AIN3 VBIAS BUF 30kΩ A = 1 ≈ 128 DIGITAL FILTER 5kΩ 15kΩ HICOM SERIAL INTERFACE 30kΩ REGISTER BANK SCLK CS MCLK IN MCLK OUT DIN CLOCK GENERATION AGND DOUT DGND DRDY RESET Figure 1. for 3-wire operation. Gain settings, signal polarity and update rate selection can be configured in software using the input serial port. The part contains self-calibration and system calibration options to eliminate gain and offset errors on the part itself or in the system. CMOS construction ensures very low power dissipation, and the power-down mode reduces the standby power consumption to 20 μW typical. This part is available in a 20-lead wide body (0.3 inch) small outline (SOIC) package and a low profile 20-lead TSSOP. The AD7707 operates from a single 2.7 V to 3.3 V or 4.75 V to 5.25 V supply. The AD7707 features two low level pseudo differential analog input channels, one high level input channel and a differential reference input. Input signal ranges of 0 mV to 20 mV through 0 V to 2.5 V can be accommodated on both low level input channels when operating with a VDD of 5 V and a reference of 2.5 V. They can also handle bipolar input signal ranges of ±20 mV through ±2.5 V, which are referenced to the LCOM input. The AD7707, with a 3 V supply and a 1.225 V reference, can handle unipolar input signal ranges of 0 mV to 10 mV through 0 V to 1.225 V. Its bipolar input signal ranges are ±10 mV through ±1.225 V. PRODUCT HIGHLIGHTS The high level input channel can accept input signal ranges of ±10 V, ±5 V, 0 V to 10 V and 0 V to 5 V. The AD7707 thus performs all signal conditioning and conversion for a 3-channel system. 4. The AD7707 is ideal for use in smart, microcontroller or DSPbased systems. It features a serial interface that can be configured Σ-Δ MODULATOR PGA 5kΩ GENERAL DESCRIPTION The AD7707 is a complete analog front end for low frequency measurement applications. This 3-channel device can accept either low level input signals directly from a transducer or high level (±10 V) signals and produce a serial digital output. It employs a Σ-Δ conversion technique to realize up to 16 bits of no missing codes performance. The selected input signal is applied to a proprietary programmable gain front end based around an analog modulator. The modulator output is processed by an on-chip digital filter. The first notch of this digital filter can be programmed via an on-chip control register allowing adjustment of the filter cutoff and output update rate. AVDD 08691-001 Charge balancing ADC 16 bits, no missing codes ±0.003% nonlinearity High level (±10 V) and low level (±10 mV) input channels True bipolar ±100 mV capability on low level input Channels without requiring charge pumps Programmable gain front end Gains from 1 to 128 3-wire serial interface SPI, QSPI™, MICROWIRE™ and DSP compatible Schmitt trigger input on SCLK Ability to buffer the analog input 2.7 V to 3.3 V or 4.75 V to 5.25 V operation Power dissipation 1 mW at 3 V Standby current 8 μA maximum 20-lead SOIC and TSSOP packages 1. 2. 3. The AD7707 consumes less than 1 mW at 3 V supplies and 1 MHz master clock, making it ideal for use in low power systems. Standby current is less than 8 μA. On-chip thin-film resistors allow ±10 V, ±5 V, 0 V to 10 V, and 0 V to 5 V high level input signals to be directly accommodated on the analog inputs without requiring split supplies or charge-pumps. The low level input channels allow the AD7707 to accept input signals directly from a strain gage or transducer removing a considerable amount of signal conditioning. The part features excellent static performance specifications with 16 bits, no missing codes, ±0.003% accuracy, and low rms noise. Endpoint errors and the effects of temperature drift are eliminated by on-chip calibration options, which remove zero-scale and full-scale errors. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000–2010 Analog Devices, Inc. All rights reserved. AD7707 TABLE OF CONTENTS Features .............................................................................................. 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Product Highlights ........................................................................... 1  Revision History ............................................................................... 3  Specifications..................................................................................... 4  Timing Characteristics ................................................................ 8  Absolute Maximum Ratings............................................................ 9  ESD Caution .................................................................................. 9  Pin Configuration and Function Descriptions ........................... 10  Typical Performance Characteristics ........................................... 12  OVtput Noise .................................................................................. 14  Output Noise For Low Level Input Channels (5 V Operation) .......................................................................... 14  Output Noise For Low Level Input Channels (3 V Operation) .......................................................................... 15  Span and Offset Limits on the Low Level Input Channels, AIN1 and AIN2 .......................................................................... 31  Span and Offset Limits on the High Level Input Channel AIN3............................................................................................. 31  Power-Up and Calibration ........................................................ 32  Using the AD7707 .......................................................................... 33  Clocking and Oscillator Circuit ............................................... 33  System Synchronization ............................................................ 33  Reset Input .................................................................................. 34  Standby Mode ............................................................................. 34  Accuracy ...................................................................................... 34  Drift Considerations .................................................................. 34  Power Supplies ................................................................................ 35  Supply Current............................................................................ 35  Grounding and Layout .............................................................. 35  Digital Interface .............................................................................. 36  Output Noise For High Level Input Channel AIN3 (5 V Operation) .......................................................................... 16  Configuring the AD7707 ............................................................... 37  Output Noise For High Level Input Channel AIN3 (3 V Operation) .......................................................................... 17  AD7707to68HC11 Interface .................................................. 39  On-Chip Registers .......................................................................... 18  Communications Register (RS2, RS1, RS0 = 0, 0, 0) ............. 18  Calibration Sequences .................................................................... 23  Circuit Description ......................................................................... 24  Analog Input ................................................................................... 25  Analog Input Ranges .................................................................. 25  Input Sample Rate ...................................................................... 26  Bipolar/Unipolar Inputs ............................................................ 26  Reference Input ............................................................................... 27  Digital Filtering ............................................................................... 28  Filter Characteristics .................................................................. 28  Postfiltering ................................................................................. 29  Analog Filtering .......................................................................... 29  Calibration ....................................................................................... 30  Self-Calibration ........................................................................... 30  System Calibration ..................................................................... 30  Microcomputer/Microprocessor Interfacing .............................. 39  AD7707to8XC51 Interface ..................................................... 40  Code For Setting Up the AD7707 ................................................ 41  C Code for Interfacing AD7707 to 68HC11 ........................... 41  Applications Information .............................................................. 43  Data Acquisition ......................................................................... 43  Smart Valve/Actuator Control .................................................. 43  Pressure Measurement............................................................... 45  Thermocouple Measurement ................................................... 45  RTD Measurement ..................................................................... 45  Chart Recorders .......................................................................... 46  Accommodating Various High Level Input Ranges .............. 46  Typical Input Currents............................................................... 46  Output Noise For High Level Input Channel, AIN3 ................. 47  5 V Operation ............................................................................. 47  3 V Operation ............................................................................. 48  Outline Dimensions ....................................................................... 49  Ordering Guide .......................................................................... 50  Rev. B | Page 2 of 52 AD7707 REVISION HISTORY 1/10—Rev. A to Rev B Updated Format.................................................................. Universal Changes to Features Section ............................................................ 1 Changes to Table 1 ...................................................................................... 4 Changes to Table 5 ............................................................................ 9 Changes to Output Noise For Low Level Input Channels (3 V Operation) Section .................................................................14 Changes to Output Noise For High Level Input Channel AIN3 (5 V Operation) Section .................................................................15 Changed Output Noise For High Level Input Channel AIN3 (5 V Operation) Section Heading to Output Noise For High Level Input Channel AIN3 (3 V Operation) ...............................17 Changes to Table 16 ........................................................................19 Changes to Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 0x1F4000 Section ....................22 Changes to Calibration Sequences Section ..................................23 Changes to Circuit Description Section .......................................24 Deleted Evaluating the AD7707 Performance Section .............. 27 Changes to Digital Filtering Section and Filter Characteristics Section ......................................................... 28 Deleted AD7707 to ADSP-2103/ADSP-2105 Interface Section .............................................................................................. 31 Deleted Figure 23; Renumbered Sequentially ............................. 31 Moved Figure 18 .............................................................................. 33 Changes to Figure 19 and Supply Current Section ..................... 35 Change to Smart Valve/Actuator Control Section and Figure 25 ........................................................................................... 43 Changes to Figure 27 ...................................................................... 44 Added Titles to Table 28, Table 29, and Table 30 ........................ 46 Updated Outline Dimensions........................................................ 49 Changes to Ordering Guide ........................................................... 50 2/00—Rev. 0 to Rev. A Rev. B | Page 3 of 52 AD7707 SPECIFICATIONS AVDD = DVDD = 3 V or 5 V, REF IN(+) = 1.225 V with AVDD = 3 V and 2.5 V with AVDD = 5 V; REF IN(−) = GND; VBIAS = REFIN(+); MCLK IN = 2.4576 MHz unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE Low Level Input Channels (AIN1 and AIN2) No Missing Codes Output Noise B Version 1 Unit Conditions/Comments 16 See Table 7 to Bits min Guaranteed by design; filter notch < 60 Hz Depends on filter cutoffs and selected gain ±0.003 % of FSR max Filter notch < 60 Hz; typically ±0.0003% 0.5 μV/°C typ 0.5 0.1 μV/°C typ μV/°C typ 0.5 μV/°C typ 0.5 ±0.003 1 0.6 ppm of FSR/°C typ % of FSR max μV/°C typ μV/°C typ 16 See Table 11 to Bits min Guaranteed by design; filter notch < 60 Hz Depends on filter cutoffs and selected gain % of FSR max mV max μV/°Ctyp mV max μV/°C typ μV/°C typ % typ ppm of FSR/°C typ % of FSR typ Filter notch < 60 Hz; typically ±0.0003% Typically within ±1.5 mV Table 10 Integral Nonlinearity 2 Unipolar Offset Error 3 Unipolar Offset Drift 4 Bipolar Zero Error3 Bipolar Zero Drift4 Positive Full-Scale Error3, 5 Full-Scale Drift4, 6 Gain Error3, 7 Gain Drift4, 8 Bipolar Negative Full-Scale Error2 Bipolar Negative Full-Scale Drift4 HIGH LEVEL INPUT CHANNEL (AIN3) No Missing Codes Output Noise For gains of 1, 2, and 4 For gains of 8, 16, 32, 64, and 128 Typically ±0.0007% For gains of 1 to 4 For gains of 8 to 128 Table 13 2 Integral Nonlinearity Unipolar Offset Error 9 Unipolar Offset Drift Bipolar Zero Error9 Bipolar Zero Drift Gain Error Gain Drift Negative Full-Scale Error2 LOW LEVEL ANALOG INPUTS/REFERENCE INPUTS Input Common-Mode Rejection (CMR)2 AVDD = 5 V Gain = 1 Gain = 2 Gain = 4 Gain = 8 to 128 AVDD = 3 V Gain = 1 Gain = 2 Gain = 4 Gain = 8 to 128 Normal-Mode 50 Hz Rejection2 Normal-Mode 60 Hz Rejection2 Common-Mode 50 Hz Rejection2 ±0.003 ±10 4 ±10 4 1 ±0.2 0.5 ±0.0012 Typically within ±1.5 mV For gains of 1, 2, and 4 For gains of 8, 16, 32, 64, and 128 Typically within ±0.05% Specifications for AIN and REF IN, unless otherwise noted Low level input channels, AIN1 and AIN2 100 105 110 130 dB typ dB typ dB typ dB typ 105 110 120 130 98 98 150 dB typ dB typ dB typ dB typ dB typ dB typ dB typ Rev. B | Page 4 of 52 For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × fNOTCH For filter notches of 10 Hz, 20 Hz, 60 Hz; ±0.02 × fNOTCH For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × fNOTCH AD7707 Parameter Common-Mode 60 Hz Rejection2 Absolute/Common-Mode REF IN Voltage2 Absolute/Common-Mode AIN Voltage2, 10 AIN DC Input Current2 AIN Sampling Capacitance2 AIN Differential Voltage Range11, 12 AIN Input Sampling Rate, fS Reference Input Range REF IN(+) − REF IN(−) Voltage REF IN(+) − REF IN(−) Voltage B Version1 150 AGND to AVDD AGND – 100 mV AVDD + 30 mV AGND + 50 mV AVDD − 1.5 V 1 10 0 to +VREF/gain Unit dB typ V min to V max V min V max V min V max nA max pF max V nom Conditions/Comments For filter notches of 10 Hz, 20 Hz, 60 Hz, ±0.02 × fNOTCH Bipolar input range (B/U bit of setup register = 0) For gains of 1 to 4 For gains of 8 to 128 ±VREF/gain V nom Gain × fCLKIN/64 fCLKIN/8 Hz nom 1/1.75 V min/max 1/3.5 V min/max BUF bit of setup register = 0 BUF bit of setup register = 1 BUF = 0 Unipolar input range (B/U bit of setup register = 1) AVDD = 2.7 V to 3.3 V; VREF = 1.225 V ± 1% for specified performance AVDD = 4.75 V to 5.25 V; VREF = 2.5 V ± 1% for specified performance REF IN Input Sampling Rate, fS ±100 mV INPUT RANGE fCLKIN/64 INL2 Input Common-Mode Rejection (CMR)2 Power Supply Rejection (PSR)2 HIGH LEVEL ANALOG INPUT CHANNEL (AIN3) AIN3 Voltage Range ±0.003 80 90 % of FSR max dB typ dB typ +10 −10 78 78 Gain × fCLKIN/64 fCLKIN/8 27 V max V min dB typ dB typ Hz nom Hz nom kΩ min 10 0 V/AVDD pF max V min/max Typically REFIN(+) = 2.5 V ±1 ±10 μA max μA max Typically ±20 nA Typically ±2 m A 0.8 0.4 2.0 V max V max V max DVDD = 5 V DVDD = 3 V DVDD = 3 V and 5 V DVDD = 5 V nominal 1.4/3 0.8/1.4 0.4/0.8 V min/V max V min/V max V min/V max 1/2.5 0.4/1.1 0.375/0.8 V min/V max V min/V max V min /V max Normal Mode 50 Hz Rejection Normal Mode 60 Hz Rejection AIN3 Input Sampling Rate, fS AIN3 Input Impedance2 AIN3 Sampling Capacitance2 VBIAS Input Range LOGIC INPUTS Input Current All Inputs Except MCLK IN MCLK All Inputs Except SCLK and MCLK IN VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt Triggered Input) VT+ VT− VT+ − VT− SCLK Only (Schmitt Triggered Input) VT+ VT− VT+ − VT− Low level input channels, AIN1 and AIN2; gain = 16, unbuffered mode Filter notch < 60 Hz AIN3 is with respect to HICOM For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × fNOTCH For filter notches of 10 Hz, 20 Hz, 60 Hz; ±0.02 × fNOTCH For gains of 1 to 4 For gains of 8 to 128 Typically 30 kΩ ± 10%; typical resistor Tempco is −30 ppm/°C DVDD = 3 V nominal Rev. B | Page 5 of 52 AD7707 Parameter MCLK IN Only VINL, Input Low Voltage VINH, Input High Voltage MCLK IN Only VINL, Input Low Voltage VINH, Input High Voltage LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Low Voltage VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance14 Data Output Coding SYSTEM CALIBRATION Low Level Input Channels (AIN1 and AIN2) Positive Full-Scale Calibration Limit15 Negative Full-Scale Calibration Limit15 Offset Calibration Limit16 Input Span16 High Level Input Channels (AIN3) Positive Full-Scale Calibration Limit15 Negative Full-Scale Calibration Limit15 Offset Calibration Limit16 Input Span16 POWER REQUIREMENTS Power Supply Voltages AVDD Voltage DVDD Voltage Power Supply Currents AVDD Current B Version1 Unit 0.8 3.5 V max V min 0.4 2.5 V max V min 0.4 0.4 4 DVDD − 0.6 ±10 9 Binary Offset binary V max V max V min V min μA max pF typ (1.05 × VREF)/gain −(1.05 × VREF)/gain −(1.05 × VREF)/gain (0.8 × VREF)/gain (2.1 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) V max Gain is the selected PGA gain (1 to 128) V max Gain is the selected PGA gain (1 to 128) V min V max Gain is the selected PGA gain (1 to 128) Gain is the selected PGA gain (1 to 128) (8.4 × VREF)/gain −(8.4 × VREF)/gain −(8.4 × VREF)/gain (6.4 × VREF)/gain (16.8 × VREF)/gain V max V max Gain is the selected PGA gain (1 to 128) Gain is the selected PGA gain (1 to 128) V max Gain is the selected PGA gain (1 to 128) V min V max Gain is the selected PGA gain (1 to 128) Gain is the selected PGA gain (1 to 128) 2.7 to 3.3 or 4.75 to 5.25 2.7 to 5.25 V min to V max V min to V max For specified performance For specified performance 0.27 0.6 mA max mA max 0.5 1.1 mA max mA max 0.080 0.15 0.18 0.35 mA max mA max mA max mA max dB typ DVDD = 3 V nominal ISINK = 800 μA except for MCLK OUT13; DVDD = 5 V ISINK = 100 μA except for MCLK OUT13; DVDD = 3 V ISOURCE = 200 μA except for MCLK OUT13; DVDD = 5 V ISOURCE = 100 μA except for MCLK OUT13; DVDD = 3 V Unipolar mode Bipolar mode POWER REQUIREMENTS (Continued) DVDD Current17 Power Supply Rejection18, 19 Conditions/Comments DVDD = 5 V nominal Rev. B | Page 6 of 52 AVDD = 3 V or 5 V; gain = 1 to 4 Typically 0.22 mA; BUF = 0; fCLK IN = 1 MHz or 2.4576 MHz Typically 0.45 mA; BUF = 1; fCLK IN = 1 MHz or 2.4576 MHz AVDD = 3 V or 5 V; gain = 8 to 128 Typically 0.38 mA; BUF = 0; fCLK IN = 2.4576 MHz Typically 0.81 mA; BUF = 1; fCLK IN = 2.4576 MHz Digital inputs = 0 V or DVDD; external MCLK IN Typically 0.06 mA; DVDD = 3 V; fCLK IN = 1 MHz Typically 0.13 mA; DVDD = 5 V; fCLK IN = 1 MHz Typically 0.15 mA; DVDD = 3 V; fCLK IN = 2.4576 MHz Typically 0.3 mA; DVDD = 5 V; fCLK IN = 2.4576 MHz AD7707 Parameter Normal Mode Power Dissipation17 B Version 1 Unit 1.05 2.04 1.35 mW max mW max mW max 2.34 mW max 2.1 3.75 3.1 4.75 18 mW max mW max mW max mW max μA max 8 μA max Conditions/Comments AVDD = DVDD = 3 V; digital inputs = 0 V or DVDD; external MCLK IN excluding dissipation in the AIN3 attenuator Typically 0.84 mW; BUF = 0; fCLK IN = 1 MHz, all gains Typically 1.53 mW; BUF = 1; fCLK IN = 1 MHz; all gains Typically 1.11 mW; BUF = 0; fCLK IN = 2.4576 MHz, gain = 1 to 4 Typically 1.9 mW; BUF = 1; fCLK IN = 2.457 6 MHz; gain = 1 to 4 AVDD = DVDD = 5 V; digital inputs = 0 V or DVDD; external MCLKIN Typically 1.75 mW; BUF = 0; fCLK IN = 1 MHz; all gains Typically 2.9 mW; BUF = 1; fCLK IN = 1 MHz; all gains Typically 2.6 mW; BUF = 0; fCLK IN = 2.4576 MHz Typically 3.75 mW; BUF = 1; fCLK IN = 2.4576 MHz External MCLK IN = 0 V or DVDD; typically 9 μA; AVDD = 5 V External MCLK IN = 0 V or DVDD; typically 4 μA; AVDD = 3 V Normal Mode Power Dissipation17 Standby (Power-Down) Current 20 1 Temperature range as follows: B Version, −40°C to +85°C. These numbers are established from characterization or design at initial product release. A calibration is effectively a conversion so these errors are of the order of the conversion noise shown in Table 7 and Table 9 for the low level input channels AIN1 and AIN2. This applies after calibration at the temperature of interest. 4 Recalibration at any temperature removes these drift errors. 5 Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. 6 Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges. 7 Gain error does not include zero-scale errors. It is calculated as full-scale error—unipolar offset error for unipolar ranges and full-scale error—bipolar zero error for bipolar ranges. 8 Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if POMZ
zero-scale calibrations were performed. 9 Error is removed following a system calibration. 10 This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than AVDD + 30 mV or go more negative than AGND − 100 mV. Parts are functional with voltages down to AGND − 200 mV, but with increased leakage at high temperature. 11 The analog input voltage range on AIN(+) is given here with respect to the voltage on LCOM on the low level input channels (AIN1 and AIN2) and is given with respect to the HCOM input on the high level input channel, AIN3. The absolute voltage on the low level analog inputs should not go more positive than AVDD + 100 mV, or go more negative than GND − 100 mV for specified performance. Input voltages of AGND − 200 mV can be accommodated, but with increased leakage at high temperature. 12 VREF = REF IN(+) − REF IN(−). 13 These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load. 14 Sample tested at +25°C to ensure compliance. 15 After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s. 16 These calibration and span limits apply provided that the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than AGND − 
mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. 17 When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation varies depending on the crystal or resonator type (see the Clocking and Oscillator Circuit section). 18 Measured at dc and applies in the selected pass band. PSRR at 50 Hz exceeds 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB with filter notches of 20 Hz or 60 Hz. 19 PSRR depends on both gain and AVDD. See Table 2 and Table 3. 20 If the external master clock continues to run in standby mode, the standby current increases to 150 μA typical at 5 V and 75 μA typical at 3 V. When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator type (see the Standby Mode section). 2 3 Table 2. Low Level Input Channels, AIN1 and AIN2 Gain AVDD = 3 V AVDD = 5 V 1 86 90 2 78 78 4 85 84 8 to 128 93 91 1 68 72 2 60 60 4 67 66 8 to 128 75 73 Table 3. High Level Input Channel, AIN3 Gain AVDD = 3 V AVDD = 5 V Rev. B | Page 7 of 52 AD7707 TIMING CHARACTERISTICS AVDD = DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; fCLKIN = 2.4576 MHz; input logic = 0, Logic 1 = DVDD, unless otherwise noted. Table 4. Parameter 1, 2 fCLKIN 3, 4 tCLKIN LO tCLKIN HI t1 t2 Read Operation t3 t4 t5 5 t6 t7 t8 t9 6 t10 Write Operation t11 t12 t13 t14 t15 t16 Limit at TMIN, TMAX (B Version) 400 5 0.4 × tCLKIN 0.4 × tCLKIN 500 × tCLKIN 100 Unit kHz min MHz max ns min ns min ns nom ns min Master clock input low time, tCLKIN = 1/fCLKIN Master clock input high time DRDY high time RESET pulse width 0 120 0 80 100 100 100 0 10 60 100 100 ns min ns min ns min ns max ns max ns min ns min ns min ns min ns max ns max ns max DRDY to CS setup time CS falling edge to SCLK rising edge setup time SCLK falling edge to data valid delay DVDD = 5 V DVDD = 3.0 V SCLK high pulse width SCLK low pulse width CS rising edge to SCLK rising edge hold time Bus relinquish time after SCLK rising edge DVDD = 5 V DVDD = 3.0 V SCLK falling edge to DRDY high 7 120 30 20 100 100 0 ns min ns min ns min ns min ns min ns min CS falling edge to SCLK rising edge setup time Data valid to SCLK rising edge setup time Data valid to SCLK rising edge hold time SCLK high pulse width SCLK low pulse width CS rising edge to SCLK rising edge hold time Conditions/Comments Master clock frequency: crystal oscillator or externally supplied for specified performance 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 20 and Figure 21. 3 fCLKIN duty cycle range is 45% to 55%. fCLKIN must be supplied whenever the AD7707 is not in standby mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 The AD7707 is production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz. 5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high, although care should be taken that subsequent reads do not occur close to the next output update. 2 ISINK (800µA AT VDD = 5V 100µA AT VDD = 3V) TO OUTPUT PIN 1.6V ISOURCE (200µA AT VDD = 5V 100µA AT VDD = 3V) 08691-002 50pF Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev. B | Page 8 of 52 AD7707 ABSOLUTE MAXIMUM RATINGS TA = +25°C, unless otherwise noted. Table 5. Parameter AVDD to AGND AVDD to DGND DVDD to AGND DVDD to DGND AVDD to DVDD DGND to AGND AIN1, AIN2 Input Voltage to LOCOM AIN3 Input Voltage to HICOM VBIAS to AGND HICOM, LOCOM to AGND REF IN(+), REF IN(−) to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature SOIC Package, Power Dissipation θJA Thermal Impedance Lead Temperature, Soldering Reflow TSSOP Package, Power Dissipation θJA Thermal Impedance Lead Temperature, Soldering Reflow ESD Rating Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to +7 V −0.3 V to +7 V −0.3 V to +7 V −0.3 V to +0.3 V −0.3 V to AVDD + 0.3 V −11 V to +30 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 450 mW 75°C/W 260°C 450 mW 139°C/W 260°C 2.5 kV Rev. B | Page 9 of 52 AD7707 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 20 DGND MCLK IN 2 19 DVDD MCLK OUT 3 18 DIN CS 4 17 DOUT AD7707 DRDY TOP VIEW AVDD 6 (Not to Scale) 15 AGND 14 REF IN(–) AIN1 7 16 LOCOM 8 13 REF IN(+) AIN2 9 12 VBIAS AIN3 10 11 HICOM 08691-003 RESET 5 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic SCLK 2 MCLK IN 3 MCLK OUT 4 CS 5 RESET 6 7 8 9 10 11 12 AVDD AIN1 LOCOM AIN2 AIN3 HICOM VBIAS 13 REF IN(+) 14 REF IN(−) 15 16 AGND DRDY 17 DOUT Description Serial Clock, Schmitt-Triggered Logic Input. An external serial clock is applied to this input to access serial data from the AD7707. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7707 in smaller batches of data. Master Clock Signal for the Device. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part can be operated with clock frequencies in the range of 500 kHz to 5 MHz. When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and MCLK OUT. If an external clock is applied to MCLK IN, MCLK OUT provides an inverted clock signal. This clock can be used to provide a clock source for external circuitry and is capable of driving one CMOS load. If the user does not require it, this MCLK OUT can be turned off via the CLKDIS bit of the clock register. This ensures that the part is not wasting unnecessary power driving capacitive loads on MCLK OUT. Chip Select. This pin is an active low logic input used to select the AD7707. With this input hard-wired low, the AD7707 can operate in its 3-wire interface mode with SCLK, DIN, and DOUT used to interface to the device. CS can be used to select the device in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the AD7707. Logic Input. Active low input that resets the control logic, interface logic, calibration coefficients, digital filter, and analog modulator of the part to power-on status. Analog Supply Voltage, 2.7 V to 5.25 V Operation. Low Level Analog Input Channel 1. This is used as a pseudo differential input with respect to LOCOM. Common Input for Low Level Input Channels. Analog inputs on AIN1 and AIN2 must be referenced to this input. Low Level Analog Input Channel 2. This is used as a pseudo differential input with respect to LOCOM. Single-Ended High Level Analog Input Channel with respect to HICOM. Common Input for )igh -evel *nput $hannel. Analog input on AIN3 must be referenced to this input. VBIAS is used to level shift the high level input channel signal. This signal is used to ensure that the AIN(+) and AIN(−) signals seen by the internal modulator are within its common-mode range. VBIAS is normally connected to 2.5 V when AVDD = 5 V and 1.225 V when AVDD = 3 V. Reference Input. Positive input of the differential reference input to the AD7707. The reference input is differential with the provision that REF IN(+) must be greater than REF IN(−). REF IN(+) can lie anywhere between AVDD and AGND. Reference Input. Negative input of the differential reference input to the AD7707. The REF IN(−) can lie anywhere between AVDD and AGND provided that REF IN(+) is greater than REF IN(−). Analog Ground. Ground reference point for the AD7707’s internal analog circuitry. Logic Output. A logic low on this output indicates that a new output word is available from the AD7707 data register. The DRDY pin returns high upon completion of a read operation of a full output word. If no data read has taken place between output updates, the DRDY line returns high for 500 × tCLK IN cycles prior to the next output update. While DRDY is high, a read operation should neither be attempted nor in progress to avoid reading from the data register as it is being updated. The DRDY line returns low again when the update has taken place. DRDY is also used to indicate when the AD7707 has completed its on-chip calibration sequence. Serial Data Output with Serial Data Being Read from the Output Shift Register on the Part. This output shift register can contain information from the setup register, communications register, clock register, or data register, depending on the register selection bits of the communications register. Rev. B | Page 10 of 52 AD7707 Pin No. 18 Mnemonic DIN 19 20 DVDD DGND Description Serial Data Input with Serial Data Being Written to the Input Shift Register on the Part. Data from this input shift register is transferred to the setup register, clock register, or communications register, depending on the register selection bits of the communications register. Digital Supply Voltage, 2.7 V to 5.25 V Operation. Ground Reference Point for the AD7707’s Internal Digital Circuitry. Rev. B | Page 11 of 52 AD7707 TYPICAL PERFORMANCE CHARACTERISTICS 32,771 VDD = 5V VREF = 2.5V GAIN = 128 50Hz UPDATE RATE 32,770 400 TA = 25°C RMS NOISE = 600nV 300 32,768 OCCURRENCE 32,767 32,766 100 32,765 08691-004 32,764 32,763 200 0 200 100 300 400 500 600 700 READING NUMBER 800 0 900 1000 Figure 4. Typical Noise Plot at Gain = 128 with 50 Hz Update Rate for Low Level Input Channel 32,769 08691-007 CODE READ 32,769 32,764 32,765 32,766 32,767 CODE 32,768 32,769 32,770 Figure 7. Histogram of Data in Figure 4 800 10Hz UPDATE RATE, UNBUFFERED MODE GAIN = 2 (±10V INPUT RANGE) BIPOLAR MODE ANALOG INPUT SET ON CODE TRANSITION 700 600 10Hz UPDATE RATE UNBUFFERED MODE BIPOLAR MODE GAIN = 2 (±10V INPUT RANGE) CODE OCCURRENCE 32,768 32,767 500 400 300 200 400 600 READING NUMBER 800 1000 100 0 1 32,767 2 32,768 08691-008 200 CODE Figure 8. Histogram of Data in Figure 5 Figure 5. Typical Noise Plot for AIN3, High Level Input Channel 10 0.6 HIGH LEVEL INPUT CHANNEL ±10V INPUT RANGE 10Hz UPDATE RATE 9 0.5 8 6 5 4 RMS NOISE (µV) RMS NOISE (µV) 7 BUFFERED MODE AVDD= DVDD= 5V REF IN(+) = 2.5V REF IN(–) = AGND TA = 25°C 3 0.4 UNBUFFERED MODE 0.2 0.1 –6 –2 2 AIN3 (V) 6 10 08691-006 1 0 –10 Figure 6. Typical RMS Noise vs. Analog Input Voltage for High Level Input Channel, AIN3 BUFFERED MODE 0.3 UNBUFFERED MODE 2 LOW LEVEL INPUT CHANNEL GAIN = 128 10Hz UPDATE RATE 0 –20 AVDD= DVDD= 5V REF IN(+) = 2.5V REF IN(–) = AGND TA = +25°C –15 –10 –5 0 5 INPUT VOLTAGE (mV) 10 15 20 08691-009 0 08691-005 32,766 Figure 9. Typical RMS Noise vs. Analog Input Voltage for Low Level Input Channels, AIN1 and AIN2 Rev. B | Page 12 of 52 AD7707 20 TEK STOP: SINGLE SEQ 50.0kSPS VDD 16 STANDBY CURRENT (µA) 1 2 OSCILLATOR = 4.9152MHz MCLK IN = 0V OR VDD 12 VDD = 5V 8 VDD = 3V 08691-010 2 OSCILLATOR = 2.4576MHz CH1 5.00V CH2 2.00V 5ms/DIV Figure 10. Typical Crystal Oscillator Power-Up Time 0 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 Figure 11. Standby Current vs. Temperature Rev. B | Page 13 of 52 70 80 08691-011 4 AD7707 OUTPUT NOISE OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION) Table 7 shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered mode for the selectable notch and −3 dB frequencies for the part, as selected by FS0, FS1, and FS2 of the clock register. The numbers given are for the bipolar input ranges with a VREF of 2.5 V and AVDD = 5 V. These numbers are typical and are generated at an analog input voltage of 0 V. Table 8 shows the rms noise and peak-to-peak resolution when operating in buffered mode. It is important to note that the peak-to-peak numbers represent the resolution for which there is no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. The numbers given are for bipolar input ranges with a VREF of 2.5 V. These numbers are typical and are rounded to the nearest LSB. The numbers apply for the CLKDIV bit of the clock register set to 0. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in Table 7 and Table 8
are given for the bipolar input ranges. For the unipolar ranges, the rms noise numbers are the same as the bipolar range but the peak-to-peak resolution is now based on half the signal range, which effectively means losing one bit of resolution. Table 7. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V AIN1 and AIN2 Unbuffered Mode Only Filter First Notch and Output Data −3 dB Rate Frequency MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.5 Hz Typical Output RMS Noise in μV (Peak-to-Peak Resolution in Bits) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1.2 (16) 3.6 (16) 4.7 (16) 95 (13) 600 (10.5) 0.7 (16) 2.1 (16) 2.6 (16) 65 (13) 316 (10.5) 0.7 (16) 1.25 (16) 1.5 (16) 23.4 (13) 138 (10.5) 0.54 (16) 0.89 (16) 0.94 (16) 11.6 (13) 71 (10.5) 0.28 (16) 0.62 (16) 0.73 (16) 6.5 (13) 38 (10.5) 0.28 (16) 0.60 (15.5) 0.68 (15.5) 3.4 (13) 18 (10.5) 0.28 (15.5) 0.56 (14.5) 0.66 (14.5) 2.1 (12.5) 10 (10) 0.27 (14.5) 0.56 (13.5) 0.63 (13.5) 1.5 (12) 5.7 (10) 1.19 (16) 3.68 (16) 4.78 (16) 100 (13) 543 (10.5) 0.69 (16) 2.18 (16) 2.66 (16) 50.1 (13) 318 (10.5) 0.71 (16) 1.19 (16) 1.51 (16) 23.5 (13) 132 (10.5) 0.63 (16) 0.94 (16) 1.07 (16) 11.9 (13) 68.1 (10.5) 0.27 (16) 0.6 (16) 0.7 (16) 5.83 (13) 33.1 (10.5) 0.27 (16) 0.6 (15.5) 0.67 (15.5) 3.64 (13) 17.6 (10.5) 0.26 (15.5) 0.56 (14.5) 0.66 (14.5) 2.16 (12.5) 9.26 (10.5) 0.24 (15) 0.56 (13.5) 0.65 (13.5) 1.5 (12) 6.13 (10) Table 8. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V AIN1 and AIN2 Buffered Mode Only Filter First Notch and Output Data −3 dB Rate Frequency MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.4 Hz Typical Output RMS /oise in μV (Peak-to-Peak Resolution in Bits) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1.47 (16) 4.2 (16) 4.9 (16) 104 (13) 572 (10.5) 0.95 (16) 2.6 (16) 3 (16) 52 (13) 293 (10.5) 0.88 (16) 1.6 (16) 1.8 (16) 26 (13) 125 (10.5) 0.55 (16) 1 (16) 1.1 (16) 14 (13) 69 (10.5) 0.42 (16) 0.89 (15.5) 1 (15.5) 6.5 (13) 40 (10.5) 0.42 (16) 0.94 (15) 1 (14.5) 4.1 (12.5) 19 (10.5) 0.42 (15) 0.9 (14) 0.94 (14) 2.7 (12.5) 10 (10.5) 0.41 (14) 0.9 (13) 0.94 (13) 2.3 (11.5) 5.9 (10) 1.48 (16) 3.9 (16) 5.37 (16) 98.9 (13) 596 (10.5) 8.95 (16) 2.46 (16) 3.05 (16) 52.4 (13) 298 (10.5) 0.87 (16) 1.77 (16) 1.89 (16) 26.1 (13) 133 (10.5) 0.67 (16) 1.19 (16) 1.33 (16) 12.7 (13) 69.3 (10.5) 0.41 (16) 0.94 (16) 1.11 (15.5) 6.08 (13) 34.7 (10.5) 0.40 (16) 0.93 (15) 1.06 (14.5) 4.01 (12.5) 16.9 (10.5) 0.40 (15) 0.95 (14) 1.04 (13.5) 2.62 (12.5) 9.67 (10.5) 0.40 (14) 0.9 (13) 1.02 (12.5) 2.33 (11.5) 6.34 (10) Rev. B | Page 14 of 52 AD7707 OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (3 V OPERATION) Table 9 shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered mode for the selectable notch and −3 dB frequencies for the part, as selected by FS0, FS1, and FS2 of the clock register. The numbers given are for the bipolar input ranges with a VREF of 1.225 V and an AVDD = 3 V. These numbers are typical and are generated at an analog input voltage of 0 V. Table 10 shows the rms noise and peak-to-peak resolution when operating in buffered mode. It is important to note that the peak-to-peak numbers represent the resolution for which there is no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. The numbers given are for bipolar input ranges with a VREF of 1.225 V and for either buffered or unbuffered mode. These numbers are typical and are rounded to the nearest LSB. The numbers apply for the CLKDIV bit of the clock register set to 0. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in Table 9 and Table 10 are given for the bipolar input ranges. For the unipolar ranges, the rms noise numbers are the same as the bipolar range but the peakto-peak resolution is now based on half the signal range, which effectively means losing 1 bit of resolution. Table 9. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 3 V AIN1 and AIN2 Unbuffered Mode Only Filter First Notch and Output Data −3 dB Rate Frequency MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1.60 (16) 3.8 (16) 4.4 (16) 53 (13) 300 (10.5) 0.8 (16) 1.9 (16) 2.2 (16) 24 (13) 138 (10.5) 0.48 (16) 1.1 (16) 1.35 (16) 15 (13) 80 (10.5) 0.29 (16) 0.64 (16) 0.78 (16) 6.8 (13) 34 (10.5) 0.29 (16) 0.60 (15.5) 0.7 (15) 3.6 (12.5) 18 (10.5) 0.27 (15.5) 0.6 (14.5) 0.68 (14.5) 2.1 (12.5) 8.7 (10.5) 0.26 (14.5) 0.6 (13.5) 0.64 (13.5) 1.5 (12) 4.8 (10) 0.26 (13.5) 0.6 (12.5) 0.64 (12.5) 1.3 (11) 3.4 (10) MCLK IN = 1 MHz 4.05 Hz 20 Hz 25 Hz 100 Hz 200 Hz 1.56 (16) 3.85 (16) 4.56 (16) 45.7 (13) 262 (10.5) 0.88 (16) 2.02 (16) 2.4 (16) 22 (13) 125 (10.5) 0.52 (16) 1.15 (16) 1.4 (16) 13.7 (13) 66 (10.5) 0.3 (16) 0.74 (16) 0.79 (16) 5.27 (13) 32.4 (10.5) 0.28 (16) 0.63 (15.5) 0.68 (15) 2.64 (13) 18.4 (10.5) 0.27 (15.5) 0.57 (14.5) 0.66 (14.5) 2 (12.5) 8.6 (10.5) 0.27 (14.5) 0.61 (13.5) 0.64 (13.5) 1.59 (12) 4.64 (10.5) 0.26 (13.5) 0.58 (12.5) 0.64 (12.5) 1.4 (11) 3.3 (10) 1.06 Hz 5.24 Hz 6.55 Hz 26.2 Hz 52.4 Hz Typical Output RMS Noise in μV (Peak-to-Peak Resolution in Bits) Table 10. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 3 V AIN1 and AIN2 Buffered Mode Only Filter First Notch and Output Data −3 dB Rate Frequency MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.4 Hz Typical Output RMS Noise in μV (Peak-to-Peak Resolution in Bits) Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1.80 (16) 4.1 (16) 5.1 (16) 50 (13) 275 (10.5) 1 (16) 2.4 (16) 3 (16) 27 (13) 125 (10.5) 0.7 (16) 1.5 (16) 1.8 (16) 12.3 (13) 80 (10.5) 0.41 (16) 1 (15.5) 1.1 (15.5) 6.4 (13) 39 (10.5) 0.41 (16) 0.91 (15) 0.94 (14.5) 4 (12.5) 16 (10.5) 0.41 (15) 0.89 (14) 0.94 (13.5) 2.7 (12.5) 8.9 (10.5) 0.41 (14) 0.86 (13) 0.99 (13) 2.2 (11.5) 5.2 (10) 0.41 (13) 0.83 (12) 0.99 (11.5) 1.8 (11) 4.2 (9.5) 1.75 (16) 4.21 (16) 5.15 (16) 46.1 (13) 282 (10.5) 1.18 (16) 2.5 (16) 2.8 (16) 24.3 (13) 123 (10.5) 0.67 (16) 1.48 (16) 1.8 (16) 13.6 (13) 66 (10.5) 0.44 (16) 1 (15.5) 1.15 (15.5) 6.71 (13) 35.3 (10.5) 0.41 (16) 0.94 (15) 1 (14.5) 4.1 (12.5) 14.8 (10.5) 0.44 (15) 0.96 (14) 1.02 (13.5) 2.54 (12.5) 9.91 (10.5) 0.43 (14) 0.89 (13) 0.96 (13) 2.3 (11.5) 5.48 (10) 0.43 (13) 0.86 (12) 1.03 (11.5) 2.15 (10.5) 4.01 (9.5) Rev. B | Page 15 of 52 AD7707 OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION) Table 11 shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered mode for the selectable notch and −3 dB frequencies for the part, as selected by FS0, FS1, and FS2 of the clock register. The numbers given are for the ±10 V, ±5 V, 0 to 5 V and 0 V to 10 V ranges with a VREF of 2.5 V, VBIAS = 2.5 V, HICOM = AGND, and AVDD = 5 V. These numbers are typical and are generated at an analog input voltage of 0 V. Table 12 meanwhile shows the output rms noise and peak-to-peak resolution in buffered mode. It is important to note that these numbers represent the resolution for which there is no code flicker. They are not calculated based on rms noise, but on peak-to-peak noise. Operating the high level channel with a gain of 2 in bipolar mode gives an operating range of ±10 V. Operating at a gain of 2 in unipolar mode gives a range of 0 V to +10 V. Operating the high level channel with a gain of 4 in bipolar mode gives the ±5 V operating range. Operating at a gain of 4 in unipolar mode gives an operating range of 0 V to 5 V. Noise for all input ranges is shown in Output Noise For High Level Input Channel, AIN3 section. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in Table 11 and Table 12 are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers are the same as the bipolar range, but the peak-to-peak resolution is now based on half the signal range, which effectively means losing 1 bit of resolution. Table 11. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V AIN3 Unbuffered Mode Only Filter First Notch and Output Data −3 dB Rate Frequency MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.4 Hz ±10 V Range RMS Noise P-P (Bits) (μV) Resolution ±5 V Range RMS Noise P-P (Bits) (μV) Resolution 0 V to 10 V Range RMS Noise P-P (Bits) (μV) Resolution 0 V to 5 V Range RMS P-P (Bits) Noise (μV) Resolution 5.10 15.82 20.36 430 2350 16 16 16 13 10 3.52 9.77 12.29 212 1287 16 16 16 13 10 5.10 15.82 20.36 430 2350 16 16 16 12 9 3.52 9.77 12.29 212 1287 16 16 16 12 9 5.13 18.9 23.7 406 2184 16 16 16 13 10.5 3.53 13.25 15.3 174 1144 16 16 16 13 10.5 5.13 18.9 23.7 406 2184 16 16 16 12 9.5 3.53 13.25 15.3 174 1144 16 16 15.5 12 9.5 Table 12. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V AIN3 Buffered Mode Only Filter First Notch and Output Data −3 dB Rate Frequency MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.4 Hz ±10 V Range RMS Noise P-P (Bits) (μV) Resolution ±5 V Range RMS Noise P-P (Bits) (μV) Resolution 0 V to 10 V Range RMS Noise P-P (Bits) (μV) Resolution 0 to 5 V Range RMS Noise P-P (Bits) (μV) Resolution 7.4 22.2 26.6 475 2423 16 16 16 13 10.5 5.2 14.3 15.85 187 1097 16 16 16 13 10.5 7.4 22.2 26.6 475 2423 16 16 16 12 9.5 5.2 14.3 15.85 187 1097 16 16 16 12 9.5 7.63 20.25 23.5 377 2226 16 16 16 13 10.5 5.45 13.3 14.6 210 1132 16 16 16 13 10.5 7.63 20.25 23.5 377 2226 16 16 16 12 9.5 5.45 13.3 14.6 210 1132 16 16 15.5 12 9.5 Rev. B | Page 16 of 52 AD7707 OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (3 V OPERATION) Table 13 shows the AD7707 output rms noise and peak-to-peak resolution for the selectable notch and −3 dB frequencies for the part, as selected by FS0, FS1, and FS2 of the clock register. The numbers given are for the ±5 V, 0 V to 5 V and 0 V to 10 V ranges with a VREF of 1.225 V, VBIAS = 1.225 V, HICOM = AGND, and AVDD = 3 V. These numbers are typical and are generated at an analog input voltage of 0 V for unbuffered mode of operation. The ±5 V, 0 V to 5 V, and 0 V to 10 V operating ranges are only achievable in unbuffered mode when operating at 3 V due to common-mode limitations on the input amplifier. It is important to note that these numbers represent the resolution for which there are no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. Operating at a gain of 1 in unipolar mode provides a range of 0 V to +10 V. Operating the high level channel with a gain of 2 in bipolar mode provides a ±5 V operating range. Operating at a gain of 2 in unipolar mode provides an operating range of 0 V to 5 V. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in Table 13 are given for the bipolar input ranges. For the unipolar ranges, the rms noise numbers are the same as the bipolar range, but the peak-to-peak resolution is now based on half the signal range, which effectively means losing 1 bit of resolution. Table 13. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +3 V AIN3 Unbuffered Mode Only Filter First Notch and Output −3 dB Data Rate Frequency MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.4 Hz 0 V to 10 V Range RMS Noise P-P (Bits) (μV) Resolution ±5 V Range RMS Noise P-P (Bits) (μV) Resolution 0 to 5 V Range RMS Noise P-P (Bits) (μV) Resolution 12.4 30.35 34.55 498 2266 16 16 16 12.5 10.5 7.02 16.4 19.13 204 1151 16 16 16 13 10.5 7.02 16.4 19.13 204 1151 16 15.5 15 12 9.5 13.9 32.2 33.4 430 2207 16 16 16 13 10.5 7.3 17.4 18.57 200 1048 16 16 16 13 10.5 7.3 17.4 18.57 200 1048 16 15 15 12 9.5 Rev. B | Page 17 of 52 AD7707 ON-CHIP REGISTERS The AD7707 contains eight on-chip registers that can be accessed via the serial port of the part. The first of these is a communications register that controls the channel selection, decides whether the next operation is a read or write operation and selects which register the next read or write operation accesses. All communications to the part must start with a write operation to the communications register. After power-on or RESET, the device expects a write to its communications register. The data written to this register determines whether the next operation to the part is a read or a write operation and determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the communications register followed by a write to the selected register. A read operation from any other register on the part (including the communications register itself and the data register) starts with a write operation to the communications register followed by a read operation from the selected register. The communications register also controls the standby mode and channel selection and the DRDY status is available by reading from the communications register. The second register is a setup register that determines calibration mode, gain setting, bipolar/unipolar operation, and buffered mode. The third register is the clock register and contains the filter selection bits and clock control bits. The fourth register is the data register from which the output data from the part is accessed. The final registers are the calibration registers, which store channel calibration data. The registers are described in more detail in the following sections. COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) The communications register is an 8-bit register from which data can either be read or to which data can be written. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation and to which register this operation takes place. When the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface, and on power-up or after a RESET, the AD7707 is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, if a write operation of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7707 returns to this default state. Table 14 outlines the bit designations for the communications register. Table 14. Communications Register 0/DRDY (0) RS2 (0) RS1 (0) RS0 (0) R/W (0) STBY (0) CH1 (0) CH0 (0) Table 15. Communications Register Bit Descriptions Bit 0/DRDY RS2 to RS0 R/W STBY CH1, CH0 Description For a write operation, a 0 must be written to this bit so that the write operation to the communications register actually takes place. If a 1 is written to this bit, the part does not clock on to subsequent bits in the register. The serial interface stays at this bit location until a 0 is written to this bit. Once a 0 is written to this bit, the next seven bits are loaded to the communications register. For a read operation, this bit provides the status of the DRDY flag from the part. The status of this bit is the same as the DRDY output pin. Register selection bits. These three bits select to which one of eight on-chip registers the next read or write operation takes place, as shown in Table 16, along with the register size. When the read or write operation to the selected register is complete, the part waits for a write operation to the communications register. It does not remain in a state where it continues to access the register. Read/Write select. This bit selects whether the next operation is a read or write operation to the selected register. A 0 indicates a write cycle for the next operation to the appropriate register, while a 1 indicates a read operation from the appropriate register. Standby. Writing a 1 to this bit puts the part into its standby or power-down mode. In this mode, the part consumes only 8 μA of power supply current. The part retains its calibration coefficients and control word information when in standby. Writing a 0 to this bit places the part in its normal operating mode. The serial interface on the AD7707 remains operational when the part is in standby mode. Channel select. These two bits select a channel for conversion or for access to the calibration coefficients as outlined in Table 17. Three pairs of calibration registers on the part are used to store the calibration coefficients following a calibration on a channel. They are shown in Table 17 for the AD7707 to indicate which channel combinations have independent calibration coefficients. With CH1 at Logic 1 and CH0 at a Logic 0, the part looks at the LOCOM input internally shorted to itself. This can be used as a test method to evaluate the noise performance of the part with no external noise sources. In this mode, the LOCOM input should be connected to an external voltage within the allowable common-mode range for the part. Rev. B | Page 18 of 52 AD7707 Table 16. Register Selection RS2 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 Register Communications register Setup register Clock register Data register Test register No operation Zero-scale calibration register Full-scale calibration register Register Size 8 bits 8 bits 8 bits 16 bits 8 bits 24 bits 24 bits Table 17. Channel Selection for AD7707 CH1 0 0 1 1 CH0 0 1 0 1 AIN AIN1 AIN2 LOCOM AIN3 Reference LOCOM LOCOM LOCOM HICOM Rev. B | Page 19 of 52 Calibration Register Pair Register Pair 0 Register Pair 1 Register Pair 0 Register Pair 2 AD7707 Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01 The setup register is an eight-bit register from which data can either be read or to which data can be written. Table 18 outlines the bit designations for the setup register. Table 18. Setup Register MD1 (0) MD0 (0) G2 (0) G1 (0) G0 (0) B/U (0) BUF (0) FSYNC (1) Table 19. Bit MD1, MD0 G2 to G0 B/U BUF FSYNC Description Operating mode selection bits. Gain selection bits. These bits select the gain setting for the on-chip PGA, as outlined in Table 21. Bipolar/unipolar operation. A 0 in this bit selects Bipolar operation. A 1 in this bit selects unipolar operation. Buffer control. With this bit at 0, the on-chip buffer on the analog input is shorted out. With the buffer shorted out, the current flowing in the AVDD line is reduced. When this bit is high, the on-chip buffer is in series with the analog input allowing the input to handle higher source impedances. Filter synchronization. When this bit is high, the nodes of the digital filter, the filter control logic, and the calibration control logic are held in a reset state, and the analog modulator is held in its reset state. When this bit goes low, the modulator and filter start to process data and a valid word is available in 3 × 1/(output update rate), that is, the settling time of the filter. This FSYNC bit does not affect the digital interface and does not reset the DRDY output if it is low. Table 20. Operating Modes MD1 0 0 MD0 0 1 1 0 1 1 Operating Mode Normal mode: this is the normal mode of operation of the device whereby the device is performing normal conversions. Self-calibration: this activates self-calibration on the channel selected by CH1 and CH0 of the communications register. This is a one-step calibration sequence and, when complete, the part returns to normal mode with MD1 and MD0 returning to 0, 0. The DRDY output or bit goes high when calibration is initiated and returns low when this selfcalibration is complete and a new valid word is available in the data register. The zero-scale calibration is performed at the selected gain on internally shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on an internally-generated VREF/selected gain. Zero-scale (ZS) system calibration: this activates zero-scale system calibration on the channel selected by CH1 and CH0 of the communications register. Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes high when calibration is initiated and returns low when this zero-scale calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to Oormal Node with MD1 and MD0 returning to 0, 0. Full-scale (FS) system calibration: this activates full-scale system calibration on the selected input channel. Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes high when calibration is initiated and returns low when this full-scale calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to normal mode with MD1 and MD0 returning to 0, 0. Table 21. Gain Selection G2 0 0 0 0 1 1 1 1 G1 0 0 1 1 0 0 1 1 G0 0 1 0 1 0 1 0 1 Gain Setting 1 2 4 8 16 32 64 128 Rev. B | Page 20 of 52 AD7707 Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 0x05 The clock register is an 8-bit register from which data can either be read or to which data can be written. Table 22 outlines the bit designations for the clock register. Table 22. Clock Register Zero (0) Zero (0) CLKDIS (0) CLKDIV (0) CLK (1) FS2 (0) FS1 (0) FS0 (1) Table 23. Clock Register Bit Descriptions Bit Zero CLKDIS CLKDIV CLK FS2, FS1, FS0 Description Zero. A zero must be written to these bits to ensure correct operation of the AD7707. Failure to do so may result in unspecified operation of the device. Master clock disable bit. A Logic 1 in this bit disables the master clock from appearing at the MCLK OUT pin. When disabled, the MCLK OUT pin is forced low. This feature allows the user the flexibility of using the MCLK OUT as a clock source for other devices in the system or of turning off the MCLK OUT as a power saving feature. When using an external master clock on the MCLK IN pin, the AD7707 continues to have internal clocks and converts normally with the CLKDIS bit active. When using a crystal oscillator or ceramic resonator across the MCLK IN and MCLK OUT pins, the AD7707 clock is stopped and no conversions take place when the CLKDIS bit is active. Clock divider bit. With this bit at a Logic 1, the clock frequency appearing at the MCLK IN pin is divided by two before being used internally by the AD7707. For example, when this bit is set to 1, the user can operate with a 4.9152 MHz crystal between MCLK IN and MCLK OUT, and internally the part operates with the specified 2.4576 MHz. With this bit at a Logic 0, the clock frequency appearing at the MCLK IN pin is the frequency used internally by the part. Clock bit. This bit should be set in accordance with the operating frequency of the AD7707. If the device has a master clock frequency of 2.4576 MHz (CLKDIV = 0) or 4.9152 MHz (CLKDIV = 1), then this bit should be set to a 1. If the device has a master clock frequency of 1 MHz (CLKDIV = 0) or 2 MHz (CLKDIV = 1), this bit should be set to a 0. This bit sets up the appropriate scaling currents for a given operating frequency and also chooses (along with FS2, FS1 and FS0) the output update rate for the device. If this bit is not set correctly for the master clock frequency of the device, then the AD7707 may not operate to specification. Filter selection bits. Along with the CLK bit, FS2, FS1, and FS0 determine the output update rate, filter first notch, and −3 dB frequency as outlined in Table 24. The on-chip digital filter provides a sinc3 (or Sinx/x3) filter response. Placing the first notch at 10 Hz places notches at both 50 Hz and 60 Hz, giving better than 150 dB rejection at these frequencies. In association with the gain selection, the filter cutoff also determines the output noise of the device. Changing the filter notch frequency, as well as the selected gain, impacts resolution. Table 7 to Table 13 show the effect of filter notch frequency and gain on the output noise and effective resolution of the part. The output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz, a new word is available at a 50 Hz output rate, or every 20 ms. If the first notch is at 500 Hz, a new word is available every 2 ms. A calibration should be initiated when any of these bits are changed. The settling time of the filter to a full-scale step input is worst-case 4 × 1/(output data rate). For example, with the filter first notch at 50 Hz, the settling time of the filter to a full-scale step input is 80 ms maximum. If the first notch is at 500 Hz, the settling time is 8 ms maximum. This settling time can be reduced to 3 × 1/(output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step input takes place with the FSYNC bit high, the settling time is 3 × 1/(output data rate) from when the FSYNC bit returns low. The −3 dB frequency is determined by the programmed first notch frequency according to the following relationship: filter − 3 dB frequency = 0.262 × filter first notch frequency Rev. B | Page 21 of 52 AD7707 Table 24. Output Update Rates CLK 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 FS2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Update Rate 20 Hz 25 Hz 100 Hz 200 Hz 50 Hz 60 Hz 250 Hz 500 Hz 4.054 Hz 4.23 Hz 4.84 Hz 4.96 Hz 10 Hz 10.34 Hz 11.90 Hz 12.2 Hz −3 dB Filter Cutoff 5.24 Hz 6.55 Hz 26.2 Hz 52.4 Hz 13.1 Hz 15.7 Hz 65.5 Hz 131 Hz 1.06 Hz 1.11 Hz 1.27 Hz 1.3 Hz 2.62 Hz 2.71 Hz 3.13 Hz 3.2 Hz Assumes correct clock frequency on the MCLK IN pin with the CLKDIV bit set appropriately. Data Register (RS2, RS1, RS0 = 0, 1, 1) The data register on the part is a 16-bit read-only register that contains the most up-to-date conversion result from the AD7707. If the communications register sets up the part for a write operation to this register, a write operation must actually take place to return the part to where it is expecting a write operation to the communications register. However, the 16 bits of data written to the part are ignored by the AD7707. Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 0x00 The part contains a Uest Segister that is used when testing the device. The user is advised not to change the status of any of the bits in this register from the default (power-on or RESET) status of all 0s because the part will be placed in one of its test modes and will not operate correctly. Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 0x1F4000 The AD7707 contains independent sets of zero-scale registers, one for each of the input channels. Each of these registers is a 24-bit read/write register; 24 bits of data must be written; otherwise, no data is transferred to the register. This register is used in conjunction with its associated full-scale register to form a register pair. These register pairs are associated with input channel pairs as outlined in Table 17. Although the part is set up to allow access to these registers over the digital interface, the part itself no longer has access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibration registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a write to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking the FSYNC bit in the setup register high before the calibration register operation and taking it low after the operation is complete. Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 0x5761AB The AD7707 contains independent sets of full-scale registers, one for each of the input channels. Each of these registers is a 24-bit read/write register; 24 bits of data must be written; otherwise, no data is transferred to the register. This register is used in conjunction with its associated zero-scale register to form a register pair. These register pairs are associated with input channel pairs as outlined in Table 17. Although the part is set up to allow access to these registers over the digital interface, the part itself no longer has access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibration registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a write to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking UIF
FSYNC bit in the setup register high before the calibration register operation and taking it low after the operation is complete. Rev. B | Page 22 of 52 AD7707 CALIBRATION SEQUENCES The AD7707 contains a number of calibration options as previously outlined. Table 25 summarizes the calibration types, the operations involved, and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor when DRDY returns low at the end of the sequence. DRDY not only indicates when the sequence is complete, but also that the part has a valid new sample in its data register. This valid new sample is the result of a normal conversion, which follows the calibration sequence. The second method of determining when calibration is complete is to monitor the MD1 and MD0 bits of the setup register. When these bits return to 0 (0 following a calibration command), it indicates that the calibration sequence is complete. This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier indication than DRDY that calibration is complete. The duration to when the Mode Bits (MD1 and MD0) return to 00 represents the duration of the calibration carried out). The sequence to when DRDY goes low also includes a normal conversion and a pipeline delay, tP, to correctly scale the results of this first conversion. tP will never exceed 2000 × tCLKIN. The time for both methods is given in the Table 25. Table 25. Calibration Sequences Calibration Type Self-Calibration MD1, MD0 0, 1 ZS System Calibration FS System Calibration 1, 0 1, 1 Calibration Sequence Internal ZS calibration at selected gain + Internal FS calibration at selected gain ZS calibration on AIN at selected gain FS calibration on AIN at selected gain Rev. B | Page 23 of 52 Duration to Mode Bits 6 × 1/output rate Duration to DRDY 3 × 1/output rate 3 × 1/output rate 4 × 1/output rate + tP 4 × 1/output rate + tP 9 × 1/output rate + tP AD7707 CIRCUIT DESCRIPTION modulator) converts the sampled signal into a digital pulse train whose duty cycle contains the digital information. The programmable gain function on the analog input is also incorporated in this Σ-Δ modulator with the input sampling frequency being modified to give the higher gains. A sinc3 digital low-pass filter processes the output of the Σ-Δ modulator and updates the output register at a rate determined by the first notch frequency of this filter. The output data can be read from the serial port randomly or periodically at any rate up to the output register update rate. The first notch of this digital filter (and therefore its −3 dB frequency) can be programmed via the clock register bits, FS0 to FS2. With a master clock frequency of 2.4576 MHz, the programmable range for this first notch frequency is from 10 Hz to 500 Hz, giving a programmable range for the −3 dB frequency of 2.62 Hz to 131 Hz. With a master clock frequency of 1 MHz, the programmable range for this first notch frequency is from 4 Hz to 200 Hz, giving a programmable range for the −3 dB frequency of 1.06 Hz to 52.4 Hz. The AD7707 is a Σ-Δ ADC with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those in industrial control or process control applications. It contains a Σ-Δ (or charge balancing) ADC, a calibration microcontroller with on-chip static RAM, a clock oscillator, a digital filter, and a bidirectional serial communications port. The part consumes only 320 μA of power supply current, making it ideal for battery-powered or loop-powered instruments. On-chip thin-film resistors allow ±10 V, ±5 V, 0 V to 10 V, and 0 V to 5 V high level input signals to be directly accommodated on the analog input without requiring split supplies, dc-to-dc converters, or charge pumps. This part operates with a supply voltage of 2.7 V to 3.3 V, or 4.75 V to 5.25 V. The AD7707 contains two low level (AIN1 and AIN2) programmable-gain pseudo differential analog input channels and one high level (AIN3) single-ended input channel. For the low level input channels, the selectable gains are 1, 2, 4, 8, 16, 32, 64, and 128, allowing the part to accept unipolar signals of between 0 mV to 20 mV and 0 V to 2.5 V, or bipolar signals in the range from ±20 mV to ±2.5 V when the reference input voltage equals 2.5 V. With a reference voltage of 1.225 V, the input ranges are from 0 mV to 10 mV to 0 V to 1.225 V in unipolar mode, and from ±10 mV to ±1.225 V in bipolar mode. Note that the signals are with respect to the LOCOM input. The basic connection diagram for the AD7707 is shown in Figure 12. An AD780 or REF192 precision 2.5 V reference provides the reference source for the part. On the digital side, the part is configured for 3-wire operation with CS tied to DGND. A quartz crystal or ceramic resonator provides the master clock source for the part. In most cases, it is necessary to connect capacitors on the crystal or resonator to ensure that it does not oscillate at overtones of its fundamental operating frequency. The values of capacitors can vary, depending on the manufacturer’s specifications. A similar circuit is applicable for operation with 3 V supplies; in this case, a 1.225 V reference (AD1580) should be used for specified performance. The high level input channel can directly accept input signals of ±10 V with respect to HICOM when operating with 5 V supplies and a reference of 2.5 V. With 3 V supplies, ±5 V can be accommodated on the AIN3 input. The input signal to the analog input is continuously sampled at a rate determined by the frequency of the master clock, MCLK IN, and the selected gain. A charge-balancing ADC (Σ-Δ ANALOG 5V SUPPLY 10µF 0.1µF 0.1µF AVDD LOW LEVEL ANALOG INPUT DVDD AIN1 DRDY DATA READY AIN2 LOCOM DOUT RECEIVE (READ) AIN3 HIGH LEVEL ANALOG INPUT DIN VBIAS HICOM AGND ANALOG 5V SUPPLY SERIAL DATA SCLK AD7707 SERIAL CLOCK 5V RESET DGND CS VIN VOUT AD780/ REF192 REF IN(+) 10µF 0.1µF REF IN(–) MCLK IN MCLK OUT CRYSTAL OR CERAMIC RESONATOR 08691-012 GND Figure 12. Basic Connection Diagram for 5 V Operation Rev. B | Page 24 of 52 AD7707 ANALOG INPUT The AD7707 contains two low level pseudo differential analog input channels, AIN1 and AIN2. These input pairs provide programmable-gain, differential input channels that can handle either unipolar or pseudo bipolar input signals. It should be noted that the bipolar input signals are referenced to the LOCOM input. The AD7707 also has a high level analog input channel AIN3, which is referenced to HICOM. Figure 13 shows the input structure on the high level input channel. In normal 5 V operation, VBIAS is normally connected to 2.5 V and HICOM is connected to AGND. This arrangement ensures that the voltages seen internally are within the common-mode range of the buffer in buffered mode and within the supply range in unbuffered mode. This device can be programmed to operate in either buffered or unbuffered mode via the BUF bit in the setup register. Note that the signals on AIN3 are with respect to the HICOM input and not with respect to AGND or DGND. this unbuffered mode is 1 nA maximum. As a result, the analog inputs see a dynamic load that is switched at the input sample rate (see Figure 14). This sample rate depends on master clock frequency and selected gain. CSAMP is charged to AIN(+) and discharged to AIN(−) every input sample cycle. The effective PO resistance of the switch, RSW, is typically 7 kΩ. CSAMP must be charged through RSW and any additional source impedances every input sample cycle. Therefore, in unbuffered mode, source impedances mean a longer charge time for CSAMP and this may result in gain errors on the part. Table 26 shows the allowable external resistance/capacitance values, for unbuffered mode, such that no gain error to the 16-bit level is introduced on the part. Note that these capacitances are total capacitances on the analog input. This external capacitance includes 10 pF from the pins and lead frame of the device. The differential voltage seen by the AD7707 when using the high level input channel is the difference between AIN3(+) and AIN3(−) on the mux as shown in Figure 13. AIN(+) RSW (7kΩ TYP) AIN(–) CSAMP (7pF) VDD/2 AIN3(+) = (AIN3 + 6 × VBIAS
+ VHICOM)/8 SWITCHING FREQUENCY DEPENDS ON fCLKIN AND SELECTED GAIN 6R AIN3 FIRST INTEGRATOR HIGH INPUT IMPEDANCE >1G 08691-014 ANALOG INPUT RANGES Figure 14. Unbuffered Analog Input Structure 1R = 5kΩ VBIAS Table 26. External R, C Combination for No 16-Bit Gain Error on Low Level Input Channels (Unbuffered Mode Only) AIN3(+) MUX 1R Gain 1 2 4 8 to 128 3R 6R HICOM 08691-013 AIN3(–) Figure 13. AIN3 Input Structure 0 368 kΩ 177.2 kΩ 82.8 kΩ 35.2 kΩ External Capacitance (pF) 50 100 500 1000 90.6 kΩ 54.2 kΩ 14.6 kΩ 8.2 kΩ 44.2 kΩ 26.4 kΩ 7.2 kΩ 4 kΩ 21.2 kΩ 12.6 kΩ 3.4 kΩ 1.94 kΩ 9.6 kΩ 5.8 kΩ 1.58 Ω 880 Ω 5000 2.2 kΩ 1.12 kΩ 540 Ω 240 Ω AIN3(−) = VHICOM + 0.75 × (VBIAS − VHICOM) 400 350 EXTERNAL RESISTANCE (kΩ) GAIN = 1 300 250 200 GAIN = 2 150 GAIN = 8 TO 128 100 GAIN = 4 50 0 0 10 100 1000 EXTERNAL CAPACITANCE (pF) 10000 08691-015 In unbuffered mode, the common-mode range of the low level input channels is from AGND − 100 mV to AVDD + 30 mV. This means that in unbuffered mode, the part can handle both unipolar and bipolar input ranges for all gains. Absolute voltages of AGND − 100 mV can be accommodated on the analog inputs without degradation in performance, but leakage current increases appreciably with increasing temperature. In buffered mode, the analog inputs can handle much larger source impedances, but the absolute input voltage range is restricted to between AGND + 50 mV to AVDD − 1.5 V, which also places restrictions on the common-mode range. This means that in buffered mode, there are some restrictions on the allowable gains for bipolar input ranges. Care must be taken in setting up the common-mode voltage and input voltage range so that these limits are not exceeded; otherwise, there will be a degradation in linearity performance. Figure 15. External R, C Combination for No 16-Bit Gain Error on Low Level Input Channels (Unbuffered Mode Only) In unbuffered mode, the analog inputs look directly into the 7 pF input sampling capacitor, CSAMP. The dc input leakage current in Rev. B | Page 25 of 52 AD7707 In buffered mode, the analog inputs look into the high impedance inputs stage of the on-chip buffer amplifier. CSAMP is charged via this buffer amplifier such that source impedances do not affect the charging of CSAMP. This buffer amplifier has an offset leakage current of 1 nA. In buffered mode, large source impedances result in a small dc offset voltage developed across the source impedance, but not in a gain error. INPUT SAMPLE RATE The modulator sample frequency for the AD7707 remains at fCLKIN/128 (19.2 kHz at fCLKIN = 2.4576 MHz) regardless of the selected gain. However, gains greater than 1 are achieved by a combination of multiple input samples per modulator cycle and a scaling of the ratio of reference capacitor to input capacitor. As a result of the multiple sampling, the input sample rate of the device varies with the selected gain (see Table 27). In buffered mode, the input impedance is constant. In unbuffered mode, where the analog input looks directly into the sampling capacitor, the effective input impedance is 1/CSAMP × fS where CSAMP is the input sampling capacitance and fS is the input sample rate. Table 27. Input Sampling Frequency vs. Gain Gain 1 2 4 8 to 128 Input Sampling Frequency (fS) fCLKIN/64 (38.4 kHz at fCLKIN = 2.4576 MHz) 2 × fCLKIN/64 (76.8 kHz at fCLKIN =2.4576 MHz) 4 × fCLKIN/64 (76.8 kHz at fCLKIN =2.4576 MHz) 8 × fCLKIN/64 (307.2 kHz at fCLKIN = 2.4576 MHz) BIPOLAR/UNIPOLAR INPUTS The analog inputs on the low level input channels on the AD7707 can accept either unipolar or bipolar input voltage ranges with respect to LOCOM. The high level input channel handles true bipolar signals of ±10 V maxJNVN for guaranteed operation. Bipolar or unipolar options are chosen by programming the B/U bit of the setup register. This programs the channel for either unipolar or bipolar operation. Programming the channel for either unipolar or bipolar operation does not change any of the channel conditions, it simply changes the data output coding and the points on the transfer function where calibrations occur. In unipolar operation, the output coding is straight binary. In bipolar mode, the output coding is offset binary. Rev. B | Page 26 of 52 AD7707 REFERENCE INPUT The AD7707 reference inputs, REF IN(+) and REF IN(−), provide a differential reference input capability. The commonmode range for these differential inputs is from GND to AVDD. The nominal reference voltage, VREF REF IN(+) − REF IN(−), for specified operation is +2.5 V for the AD7707 operated with an AVDD of 5 V and 1.225 V for the AD7707 operated with an AVDD of 3 V. The part is functional with VREF voltages down to 1 V, but with degraded performance because the LSB size is smaller. REF IN(+) must always be greater than REF IN(−) for correct operation of the AD7707. Both reference inputs provide a high impedance, dynamic load similar to the analog inputs in unbuffered mode. The maximum dc input leakage current is ±1 nA over temperature, and source resistance may result in gain errors on the part. In this case, the sampling switch resistance is 5 kΩ typical and the reference capacitor (CREF) varies with gain. The sample rate on the reference inputs is fCLKIN/64 and does not vary with gain. For gains of 1 and 2, CREF is 8 pF; for a gain of 16, it is 5.5 pF; for a gain of 32, it is 4.25 pF; for a gain of 64, it is 3.625 pF; and for a gain of 128, it is 3.3125 pF. The output noise performance outlined in Table 7 through Table 13 is for an analog input of 0 V, which effectively removes the effect of noise from the reference. To obtain the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7707. If the reference noise in the bandwidth of interest is excessive, it degrades the performance of the AD7707. In bridge transducer applications where the reference voltage for the ADC is derived from the excitation voltage, the effect of the noise in the excitation voltage is removed because the application is ratiometric. Recommended reference voltage sources for the AD7707 with an AVDD of 5 V include the AD780, REF43, and REF192, and the recommended reference sources for the AD7707 operated with an AVDD of 3 V include the AD589 and AD1580. It is generally recommended to decouple the output of these references to further reduce the noise level. Rev. B | Page 27 of 52 AD7707 DIGITAL FILTERING On the other hand, analog filtering can remove noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. To alleviate this problem, the AD7707 has overrange headroom built into the Σ-Δ modulator and digital filter, which allows overrange excursions of 5% above the analog input range. If noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. This provides an overrange capability greater than 100% at the expense of reducing the dynamic range by one bit (50%). In addition, the digital filter does not provide any rejection at integer multiples of the digital filter’s sample frequency. However, the input sampling on the part provides attenuation at multiples of the digital filter’s sampling frequency so that the unattenuated bands actually occur around multiples of the sampling frequency, fS (as defined in Table 27). Thus, the unattenuated bands occur at n × fS (where n = 1, 2, 3…). At these frequencies, there are frequency bands of ±f3 dB width (f3 dB is the cutoff frequency of the digital filter) where noise passes unattenuated to the output. FILTER CHARACTERISTICS The AD7707’s digital filter is a low-pass filter with a (sinx/x)3 response (also called sinc3). The transfer function for this filter is described in the z domain by: −N 1 1− Z H (z ) = × N 1 − Z −1 3 and in the frequency domain by: 1 SIN (N × π × f / f S ) H( f ) − × N SIN (π × f / f S 3 where N is the ratio of the modulator rate to the output rate. ∠H = − 3 π (N − 2) × f / f S Rad Figure 16 shows the filter frequency response for a cutoff frequency of 2.62 Hz, which corresponds to a first filter notch frequency of 10 Hz. The plot is shown from dc to 65 Hz. This response is repeated at either side of the digital filter’s sample frequency and at either side of multiples of the filter’s sample frequency. The response of the filter is similar to that of an averaging filter, but with a sharper roll-off. The output rate for the digital filter corresponds with the positioning of the first notch of the filter’s frequency response. Thus, for the plot of Figure 16 where the output rate is 10 Hz, the first notch of the filter is at 10 Hz. The notches of this (sinx/x)3 filter are repeated at multiples of the first notch. The filter provides attenuation of better than 100 dB at these notches. 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 08691-016 First, because digital filtering occurs after the ADC process, it can remove noise injected during the conversion process. Analog filtering cannot do this. Also, the digital filter can be made programmable far more readily than an analog filter. Depending on the digital filter design, this gives the user the capability of programming cutoff frequency and output update rate. Phase response: GAIN (dB) The AD7707 contains an on-chip low-pass digital filter that processes the output of the part’s Σ-Δ modulator. Therefore, the part not only provides the analog-to-digital conversion function but also provides a level of filtering. There are a number of system differences when the filtering function is provided in the digital domain rather than the analog domain and the user should be aware of these. –220 –240 0 10 20 30 40 FREQUENCY (Hz) 50 60 Figure 16. Frequency Response of AD7707 Filter Simultaneous 50 Hz and 60 Hz rejection is obtained by placing the first notch at 10 Hz. Operating with an update rate of 10 Hz places notches at both 50 Hz and 60 Hz giving better than 100 dB rejection at these frequencies. The cutoff frequency of the digital filter is determined by the value loaded to Bit FS0 to Bit FS2 in the clock register. Programming a different cutoff frequency via FS0, FS1, and FS2 does not alter the profile of the filter response; it changes the frequency of the notches. The output update of the part and the frequency of the first notch correspond. Because the AD7707 contains this on-chip, low-pass filtering, a settling time is associated with step function inputs and data on the output will be invalid after a step change until the settling time has elapsed. The settling time depends upon the output rate chosen for the filter. The settling time of the filter to a full-scale step input can be up to four times the output data period. For a synchronized step input (using the FSYNC function), the settling time is three times the output data period. Rev. B | Page 28 of 52 AD7707 POSTFILTERING ANALOG FILTERING The on-chip modulator provides samples at a 19.2 kHz output rate with fCLKIN at 2.4576 MHz. The on-chip digital filter decimates these samples to provide data at an output rate that corresponds to the programmed output rate of the filter. Because the output data rate is higher than the Nyquist criterion, the output rate for a given bandwidth satisfies most application requirements. There may, however, be some applications that require a higher data rate for a given bandwidth and noise performance. Applications that need this higher data rate require some postfiltering following the digital filter of the AD7707. The digital filter does not provide any rejection at integer multiples of the modulator sample frequency, as previously outlined. However, due to the AD7707’s high oversampling ratio, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. This means that the analog filtering requirements in front of the AD7707 are considerably reduced vs. a conventional converter with no on-chip filtering. In addition, because the part’s common-mode rejection performance of 100 dB extends out to several kHz, common-mode noise in this frequency range is substantially reduced. For example, if the required bandwidth is 7.86 Hz, but the required update rate is 100 Hz, the data can be taken from the AD7707 at the 100 Hz rate, giving a −3 dB bandwidth of 26.2 Hz. Postfiltering can be applied to this to reduce the bandwidth and output noise, to the 7.86 Hz bandwidth level, while maintaining an output rate of 100 Hz. Depending on the application, however, it may be necessary to provide attenuation prior to the AD7707 to eliminate unwanted frequencies from these bands, which the digital filter will pass. It may also be necessary in some applications to provide analog filtering in front of the AD7707 to ensure that differential noise signals outside the band of interest do not saturate the analog modulator. Postfiltering can also be used to reduce the output noise from the device for bandwidths below 2.62 Hz. At a gain of 128 and a bandwidth of 2.62 Hz, the output rms noise is 450 nV. This is essentially device noise or white noise and because the input is chopped, the noise has a primarily flat frequency response. By reducing the bandwidth below 2.62 Hz, the noise in the resultant pass band can be reduced. A reduction in bandwidth by a factor of 2 results in a reduction of approximately 1.25 in the output rms noise. This additional filtering results in a longer settling time. If passive components are placed in front of the AD7707 in unbuffered mode, care must be taken to ensure that the source impedance is low enough not to introduce gain errors in the system. This significantly limits the amount of passive antialiasing filtering, which can be provided in front of the AD7707 when it is used in unbuffered mode. However, when the part is used in buffered mode, large source impedances simply result in a small dc offset error (a 10 kΩ source resistance causes an offset error of less than 10 μV). Therefore, if the system requires any TJHOJGJ cant source impedances to provide passive analog GJMUFSJOH
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PQFSBUFE in buffered mode. Rev. B | Page 29 of 52 AD7707 CALIBRATION The AD7707 provides a number of calibration options that can be programmed via the MD1 and MD0 bits of the setup register. The different calibration options are outlined in the Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01 section and the Calibration Sequences section. A calibration cycle can be initiated at any time by writing to these bits of the setup register. Calibration on the AD7707 removes offset and gain errors from the device. A calibration routine should be initiated on the device whenever there is a change in the ambient operating temperature or supply voltage. It should also be initiated if there is a change in the selected gain, filter notch, or bipolar/unipolar input range. The AD7707 offers self-calibration and system calibration facilities. For full calibration to occur on the selected channel, the on-chip microcontroller must record the modulator output for two different input conditions. These are zero-scale and full-scale points. These points are derived by performing a conversion on the different input voltages provided to the input of the modulator during calibration. As a result, the accuracy of the calibration can only be as good as the noise level that it provides in normal mode. The result of the zero-scale calibration conversion is stored in the zero-scale calibration register whereas the result of the full-scale calibration conversion is stored in the full-scale calibration register. With these readings, the microcontroller can calculate the offset and the gain slope for the input-tooutput transfer function of the converter. SELF-CALIBRATION A self-calibration is initiated on the AD7707 by writing the appropriate values (0, 1) to the MD1 and MD0 bits of the setup register. In the self-calibration mode with a unipolar input range, the zero-scale point used in determining the calibration coefficients is with the inputs of the differential pair internally shorted on the part (that is, AIN1 = LOCOM = internal bias voltage in the case of the AD7707. The PGA is set for the selected gain (as per the G2, G1, and G0 bits in the setup register) for this zero-scale calibration conversion. The fullscale calibration conversion is performed at the selected gain on an internally-generated voltage of VREF/selected gain. The duration time for the calibration is 6 × 1/output rate. This is made up of 3 × 1/output rate for the zero-scale calibration and 3 × 1/output rate for the full-scale calibration. At this time, the MD1 and MD0 bits in the setup register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 9 × 1/output rate. This is made up of 3 × 1/output rate for the zero-scale calibration, 3 × 1/output rate for the full-scale calibration, 3 × 1/output rate for a conversion on the analog input, and some overhead to correctly set up the coefficients. If DRDY is low before (or goes low during) the calibration command write to the setup register, it may take up to one modulator cycle (MCLK IN/ 128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the setup register in the calibration command. For bipolar input ranges in the self-calibrating mode, the sequence is very similar to that just outlined. In this case, the two points are exactly the same as in the previous case but because the part is configured for bipolar operation, the shorted inputs point is actually midscale of the transfer function. Errors due to resistor mismatch in the attenuator on the high level input channel AIN3 are not removed by a self-calibration. SYSTEM CALIBRATION System calibration allows the AD7707 to compensate for system gain and offset errors as well as its own internal errors. System calibration performs the same slope factor calculations as selfcalibration, but uses voltage values presented by the system to the AIN inputs for the zero-scale and full-scale points. Full system calibration requires a two-step process, a ZS system calibration followed by an FS system calibration. For a full system calibration, the zero-scale point must be presented to the converter first. It must be applied to the converter before the calibration step is initiated, and remain stable until the step is complete. Once the system zero-scale voltage has been set up, a ZS system calibration is then initiated by writing the appropriate values (1, 0) to the MD1 and MD0 bits of the setup register. The zero-scale system calibration is performed at the selected gain. The duration of the calibration is 3 × 1/output rate. At this time, the MD1 and MD0 bits in the setup register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 4 × 1/output rate as the part performs a normal conversion on the analog input voltage before DRDY goes low. If DRDY is low before (or goes low during) the calibration command write to the Tetup Segister, it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the setup register in the calibration command. After the zero-scale point is calibrated, the full-scale point is applied to the analog input and the second step of the calibration process is initiated by again writing the appropriate values (1, 1) to MD1 and MD0. Again, the full-scale voltage must be set up before the calibration is initiated and it must remain stable throughout the calibration step. The full-scale system calibration is performed at the selected gain. The duration of the calibration is 3 × 1/output rate. At this time, the MD1 and Rev. B | Page 30 of 52 AD7707 Therefore, in determining the limits for system zero-scale and full-scale calibrations, the user must ensure that the offset range plus the span range does exceed 1.05 × VREF/gain. This is best illustrated with the following examples. If the part is used in unipolar mode with a required span of 0.8 × VREF/gain, the offset range the system calibration can handle is from −1.05 × VREF/gain to +0.25 × VREF/gain. If the part is used in unipolar mode with a required span of VREF/gain, the offset range the system calibration can handle is from −1.05 × VREF/gain to +0.05 × VREF/gain. Similarly, if the part is used in unipolar mode and required to remove an offset of 0.2 × VREF/gain, the span range the system calibration can handle is 0.85 × VREF/gain. 1.05 × VREF /GAIN In the unipolar mode, the system calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale (zero differential voltage) and positive full scale. SPAN AND OFFSET LIMITS ON THE LOW LEVEL INPUT CHANNELS, AIN1 AND AIN2 Whenever a system calibration mode is used, there are limits on the amount of offset and span that can be accommodated. The overriding requirement in determining the amount of offset and gain that can be accommodated by the part is the requirement that the positive full-scale calibration limit is