AD7714ARSZ-5

a APPLICATIONS Portable Industrial Instruments Portable Weigh Scales Loop-Powered Systems Pressure Transducers GENERAL DESCRIPTION† The AD7714 is a complete analog front end for low-frequency measurement applications. The device accepts low level signals directly from a transducer and outputs a serial digital word. It employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes performance. The input signal is applied to a proprietary programmable gain front end based around an analog modulator. The modulator output is processed by an onchip digital filter. The first notch of this digital filter can be programmed via the on-chip control register allowing adjustment of the filter cutoff and settling time. The part features three differential analog inputs (which can also be configured as five pseudo-differential analog inputs) as well as a differential reference input. It operates from a single supply (+3␣ V or +5␣ V). The AD7714 thus performs all signal conditioning and conversion for a system consisting of up to five channels. The AD7714 is ideal for use in smart, microcontroller- or DSPbased systems. It features a serial interface that can be configured †See page 39 for data sheet index. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM AVDD DVDD REF IN(–) REF IN(+) AVDD CHARGE BALANCING A/D CONVERTER 1mA AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 Σ -∆ MODULATOR SWITCHING MATRIX FEATURES Charge Balancing ADC 24 Bits No Missing Codes 0.0015% Nonlinearity Five-Channel Programmable Gain Front End Gains from 1 to 128 Can Be Configured as Three Fully Differential Inputs or Five Pseudo-Differential Inputs Three-Wire Serial Interface SPI™, QSPI™, MICROWIRE™ and DSP Compatible 3 V (AD7714-3) or 5 V (AD7714-5) Operation Low Noise (1GV VBIAS SWITCHING FREQUENCY DEPENDS ON fCLKIN AND SELECTED GAIN Figure 3. Unbuffered Analog Input Structure CSAMP must be charged through RSW and through any external source impedances every input sample cycle. Therefore, in unbuffered mode, source impedances mean a longer charge time for CSAMP and this may result in gain errors on the part. Table XII shows the allowable external resistance/capacitance values, for unbuffered mode, such that no gain error to the 16-bit level is introduced on the part. Table XIII shows the allowable external resistance/capacitance values, once again for unbuffered mode, such that no gain error to the 20-bit level is introduced. Table XII. External R, C Combination for No 16-Bit Gain Error (Unbuffered Mode Only) Gain 1 2 4 8–128 External Capacitance (pF) 0 50 100 500 1000 5000 368 kΩ 177.2 kΩ 82.8 kΩ 35.2 kΩ 90.6 kΩ 44.2 kΩ 21.2 kΩ 9.6 kΩ 54.2 kΩ 26.4 kΩ 12.6 kΩ 5.8 kΩ 14.6 kΩ 7.2 kΩ 3.4 kΩ 1.58 kΩ 8.2 kΩ 4 kΩ 1.94 kΩ 880 Ω 2.2 kΩ 1.12 kΩ 540 Ω 240 Ω Table XIII. External R, C Combination for No 20-Bit Gain Error (Unbuffered Mode Only) Gain 1 2 4 8–128 External Capacitance (pF) 0 50 100 500 1000 5000 290 kΩ 141 kΩ 63.6 kΩ 26.8 kΩ 69 kΩ 33.8 kΩ 16 kΩ 7.2 kΩ 40.8 kΩ 20 kΩ 9.6 kΩ 4.4 kΩ 10.4 kΩ 5 kΩ 2.4 kΩ 1.1 kΩ 5.6 kΩ 2.8 kΩ 1.34 kΩ 600 Ω 1.4 kΩ 700 Ω 340 Ω 160 Ω In buffered mode, the analog inputs look into the high impedance inputs stage of the on-chip buffer amplifier. CSAMP is charged via this buffer amplifier such that source impedances do not affect the charging of CSAMP. This buffer amplifier has an offset leakage current of 1␣ nA. In this buffered mode, large source impedances result in a dc offset voltage developed across the source impedance but not in a gain error. Input Sample Rate The modulator sample frequency for the AD7714 remains at fCLK␣ IN/128 (19.2␣ kHz @ fCLK IN = 2.4576␣ MHz) regardless of the selected gain. However, gains greater than 1 are achieved by a combination of multiple input samples per modulator cycle and a scaling of the ratio of reference capacitor to input capacitor. As a result of the multiple sampling, the input sample rate of the device varies with the selected gain (see Table XIV). In buffered mode, the input is buffered before the input sampling capacitor. In unbuffered mode, where the analog input looks directly into the sampling capacitor, the effective input impedance is 1/CSAMP × fS where CSAMP is the input sampling capacitance and fS is the input sample rate. –20– REV. C AD7714 Table XIV. Input Sampling Frequency vs. Gain Gain Input Sampling Freq (fS) 1 2 4 8 16 32 64 128 fCLK IN/64 (38.4␣ kHz @ f CLK IN = 2.4576␣ MHz) 2 × fCLK IN/64 (76.8␣ kHz @ f CLK IN = 2.4576␣ MHz) 4 × fCLK IN/64 (153.6␣ kHz @ fCLK IN = 2.4576␣ MHz) 8 × fCLK IN/64 (307.2␣ kHz @ fCLK IN = 2.4576␣ MHz) 8 × fCLK IN/64 (307.2␣ kHz @ fCLK IN = 2.4576␣ MHz) 8 × fCLK IN/64 (307.2␣ kHz @ fCLK IN = 2.4576␣ MHz) 8 × fCLK IN/64 (307.2␣ kHz @ fCLK IN = 2.4576␣ MHz) 8 × fCLK IN/64 (307.2␣ kHz @ fCLK IN = 2.4576␣ MHz) Burnout Current The AD7714 contains two 1␣ µA currents, one source current from AVDD to AIN(+) and one sink from AIN(–) to AGND. The currents are either both on or off depending on the BO bit of the Mode Register. These currents can be used in checking that a transducer has not burned out nor gone open-circuit before attempting to take measurements on that channel. If the currents are turned on, allowed flow in the transducer, a measurement of the input voltage on the analog input taken and the voltage measured is full scale, it indicates that the transducer has gone open-circuit; if the voltage measured is zero, it indicates that the transducer has gone short-circuit. For normal operation, these burnout currents are turned off by writing a 0 to the BO bit. For the source current to work correctly, the applied voltage on AIN(+) should not go within 500␣ mV of AVDD . For the sink current to work correctly, the applied voltage on the AIN(–) input should not go within 500␣ mV of AGND. Bipolar/Unipolar Inputs The analog inputs on the AD7714 can accept either unipolar or bipolar input voltage ranges. Bipolar input ranges do not imply that the part can handle negative voltages on its analog inputs, since the analog input cannot go more negative than –30␣ mV to ensure correct operation of the part. The input channels are either fully differential or pseudo-differential (all other channels referenced to AIN6). In either case, the input channels are arranged in pairs with an AIN(+) and AIN(–). As a result, the voltage to which the unipolar and bipolar signals on the AIN(+) input are referenced is the voltage on the respective AIN(–) input. For example, if AIN(–) is +2.5␣ V and the AD7714 is configured for unipolar operation with a gain of 2 and a VREF of +2.5␣ V, the input voltage range on the AIN(+) input is +2.5 V to +3.75␣ V. If AIN(–) is +2.5␣ V and the AD7714 is configured for bipolar mode with a gain of 2 and a VREF of +2.5␣ V, the analog input range on the AIN(+) input is +1.25␣ V to +3.75 V (i.e., 2.5␣ V ± 1.25␣ V). If AIN(–) is at AGND, the part cannot be configured for bipolar ranges in excess of ± 30␣ mV. Bipolar or unipolar options are chosen by programming the B/U bit of the Filter High Register. This programs the selected channel for either unipolar or bipolar operation. Programming the channel for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding and the points on the transfer function where calibrations occur. REFERENCE INPUT for the AD7714-3. The part is functional with VREF voltages down to 1 V but with degraded performance as the output noise will, in terms of LSB size, be larger. REF␣ IN(+) must always be greater than REF␣ IN(–) for correct operation of the AD7714. Both reference inputs provide a high impedance, dynamic load similar to the analog inputs in unbuffered mode. The maximum dc input leakage current is ± 1 nA over temperature and source resistance may result in gain errors on the part. In this case, the sampling switch resistance is 5␣ kΩ typ and the reference capacitor (CREF) varies with gain. The sample rate on the reference inputs is fCLK IN/64 and does not vary with gain. For gains of 1 to 8, CREF is 8 pF; for a gain of 16, it is 5.5 pF, for a gain of 32, it is 4.25 pF, for a gain of 64, it is 3.625 pF and for a gain of 128, it is 3.3125 pF. The output noise performance outlined in Tables I through IV is for an analog input of 0 V and is unaffected by noise on the reference. To obtain the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7714. If the reference noise in the bandwidth of interest is excessive, it will degrade the performance of the AD7714. In applications where the excitation voltage for the bridge transducer on the analog input also derives the reference voltage for the part, the effect of the noise in the excitation voltage will be removed as the application is ratiometric. Recommended reference voltage sources for the AD7714-5 and AD7714Y grade with AVDD = 5 V include the AD780, REF43 and REF192 while the recommended reference sources for the AD7714-3 and AD7714Y with AVDD = 3 V include the AD589 and AD1580. It is generally recommended to decouple the output of these references to further reduce the noise level. DIGITAL FILTERING The AD7714 contains an on-chip low-pass digital filter which processes the output of the part’s sigma-delta modulator. Therefore, the part not only provides the analog-to-digital conversion function but it also provides a level of filtering. There are a number of system differences when the filtering function is provided in the digital domain rather than the analog domain and the user should be aware of these. First, since digital filtering occurs after the A-to-D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. Also, the digital filter can be made programmable far more readily than an analog filter. Depending on the digital filter design, this gives the user the capability of programming cutoff frequency and output update rate. On the other hand, analog filtering can remove noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. To alleviate this problem, the AD7714 has overrange headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 5% above the analog input range. If noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. This will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%). The AD7714’s reference inputs, REF␣ IN(+) and REF␣ IN(–), provide a differential reference input capability. The commonmode range for these differential inputs is from AGND to AVDD. The nominal reference voltage, VREF (REF␣ IN(+)␣ –REF␣ IN(–)), for specified operation is +2.5␣ V for the AD7714-5 and +1.25␣ V REV. C –21– 2 AD7714 In addition, the digital filter does not provide any rejection at integer multiples of the digital filter’s sample frequency. However, the input sampling on the part provides attenuation at multiples of the digital filter’s sampling frequency so that the unattenuated bands actually occur around multiples of the input sampling frequency fS (as defined in Table XIV). Thus, the unattenuated bands occur at n × fS (where n = 1, 2, 3. . .). At these frequencies, there are frequency bands, ± f3 dB wide (f3 dB is the cutoff frequency of the digital filter) at either side where noise passes unattenuated to the output. Filter Characteristics     –3␣ dB frequency = 0.262 × filter first notch frequency The filter provides a linear phase response with a group delay determined by: 3 1 Sin ( N .π. f fS ) H( f ) = × N Sin ( π. f fS ) Group Delay = –3π.(N.f/fMOD ) where N is the decimal equivalent of the word loaded to the FS0 to FS11 bits of the Filter Registers and fMOD = fCLK IN/128. Since the AD7714 contains this on-chip, low-pass filtering, a settling time is associated with step function inputs and data on the output will be invalid after a step change until the settling time has elapsed. The settling time depends upon the output rate chosen for the filter. The settling time of the filter to a fullscale step input can be up to four times the output data period. For a synchronized step input (using the SYNC or FSYNC functions) the settling time is three times the output data period. When changing channels on the part, the change from one channel to the other is synchronized so the output settling time is also three times the output data period. Thus, in switching between channels, the output data register is not updated until the settling time of the filter has elapsed. 3 Figure 4 shows the filter frequency response for a cutoff frequency of 2.62␣ Hz which corresponds to a first filter notch frequency of 10␣ Hz. The plot is shown from dc to 65␣ Hz. This response is repeated at either side of the input sampling frequency and at either side of multiples of the input sampling frequency. 0 –20 –40 Post-Filtering –60 The on-chip modulator provides samples at a 19.2␣ kHz output rate with fCLK IN at 2.4576␣ MHz. The on-chip digital filter decimates these samples to provide data at an output rate that corresponds to the programmed output rate of the filter. Since the output data rate is higher than the Nyquist criterion, the output rate for a given bandwidth will satisfy most application requirements. However, there may be some applications that require a higher data rate for a given bandwidth and noise performance. Applications that need this higher data rate will require some post-filtering following the part’s digital filter. –80 GAIN – dB Output Rate = fCLK IN/(N.128) where N is the decimal equivalent of the word loaded to the FS0 to FS11 bits of the Filter Registers while the –3␣ dB frequency is determined by the relationship: The AD7714’s digital filter is a low-pass filter with a (sinx/x)3 response (also called sinc3). The transfer function for this filter is described in the z-domain by:  1 1 − Z −N H(z) =  ×  N 1 − Z −1  and in the frequency domain by: The cutoff frequency of the digital filter is determined by the value loaded to bits FS0 to FS11 in the Filter High and Filter Low Registers. Programming a different cutoff frequency via FS0 – FS11 does not alter the profile of the filter response; it changes the frequency of the notches as outlined in the Filter Registers section. The output update and first notch correspond and are determined by the relationship: –100 –120 –140 –160 –180 –200 –220 –240 0 10 20 30 40 FREQUENCY – Hz 50 60 Figure 4. Frequency Response of AD7714 Filter The response of the filter is similar to that of an averaging filter but with a sharper roll-off. The output rate for the digital filter corresponds with the positioning of the first notch of the filter’s frequency response. Thus, for the plot of Figure 4 where the output rate is 10␣ Hz, the first notch of the filter is at 10␣ Hz. The notches of this (sinx/x)3 filter are repeated at multiples of the first notch. The filter provides attenuation of better than 100 dB at these notches. For the example given, if the first notch is at 10␣ Hz, there will be notches (and hence >100␣ dB rejection) at both 50␣ Hz and 60␣ Hz. For example, if the required bandwidth is 7.86␣ Hz but the required update rate is 100␣ Hz, the data can be taken from the AD7714 at the 100␣ Hz rate giving a –3 dB bandwidth of 26.2␣ Hz. Post-filtering can be applied to this to reduce the bandwidth and output noise, to the 7.86␣ Hz bandwidth level, while maintaining an output rate of 100␣ Hz. Post-filtering can also be used to reduce the output noise from the device for bandwidths below 1.26␣ Hz. At a gain of 128 and a bandwidth of 1.26␣ Hz, the output rms noise is 140␣ nV. This is essentially device noise or white noise and since the input is chopped, the noise has a primarily flat frequency response. By reducing the bandwidth below 1.26␣ Hz, the noise in the resultant passband can be reduced. A reduction in bandwidth by a factor of 2 results in a reduction of approximately 1.25 in the output rms noise. This additional filtering will result in a longer settling time. –22– REV. C AD7714 ANALOG FILTERING The digital filter does not provide any rejection at integer multiples of the input sampling frequency, as outlined earlier. However, due to the AD7714’s high oversampling ratio, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. This means that the analog filtering requirements in front of the AD7714 are considerably reduced versus a conventional converter with no on-chip filtering. In addition, because the part’s common-mode rejection performance of 100␣ dB extends out to several kHz, common-mode noise in this frequency range will be substantially reduced. Depending on the application, however, it may be necessary to provide attenuation prior to the AD7714 in order to eliminate unwanted frequencies from these bands which the digital filter will pass. It may also be necessary in some applications to provide analog filtering in front of the AD7714 to ensure that differential noise signals outside the band of interest do not saturate the analog modulator. If passive components are placed in front of the AD7714, in unbuffered mode, care must be taken to ensure that the source impedance is low enough so as not to introduce gain errors in the system. This significantly limits the amount of passive antialiasing filtering which can be provided in front of the AD7714 when it is used in unbuffered mode. However, when the part is used in buffered mode, large source impedances will simply result in a small dc offset error (a 10␣ kΩ source resistance will cause an offset error of less than 10␣ µV). Therefore, if the system requires any significant source impedances to provide passive analog filtering in front of the AD7714, it is recommended that the part be operated in buffered mode. value which, when normalized, is subtracted from all conversion results. The full-scale calibration register contains a value which, when normalized, is multiplied by all conversion results. The offset calibration coefficient is subtracted from the result prior to the multiplication by the full-scale coefficient. This means that the full-scale coefficient is effectively a span or gain coefficient. The AD7714 offers self-calibration, system calibration and background calibration facilities. For full calibration to occur on the selected channel, the on-chip microcontroller must record the modulator output for two different input conditions. These are “zero-scale” and “full-scale” points. These points are derived by performing a conversion on the different input voltages provided to the input of the modulator during calibration. As a result, the accuracy of the calibration can only be as good as the noise level which the part provides in normal mode. The result of the “zero-scale” calibration conversion is stored in the Zero Scale Calibration Register for the appropriate channel. The result of the “full-scale” calibration conversion is stored in the Full-Scale Calibration Register for the appropriate channel. With these readings, the microcontroller can calculate the offset and the gain slope for the input to output transfer function of the converter. Internally, the part works with 33 bits of resolution to determine its conversion result of either 16 bits or 24 bits. Self-Calibration CALIBRATION The AD7714 provides a number of calibration options which can be programmed via the MD2, MD1 and MD0 bits of the Mode Register. The different calibration options are outlined in the Mode Register and Calibration Sequences sections. A calibration cycle may be initiated at any time by writing to these bits of the Mode Register. Calibration on the AD7714 removes offset and gain errors from the device. A calibration routine should be initiated on the device whenever there is a change in the ambient operating temperature or supply voltage. It should also be initiated if there is a change in the selected gain, filter notch or bipolar/unipolar input range. A self-calibration is initiated on the AD7714 by writing the appropriate values (0, 0, 1) to the MD2, MD1 and MD0 bits of the Mode Register. In the self-calibration mode with a unipolar input range, the zero-scale point used in determining the calibration coefficients is with the inputs of the differential pair internally shorted on the part (i.e., AIN(+) = AIN(–) = Internal Bias Voltage). The PGA is set for the selected gain (as per G2, G1, G0 bits in the Mode Register) for this zero-scale calibration conversion. The full-scale calibration conversion is performed at the selected gain on an internally-generated voltage of VREF/ Selected Gain. The AD7714 gives the user access to the on-chip calibration registers allowing the microprocessor to read the device’s calibration coefficients and also to write its own calibration coefficients to the part from prestored values in E2PROM. This gives the microprocessor much greater control over the AD7714’s calibration procedure. It also means that the user can verify that the device has performed its calibration correctly by comparing the coefficients after calibration with prestored values in E2PROM. The values in these calibration registers are 24-bit wide. In addition, the span and offset for the part can be adjusted by the user. The duration time of the calibration is 6 × 1/Output Rate. This is made up of 3 × 1/Output Rate for the zero-scale calibration and 3 × 1/Output Rate for the full-scale calibration. At this time the MD2, MD1 and MD0 bits in the Mode Register return to 0, 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 9 × 1/ Output Rate. This is made up of 3 × 1/Output Rate for the zeroscale calibration, 3 × 1/Output Rate for the full-scale calibration and 3 × 1/Output Rate for a conversion on the analog input. If DRDY is low before (or goes low during) the calibration command write to the Mode Register, it may take up to one modulator cycle (MCLK␣ IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the Mode Register. There is a significant variation in the value of these coefficients across the different output update rates, gains and unipolar/ bipolar operation. Internally in the AD7714, these coefficients are normalized before being used to scale the words coming out of the digital filter. The offset calibration register contains a For bipolar input ranges in the self-calibrating mode, the sequence is very similar to that just outlined. In this case, the two points are exactly the same as above but since the part is configured for bipolar operation, the output code for zero differential input is 800000 Hex in 24-bit mode. REV. C –23– 2 AD7714 The part also offers ZS Self-Calibration and FS Self-Calibration options. In these cases, the part performs just a zero-scale or full-scale calibration respectively and not a full calibration of the part. A full-scale calibration should not be carried out unless the part contains valid zero-scale coefficients. These calibrations are initiated on the AD7714 by writing the appropriate values (1, 1, 0 for ZS Self-Calibration and 1, 1, 1 for FS Self Calibration) to the MD2, MD1 and MD0 bits of the Mode Register. The zero-scale or full-scale calibration is exactly the same as that described for the full self-calibration. In these cases, the duration of the calibration is 3 × 1/Output Rate. At this time the MD2, MD1 and MD0 bits in the Mode Register return to 0, 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The time from the calibration command being issued to DRDY going low is 6 × 1/Output Rate. This is made up of 3 × 1/Output Rate for the zero-scale or full-scale calibration and 3 × 1/Output Rate for a conversion on the analog input. If DRDY is low before (or goes low during) the calibration command write to the Mode Register, it may take up to one modulator cycle (MCLK␣ IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the Mode Register. The fact that the self-calibration can be performed as a two step calibration offers another feature. After the sequence of a full self calibration has been completed, additional offset or gain calibrations can be performed by themselves to adjust the part’s zero point or gain. Calibrating one of the parameters, either offset or gain, will not affect the other parameter. System Calibration System calibration allows the AD7714 to compensate for system gain and offset errors as well as its own internal errors. System calibration performs the same slope factor calculations as selfcalibration but uses voltage values presented by the system to the AIN inputs for the zero- and full-scale points. Full System calibration requires a two-step process, a ZS System Calibration followed by a FS System Calibration. For a full system calibration, the zero-scale point must be presented to the converter first. It must be applied to the converter before the calibration step is initiated and remain stable until the step is complete. Once the system zero scale has been set up at the analog input, a ZS System Calibration is then initiated by writing the appropriate values (0, 1, 0) to the MD2, MD1 and MD0 bits of the Mode Register. The zero-scale system calibration is performed at the selected gain. The duration of the calibration is 3 × 1/Output Rate. At this time, the MD2, MD1 and MD0 bits in the Mode Register return to 0, 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The time from the calibration command being issued to DRDY going low is 4 × 1/Output Rate. This is made up of 3 × 1/Output Rate for the zero-scale system calibration and 1/Output Rate for a conversion on the analog input. This conversion on the analog input is on the same voltage as the zero-scale system calibration and, therefore, the resultant word in the data register from this conversion should be a zero-scale reading. If DRDY is low before (or goes low during) the calibration command write to the Mode Register, it may take up to one modulator cycle (MCLK␣ IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the Mode Register. After the zero-scale point is calibrated, the full-scale point is applied to AIN and the second step of the calibration process is initiated by again writing the appropriate values (0, 1, 1) to MD2, MD1 and MD0. Again the full-scale voltage must be set up before the calibration is initiated, and it must remain stable throughout the calibration step. The full-scale system calibration is performed at the selected gain. The duration of the calibration is 3 × 1/Output Rate. At this time, the MD2, MD1 and MD0 bits in the Mode Register return to 0, 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The time from the calibration command being issued to DRDY going low is 4 × 1/Output Rate. This is made up of 3 × 1/Output Rate for the full-scale system calibration and 1/Output Rate for a conversion on the analog input. This conversion on the analog input is on the same voltage as the full-scale system calibration and, therefore, the resultant word in the data register from this conversion should be a full-scale reading. If DRDY is low before (or goes low during) the calibration command write to the Mode Register, it may take up to one modulator cycle (MCLK␣ IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the Mode Register. In the unipolar mode, the system calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale (zero differential voltage) and positive full scale. The fact that the system calibration is a two step calibration offers another feature. After the sequence of a full system calibration has been completed, additional offset or gain calibrations can be performed by themselves to adjust the system zero reference point or the system gain. Calibrating one of the parameters, either system offset or system gain, will not affect the other parameter. A full-scale calibration should not be carried out unless the part contains valid zero-scale coefficients. System calibration can also be used to remove any errors from source impedances on the analog input when the part is used in unbuffered mode. A simple R, C antialiasing filter on the front end may introduce a gain error on the analog input voltage but the system calibration can be used to remove this error. –24– REV. C AD7714 System-Offset Calibration System-offset calibration is a variation of both the system calibration and self-calibration. In this case, the zero-scale point is determined in exactly the same way as a ZS System Calibration. The system zero-scale point is presented to the AIN inputs of the converter. This must be applied to the converter before the calibration step is initiated and remain stable until the step is complete. Once the system zero scale has been set up, a System-Offset Calibration is then initiated by writing the appropriate values (1, 0, 0) to the MD2, MD1 and MD0 bits of the Mode Register. The zero-scale system calibration is performed at the selected gain. The full-scale calibration is performed in exactly the same way as an FS Self Calibration. The full-scale calibration conversion is performed at the selected gain on an internally generated voltage of VREF/Selected Gain. This is a one step calibration sequence and the time for calibration is 6 × 1/Output Rate. At this time, the MD2, MD1 and MD0 bits in the Mode Register return to 0, 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 9 × 1/ Output Rate. This is made up of 3 × 1/Output Rate for the zeroscale system calibration, 3 × 1/Output Rate for the full-scale self-calibration and 3 × 1/Output Rate for a conversion on the analog input. This conversion on the analog input is on the same voltage as the zero-scale system calibration and, therefore, the resultant word in the data register from this conversion should be a zero-scale reading. If DRDY is low before (or goes low during) the calibration command write to the Mode Register, it may take up to one modulator cycle (MCLK␣ IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the Mode Register. In the unipolar mode, the system-offset calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale and positive full scale. Background Calibration The AD7714 also offers a background calibration mode where the part interleaves its calibration procedure with its normal conversion sequence. In the background calibration mode, the part provides continuous zero-scale self-calibrations; it does not provide any full-scale calibrations. The zero-scale point used in determining the calibration coefficients in this mode is exactly the same as for a ZS Self-Calibration. The background calibration mode is invoked by writing 1, 0, 1 to the MD2, MD1, MD0 bits of the Mode Register. When invoked, the background calibration mode performs a zero-scale self calibration after every output update and this reduces the output data rate of the AD7714 by a factor of six. Its advantage is that the part is continually performing offset calibrations and automatically updating its zero-scale calibration coefficients. As a result, the effects of temperature drift, supply sensitivity and time drift on zero-scale errors are automatically removed. When the background calibration mode is turned on, the part will remain in this mode until bits MD2, MD1 and MD0 of the Mode Register are changed. REV. C Because the background calibration does not perform full-scale calibrations, a self-calibration should be performed before placing the part in background calibration mode. Removal of the offset drift in this mode leaves gain drift as the only source of error not removed from the part. The typical gain drift of the AD7714 with temperature is 0.2␣ ppm/°C. The SYNC input or FSYNC bit should not be exercised when the part is in background calibration mode. Span and Offset Limits Whenever a system calibration mode is used, there are limits on the amount of offset and span which can be accommodated. The overriding requirement in determining the amount of offset and gain which can be accommodated by the part is the requirement that the positive full-scale calibration limit is ≤ 1.05 × VREF/GAIN. This allows the input range to go 5% above the nominal range. The built-in headroom in the AD7714’s analog modulator ensures that the part will still operate correctly with a positive full-scale voltage which is 5% beyond the nominal. The range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 × VREF/GAIN and a maximum value of 2.1 × VREF/GAIN. However, the span (which is the difference between the bottom of the AD7714’s input range and the top of its input range) has to take into account the limitation on the positive full-scale voltage. The amount of offset which can be accommodated depends on whether the unipolar or bipolar mode is being used. Once again, the offset has to take into account the limitation on the positive full-scale voltage. In unipolar mode, there is considerable flexibility in handling negative (with respect to AIN(–)) offsets. In both unipolar and bipolar modes, the range of positive offsets which can be handled by the part depends on the selected span. Therefore, in determining the limits for system zero-scale and full-scale calibrations, the user has to ensure that the offset range plus the span range does exceed 1.05 × VREF/GAIN. This is best illustrated by looking at a few examples. If the part is used in unipolar mode with a required span of 0.8 × VREF/GAIN, the offset range the system calibration can handle is from –1.05 × VREF/GAIN to +0.25 × VREF/GAIN. If the part is used in unipolar mode with a required span of VREF/ GAIN, the offset range the system calibration can handle is from –1.05 × VREF/GAIN to +0.05 × VREF/GAIN. Similarly, if the part is used in unipolar mode and required to remove an offset of 0.2 × VREF/GAIN, the span range the system calibration can handle is 0.85 × VREF/GAIN. If the part is used in bipolar mode with a required span of ± 0.4 × VREF/GAIN, then the offset range which the system calibration can handle is from –0.65 × VREF /GAIN to +0.65 × VREF/GAIN. If the part is used in bipolar mode with a required span of ± VREF/GAIN, the offset range the system calibration can handle is from –0.05 × VREF/GAIN to +0.05 × VREF/GAIN. Similarly, if the part is used in bipolar mode and required to remove an offset of ± 0.2 × VREF/GAIN, the span range the system calibration can handle is ± 0.85 × VREF/GAIN. –25– 2 AD7714 Power-Up and Calibration On power-up, the AD7714 performs an internal reset which sets the contents of the internal registers to a known state. There are default values loaded to all registers after a power-on or reset. The default values contain nominal calibration coefficients for the calibration registers. However, to ensure correct calibration for the device a calibration routine should be performed after power-up. The power dissipation and temperature drift of the AD7714 are low and no warm-up time is required before the initial calibration is performed. However, if an external reference is being used, this reference must have stabilized before calibration is initiated. Similarly, if the clock source for the part is generated from a crystal or resonator across the MCLK pins, the start-up time for the oscillator circuit should elapse before a calibration is initiated on the part (see below). USING THE AD7714 Clocking and Oscillator Circuit The AD7714 requires a master clock input, which may be an external CMOS compatible clock signal applied to the MCLK␣ IN pin with the MCLK␣ OUT pin left unconnected. Alternatively, a crystal or ceramic resonator of the correct frequency can be connected between MCLK␣ IN and MCLK␣ OUT in which case the clock circuit will function as an oscillator, providing the clock source for the part. The input sampling frequency, the modulator sampling frequency, the –3␣ dB frequency, output update rate and calibration time are all directly related to the master clock frequency, fCLK␣ IN. Reducing the master clock frequency by a factor of 2 will halve the above frequencies and update rate and double the calibration time. The current drawn from the DVDD power supply is also directly related to fCLK␣ IN. Reducing fCLK␣ IN by a factor of 2 will halve the DVDD current but will not affect the current drawn from the AVDD power supply. Using the part with a crystal or ceramic resonator between the MCLK IN and MCLK OUT pins generally causes more current to be drawn from DVDD than when the part is clocked from a driven clock signal at the MCLK IN pin. This is because the on-chip oscillator circuit is active in the case of the crystal or ceramic resonator. Therefore, the lowest possible current on the AD7714 is achieved with an externally applied clock at the MCLK IN pin with MCLK OUT unconnected and unloaded. When operating with a clock frequency of 2.4576␣ MHz, there is no appreciable difference in the DVDD current between an externally applied clock and a crystal resonator when operating with a DVDD of +3␣ V. With DVDD = +5␣ V and fCLK IN = 2.4576␣ MHz, the typical DVDD current increases by 50␣ µA for a crystal/resonator supplied clock versus an externally applied clock. The ESR values for crystals and resonators at this frequency tend to be low and as a result there tends to be little difference between different crystal and resonator types. When operating with a clock frequency of 1␣ MHz, the ESR value for different crystal types varies significantly. As a result, the DVDD current drain varies across crystal types. When using a crystal with an ESR of 700␣ Ω or when using a ceramic resonator, the increase in the typical DVDD current over an externallyapplied clock is 50␣ µA with DVDD = +3␣ V and 175␣ µA with DVDD = +5␣ V. When using a crystal with an ESR of 3␣ kΩ, the increase in the typical DVDD current over an externally applied clock is again 50␣ µA with DVDD = +3␣ V but 300␣ µA with DVDD = +5␣ V. The on-chip oscillator circuit also has a start-up time associated with it before it is oscillating at its correct frequency and correct voltage levels. The typical start up time for the circuit is 10␣ ms with a DVDD of +5␣ V and 15␣ ms with a DVDD of +3␣ V. At 3␣ V supplies, depending on the loading capacitances on the MCLK pins, a 1␣ MΩ feedback resistor may be required across the crystal or resonator in order to keep the start up times around the 15␣ ms duration. The AD7714’s master clock appears on the MCLK OUT pin of the device. The maximum recommended load on this pin is one CMOS load. When using a crystal or ceramic resonator to generate the AD7714’s clock, it may be desirable to then use this clock as the clock source for the system. In this case, it is recommended that the MCLK OUT signal is buffered with a CMOS buffer before being applied to the rest of the circuit. System Synchronization The SYNC input (or FSYNC bit) allows the user to reset the modulator and digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a known point in time, i.e., the rising edge of SYNC or when a 1 is written to FSYNC. The amount of additional current taken by the oscillator depends on a number of factors—first, the larger the value of capacitor placed on the MCLK␣ IN and MCLK␣ OUT pins, then the larger the DVDD current consumption on the AD7714. Care should be taken not to exceed the capacitor values recommended by the crystal and ceramic resonator manufacturers to avoid consuming unnecessary DVDD current. Typical values recommended by crystal or ceramic resonator manufacturers are in the range of 30␣ pF to 50␣ pF and if the capacitor values on MCLK IN and MCLK OUT are kept in this range they will not result in any excessive DVDD current. Another factor that influences the DVDD current is the effective series resistance (ESR) of the crystal which appears between the MCLK IN and MCLK OUT pins of the AD7714. As a general rule, the lower the ESR value then the lower the current taken by the oscillator circuit. The SYNC input can also be used to allow two other functions. If multiple AD7714s are operated from a common master clock, they can be synchronized to update their output registers simultaneously. A falling edge on the SYNC input (or a 1 written to the FSYNC bit of the Mode Register) resets the digital filter and analog modulator and places the AD7714 into a consistent, known state. While the SYNC input is low (or FSYNC high), the AD7714 will be maintained in this state. On the rising edge of SYNC (or when a 0 is written to the FSYNC bit), the modulator and filter are taken out of this reset state and on the next clock edge the part starts to gather input samples again. In a system using multiple AD7714s, a common signal to their SYNC inputs will synchronize their operation. This would normally be done after each AD7714 has performed its own calibration or has had calibration coefficients loaded to it. The output updates will then be synchronized with the maximum possible difference between the output updates of the individual AD7714s being one MCLK IN cycle. –26– REV. C AD7714 The SYNC input can also be used as a start convert command allowing the AD7714 to be operated in a conventional converter fashion. In this mode, the rising edge of SYNC starts conversion and the falling edge of DRDY indicates when conversion is complete. The disadvantage of this scheme is that the settling time of the filter has to be taken into account for every data register update. This means that the rate at which the data register is updated at a three times slower rate in this mode. Since the SYNC input (or FSYNC bit) resets the digital filter, the full settling-time of 3 × 1/Output Rate has to elapse before there is a new word loaded to the output register on the part. If the DRDY signal is low when SYNC returns high (or FSYNC goes to a 0), the DRDY signal will not be reset high by the SYNC (or FSYNC) command. This is because the AD7714 recognizes that there is a word in the data register which has not been read. The DRDY line will stay low until an update of the data register takes place at which time it will go high for 500 × tCLK IN before returning low again. A read from the data register resets the DRDY signal high and it will not return low until the settling time of the filter has elapsed (from the SYNC or FSYNC command) and there is a valid new word in the data register. If the DRDY line is high when the SYNC (or FSYNC) command is issued, the DRDY line will not return low until the settling time of the filter has elapsed. Reset Input The RESET input on the AD7714 resets all the logic, the digital filter and the analog modulator while all on-chip registers are reset to their default state. DRDY is driven high and the AD7714 ignores all communications to any of its registers while the RESET input is low. When the RESET input returns high, the AD7714 starts to process data and DRDY will return low in 3 × 1/Output Rate indicating a valid new word in the data register. However, the AD7714 operates with its default setup conditions after a RESET and it is generally necessary to set up all registers and carry out a calibration after a RESET command. The AD7714’s on-chip oscillator circuit continues to function even when the RESET input is low. The master clock signal continues to be available on the MCLK OUT pin. Therefore, in applications where the system clock is provided by the AD7714’s clock, the AD7714 produces an uninterrupted master clock during RESET commands. Standby Mode The STANDBY input on the AD7714 allows the user to place the part in a power-down mode when it is not required to provide conversion results The AD7714 retains the contents of all its on-chip registers (including the data register) while in standby mode. When in standby mode, the digital interface is reset and DRDY is reset to a Logic 1. Data cannot be accessed from the part while in standby mode. When released from standby mode, the part starts to process data and a new word is available in the data register in 3 × 1/Output rate from when the STANDBY input goes high. Placing the part in standby mode reduces the total current to 5␣ µA typical when the part is operated from an external master clock, provided this master clock is stopped. If the external clock continues to run in standby mode, the standby current increases to 150␣ µA typical with 5 V supplies and 75 µA typical with 3.3 V supplies. If a crystal or ceramic resonator is used as REV. C the clock source, the total current in standby mode is 400␣ µA typical with 5 V supplies and 90 µA with 3.3 V supplies. This is because the on-chip oscillator circuit continues to run when the part is in its standby mode. This is important in applications where the system clock is provided by the AD7714’s clock, so that the AD7714 produces an uninterrupted master clock even when it is in its standby mode. Accuracy Sigma-Delta ADCs, like VFCs and other integrating ADCs, do not contain any source of nonmonotonicity and inherently offer no missing codes performance. The AD7714 achieves excellent linearity by the use of high quality, on-chip capacitors, which have a very low capacitance/voltage coefficient. The device also achieves low input drift through the use of chopper-stabilized techniques in its input stage. To ensure excellent performance over time and temperature, the AD7714 uses digital calibration techniques that minimize offset and gain error. Drift Considerations The AD7714 uses chopper stabilization techniques to minimize input offset drift. Charge injection in the analog switches and dc leakage currents at the sampling node are the primary sources of offset voltage drift in the converter. The dc input leakage current is essentially independent of the selected gain. Gain drift within the converter depends primarily upon the temperature tracking of the internal capacitors. It is not affected by leakage currents. Measurement errors due to offset drift or gain drift can be eliminated at any time by recalibrating the converter or by operating the part in the background calibration mode. Using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. Integral and differential linearity errors are not significantly affected by temperature changes. POWER SUPPLIES No specific power sequence is required for the AD7714; either the AVDD or the DVDD supply can come up first. While the latch-up performance of the AD7714 is good, it is important that power is applied to the AD7714 before signals at REF␣ IN, AIN or the logic input pins in order to avoid latch-up. If this is not possible, then the current which flows in any of these pins should be limited. If separate supplies are used for the AD7714 and the system digital circuitry, then the AD7714 should be powered up first. If it is not possible to guarantee this, then current limiting resistors should be placed in series with the logic inputs to again limit the current. Supply Current The current consumption on the AD7714 is specified for supplies in the range +3␣ V to +3.6␣ V and in the range +4.75␣ V to +5.25␣ V. The part operates over a +2.85␣ V to +5.25␣ V supply range and the IDD for the part varies as the supply voltage varies over this range. Figure 5 shows the variation of the typical IDD with VDD voltage for both a 1 MHz external clock and a 2.4576 MHz external clock at +25°C. The AD7714 is operated in unbuffered mode and the internal boost bit on the part is turned off. The relationship shows that the IDD is minimized by operating the part with lower VDD voltages. IDD on the AD7714 is also minimized by using an external master clock or by optimizing external components when using the on-chip oscillator circuit. The Y grade part is specified from 2.7 V to 3.3 V and 4.75 V to 5.25 V. –27– 2 AD7714 noise to other sections of the board and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. SUPPLY CURRENT (AVDD & DVDD) – mA 1.0 0.9 0.8 MCLK IN = 2.4576MHz 0.7 0.6 0.5 MCLK IN = 1MHz 0.4 0.3 0.2 0.1 0 2.85 3.15 3.45 3.75 4.05 4.35 4.65 4.95 SUPPLY VOLTAGE (AVDD & DVDD) – Volts 5.25 Figure 5. IDD vs. Supply Voltage Grounding and Layout Since the analog inputs and reference input are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent Common-Mode Rejection of the part will remove common-mode noise on these inputs. The analog and digital supplies to the AD7714 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs provided those noise sources do not saturate the analog modulator. As a result, the AD7714 is more immune to noise interference that a conventional high resolution converter. However, because the resolution of the AD7714 is so high and the noise levels from the AD7714 so low, care must be taken with regard to grounding and layout. The printed circuit board which houses the AD7714 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes which can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD7714 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD7714. If the AD7714 is in a system where multiple devices require AGND to DGND connections, the connection should still be made at one point only, a star ground point which should be established as close as possible to the AD7714. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7714 to avoid noise coupling. The power supply lines to the AD7714 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating Good decoupling is important when using high resolution ADCs. All analog supplies should be decoupled with 10␣ µF tantalum in parallel with 0.1␣ µF capacitors to AGND. To achieve the best from these decoupling components, they have to be placed as close as possible to the device, ideally right up against the device. All logic chips should be decoupled with 0.1␣ µF disc ceramic capacitors to DGND. In systems where a common supply voltage is used to drive both the AVDD and DVDD of the AD7714, it is recommended that the system’s AVDD supply is used. This supply should have the recommended analog supply decoupling capacitors between the AVDD pin of the AD7714 and AGND and the recommended digital supply decoupling capacitor between the DVDD pin of the AD7714 and DGND. Evaluating the AD7714 Performance The recommended layout for the AD7714 is outlined in the evaluation board for the AD7714. The evaluation board package includes a fully assembled and tested evaluation board, documentation, software for controlling the board over the printer port of a PC and software for analyzing the AD7714’s performance on the PC. For the AD7714-5, the evaluation board order number is EVAL-AD7714-5EB and for the AD7714-3, the order number is EVAL-AD7714-3EB. Noise levels in the signals applied to the AD7714 may also affect performance of the part. The AD7714 allows two techniques for evaluating the true performance of the part, independent of the analog input signal. These schemes should be used after a calibration has been performed on the part. The first of these is to select the AIN6/AIN6 input channel arrangement. In this case, the differential inputs to the AD7714 are internally shorted together to provide a zero differential voltage for the analog modulator. External to the device, the AIN6 input should be connected to a voltage that is within the allowable common-mode range of the part. The second scheme is to evaluate the part with a voltage near the input full scale voltage for a gain of 1. To do this, the reference voltage for the part should be applied to the analog input. This will give a fixed full-scale reading from the device. If the zero-scale calibration coefficient is now read from the device, increased by a number equivalent to about 200 decimal and this value reloaded to the zero-scale calibration register, the input range will be offset such that a voltage equal to reference voltage no longer corresponds to a full-scale reading. This allows the user to evaluate the noise performance of the part with a near full-scale voltage. –28– REV. C AD7714 DIGITAL INTERFACE The AD7714’s programmable functions are controlled using a set of on-chip registers as previously outlined. Data is written to these registers via the part’s serial interface, and read access to the on-chip registers is also provided by this interface. All communications to the part must start with a write operation to the Communications Register. After power-on or RESET, the device expects a write to its Communications Register. The data written to this register determines whether the next operation to the part is a read or a write operation and also determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the Communications Register followed by a write to the selected register. A read operation from any register on the part (including the output data register) starts with a write operation to the Communications Register followed by a read operation from the selected register. The AD7714’s serial interface consists of five signals, CS, SCLK, DIN, DOUT and DRDY. The DIN line is used for transferring data into the on-chip registers while the DOUT line is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device and all data transfers (either on DIN or DOUT) take place with respect to this SCLK signal. The DRDY line is used as a status signal to indicate when data is ready to be read from the AD7714’s data register. DRDY goes low when a new data word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. CS is used to select the device. It can be used to decode the AD7714 in systems where a number of parts are connected to the serial bus. The AD7714 serial interface can operate in three-wire mode by tying the CS input low. In this case, the SCLK, DIN and DOUT lines are used to communicate with the AD7714 and the status of DRDY can be obtained by interrogating the MSB of the Communications Register. Figures 6 and 7 show timing diagrams for interfacing to the AD7714 with CS used to decode the part. Figure 6 is for a read operation from the AD7714’s output shift register, while Figure 7 shows a write operation to the input shift register. Both diagrams are for the POL input at a logic high; for operation with the POL input at a logic low simply invert the SCLK waveform shown in the diagrams. It is possible to read the same data twice from the output register even though the DRDY line returns high after the first read operation. Care must be taken, however, to ensure that the read operations have been completed before the next output update is about to take place. The serial interface can be reset by exercising the RESET input on the part. It can also be reset by writing a series of 1s on the DIN input. If a logic 1 is written to the AD7714 DIN line for at least 32 serial clock cycles the serial interface is reset. This ensures in three-wire systems that if the interface gets lost, either via a software error or by some glitch in the system, it can be reset back into a known state. This state returns the interface to where the AD7714 is expecting a write operation to the Communications Register. This operation does not in itself reset the contents of any registers but since the interface was lost, the information that was written to any of the registers is unknown and it is advisable to set up all registers again. DRDY t10 t3 CS t4 t8 t6 SCLK t7 t5 DOUT t9 MSB LSB Figure 6. Read Cycle Timing Diagram (POL = 1) CS t11 t16 t14 SCLK t15 t12 t13 DIN MSB LSB Figure 7. Write Cycle Timing Diagram (POL = 1) REV. C –29– 2 AD7714 CONFIGURING THE AD7714 The AD7714 contains eight on-chip registers that can be accessed via the serial interface. Communication with any of these registers is initiated by writing to the Communications Register first. Figure 8 outlines a flow diagram of the sequence which is used to configure all registers after a power-up or reset. The flowchart also shows two different read options—the first where the DRDY pin is polled to determine when an update of the data register has taken place, the second where the DRDY bit of the Communications Register is interrogated to see if a data register update has taken place. Also included in the flowing diagram is a series of words which should be written to the registers for a particular set of operating conditions. These conditions are test channel (AIN6/AIN6), gain of 1, burnout current off, no filter sync, bipolar mode, 24-bit word length, boost off and maximum filter word (4000 decimal). START POWER-ON/RESET FOR AD7714 CONFIGURE & INITIALIZE µC/µP SERIAL PORT WRITE TO COMMUNICATIONS REGISTER SETTING UP CHANNEL & SETTING UP NEXT OPERATION TO BE A WRITE TO THE FILTER HIGH REGISTER (27 HEX) WRITE TO FILTER HIGH REGISTER SETTING UP REQUIRED VALUES (4F HEX) WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME CHANNEL & SETTING UP NEXT OPERATION TO BE A WRITE TO THE FILTER LOW REGISTER (37 HEX) WRITE TO FILTER LOW REGISTER SETTING UP REQUIRED VALUES (A0 HEX) WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME CHANNEL & SETTING UP NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER (17 HEX) WRITE TO MODE REGISTER SETTING UP REQUIRED VALUES & INITIATING A CALIBRATION (20 HEX) POLL DRDY PIN POLL DRDY BIT OF COMMUNICATIONS REGISTER NO DRDY LOW? WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME CHANNEL & SETTING UP NEXT OPERATION TO BE A READ FROM THE COMMUNICATIONS REGISTER (0F HEX) YES WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME CHANNEL & SETTING UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (5F HEX) READ FROM COMMUNICATIONS REGISTER READ FROM DATA REGISTER NO DRDY LOW? YES WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME CHANNEL & SETTING UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (5F HEX) READ FROM DATA REGISTER Figure 8. Flowchart for Setting Up and Reading from the AD7714 –30– REV. C AD7714 MICROCOMPUTER/MICROPROCESSOR INTERFACING The AD7714’s flexible serial interface allows for easy interface to most microcomputers and microprocessors. The flowchart of Figure 8 outlines the sequence which should be followed when interfacing a microcontroller or microprocessor to the AD7714. Figures 9, 10 and 11 show some typical interface circuits. The serial interface on the AD7714 has the capability of operating from just three wires and is compatible with SPI interface protocols. The three-wire operation makes the part ideal for isolated systems where minimizing the number of interface lines minimizes the number of opto-isolators required in the system. The rise and fall times of the digital inputs to the AD7714 (especially the SCLK input) should be no longer than 1␣ µs. The 68HC11 is configured in the master mode with its CPOL bit set to a logic zero and its CPHA bit set to a logic one. When the 68HC11 is configured like this, its SCLK line idles low between data transfers. Therefore, the POL input of the AD7714 should be hard-wired low. For systems where it is preferable that the SCLK idle high, the CPOL bit of the 68HC11 should be set to a logic 1 and the POL input of the AD7714 should be hard-wired to a logic high. DVDD SS AD7714 to 68HC11 Interface Figure 9 shows an interface between the AD7714 and the 68HC11 microcontroller. The diagram shows the minimum (three-wire) interface with CS on the AD7714 hard-wired low. In this scheme, the DRDY bit of the Communications Register is monitored to determine when the Data Register is updated. An alternative scheme, which increases the number of interface lines to four, is to monitor the DRDY output line from the AD7714. The monitoring of the DRDY line can be done in two ways. First, DRDY can be connected to one of the 68HC11’s port bits (such as PC0) which is configured as an input. This port bit is then polled to determine the status of DRDY. The second scheme is to use an interrupt driven system in which case, the DRDY output is connected to the IRQ input of the 68HC11. For interfaces which require control of the CS input on the AD7714, one of the port bits of the 68HC11 (such as PC1), which is configured as an output, can be used to drive the CS input. REV. C SYNC RESET Most of the registers on the AD7714 are 8-bit registers which facilitates easy interfacing to the 8-bit serial ports of microcontrollers. Some of the registers on the part are up to 24 bits, but data transfers to these 24-bit registers can consist of a full 24-bit transfer or three 8-bit transfers to the serial port of the microcontroller. DSP processors and microprocessors generally transfer 16 bits of data in a serial data operation. Some of these processors, such as the ADSP-2105, have the facility to program the amount of cycles in a serial transfer. This allows the user to tailor the number of bits in any transfer to match the register length of the required register in the AD7714. Even though some of the registers on the AD7714 are only eight bits in length, communicating with two of these registers in successive write operations can be handled as a single 16-bit data transfer if required. For example, if the Mode Register is to be updated, the processor must first write to the Communications Register (saying that the next operation is a write to the Mode Register) and then write eight bits to the Mode Register. This can all be done in a single 16-bit transfer if required because once the eight serial clocks of the write operation to the Communications Register have been completed the part immediately sets itself up for a write operation to the Mode Register. DVDD SCK SCLK 68HC11 AD7714 MISO DATA OUT MOSI DATA IN POL CS Figure 9. AD7714 to 68HC11 Interface The AD7714 is not capable of full duplex operation. If the AD7714 is configured for a write operation, no data appears on the DATA OUT lines even when the SCLK input is active. Similarly, if the AD7714 is configured for a read operation, data presented to the part on the DATA IN line is ignored even when SCLK is active. Coding for an interface between the 68HC11 and the AD7714 is given in Table XV. In this example, the DRDY output line of the AD7714 is connected to the PC0 port bit of the 68HC11 and is polled to determine its status. AD7714 to 8051 Interface An interface circuit between the AD7714 and the 8XC51 microcontroller is shown in Figure 10. The diagram shows the minimum number of interface connections with CS on the AD7714 hard-wired low. In the case of the 8XC51 interface the minimum number of interconnects is just two. In this scheme, the DRDY bit of the Communications Register is monitored to determine when the Data Register is updated. The alternative scheme, which increases the number of interface lines to three, is to monitor the DRDY output line from the AD7714. The monitoring of the DRDY line can be done in two ways. First, DRDY can be connected to one of the 8XC51’s port bits (such as P1.0) which is configured as an input. This port bit is then polled to determine the status of DRDY. The second scheme is to use an interrupt driven system in which case, the DRDY output is connected to the INT1 input of the 8XC51. For –31– 2 AD7714 interfaces which require control of the CS input on the AD7714, one of the port bits of the 8XC51 (such as P1.1), which is configured as an output, can be used to drive the CS input. outputs from the ADSP-2103/ADSP-2105 are active. The serial clock rate on the ADSP-2103/ADSP-2105 should be limited to 3␣ MHz to ensure correct operation with the AD7714. DVDD DVDD SYNC SYNC RESET RFS RESET TFS POL 8XC51 P3.1 AD7714 ADSP-2103/2105 AD7714 P3.0 CS DATA OUT DR DATA OUT DATA IN DT DATA IN SCLK SCLK SCLK POL CS Figure 11. AD7714 to ADSP-2103/ADSP-2105 Interface Figure 10. AD7714 to 8051 Interface CODE FOR SETTING UP THE AD7714 The 8XC51 is configured in its Mode 0 serial interface mode. Its serial interface contains a single data line. As a result, the DATA OUT and DATA IN pins of the AD7714 should be connected together. The serial clock on the 8XC51 idles high between data transfers and, therefore, the POL input of the AD7714 should be hard-wired to a logic high. The 8XC51 outputs the LSB first in a write operation while the AD7714 expects the MSB first so the data to be transmitted has to be rearranged before being written to the output serial register. Similarly, the AD7714 outputs the MSB first during a read operation while the 8XC51 expects the LSB first. Therefore, the data that is read into the serial buffer needs to be rearranged before the correct data word from the AD7714 is available in the accumulator. Table XV gives a set of read and write routines in C code for interfacing the 68HC11 microcontroller to the AD7714. The sample program sets up the various registers on the AD7714 and reads 1000 samples from the part into the 68HC11. The setup conditions on the part are exactly the same as those outlined for the flowchart of Figure 8. In the example code given here the DRDY output is polled to determine if a new valid word is available in the output register. AD7714 to ADSP-2103/ADSP-2105 Interface 3. Write to the Filter Low Register, setting the 8 LSBs of the filter word. Figure 11 shows an interface between the AD7714 and the ADSP-2103/ADSP-2105 DSP processor. In the interface shown, the DRDY bit of the Communications Register is again monitored to determine when the Data Register is updated. The alternative scheme is to use an interrupt driven system in which case, the DRDY output is connected to the IRQ2 input of the ADSP-2103/ADSP-2105. The RFS and TFS pins of the ADSP-2103/ADSP-2105 are configured as active low outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is also configured as an output. The POL pin of the AD7714 is hard-wired low. Because the SCLK from the ADSP-2103/ ADSP-2105 is a continuous clock, the CS of the AD7714 must be used to gate off the clock once the transfer is complete. The CS for the AD7714 is active when either the RFS or TFS The sequence of the events in this program are as follows: 1. Write to the Communications Register, setting the channel. 2. Write to the Filter High Register, setting the 4 MSBs of the filter word and setting the part for 24-bit read, bipolar mode with boost off. 4. Write to the Mode Register, setting the part for a gain of 1, burnout current off, no filter synchronization and initiating a self-calibration. 5. Poll the DRDY Output. 6. Read the data from the Data Register. 7. Loop around doing steps 5 and 6 until the specified number of samples have been taken. –32– REV. C AD7714 Table XV. C Code for Interfacing AD7714 to 68HC11 /* This program has read and write routines for the 68HC11 to interface to the AD7714 and the sample program sets the various registers and then reads 1000 samples from the part. */ #include #include #define NUM_SAMPLES 1000 /* change the number of data samples */ #define MAX_REG_LENGTH 3 /* this says that the max length of a register is 3 bytes */ Writetoreg (int); Read (int,char); char *datapointer = store; char store[NUM_SAMPLES*MAX_REG_LENGTH + 30]; void main() { /* the only pin that is programmed here from the 68HC11 is the /CS and this is why the PC2 bit of PORTC is made as an output */ char a; DDRC = 0x04; /* PC2 is an output the rest of the port bits are inputs */ PORTC | = 0x04; /* make the /CS line high */ Writetoreg(0x27); /* set the channel AIN6/AIN6 and set the next operation as write to the filter high register */ Writetoreg(0x4f); /* set Bipolar mode, 24 bits, boost off, all 4 MSBs of filterword to 1 */ Writetoreg(0x37); /* set the next operation as a write to the filter low register */ Writetoreg(0xA0); /* max filter word allowed for low part of the filterword */ Writetoreg(0x17); /* set the operation as a write to the mode register */ Writetoreg(0x20); /* set gain to 1, burnout current off, no filter sync, and do a self calibration */ while(PORTC & 0x10); /* wait for /DRDY to go low */ for(a=0;a