AD7715

a FEATURES Charge-Balancing ADC 16 Bits No Missing Codes 0.0015% Nonlinearity Programmable Gain Front End Gains of 1, 2, 32 and 128 Differential Input Capability Three-Wire Serial Interface SPI™, QSPI™, MICROWIRE™ and DSP Compatible Ability to Buffer the Analog Input 3 V (AD7715-3) or 5 V (AD7715-5) Operation Low Supply Current: 450 A max @ 3 V Supplies Low-Pass Filter with Programmable Output Update 16-Lead SOIC/DIP/TSSOP AIN(+) AIN(–) 3 V/5 V, 450 A 16-Bit, Sigma-Delta ADC AD7715* FUNCTIONAL BLOCK DIAGRAM REF IN(–) REF IN(+) AVDD DVDD CHARGE BALANCING A/D CONVERTER SIGMA-DELTA MODULATOR DIGITAL FILTER BUFFER PGA A = 1–128 CLOCK GENERATION MCLK IN MCLK OUT RESET SCLK CS DIN DOUT DRDY SERIAL INTERFACE REGISTER BANK AD7715 AGND DGND GENERAL DESCRIPTION The AD7715 is a complete analog front end for low frequency measurement applications. The part can accept low level input signals directly from a transducer and outputs a serial digital word. It employs a sigma-delta conversion technique to realize up to 16 bits of no missing codes performance. The input signal is applied to a proprietary programmable gain front end based around an analog modulator. The modulator output is processed by an on-chip digital filter. The first notch of this digital filter can be programmed via the on-chip control register allowing adjustment of the filter cutoff and output update rate. The AD7715 features a differential analog input as well as a differential reference input. It operates from a single supply (+3 V or +5 V). It can handle unipolar input signal ranges of 0 mV to +20 mV, 0 mV to +80 mV, 0 V to +1.25 V and 0 V to +2.5 V. It can also handle bipolar input signal ranges of ± 20 mV, ± 80 mV, ± 1.25 V and ± 2.5 V. These bipolar ranges are referenced to the negative input of the differential analog input. The AD7715 thus performs all signal conditioning and conversion for a singlechannel system. The AD7715 is ideal for use in smart, microcontroller or DSP based systems. It features a serial interface that can be configured for three-wire operation. Gain settings, signal polarity and update rate selection can be configured in software using the input serial port. The part contains self-calibration and system calibration options to eliminate gain and offset errors on the part itself or in the system. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. *Protected by U.S. Patent No: 5,134,401. See page 30 for data sheet index. CMOS construction ensures very low power dissipation, and the power-down mode reduces the standby power consumption to 50 µW typ. The part is available in a 16-lead, 0.3 inch-wide, plastic dual-in-line package (DIP) as well as a 16-lead 0.3 inchwide small outline (SOIC) package and a 16-lead TSSOP package. PRODUCT HIGHLIGHTS 1. The AD7715 consumes less than 450 µA in total supply current at 3 V supplies and 1 MHz master clock, making it ideal for use in low-power systems. Standby current is less than 10 µA. 2. The programmable gain input allows the AD7715 to accept input signals directly from a strain gage or transducer removing a considerable amount of signal conditioning. 3. The AD7715 is ideal for microcontroller or DSP processor applications with a three-wire serial interface reducing the number of interconnect lines and reducing the number of opto-couplers required in isolated systems. The part contains on-chip registers which allow software control over output update rate, input gain, signal polarity and calibration modes. 4. The part features excellent static performance specifications with 16-bits no missing codes, ± 0.0015% accuracy and low rms noise (4000 V *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SCLK 1 MCLK IN 2 MCLK OUT 3 CS 4 16 DGND 15 DVDD 14 DIN 13 DOUT TOP VIEW 5 (Not to Scale) 12 DRDY RESET AVDD 6 AIN(+) 7 AIN(–) 8 11 AGND 10 REF IN(–) 9 REF IN(+) AD7715 ORDERING GUIDE Model AD7715AN-5 AD7715AR-5 AD7715ARU-5 AD7715AN-3 AD7715AR-3 AD7715ARU-3 AD7715AChips-5 AD7715AChips-3 EVAL-AD7715-5EB EVAL-AD7715-3EB AVDD Supply 5V 5V 5V 3V 3V 3V 5V 3V 5V 3V Temperature Range –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C Evaluation Board Evaluation Board Package Options* N-16 R-16 RU-16 N-16 R-16 RU-16 Die Die *N = Plastic DIP; R = SOIC RU = TSSOP. –6– REV. C AD7715 PIN FUNCTION DESCRIPTION Pin No. 1 Mnemonic SCLK Function Serial Clock. Logic Input. An external serial clock is applied to this input to access serial data from the AD7715. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7715 in smaller batches of data. Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part is specified with clock input frequencies of both 1 MHz and 2.4576 MHz. When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and MCLK OUT. If an external clock is applied to MCLK IN, MCLK OUT provides an inverted clock signal. This clock can be used to provide a clock source for external circuitry. Chip Select. Active low Logic Input used to select the AD7715. With this input hardwired low, the AD7715 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device. CS can be used to select the device in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the AD7715. Logic Input. Active low input which resets the control logic, interface logic, calibration coefficients, digital filter and analog modulator of the part to power-on status. Analog Positive Supply Voltage, +3.3 V nominal (AD7715-3) or +5 V nominal (AD7715-5). Analog Input. Positive input of the programmable gain differential analog input to the AD7715. Analog Input. Negative input of the programmable gain differential analog input to the AD7715. Reference Input. Positive input of the differential reference input to the AD7715. The reference input is differential with the provision that REF IN(+) must be greater than REF IN(–). REF IN(+) can lie anywhere between AVDD and AGND. Reference Input. Negative input of the differential reference input to the AD7715. The REF IN(–) can lie anywhere between AVDD and AGND provided REF IN(+) is greater than REF IN(–). Ground reference point for analog circuitry. For correct operation of the AD7715, no voltage on any of the other pins should go more than 30 mV negative with respect to AGND. Logic Output. A logic low on this output indicates that a new output word is available from the AD7715 data register. The DRDY pin will return high upon completion of a read operation of a full output word. If no data read has taken place between output updates, the DRDY line will return high for 500 × tCLK IN cycles prior to the next output update. While DRDY is high, a read operation should not be attempted or in progress to avoid reading from the data register as it is being updated. The DRDY line will return low again when the update has taken place. DRDY is also used to indicate when the AD7715 has completed its on-chip calibration sequence. Serial Data Output with serial data being read from the output shift register on the part. This output shift register can contain information from the setup register, communications register or data register depending on the register selection bits of the Communications Register. Serial Data Input with serial data being written to the input shift register on the part. Data from this input shift register is transferred to the setup register or communications register depending on the register selection bits of the Communications Register. Digital Supply Voltage, +3.3 V or +5 V nominal. Ground reference point for digital circuitry. 2 MCLK IN 3 MCLK OUT 4 CS 5 6 7 8 9 RESET AVDD AIN(+) AIN(–) REF IN(+) 10 11 12 REF IN(–) AGND DRDY 13 DOUT 14 DIN 15 16 DVDD DGND REV. C –7– AD7715 TERMINOLOGY Integral Nonlinearity Positive Full-Scale Overrange This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are Zero-Scale (not to be confused with Bipolar Zero), a point 0.5 LSB below the first code transition (000 . . . 000 to 000 . . . 001) and Full-Scale, a point 0.5 LSB above the last code transition (111 . . . 110 to 111 . . . 111). The error is expressed as a percentage of full scale. Positive Full-Scale Error Positive full-scale overrange is the amount of overhead available to handle input voltages on AIN(+) input greater than AIN(–) + VREF/GAIN (for example, noise peaks or excess voltages due to system gain errors in system calibration routines) without introducing errors due to overloading the analog modulator or overflowing the digital filter. Negative Full-Scale Overrange Positive Full-Scale Error is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage (AIN(–) + VREF/GAIN –3/2 LSBs). It applies to both unipolar and bipolar analog input ranges. Unipolar Offset Error This is the amount of overhead available to handle voltages on AIN(+) below AIN(–) –VREF/GAIN without overloading the analog modulator or overflowing the digital filter. Note that the analog input will accept negative voltage peaks even in the unipolar mode provided that AIN(+) is greater than AIN(–) and greater than AGND – 30 mV. Offset Calibration Range Unipolar Offset Error is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when operating in the unipolar mode. Bipolar Zero Error In the system calibration modes, the AD7715 calibrates its offset with respect to the analog input. The offset calibration range specification defines the range of voltages that the AD7715 can accept and still calibrate offset accurately. Full-Scale Calibration Range This is the deviation of the midscale transition (0111 . . . 111 to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5 LSB) when operating in the bipolar mode. Gain Error This is the range of voltages that the AD7715 can accept in the system calibration mode and still calibrate full scale correctly. Input Span This is a measure of the span error of the ADC. It includes fullscale errors but not zero-scale errors. For unipolar input ranges it is defined as (full scale error–unipolar offset error) while for bipolar input ranges it is defined as (full-scale error–bipolar zero error). Bipolar Negative Full-Scale Error In system calibration schemes, two voltages applied in sequence to the AD7715’s analog input define the analog input range. The input span specification defines the minimum and maximum input voltages from zero to full scale that the AD7715 can accept and still calibrate gain accurately. This is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5 LSB), when operating in the bipolar mode. ON-CHIP REGISTERS The part contains four on-chip registers which can be accessed by via the serial port on the part. The first of these is a Communications Register that decides whether the next operation is a read or write operation and also decides which register the read or write operation accesses. All communications to the part must start with a write operation to the Communications Register. After poweron or RESET, the device expects a write to its Communications Register. The data written to this register determines whether the next operation to the part is a write or a read operation and also determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the Communications Register followed by a write to the selected register. A read operation from any register on the part (including the Communications Register itself and the output data register) starts with a write operation to the Communications Register followed by a read operation from the selected register. The Communication Register also controls the standby mode and the operating gain of the part. The DRDY status is also available by reading from the Communications Register. The second register is a Setup Register that determines calibration modes, filter selection and bipolar/unipolar operation. The third register is the Data Register from which the output data from the part is accessed. The final register is a Test Register that is accessed when testing the device. It is advised that the user does not attempt to access or change the contents of the test register as it may lead to unspecified operation of the device. The registers are discussed in more detail in the following sections. –8– REV. C AD7715 Communications Register (RS1, RS0 = 0, 0) The Communications Register is an eight-bit register from which data can either be read or to which data can be written. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation and to which register this operation takes place. Once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7715 is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, if a write operation to the device of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7715 returns to this default state. Table I outlines the bit designations for the Communications Register. Table I. Communications Register 0/DRDY 0/DRDY ZERO RS1 RS0 R/W STBY G1 G0 For a write operation, a 0 must be written to this bit so that the write operation to the Communications Register actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to this bit, the next 7 bits will be loaded to the Communications Register. For a read operation, this bit provides the status of the DRDY flag from the part. The status of this bit is the same as the DRDY output pin. For a write operation, a 0 must be written to this bit for correct operation of the part. Failure to do this will result in unspecified operation of the device. For a read operation, a 0 will be read back from this bit location. Register Selection Bits. These bits select to which one of four on-chip registers the next read or write operation takes place as shown in Table II along with the register size. When the read or write to the selected register is complete, the part returns to where it is waiting for a write operation to the Communications Register. It does not remain in a state where it will continue to access the selected register. Read/Write Select. This bit selects whether the next operation is a read or write operation to the selected register. A 0 indicates a write cycle as the next operation to the appropriate register, while a 1 indicates a read operation from the appropriate register. Table II. Register Selection ZERO RS1– RS0 R/W RS1 0 0 1 1 STBY RS0 0 1 0 1 Register Communications Register Setup Register Test Register Data Register Register Size 8 Bits 8 Bits 8 Bits 16 Bits Standby. Writing a 1 to this bit puts the part in its standby or power-down mode. In this mode, the part consumes only 10 µA of power supply current. The part retains its calibration and control word information when in STANDBY. Writing a 0 to this bit places the part in its normal operating mode. The default value for this bit after power-on or RESET is 0. G2 0 0 1 1 G1 0 1 0 1 Gain Setting 1 2 32 128 REV. C –9– AD7715 Setup Register (RS1, RS0 = 0, 1); Power On/Reset Status: 28 Hex The Setup Register is an eight-bit register from which data can either be read or to which data can be written. This register controls the setup which the device is to operate in such as the calibration mode, output rate, unipolar/bipolar operation etc. Table III outlines the bit designations for the Setup Register. Table III. Setup Register MD1 MD0 CLK FS1 FS0 B/U BUF FSYNC MD1 0 0 MD0 0 1 Operating Mode Normal Mode; this is the normal mode of operation of the device whereby the device is performing normal conversions. This is the default condition of these bits after Power-On or RESET. Self-Calibration; this activates self-calibration on the part. This is a one step calibration sequence and when complete the part returns to Normal Mode with MD1 and MD0 returning to 0, 0. The DRDY output or bit goes high when calibration is initiated and returns low when this self-calibration is complete and a new valid word is available in the data register. The zero-scale calibration is performed at the selected gain on internally shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on an internally generated VREF/Selected Gain. Zero-Scale System Calibration; this activates zero-scale system calibration on the part. Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes high when calibration is initiated and returns low when this zero-scale calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to Normal Mode with MD1 and MD0 returning to 0, 0. Full-Scale System Calibration; this activates full-scale system calibration on the part. Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. Once again, the DRDY output or bit goes high when calibration is initiated and returns low when this full-scale calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to Normal Mode with MD1 and MD0 returning to 0, 0. Clock Bit. This bit should be set in accordance with the operating frequency of the AD7715. If the device has a master clock frequency of 2.4576 MHz, then this bit should be set to a 1. If the device has a master clock frequency of 1 MHz, then this bit should be set to a 0. This bit sets up the correct scaling currents for a given master clock and also chooses (along with FS1 and FS0) the output update rate for the device. If this bit is not set correctly for the master clock frequency of the device, then the device may not operate to specification. The default value for this bit after power-on or RESET is 1. Filter Selection Bits. Along with the CLK bit, FS1 and FS0 determine the output update rate, filter first notch and –3 dB frequency as outlined in Table IV. The on-chip digital filter provides a Sinc3 (or (Sinx/x)3 ) filter response. In association with the gain selection, it also determines the output noise (and hence the resolution) of the device. Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables V through XII show the effect of the filter notch frequency and gain on the output noise and effective resolution of the part. The output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz then a new word is available at a 50 Hz rate or every 20 ms. If the first notch is at 500 Hz, a new word is available every 2 ms. The default value for these bits is 1, 0. The settling-time of the filter to a full-scale step input change is worst case 4 × 1/(output data rate). For example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is 80 ms max. If the first notch is at 500 Hz, the settling time of the filter to a full-scale input step is 8 ms max. This settling-time can be reduced to 3 × 1/(output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step input takes place with the FSYNC bit high, the settlingtime time will be 3 × 1/(output data rate) from when FSYNC returns low. The –3 dB frequency is determined by the programmed first notch frequency according to the relationship: filter –3 dB frequency = 0.262 × filter first notch frequency. 1 0 1 1 CLK FS1, FS0 –10– REV. C AD7715 Table IV. Output Update Rates CLK* 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 Output Update Rate 20 Hz 25 Hz 100 Hz 200 Hz 50 Hz 60 Hz 250 Hz 500 Hz –3 dB Filter Cutoff 5.24 Hz 6.55 Hz 26.2 Hz 52.4 Hz 13.1 Hz 15.7 Hz 65.5 Hz 131 Hz Default Status *Assumes correct clock frequency at MCLK IN pin B/U BUF Bipolar/Unipolar Operation. A 0 in this bit selects Bipolar Operation. This is the default (Power-On or RESET) status of this bit. A 1 in this bit selects unipolar operation. Buffer Control. With this bit low, the on-chip buffer on the analog input is shorted out. With the buffer shorted out, the current flowing in the AVDD line is reduced to 250 µA (all gains at fCLK IN = 1 MHz and gain of 1 or 2 at fCLK IN = 2.4576 MHz) or 500 µA (gains of 32 and 128 @ fCLK IN = 2.4576 MHz) and the output noise from the part is at its lowest. When this bit is high, the on-chip buffer is in series with the analog input allowing the input to handle higher source impedances. Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and the calibration control logic are held in a reset state and the analog modulator is also held in its reset state. When this bit goes low, the modulator and filter start to process data and a valid word is available in 3 × 1/(output update rate), i.e., the settling-time of the filter. This FSYNC bit does not affect the digital interface and does not reset the DRDY output if it is low. FSYNC Test Register (RS1, RS0 = 1, 0) The part contains a Test Register which is used in testing the device. The user is advised not to change the status of any of the bits in this register from the default (Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and will not operate correctly. If the part enters one of its test modes, exercising RESET will exit the part from the mode. An alternative scheme for getting the part out of one of its test modes, is to reset the interface by writing 32 successive 1s to the part and then load all 0s to the Test Register. Data Register (RS1, RS0 = 1, 1) The Data Register on the part is a read-only 16-bit register which contains the most up-to-date conversion result from the AD7715. If the Communications Register data sets up the part for a write operation to this register, a write operation must actually take place to return the part to where it is expecting a write operation to the Communications Register (the default state of the interface). However, the 16 bits of data written to the part will be ignored by the AD7715. REV. C –11– AD7715 OUTPUT NOISE AD7715-5 Table V shows the AD7715-5 output rms noise for the selectable notch and –3 dB frequencies for the part, as selected by FS1 and FS0 of the Setup Register. The numbers given are for the bipolar input ranges with a VREF of +2.5 V. These numbers are typical and are generated at a differential analog input voltage of 0 V with the part used in unbuffered mode (BUF bit of the Setup Register = 0). Table VI meanwhile shows the output peak-to-peak noise for the selectable notch and –3 dB frequencies for the part. It is important to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. The numbers given are for the bipolar input ranges with a VREF of +2.5 V and for the BUF bit of the Setup Register = 0. These numbers are typical, are generated at an analog input voltage of 0 V and are rounded to the nearest LSB. Meanwhile, Table VII and Table VIII show rms noise and peak-to-peak resolution respectively with the AD7715-5 operating under the same conditions as above except that now the part is operating in buffered mode (BUF Bit of the Setup Register = 1). Table V. Output RMS Noise vs. Gain and Output Update Rate for AD7715-5 (Unbuffered Mode) Filter First Notch & O/P Data Rate MCLK IN = 2.4576 MHz MCLK IN = 1 MHz –3 dB Frequency MCLK IN = 2.4576 MHz MCLK IN = 1 MHz Typical Output RMS Noise in V GAIN = 1 GAIN = 2 GAIN = 32 GAIN = 128 50 Hz 60 Hz 250 Hz 500 Hz 20 Hz 25 Hz 100 Hz 200 Hz 13.1 Hz 15.72 Hz 65.5 Hz 131 Hz 5.24 Hz 6.55 Hz 26.2 Hz 52.4 Hz 3.8 4.8 103 530 1.9 2.4 45 250 0.6 0.6 3.0 18 0.52 0.62 1.6 5.5 Table VI. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-5 (Unbuffered Mode) Filter First Notch & O/P Data Rate –3 dB Frequency Typical Peak-to-Peak Resolution in Bits MCLK IN = 2.4576 MHz 50 Hz 60 Hz 250 Hz 500 Hz MCLK IN = 1 MHz 20 Hz 25 Hz 100 Hz 200 Hz MCLK IN = 2.4576 MHz 13.1 Hz 15.72 Hz 65.5 Hz 131 Hz MCLK IN = 1 MHz 5.24 Hz 6.55 Hz 26.2 Hz 52.4 Hz GAIN = 1 16 16 13 10 GAIN = 2 16 16 13 10 GAIN = 32 16 16 13 10 GAIN = 128 14 13 12 10 Table VII. Output RMS Noise vs. Gain and Output Update Rate for AD7715-5 (Buffered Mode) Filter First Notch & O/P Data Rate –3 dB Frequency Typical Output RMS Noise in V MCLK IN = 2.4576 MHz 50 Hz 60 Hz 250 Hz 500 Hz MCLK IN = 1 MHz 20 Hz 25 Hz 100 Hz 200 Hz MCLK IN = 2.4576 MHz 13.1 Hz 15.72 Hz 65.5 Hz 131 Hz MCLK IN = 1 MHz 5.24 Hz 6.55 Hz 26.2 Hz 52.4 Hz GAIN = 1 4.3 5.1 103 550 GAIN = 2 2.2 3.1 50 280 GAIN = 32 0.9 1.0 3.9 18 GAIN = 128 0.9 1.0 2.1 6 Table VIII. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-5 (Buffered Mode) Filter First Notch & O/P Data Rate –3 dB Frequency Typical Peak-to-Peak Resolution in Bits MCLK IN = 2.4576 MHz 50 Hz 60 Hz 250 Hz 500 Hz MCLK IN = 1 MHz 20 Hz 25 Hz 100 Hz 200 Hz MCLK IN = 2.4576 MHz 13.1 Hz 15.72 Hz 65.5 Hz 131 Hz MCLK IN = 1 MHz 5.24 Hz 6.55 Hz 26.2 Hz 52.4 Hz GAIN = 1 16 16 13 10 GAIN = 2 16 16 13 10 GAIN = 32 15 15 13 10 GAIN = 128 13 13 12 10 –12– REV. C AD7715 AD7715-3 Table IX shows the AD7715-3 output rms noise for the selectable notch and –3 dB frequencies for the part, as selected by FS1 and FS0 of the Setup Register. The numbers given are for the bipolar input ranges with a VREF of +1.25 V. These numbers are typical and are generated at an analog input voltage of 0 V with the part used in unbuffered mode (BUF bit of the Setup Register = 0). Table X meanwhile shows the output peak-to-peak noise for the selectable notch and –3 dB frequencies for the part. It is important to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peakto-peak noise. The numbers given are for the bipolar input ranges with a VREF of +1.25 V and for the BUF bit of the Setup Register = 0. These numbers are typical, are generated at an analog input voltage of 0 V and are rounded to the nearest LSB. Meanwhile, Table XI and Table XII show rms noise and peak-to-peak resolution respectively with the AD7715-3 operating under the same conditions as above except that now the part is operating in buffered mode (BUF Bit of the Setup Register = 1). Table IX. Output RMS Noise vs. Gain and Output Update Rate for AD7715-3 (Unbuffered Mode) Filter First Notch & O/P Data Rate –3 dB Frequency Typical Output RMS Noise in V MCLK IN = 2.4576 MHz 50 Hz 60 Hz 250 Hz 500 Hz MCLK IN = 1 MHz 20 Hz 25 Hz 100 Hz 200 Hz MCLK IN = 2.4576 MHz 13.1 Hz 15.72 Hz 65.5 Hz 131 Hz MCLK IN = 1 MHz 5.24 Hz 6.55 Hz 26.2 Hz 52.4 Hz GAIN = 1 3.0 3.4 45 270 GAIN = 2 1.7 2.1 20 135 GAIN = 32 0.7 0.7 2.2 9.7 GAIN = 128 0.65 0.7 1.6 3.3 Table X. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-3 (Unbuffered Mode) Filter First Notch & O/P Data Rate –3 dB Frequency Typical Peak-to-Peak Resolution in Bits MCLK IN = 2.4576 MHz 50 Hz 60 Hz 250 Hz 500 Hz MCLK IN = 1 MHz 20 Hz 25 Hz 100 Hz 200 Hz MCLK IN = 2.4576 MHz 13.1 Hz 15.72 Hz 65.5 Hz 131 Hz MCLK IN = 1 MHz 5.24 Hz 6.55 Hz 26.2 Hz 52.4 Hz GAIN = 1 16 16 13 11 GAIN = 2 16 16 13 11 GAIN = 32 14 14 13 10 GAIN = 128 12 12 11 10 Table XI. Output RMS Noise vs. Gain and Output Update Rate for AD7715-3 (Buffered Mode) Filter First Notch & O/P Data Rate –3 dB Frequency Typical Output RMS Noise in V MCLK IN = 2.4576 MHz 50 Hz 60 Hz 250 Hz 500 Hz MCLK IN = 1 MHz 20 Hz 25 Hz 100 Hz 200 Hz MCLK IN = 2.4576 MHz 13.1 Hz 15.72 Hz 65.5 Hz 131 Hz MCLK IN = 1 MHz 5.24 Hz 6.55 Hz 26.2 Hz 52.4 Hz GAIN = 1 4.5 5.1 50 270 GAIN = 2 2.4 2.9 25 135 GAIN = 32 0.9 0.9 2.6 9.7 GAIN = 128 0.9 1.0 2 3.3 Table XII. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-3 (Buffered Mode) Filter First Notch & O/P Data Rate –3 dB Frequency Typical Peak-to-Peak Resolution in Bits MCLK IN = 2.4576 MHz 50 Hz 60 Hz 250 Hz 500 Hz MCLK IN = 1 MHz 20 Hz 25 Hz 100 Hz 200 Hz MCLK IN = 2.4576 MHz 13.1 Hz 15.72 Hz 65.5 Hz 131 Hz MCLK IN = 1 MHz 5.24 Hz 6.55 Hz 26.2 Hz 52.4 Hz GAIN = 1 16 16 13 10 GAIN = 2 16 16 13 11 GAIN = 32 14 14 12 10 GAIN = 128 12 12 11 10 REV. C –13– AD7715 CALIBRATION SEQUENCES The AD7715 contains a number of calibration options as outlined previously. Table XIII summarizes the calibration types, the operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor when DRDY returns low at the end of the sequence. DRDY not only indicates when the sequence is complete but also that the part has a valid new sample in its data register. This valid new sample is the result of a normal conversion which follows the calibration sequence. The second method of determining when calibration is complete is to monitor the MD1 and MD0 bits of the Setup Register. When these bits return to 0, 0 following a calibration command, it indicates that the calibration sequence is complete. This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier indication than DRDY that calibration is complete. The duration to when the Mode Bits (MD1 and MD0) return to 0, 0 represents the duration of the calibration carried out. The sequence to when DRDY goes low also includes a normal conversion and a pipeline delay, tP, to correctly scale the results of this first conversion. tP will never exceed 2000 × tCLK IN . The time for both methods is given in the table. Table XIII. Calibration Sequences Calibration Type Self Calibration ZS System Calibration FS System Calibration MD1, MD0 0, 1 1, 0 1, 1 Calibration Sequence Internal ZS Cal @ Selected Gain + Internal FS Cal @ Selected Gain ZS Cal on AIN @ Selected Gain FS Cal on AIN @ Selected Gain Duration to Mode Bits 6 × 1/Output Rate 3 × 1/Output Rate 3 × 1/Output Rate Duration to DRDY 9 × 1/Output Rate + tP 4 × 1/Output Rate + tP 4 × 1/Output Rate + tP CIRCUIT DESCRIPTION The AD7715 is a sigma-delta A/D converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those in industrial control or process control applications. It contains a sigma-delta (or chargebalancing) ADC, a calibration microcontroller with on-chip static RAM, a clock oscillator, a digital filter and a bidirectional serial communications port. The part consumes only 450 µA of power supply current, making it ideal for battery-powered or loop-powered instruments. The part comes in two versions, the AD7715-5 which is specified for operation from a nominal +5 V analog supply (AVDD) and the AD7715-3 which is specified for operation from a nominal +3.3 V analog supply. Both versions can be operated with a digital supply (DVDD ) voltage of +3.3 V or +5 V. The part contains a programmable-gain fully differential analog input channel. The selectable gains on this input are 1, 2, 32 and 128 allowing the part to accept unipolar signals of between 0 mV to +20 mV and 0 V to +2.5 V or bipolar signals in the range from ± 20 mV to ± 2.5 V when the reference input voltage equals +2.5 V. With a reference voltage of +1.25 V, the input ranges are from 0 mV to +10 mV to 0 V to +1.25 V in unipolar mode and from ± 10 mV to ± 1.25 V in bipolar mode. Note that the bipolar ranges are with respect to AIN(–) and not with respect to AGND. The input signal to the analog input is continuously sampled at a rate determined by the frequency of the master clock, MCLK IN, and the selected gain. A charge-balancing A/D converter (sigma-delta modulator) converts the sampled signal into a digital pulse train whose duty cycle contains the digital information. The programmable gain function on the analog input is also incorporated in this sigma-delta modulator with the input sampling frequency being modified to give the higher gains. A sinc3 digital low-pass filter processes the output of the sigma-delta modulator and updates the output register at a rate determined by the first notch frequency of this filter. The output data can be read from the serial port randomly or periodically at any rate up to the output register update rate. The first notch of this digital filter (and hence its –3 dB frequency) can be programmed via the Setup Register bits FS0 and FS1. With a master clock frequency of 2.4576 MHz, the programmable range for this first notch frequency is from 50 Hz to 500 Hz giving a programmable range for the –3 dB frequency of 13.1 Hz to 131 Hz. With a master clock frequency of 1 MHz, the programmable range for this first notch frequency is from 20 Hz to 200 Hz giving a programmable range for the –3 dB frequency of 5.24 Hz to 52.4 Hz. The basic connection diagram for the AD7715-5 is shown in Figure 2. This shows both the AVDD and DVDD pins of the AD7715 being driven from the analog +5 V supply. Some applications will have AVDD and DVDD driven from separate supplies. An AD780, precision +2.5 V reference, provides the reference source for the part. On the digital side, the part is configured for three-wire operation with CS tied to DGND. A quartz crystal or ceramic resonator provides the master clock source for the part. In most cases, it will be necessary to connect capacitors on the crystal or resonator to ensure that it does not oscillate at overtones of its fundamental operating frequency. The values of capacitors will vary depending on the manufacturer’s specifications. –14– REV. C AD7715 ANALOG +5V SUPPLY 10 F 0.1 F AVDD DVDD 0.1 F AD7715 DRDY DIFFERENTIAL ANALOG INPUT ANALOG GROUND ANALOG +5V SUPPLY VIN VOUT DIGITAL GROUND AIN(+) AIN(–) DOUT AGND DIN SCLK RESET REF IN(+) 10 F 0.1 F MCLK IN REF IN(–) MCLK OUT CRYSTAL OR CERAMIC RESONATOR RECEIVE (READ) SERIAL DATA SERIAL CLOCK +5V CS DATA READY CSAMP must be charged through RSW and through any external source impedances every input sample cycle. Therefore, in unbuffered mode, source impedances mean a longer charge time for CSAMP , and this may result in gain errors on the part. Table XIV shows the allowable external resistance/capacitance values, for unbuffered mode, such that no gain error to the 16-bit level is introduced on the part. Note that these capacitances are total capacitances on the analog input, external capacitance plus 10 pF capacitance from the pins and lead frame of the device. Table XIV. External R, C Combination for No 16-Bit Gain Error (Unbuffered Mode Only) DGND AD780 GND Gain 10 1 2 32 128 152 kΩ 75.1 kΩ 16.7 kΩ 16.7 kΩ External Capacitance (pF) 50 53.9 kΩ 26.6 kΩ 5.95 kΩ 5.95 kΩ 100 31.4 kΩ 15.4 kΩ 3.46 kΩ 3.46 kΩ 500 8.4 kΩ 4.14 kΩ 924 Ω 924 Ω 1000 4.76 kΩ 2.36 kΩ 526 Ω 526 Ω 5000 1.36 kΩ 670 Ω 150 Ω 150 Ω Figure 2. AD7715-5 Basic Connection Diagram ANALOG INPUT Analog Input Ranges The AD7715 contains a differential analog input pair AIN(+) and AIN(–). This input pair provides a programmable-gain, differential input channel which can handle either unipolar or bipolar input signals. It should be noted that the bipolar input signals are referenced to the respective AIN(–) input of the input pair. In unbuffered mode, the common-mode range of the input is from AGND to AVDD provided that the absolute value of the analog input voltage lies between AGND – 30 mV and AVDD + 30 mV. This means that in unbuffered mode the part can handle both unipolar and bipolar input ranges for all gains. In buffered mode, the analog inputs can handle much larger source impedances but the absolute input voltage range is restricted to between AGND + 50 mV to AVDD – 1.5 V which also places restrictions on the common-mode range. This means that in buffered mode there are some restrictions on the allowable gains for bipolar input ranges. Care must be taken in setting up the common-mode voltage and input voltage range so that the above limits are not exceeded, otherwise there will be a degradation in linearity performance. In unbuffered mode, the analog inputs look directly into the input sampling capacitor, CSAMP. The dc input leakage current in this unbuffered mode is 1 nA maximum. As a result, the analog inputs see a dynamic load that is switched at the input sample rate (see Figure 3). This sample rate depends on master clock frequency and selected gain. CSAMP is charged to AIN(+) and discharged to AIN(–) every input sample cycle. The effective on-resistance of the switch, RSW , is typically 7 kΩ. In buffered mode, the analog inputs look into the high impedance inputs stage of the on-chip buffer amplifier. CSAMP is charged via this buffer amplifier such that source impedances do not affect the charging of CSAMP. This buffer amplifier has an offset leakage current of 1 nA. In this buffered mode, large source impedances result in a small dc offset voltage developed across the source impedance but not in a gain error. Input Sample Rate The modulator sample frequency for the AD7715 remains at fCLK IN/128 (19.2 kHz @ fCLK IN = 2.4576 MHz) regardless of the selected gain. However, gains greater than 1 are achieved by a combination of multiple input samples per modulator cycle and a scaling of the ratio of reference capacitor to input capacitor. As a result of the multiple sampling, the input sample rate of the device varies with the selected gain (see Table XV). In buffered mode, the input is buffered before the input sampling Table XV. Input Sampling Frequency vs. Gain Gain 1 2 32 128 Input Sampling Freq (fS) fCLK IN/64 (38.4 kHz @ fCLK IN = 2.4576 MHz) 2 × fCLK IN/64 (76.8 kHz @ fCLK IN = 2.4576 MHz) 8 × fCLK IN/64 (307.2 kHz @ fCLK IN = 2.4576 MHz) 8 × fCLK IN/64 (307.2 kHz @ fCLK IN = 2.4576 MHz) capacitor. In unbuffered mode, where the analog input looks directly into the sampling capacitor, the effective input impedance is 1/CSAMP × fS where CSAMP is the input sampling capacitance and fS is the input sample rate. Bipolar/Unipolar Inputs AIN(+) RSW (7k AIN(–) TYP) CSAMP (10pF ) VBIAS SWITCHING FREQUENCY DEPENDS ON fCLKIN AND SELECTED GAIN HIGH IMPEDANCE 1G Figure 3. Unbuffered Analog Input Structure The analog input on the AD7715 can accept either unipolar or bipolar input voltage ranges. Bipolar input ranges do not imply that the part can handle negative voltages on its analog input since the analog input cannot go more negative than –30 mV to ensure correct operation of the part. The input channel is fully differential. As a result, the voltage to which the unipolar and bipolar signals on the AIN(+) input are referenced is the voltage on the respective AIN(–) input. For example, if AIN(–) is +2.5 V and the AD7715 is configured for unipolar operation REV. C –15– AD7715 with a gain of 2 and a VREF of +2.5 V, the input voltage range on the AIN(+) input is +2.5 V to +3.75 V. If AIN(–) is +2.5 V and the AD7715 is configured for bipolar mode with a gain of 2 and a VREF of +2.5 V, the analog input range on the AIN(+) input is +1.25 V to +3.75 V (i.e., 2.5 V ± 1.25 V). If AIN(–) is at AGND, the part cannot be configured for bipolar ranges in excess of ± 30 mV. Bipolar or unipolar options are chosen by programming the B /U bit of the Setup Register. This programs the channel for either unipolar or bipolar operation. Programming the channel for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding and the points on the transfer function where calibrations occur. REFERENCE INPUT DIGITAL FILTERING The AD7715 contains an on-chip low-pass digital filter that processes the output of the part’s sigma-delta modulator. Therefore, the part not only provides the analog-to-digital conversion function but it also provides a level of filtering. There are a number of system differences when the filtering function is provided in the digital domain rather than the analog domain and the user should be aware of these. First, since digital filtering occurs after the A-to-D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. Also, the digital filter can be made programmable far more readily than an analog filter. Depending on the digital filter design, this gives the user the capability of programming cutoff frequency and output update rate. On the other hand, analog filtering can remove noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. To alleviate this problem, the AD7715 has overrange headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 5% above the analog input range. If noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. This will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%). In addition, the digital filter does not provide any rejection at integer multiples of the digital filter’s sample frequency. However, the input sampling on the part provides attenuation at multiples of the digital filter’s sampling frequency so that the unattenu-ated bands actually occur around multiples of the sampling frequency fS (as defined in Table XV). Thus the unattenuated bands occur at n × fS (where n = 1, 2, 3. . . ). At these frequencies, there are frequency bands, ± f3 dB wide (f3 dB is the cutoff frequency of the digital filter) at either side where noise passes unattenuated to the output. Filter Characteristics The AD7715’s reference inputs, REF IN(+) and REF IN(–), provide a differential reference input capability. The commonmode range for these differential inputs is from AGND to AVDD . The nominal reference voltage, VREF (REF IN(+) – REF IN(–)), for specified operation is +2.5 V for the AD7715-5 and +1.25 V for the AD7715-3. The part is functional with VREF voltages down to 1 V but with degraded performance as the output noise will, in terms of LSB size, be larger. REF IN(+) must always be greater than REF IN(–) for correct operation of the AD7715. Both reference inputs provide a high impedance, dynamic load similar to the analog inputs in unbuffered mode. The maximum dc input leakage current is ± 1 nA over temperature and source resistance may result in gain errors on the part. In this case, the sampling switch resistance is 5 kΩ typ and the reference capacitor (CREF) varies with gain. The sample rate on the reference inputs is fCLK IN /64 and does not vary with gain. For gains of 1 and 2, CREF is 8 pF; for a gain of 32, it is 4.25 pF, and for a gain of 128, it is 3.3125 pF. The output noise performance outlined in Tables V through XII is for an analog input of 0 V which effectively removes the effect of noise on the reference. To obtain the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7715. If the reference noise in the bandwidth of interest is excessive, it will degrade the performance of the AD7715. In applications where the excitation voltage for the bridge transducer on the analog input also derives the reference voltage for the part, the effect of the noise in the excitation voltage will be removed as the application is ratiometric. Recommended reference voltage sources for the AD7715-5 include the AD780, REF43 and REF192, while the recommended reference sources for the AD7715-3 include the AD589 and AD1580. It is generally recommended to decouple the output of these references in order to further reduce the noise level. The AD7715’s digital filter is a low-pass filter with a (sinx/x)3 response (also called sinc3). The transfer function for this filter is described in the z-domain by:  1 1– z  H (z ) =  × –1  N 1 – z    −N 3 and in the frequency domain by:  f Sin  N × π ×  fs  1  |H( f )|= × N  f Sin  π ×  fs   3 where N is the ratio of the modulator rate to the output rate and fMOD is the modulator rate. –16– REV. C AD7715 Figure 4 shows the filter frequency response for a cutoff frequency of 15.72 Hz which corresponds to a first filter notch frequency of 60 Hz. The plot is shown from dc to 390 Hz. This response is repeated at either side of the digital filter’s sample frequency and at either side of multiples of the filter’s sample frequency. 0 –20 –40 –60 –80 GAIN – dB –100 –120 –140 –160 –180 –200 –220 –240 0 60 180 120 240 FREQUENCY – Hz 300 360 26.2 Hz. Post-filtering can be applied to this to reduce the bandwidth and output noise, to the 7.86 Hz bandwidth level, while maintaining an output rate of 100 Hz. Post-filtering can also be used to reduce the output noise from the device for bandwidths below 13.1 Hz. At a gain of 128 and a bandwidth of 13.1 Hz, the output rms noise is 520 nV. This is essentially device noise or white noise and since the input is chopped, the noise has a primarily flat frequency response. By reducing the bandwidth below 13.1 Hz, the noise in the resultant passband can be reduced. A reduction in bandwidth by a factor of 2 results in a reduction of approximately 1.25 in the output rms noise. This additional filtering will result in a longer settling time. ANALOG FILTERING Figure 4. Frequency Response of AD7715 Filter The response of the filter is similar to that of an averaging filter but with a sharper roll-off. The output rate for the digital filter corresponds with the positioning of the first notch of the filter’s frequency response. Thus, for the plot of Figure 4 where the output rate is 60 Hz, the first notch of the filter is at 60 Hz. The notches of this (sinx/x)3 filter are repeated at multiples of the first notch. The filter provides attenuation of better than 100 dB at these notches. The cutoff frequency of the digital filter is determined by the value loaded to bits FS0 to FS1 in the Setup Register. Programming a different cutoff frequency via FS0 and FS1 does not alter the profile of the filter response; it changes the frequency of the notches. The output update of the part and the frequency of the first notch correspond. Since the AD7715 contains this on-chip, low-pass filtering, there is a settling time associated with step function inputs and data on the output will be invalid after a step change until the settling time has elapsed. The settling time depends upon the output rate chosen for the filter. The settling time of the filter to a full-scale step input can be up 4 times the output data period. For a synchronized step input (using the FSYNC function), the settling time is 3 times the output data period. Post-Filtering The digital filter does not provide any rejection at integer multiples of the modulator sample frequency, as outlined earlier. However, due to the AD7715’s high oversampling ratio, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. This means that the analog filtering requirements in front of the AD7715 are considerably reduced versus a conventional converter with no on-chip filtering. In addition, because the part’s common-mode rejection performance of 95 dB extends out to several kHz, common-mode noise in this frequency range will be substantially reduced. Depending on the application, however, it may be necessary to provide attenuation prior to the AD7715 in order to eliminate unwanted frequencies from these bands which the digital filter will pass. It may also be necessary in some applications to provide analog filtering in front of the AD7715 to ensure that differential noise signals outside the band of interest do not saturate the analog modulator. If passive components are placed in front of the AD7715, in unbuffered mode, care must be taken to ensure that the source impedance is low enough so as not to introduce gain errors in the system. This significantly limits the amount of passive antialiasing filtering which can be provided in front of the AD7715 when it is used in unbuffered mode. However, when the part is used in buffered mode, large source impedances will simply result in a small dc offset error (a 10 kΩ source resistance will cause an offset error of less than 10 µV). Therefore, if the system requires any significant source impedances to provide passive analog filtering in front of the AD7715, it is recommended that the part be operated in buffered mode. CALIBRATION The on-chip modulator provides samples at a 19.2 kHz output rate with fCLK IN at 2.4576 MHz. The on-chip digital filter decimates these samples to provide data at an output rate which corresponds to the programmed output rate of the filter. Since the output data rate is higher than the Nyquist criterion, the output rate for a given bandwidth will satisfy most application requirements. However, there may be some applications which require a higher data rate for a given bandwidth and noise performance. Applications that need this higher data rate will require some post-filtering following the digital filter of the AD7715. For example, if the required bandwidth is 7.86 Hz but the required update rate is 100 Hz, the data can be taken from the AD7715 at the 100 Hz rate giving a –3 dB bandwidth of REV. C The AD7715 provides a number of calibration options that can be programmed via the MD1 and MD0 bits of the Setup Register. The different calibration options are outlined in the Setup Register and Calibration Sequences sections. A calibration cycle may be initiated at any time by writing to these bits of the Setup Register. Calibration on the AD7715 removes offset and gain errors from the device. A calibration routine should be initiated on the device whenever there is a change in the ambient operating temperature or supply voltage. It should also be initiated if there is a change in the selected gain, filter notch or bipolar/ unipolar input range. The AD7715 offers self-calibration and system-calibration facilities. For full calibration to occur on the selected channel, the on-chip microcontroller must record the modulator output for two different input conditions. These are “zero-scale” and –17– AD7715 “full-scale” points. These points are derived by performing a conversion on the different input voltages provided to the input of the modulator during calibration. As a result, the accuracy of the calibration can only be as good as the noise level that it provides in normal mode. The result of the “zero-scale” calibration conversion is stored in the Zero-Scale Calibration Register while the result of the “full-scale” calibration conversion is stored in the Full-Scale Calibration Register. With these readings, the on-chip microcontroller can calculate the offset and the gain slope for the input to output transfer function of the converter. Internally, the part works with a resolution of 33 bits to determine its conversion result of 16 bits. Self-Calibration A self-calibration is initiated on the AD7715 by writing the appropriate values (0, 1) to the MD1 and MD0 bits of the Setup Register. In the self-calibration mode with a unipolar input range, the zero-scale point used in determining the calibration coefficients is with the inputs of the differential pair internally shorted on the part (i.e., AIN(+) = AIN(–) = Internal Bias Voltage). The PGA is set for the selected gain (as per G1 and G0 bits in the Communications Register) for this zero-scale calibration conversion. The full-scale calibration conversion is performed at the selected gain on an internally generated voltage of VREF/Selected Gain. The duration time for the calibration is 6 × 1/Output Rate. This is made up of 3 × 1/Output Rate for the zero-scale calibration and 3 × 1/Output Rate for the full-scale calibration. At this time the MD1 and MD0 bits in the Setup Register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 9 × 1/Output Rate. This is made up of 3 × 1/Output Rate for the zero-scale calibration, 3 × 1/Output Rate for the full-scale calibration, 3 × 1/ Output Rate for a conversion on the analog input and some overhead to set up the coefficients correctly. If DRDY is low before (or goes low during) the calibration command write to the Setup Register, it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the Setup Register in the calibration command. For bipolar input ranges in the self-calibrating mode, the sequence is very similar to that just outlined. In this case, the two points are exactly the same as above, but since the part is configured for bipolar operation, the shorted inputs point is actually midscale of the transfer function. System Calibration step is complete. Once the system zero scale voltage has been set up, a ZS System Calibration is then initiated by writing the appropriate values (1, 0) to the MD1 and MD0 bits of the Setup Register. The zero-scale system calibration is performed at the selected gain. The duration of the calibration is 3 × 1/Output Rate. At this time the MD1 and MD0 bits in the Setup Register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 4 × 1/Output Rate as the part performs a normal conversion on the AIN voltage before DRDY goes low. If DRDY is low before (or goes low during) the calibration command write to the Setup Register, it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the Setup Register in the calibration command. After the zero-scale point is calibrated, the full-scale point is applied to AIN and the second step of the calibration process is initiated by again writing the appropriate values (1, 1) to MD1 and MD0. Again the full-scale voltage must be set up before the calibration is initiated and it must remain stable throughout the calibration step. The full-scale system calibration is performed at the selected gain. The duration of the calibration is 3 × 1/Output Rate. At this time the MD1 and MD0 bits in the Setup Register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 4 × 1/Output Rate as the part performs a normal conversion on the AIN voltage before DRDY goes low. If DRDY is low before (or goes low during) the calibration command, write to the Setup Register, it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the Setup Register in the calibration command. In the unipolar mode, the system calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale (zero differential voltage) and positive full scale. The fact that the system calibration is a two-step calibration offers another feature. After the sequence of a full system calibration has been completed, additional offset or gain calibrations can be performed by themselves to adjust the system zero reference point or the system gain. Calibrating one of the parameters, either system offset or system gain, will not affect the other parameter. System calibration can also be used to remove any errors from source impedances on the analog input when the part is used in unbuffered mode. A simple R, C antialiasing filter on the front end may introduce a gain error on the analog input voltage but the system calibration can be used to remove this error. Span and Offset Limits System calibration allows the AD7715 to compensate for system gain and offset errors as well as its own internal errors. System calibration performs the same slope factor calculations as selfcalibration but uses voltage values presented by the system to the AIN inputs for the zero- and full-scale points. Full System calibration requires a two step process, a ZS System Calibration followed by a FS System Calibration. For a full system calibration, the zero-scale point must be presented to the converter first. It must be applied to the converter before the calibration step is initiated and remain stable until the Whenever a system calibration mode is used, there are limits on the amount of offset and span which can be accommodated. The overriding requirement in determining the amount of offset REV. C –18– AD7715 and gain that can be accommodated by the part is the requirement that the positive full-scale calibration limit is ≤ 1.05 × VREF/GAIN. This allows the input range to go 5% above the nominal range. The in-built headroom in the AD7715’s analog modulator ensures that the part will still operate correctly with a positive full-scale voltage which is 5% beyond the nominal. The range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 × VREF/GAIN and a maximum value of 2.1 × VREF/GAIN. However, the span (which is the difference between the bottom of the AD7715’s input range and the top of its input range) must take into account the limitation on the positive full-scale voltage. The amount of offset that can be accommodated depends on whether the unipolar or bipolar mode is being used. Once again, the offset must take into account the limitation on the positive full-scale voltage. In unipolar mode, there is considerable flexibility in handling negative (with respect to AIN(–)) offsets. In both unipolar and bipolar modes, the range of positive offsets which can be handled by the part depends on the selected span. Therefore, in determining the limits for system zero-scale and full-scale calibrations, the user has to ensure that the offset range plus the span range does exceed 1.05 × VREF/GAIN. This is best illustrated by looking at a few examples. If the part is used in unipolar mode with a required span of 0.8 × VREF/GAIN, then the offset range which the system calibration can handle is from –1.05 × VREF/GAIN to +0.25 × VREF/ GAIN. If the part is used in unipolar mode with a required span of VREF/GAIN, then the offset range which the system calibration can handle is from –1.05 × VREF/GAIN to +0.05 × VREF/GAIN. Similarly, if the part is used in unipolar mode and required to remove an offset of 0.2 × VREF/GAIN, then the span range which the system calibration can handle is 0.85 × VREF/GAIN. If the part is used in bipolar mode with a required span of ± 0.4 × VREF /GAIN, then the offset range which the system calibration can handle is from –0.65 × VREF/GAIN to +0.65 × VREF/ GAIN. If the part is used in bipolar mode with a required span of ± VREF/GAIN, then the offset range which the system calibration can handle is from –0.05 × VREF/GAIN to +0.05 × VREF / GAIN. Similarly, if the part is used in bipolar mode and required to remove an offset of ± 0.2 × VREF/GAIN, then the span range which the system calibration can handle is ± 0.85 × VREF/GAIN. Power-Up and Calibration USING THE AD7715 Clocking and Oscillator Circuit The AD7715 requires a master clock input, which may be an external CMOS compatible clock signal applied to the MCLK IN pin with the MCLK OUT pin left unconnected. Alternatively, a crystal or ceramic resonator of the correct frequency can be connected between MCLK IN and MCLK OUT in which case the clock circuit will function as an oscillator, providing the clock source for the part. The input sampling frequency, the modulator sampling frequency, the –3 dB frequency, output update rate and calibration time are all directly related to the master clock frequency, fCLK IN. Reducing the master clock frequency by a factor of 2 will halve the above frequencies and update rate and double the calibration time. The current drawn from the DVDD power supply is also directly related to fCLK IN. Reducing fCLK IN by a factor of 2 will halve the DVDD current but will not affect the current drawn from the AVDD power supply. Using the part with a crystal or ceramic resonator between the MCLK IN and MCLK OUT pins generally causes more current to be drawn from DVDD than when the part is clocked from a driven clock signal at the MCLK IN pin. This is because the on-chip oscillator circuit is active in the case of the crystal or ceramic resonator. Therefore, the lowest possible current on the AD7715 is achieved with an externally applied clock at the MCLK IN pin with MCLK OUT unconnected and unloaded. The amount of additional current taken by the oscillator depends on a number of factors—first, the larger the value of capacitor placed on the MCLK IN and MCLK OUT pins, then the larger the DVDD current consumption on the AD7715. Care should be taken not to exceed the capacitor values recommended by the crystal and ceramic resonator manufacturers to avoid consuming unnecessary DVDD current. Typical values recommended by crystal or ceramic resonator manufacturers are in the range of 30 pF to 50 pF, and if the capacitor values on MCLK IN and MCLK OUT are kept in this range, they will not result in any excessive DVDD current. Another factor that influences the DVDD current is the effective series resistance (ESR) of the crystal which appears between the MCLK IN and MCLK OUT pins of the AD7715. As a general rule, the lower the ESR value then the lower the current taken by the oscillator circuit. When operating with a clock frequency of 2.4576 MHz, there is 50 µA difference in the DVDD current between an externally applied clock and a crystal resonator when operating with a DVDD of +3 V. With DVDD = +5 V and fCLK IN = 2.4576 MHz, the typical DVDD current increases by 200 µA for a crystal/ resonator supplied clock versus an externally applied clock. The ESR values for crystals and resonators at this frequency tend to be low and as a result there tends to be little difference between different crystal and resonator types. When operating with a clock frequency of 1 MHz, the ESR value for different crystal types varies significantly. As a result, the DVDD current drain varies across crystal types. When using a crystal with an ESR of 700 Ω or when using a ceramic resonator, the increase in the typical DVDD current over an externally-applied clock is 50 µA with DVDD = +3 V and 175 µA with DVDD = +5 V. When using a crystal with an ESR of 3 kΩ, the increase in the typical DVDD current over an externally applied clock is 100 µA with DVDD = +3 V and 400 µA with DVDD = +5 V. On power-up, the AD7715 performs an internal reset that sets the contents of the internal registers to a known state. There are default values loaded to all registers after a power-on or reset. The default values contain nominal calibration coefficients for the calibration registers. However, to ensure correct calibration for the device a calibration routine should be performed after power-up. The power dissipation and temperature drift of the AD7715 are low, and no warm-up time is required before the initial calibration is performed. However, if an external reference is being used, this reference must have stabilized before calibration is initiated. Similarly, if the clock source for the part is generated from a crystal or resonator across the MCLK pins, the start-up time for the oscillator circuit should elapse before a calibration is initiated on the part (see below). REV. C –19– AD7715 The on-chip oscillator circuit also has a start-up time associated with it before it is oscillating at its correct frequency and correct voltage levels. The typical start-up time for the circuit is 10 ms with a DVDD of +5 V and 15 ms with a DVDD of +3 V. At 3 V supplies, depending on the loading capacitances on the MCLK pins, a 1 MΩ feedback resistor may be required across the crystal or resonator in order to keep the start up times around the 15 ms duration. The AD7715’s master clock appears on the MCLK OUT pin of the device. The maximum recommended load on this pin is one CMOS load. When using a crystal or ceramic resonator to generate the AD7715’s clock, it may be desirable to then use this clock as the clock source for the system. In this case, it is recommended that the MCLK OUT signal is buffered with a CMOS buffer before being applied to the rest of the circuit. System Synchronization conditions after a RESET and it is generally necessary to set up all registers and carry out a calibration after a RESET command. The AD7715’s on-chip oscillator circuit continues to function even when the RESET input is low. The master clock signal continues to be available on the MCLK OUT pin. Therefore, in applications where the system clock is provided by the AD7715’s clock, the AD7715 produces an uninterrupted master clock during RESET commands. Standby Mode The FSYNC bit of the Setup Register allows the user to reset the modulator and digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a known point in time, i.e., when the FSYNC is changed from 1 to 0. With a 1 in the FSYNC bit of the Setup Register, the digital filter and analog modulator are held in a known reset state and the part is not processing any input samples. When a 0 is then written to the FSYNC bit, the modulator and filter are taken out of this reset state and on the next master clock edge the part starts to gather samples again. The FSYNC input can also be used as a software start convert command allowing the AD7715 to be operated in a conventional converter fashion. In this mode, writing to the FSYNC bit starts conversion and the falling edge of DRDY indicates when conversion is complete. The disadvantage of this scheme is that the settling time of the filter has to be taken into account for every data register update. This means that the rate at which the data register is updated is three times slower in this mode. Since the FSYNC bit resets the digital filter, the full settling time of 3 × 1/Output Rate must elapse before there is a new word loaded to the output register on the part. If the DRDY signal is low when FSYNC goes to a 0, the DRDY signal will not be reset high by the FSYNC command. This is because the AD7715 recognizes that there is a word in the data register that has not been read. The DRDY line will stay low until an update of the data register takes place at which time it will go high for 500 × tCLK IN before returning low again. A read from the data register resets the DRDY signal high, and it will not return low until the settling time of the filter has elapsed (from the FSYNC command) and there is a valid new word in the data register. If the DRDY line is high when the FSYNC command is issued, the DRDY line will not return low until the settling time of the filter has elapsed. Reset Input The STBY bit in the Communications Register of the AD7715 allows the user to place the part in a power-down mode when it is not required to provide conversion results. The AD7715 retains the contents of all its on-chip registers (including the data register) while in standby mode. When released from standby mode, the part starts to process data and a new word is available in the data register in 3 × 1/Output Rate from when a 0 is written to the STBY bit. The STBY bit does not affect the digital interface, and it does not affect the status of the DRDY line. If DRDY is high when the STBY bit is brought low, it will remain high until there is a valid new word in the data register. If DRDY is low when the STBY bit is brought low, it will remain low until the data register is updated at which time the DRDY line will return high for 500 × tCLK IN before returning low again. If DRDY is low when the part enters its standby mode (indicating a valid unread word in the data register), the data register can be read while the part is in standby. At the end of this read operation, the DRDY will be reset high as normal. Placing the part in standby mode reduces the total current to 5 µA typical when the part is operated from an external master clock provided this master clock is stopped. If the external clock continues to run in standby mode, the standby current increases to 150 µA typical with 5 V supplies and 75 µA typical with 3.3 V supplies. If a crystal or ceramic resonator is used as the clock source, then the total current in standby mode is 400 µA typical with 5 V supplies and 90 µA with 3.3 V supplies. This is because the on-chip oscillator circuit continues to run when the part is in its standby mode. This is important in applications where the system clock is provided by the AD7715’s clock, so that the AD7715 produces an uninterrupted master clock even when it is in its standby mode. Accuracy Sigma-delta ADCs, like VFCs and other integrating ADCs, do not contain any source of nonmonotonicity and inherently offer no missing codes performance. The AD7715 achieves excellent linearity by the use of high quality, on-chip capacitors, which have a very low capacitance/voltage coefficient. The device also achieves low input drift through the use of chopper-stabilized techniques in its input stage. To ensure excellent performance over time and temperature, the AD7715 uses digital calibration techniques which minimize offset and gain error. Drift Considerations The RESET input on the AD7715 resets all the logic, the digital filter and the analog modulator while all on-chip registers are reset to their default state. DRDY is driven high and the AD7715 ignores all communications to any of its registers while the RESET input is low. When the RESET input returns high, the AD7715 starts to process data, and DRDY will return low in 3 × 1/Output Rate indicating a valid new word in the data register. However, the AD7715 operates with its default setup The AD7715 uses chopper stabilization techniques to minimize input offset drift. Charge injection in the analog switches and dc leakage currents at the sampling node are the primary sources of offset voltage drift in the converter. The dc input leakage current is essentially independent of the selected gain. Gain drift within the converter depends primarily upon the temperature tracking of the internal capacitors. It is not affected by leakage currents. REV. C –20– AD7715 Measurement errors due to offset drift or gain drift can be eliminated at any time by recalibrating the converter. Using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. Integral and differential linearity errors are not significantly affected by temperature changes. POWER SUPPLIES also removes noise from the analog and reference inputs provided those noise sources do not saturate the analog modulator. As a result, the AD7715 is more immune to noise interference that a conventional high resolution converter. However, because the resolution of the AD7715 is so high and the noise levels from the AD7715 so low, care must be taken with regard to grounding and layout. The printed circuit board which houses the AD7715 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes which can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD7715 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD7715. If the AD7715 is in a system where multiple devices require AGND to DGND connections, the connection should still be made at one point only, a star ground point which should be established as close as possible to the AD7715. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7715 to avoid noise coupling. The power supply lines to the AD7715 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is important when using high resolution ADCs. All analog supplies should be decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors to AGND. To achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. All logic chips should be decoupled with 0.1 µF disc ceramic capacitors to DGND. In systems where a common supply voltage is used to drive both the AVDD and DVDD of the AD7715, it is recommended that the system’s AVDD supply is used. This supply should have the recommended analog supply decoupling capacitors between the AVDD pin of the AD7715 and AGND and the recommended digital supply decoupling capacitor between the DVDD pin of the AD7715 and DGND. Evaluating the AD7715 Performance There is no specific power sequence required for the AD7715; either the AVDD or the DVDD supply can come up first. While the latch-up performance of the AD7715 is good, it is important that power is applied to the AD7715 before signals at REF IN, AIN or the logic input pins in order to avoid excessive currents. If this is not possible, then the current which flows in any of these pins should be limited. If separate supplies are used for the AD7715 and the system digital circuitry, then the AD7715 should be powered up first. If it is not possible to guarantee this, then current limiting resistors should be placed in series with the logic inputs to again limit the current. During normal operation the AD7715 analog supply (AVDD ) should always be greater than or equal to its digital supply (DVDD). Supply Current The current consumption on the AD7715 is specified for supplies in the range +3 V to +3.6 V and in the range +4.75 V to +5.25 V. The part operates over a +2.85 V to +5.25 V supply range and the IDD for the part varies as the supply voltage varies over this range. Figure 5 shows the variation of the typical IDD with VDD voltage for both a 1 MHz external clock and a 2.4576 MHz external clock at +25° C. The AD7715 is operated in unbuffered mode. The relationship shows that the IDD is minimized by operating the part with lower VDD voltages. IDD on the AD7715 is also minimized by using an external master clock or by optimizing external components when using the onchip oscillator circuit. 1.0 SUPPLY CURRENT (AVDD & D V DD) – mA 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.85 3.15 4.05 3.45 3.75 4.35 4.65 4.95 SUPPLY VOLTAGE (AVDD & D V DD) – Volts 5.25 MCLK IN = 1MHz MCLK IN = 2.4576MHz Figure 5. IDD vs. Supply Voltage Grounding and Layout Since the analog inputs and reference input are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The analog and digital supplies to the AD7715 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital filter REV. C The recommended layout for the AD7715 is outlined in the evaluation board for the AD7715. The evaluation board package includes a fully assembled and tested evaluation board, documentation, software for controlling the board over the printer port of a PC and software for analyzing the AD7715’s performance on the PC. For the AD7715-5, the evaluation board order number is EVAL-AD7715-5EB and for the AD7715-3, the order number is EVAL-AD7715-3EB. Noise levels in the signals applied to the AD7715 may also affect performance of the part. The AD7715 software evaluation –21– AD7715 package allows the user to evaluate the true performance of the part, independent of the analog input signal. The scheme involves using a test mode on the part where the differential inputs to the AD7715 are internally shorted together to provide a zero differential voltage for the analog modulator. External to the device, the AIN(–) input should be connected to a voltage which is within the allowable common-mode range of the part. This scheme should be used after a calibration has been performed on the part. DIGITAL INTERFACE is complete. It also goes high prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. CS is used to select the device. It can be used to decode the AD7715 in systems where a number of parts are connected to the serial bus. Figures 6 and 7 show timing diagrams for interfacing to the AD7715 with CS used to decode the part. Figure 6 is for a read operation from the AD7715’s output shift register, while Figure 7 shows a write operation to the input shift register. It is possible to read the same data twice from the output register even though the DRDY line returns high after the first read operation. Care must be taken, however, to ensure that the read operations have been completed before the next output update is about to take place. The AD7715 serial interface can operate in three-wire mode by tying the CS input low. In this case, the SCLK, DIN and DOUT lines are used to communicate with the AD7715 and the status of DRDY can be obtained by interrogating the MSB of the Communications Register. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port bit. For microcontroller interfaces, it is recommended that the SCLK idles high between data transfers. The AD7715 can also be operated with CS used as a frame synchronization signal. This scheme is suitable for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS since CS would normally occur after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers provided the timing numbers are obeyed. The serial interface can be reset by exercising the RESET input on the part. It can also be reset by writing a series of 1s on the DIN input. If a logic 1 is written to the AD7715 DIN line for at least 32 serial clock cycles, the serial interface is reset. This ensures that in three-wire systems that if the interface gets lost The AD7715’s programmable functions are controlled using a set of on-chip registers as outlined previously. Data is written to these registers via the part’s serial interface and read access to the on-chip registers is also provided by this interface. All communications to the part must start with a write operation to the Communications Register. After power-on or RESET, the device expects a write to its Communications Register. The data written to this register determines whether the next operation to the part is a read or a write operation and also determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the Communications Register followed by a write to the selected register. A read operation from any other register on the part (including the output data register) starts with a write operation to the Communications Register followed by a read operation from the selected register. The AD7715’s serial interface consists of five signals, CS, SCLK, DIN, DOUT and DRDY. The DIN line is used for transferring data into the on-chip registers while the DOUT line is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device and all data transfers (either on DIN or DOUT) take place with respect to this SCLK signal. The DRDY line is used as a status signal to indicate when data is ready to be read from the AD7715’s data register. DRDY goes low when a new data word is available in the output register. It is reset high when a read operation from the data register DRDY t3 CS t10 t4 SCLK t6 t8 t5 DOUT MSB t7 LSB t9 Figure 6. Read Cycle Timing Diagram CS t11 SCLK t14 t16 t12 DIN MSB t15 t13 LSB Figure 7. Write Cycle Timing Diagram –22– REV. C AD7715 either via a software error or by some glitch in the system, it can be reset back into a known state. This state returns the interface to where the AD7715 is expecting a write operation to its Communications Register. This operation in itself does not reset the contents of any registers, but since the interface was lost, the information which was written to any of the registers is unknown and it is advisable to set up all registers again. Some microprocessor or microcontroller serial interfaces have a single serial data line. In this case, it is possible to connect the AD7715’s DATA OUT and DATA IN lines together and connect then to the single data line of the processor. A 10 kΩ pullup resistor should be used on this single data line. In this case, if the interface gets lost, because the read and write operations share the same line the procedure to reset it back to a known state is somewhat different than described previously. It requires a read operation of 24 serial clocks followed by a write operation where a logic 1 is written for at least 32 serial clock cycles to ensure that the serial interface is back into a known state. CONFIGURING THE AD7715 The AD7715 contains three on-chip registers which the user accesses via the serial interface. Communication with any of these registers is initiated by writing to the Communications Register first. Figure 8 outlines a flow diagram of the sequence which is used to configure all registers after a power-up or reset. The flowchart also shows two different read options—the first where the DRDY pin is polled to determine when an update of the data register has taken place, the second where the DRDY bit of the Communications Register is interrogated to see if a data register update has taken place. Also included in the flowing diagram is a series of words which should be written to the registers for a particular set of operating conditions. These conditions are gain of 1, no filter sync, bipolar mode, buffer off, clock of 2.4576 MHz and an output rate of 60 Hz. START POWER-ON/RESET FOR AD7715 CONFIGURE & INITIALIZE C/ P SERIAL PORT WRITE TO COMMUNICATIONS REGISTER SETTING UP GAIN & SETTING UP NEXT OPERATION TO BE A WRITE TO THE SETUP REGISTER (10 HEX) WRITE TO SETUP REGISTER SETTING UP REQUIRED VALUES & INITIATING A SELF CALIBRATION (68 HEX) POLL DRDY PIN WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME GAIN & SETTING UP NEXT OPERATION TO BE A READ FROM THE COMMUNICATIONS REGISTER (08 HEX) NO DRDY LOW? READ FROM COMMUNICATIONS REGISTER YES POLL DRDY BIT OF COMMUNICATIONS REGISTER WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME GAIN & SETTING UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (38 HEX) NO READ FROM DATA REGISTER DRDY LOW? YES WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME GAIN & SETTING UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (38 HEX) READ FROM DATA REGISTER Figure 8. Flowchart for Setting Up and Reading from the AD7715 REV. C –23– AD7715 MICROCOMPUTER/MICROPROCESSOR INTERFACING DVDD DVDD The AD7715’s flexible serial interface allows for easy interface to most microcomputers and microprocessors. The flowchart of Figure 8 outlines the sequence which should be followed when interfacing a microcontroller or microprocessor to the AD7715. Figures 9, 10 and 11 show some typical interface circuits. The serial interface on the AD7715 has the capability of operating from just three wires and is compatible with SPI interface protocols. The three-wire operation makes the part ideal for isolated systems where minimizing the number of interface lines minimizes the number of opto-isolators required in the system. The rise and fall times of the digital inputs to the AD7715 (especially the SCLK input) should be no longer than 1 µs. Most of the registers on the AD7715 are 8-bit registers. This facilitates easy interfacing to the 8-bit serial ports of microcontrollers. Some of the registers on the part are up to 16 bits, but data transfers to these 16-bit registers can consist of a full 16-bit transfer or two 8-bit transfers to the serial port of the microcontroller. DSP processors and microprocessors generally transfer 16 bits of data in a serial data operation. Some of these processors, such as the ADSP-2105, have the facility to program the amount of cycles in a serial transfer. This allows the user to tailor the number of bits in any transfer to match the register length of the required register in the AD7715. Even though some of the registers on the AD7715 are only eight bits in length, communicating with two of these registers in successive write operations can be handled as a single 16-bit data transfer if required. For example, if the Setup Register is to be updated, the processor must first write to the Communications Register (saying that the next operation is a write to the Setup Register) and then write eight bits to the Setup Register. This can all be done in a single 16-bit transfer if required because once the eight serial clocks of the write operation to the Communications Register have been completed, the part immediately sets itself up for a write operation to the Setup Register. AD7715 to 68HC11 Interface SS SCK RESET SCLK 68HC11 MISO MOSI AD7715 DATA OUT DATA IN CS Figure 9. AD7715 to 68HC11 Interface lines to four, is to monitor the DRDY output line from the AD7715. The monitoring of the DRDY line can be done in two ways. First, DRDY can be connected to one of the 68HC11’s port bits (such as PC0) which is configured as an input. This port bit is then polled to determine the status of DRDY. The second scheme is to use an interrupt driven system, in which case the DRDY output is connected to the IRQ input of the 68HC11. For interfaces that require control of the CS input on the AD7715, one of the port bits of the 68HC11 (such as PC1), which is configured as an output, can be used to drive the CS input. The 68HC11 is configured in the master mode with its CPOL bit set to a logic one and its CPHA bit set to a logic one. When the 68HC11 is configured like this, its SCLK line idles high between data transfers. The AD7715 is not capable of full duplex operation. If the AD7715 is configured for a write operation, no data appears on the DATA OUT lines even when the SCLK input is active. Similarly, if the AD7715 is configured for a read operation, data presented to the part on the DATA IN line is ignored even when SCLK is active. Coding for an interface between the 68HC11 and the AD7715 is given in Table XVI. In this example, the DRDY output line of the AD7715 is connected to the PC0 port bit of the 68HC11 and is polled to determine its status. Figure 9 shows an interface between the AD7715 and the 68HC11 microcontroller. The diagram shows the minimum (three-wire) interface with CS on the AD7715 hardwired low. In this scheme, the DRDY bit of the Communications Register is monitored to determine when the Data Register is updated. An alternative scheme, which increases the number of interface –24– REV. C AD7715 AD7715 to 8XC51 Interface AD7715 to ADSP-2103/ADSP-2105 Interface An interface circuit between the AD7715 and the 8XC51 microcontroller is shown in Figure 10. The diagram shows the minimum number of interface connections with CS on the AD7715 hardwired low. In the case of the 8XC51 interface, the minimum number of interconnects is just two. In this scheme, the DRDY bit of the Communications Register is monitored to determine when the Data Register is updated. The alternative scheme, which increases the number of interface lines to three, is to monitor the DRDY output line from the AD7715. The monitoring of the DRDY line can be done in two ways. First, DRDY can be connected to one of the 8XC51’s port bits (such as P1.0) which is configured as an input. This port bit is then polled to determine the status of DRDY. The second scheme is to use an interrupt driven system in which case, the DRDY output is connected to the INT1 input of the 8XC51. For interfaces that require control of the CS input on the AD7715, one of the port bits of the 8XC51 (such as P1.1), which is configured as an output, can be used to drive the CS input. The 8XC51 is configured in its Mode 0 serial interface mode. Its serial interface contains a single data line. As a result, the DATA OUT and DATA IN pins of the AD7715 should be connected together with a 10 kΩ pull-up resistor. The serial clock on the 8XC51 idles high between data transfers. The 8XC51 outputs the LSB first in a write operation while the AD7715 rearranged before being written to the output serial register. Similarly, the AD7715 outputs the MSB first during a read operation while the 8XC51 expects the LSB first. Therefore, the data which is read into the serial buffer needs to be rearranged before the correct data word from the AD7715 is available in the accumulator. DVDD RESET DVDD Figure 11 shows an interface between the AD7715 and the ADSP-2103/ADSP-2105 DSP processor. In the interface shown, the DRDY bit of the Communications Register is again monitored to determine when the Data Register is updated. The alternative scheme is to use an interrupt driven system, in which case the DRDY output is connected to the IRQ2 input of the ADSP-2103/ADSP-2105. The serial interface of the ADSP2103/ADSP-2105 is set up for alternate framing mode. The RFS and TFS pins of the ADSP-2103/ADSP-2105 are configured as active low outputs, and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is also configured as an output. The CS for the AD7715 is active when either the RFS or TFS outputs from the ADSP-2103/ADSP-2105 are active. The serial clock rate on the ADSP-2103/ADSP-2105 should be limited to 3 MHz to ensure correct operation with the AD7715. DVDD RESET RFS TFS CS ADSP-2103/2105 DR DT SCLK AD7715 DATA OUT DATA IN SCLK Figure 11. AD7715 to ADSP-2103/ADSP-2105 Interface CODE FOR SETTING UP THE AD7715 8XC51 10k P3.0 AD7715 DATA OUT DATA IN P3.1 SCLK CS Table XVI gives a set of read and write routines in C code for interfacing the 68HC11 microcontroller to the AD7715. The sample program sets up the various registers on the AD7715 and reads 1000 samples from the part into the 68HC11. The setup conditions on the part are exactly the same as those outlined for the flowchart of Figure 8. In the example code given here, the DRDY output is polled to determine if a new valid word is available in the data register. The sequence of the events in this program are as follows: 1. Write to the Communications Register, setting the gain to 1 with standby inactive. 2. Write to the Setup Register, setting bipolar mode, buffer off, no filter synchronization, confirming a clock frequency of 2.4576 MHz, setting the output rate for 60 Hz and initiating a self-calibration. 3. Poll the DRDY Output. 4. Read the data from the Data Register. 5. Loop around doing Steps 3 and 4 until the specified number of samples have been taken. Figure 10. AD7715 to 8XC51 Interface REV. C –25– AD7715 Table XVI. C Code for Interfacing AD7715 to 68HC11 /* This program has read and write routines for the 68HC11 to interface to the AD7715 and the sample program sets the various registers and then reads 1000 samples from the part. */ #include #include #define NUM_SAMPLES 1000 /* change the number of data samples */ #define MAX_REG_LENGTH 2 /* this says that the max length of a register is 2 bytes */ Writetoreg (int); Read (int,char); char *datapointer = store; char store[NUM_SAMPLES*MAX_REG_LENGTH + 30]; void main() { /* the only pin that is programmed here from the 68HC11 is the /CS and this is why the PC2 bit of PORTC is made as an output */ char a; DDRC = 0x04; /* PC2 is an output the rest of the port bits are inputs */ PORTC | = 0x04; /* make the /CS line high */ Writetoreg(0x10); /* set the gain to 1, standby off and set the next operation as write to the setup register */ Writetoreg(0x68); /* set bipolar mode, buffer off, no filter sync, confirm clock as 2.4576MHz, set output rate to 60Hz and do a self calibration */ while(PORTC & 0x10); /* wait for /DRDY to go low */ for(a=0;a