AD7750AR

a FEATURES Two Differential Analog Input Channels Product of Two Channels Voltage-to-Frequency Conversion on a Single Channel Real Power Measurement Capability < 0.2% Error Over the Range 400% Ibasic to 2% Ibasic Two or Four Quadrant Operation (Positive and Negative Power) Gain Select of 1 or 16 on the Current Channel (Channel 1) Choice of On-Chip or External Reference Choice of Output Pulse Frequencies Available (Pins F1 and F2) High Frequency Pulse Output for Calibration Purposes (FOUT ) HPF on Current Channel for Offset Removal Single 5 V Supply and Low Power G1 V1+ V1– x16 Product-to-Frequency Converter AD7750 FUNCTIONAL BLOCK DIAGRAM VDD ACDC ADC1 2ND ORDER MODULATOR HPF ADC2 V2+ V2– x2 REVP DELAY CLKOUT CLKIN MULT 2ND ORDER MODULATOR DTF 2.5V BAND GAP REFERENCE LPF F1 F2 AD7750 REFIN FS S1 S2 DTF FOUT AGND REFOUT DGND GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7750 is a Product-to-Frequency Converter (PFC) that can be configured for power measurement or voltage-tofrequency conversion. The part contains the equivalent of two channels of A/D conversion, a multiplier, a digital-to-frequency converter, a reference and other conditioning circuitry. Channel 1 has a differential gain amplifier with selectable gains of 1 or 16. Channel 2 has a differential gain amplifier with a gain of 2. A highpass filter can be switched into the signal path of Channel 1 to remove any offsets. The outputs F1 and F2 are fixed width (275 ms) logic low going pulse streams for output frequencies less than 1.8 Hz. A range of output frequencies is available and the frequency of F1 and F2 is proportional to the product of V1 and V2. These outputs are suitable for directly driving an electromechanical pulse counter or full stepping two phase stepper motors. The outputs can be configured to represent the result of four-quadrant multiplication (i.e., Sign and Magnitude) or to represent the result of a two quadrant multiplication (i.e., Magnitude Only). In this configuration the outputs are always positive regardless of the input polarities. In addition, there is a reverse polarity indicator output that becomes active when negative power is detected in the Magnitude Only Mode, see Reverse Polarity Indicator. The error as a percent (%) of reading is less than 0.3% over a dynamic range of 1000:1. The AD7750 is fabricated on 0.6 µ CMOS technology; a process that combines low power and low cost. 1. The part can be configured for power measurement or voltage-to-frequency conversion. 2. The output format and maximum frequency is selectable; from low-frequency outputs, suitable for driving stepper motors, to higher frequency outputs, suitable for calibration and test. 3. There is a reverse polarity indicator output that becomes active when negative power is detected in the Magnitude Only Mode. 4. Error as a % of reading over a dynamic range of 1000:1 is < 0.3%. R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997 AD7750–SPECIFICATIONS Parameter ACCURACY Measurement Error1 Gain = 1 Gain = 16 Phase Error Between Channels Phase Lead 40° (PF = +0.8) Phase Lag 60 ° (PF = –0.5) Feedthrough Between Channels Output Frequency Variation (F OUT) Power Supply Rejection Output Frequency Variation (F OUT) ANALOG INPUTS Maximum Signal Levels Input Impedance (DC) Bandwidth Offset Error Gain Error Gain Error Match REFERENCE INPUT REFIN Input Voltage Range Input Impedance ON-CHIP REFERENCE Reference Error Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS FS, S1, S2, ACDC and G1 Input High Voltage, VINH Input Low Voltage, VINL Input Current, I IN Input Capacitance, CIN CLKIN Input High Voltage, VINH Input Low Voltage, VINL LOGIC OUTPUTS2 F1 and F2 Output High Voltage, VOH 4.3 Output Low Voltage, VOL 0.5 FOUT and REVP Output High Voltage, VOH 4 Output Low Voltage, VOL High Impedance Leakage Current High Impedance Capacitance 0.4 ± 10 15 (VDD = 5 V 5%, AGND = 0 V, DGND = 0 V, REFIN = +2.5 V, CLKIN = 3.58 MHz TMIN to TMAX = –40 C to +85 C, ACDC = Logic High) A Version –40 C to +85 C Units Test Conditions/Comments Channel 2 with Full-Scale Signal Measured Over a Dynamic Range on Channel 1 of 500:1 Measured Over a Dynamic Range on Channel 1 of 1000:1 Measured Over a Dynamic Range on Channel 1 of 500:1 Measured Over a Dynamic Range on Channel 1 of 1000:1 CLKIN = 3.58 MHz, Line Frequency = 50 Hz HPF Filter On, ACDC = 1 HPF Filter On, ACDC = 1 HPF Filter On, ACDC = 1, Mode 3, Channel 1 = 0 V Channel 2 = 500 mV rms at 50 Hz HPF Filter On, ACDC = 1, Mode 3, Channel 1 = 0 V Channel 2 = 500 mV rms, Power Supply Ripple 250 mV at 50 Hz. See Figures 1 and 3. On Any Input, V1+, V1–, V2+ and V2–. See Analog Inputs. CLKIN = 3.58 MHz CLKIN = 3.58 MHz, CLKIN/1024 0.2 0.3 0.2 0.4 ± 0.2 ± 0.2 0.0005 0.03 % Reading max % Reading max % Reading max % Reading max Degrees (°) max Degrees (°) max % Full-Scale max % Full-Scale max ±1 400 3.5 ± 10 ±4 ± 0.3 2.7 2.3 50 ± 200 55 4.5 2 V max kΩ min kHz typ mV typ % Full-Scale typ % Full-Scale typ V max V min kΩ min mV max ppm/°C typ MHz max MHz min 2.5 V + 8% 2.5 V – 8% Nominal 2.5 V 2.4 0.8 ± 10 10 4 0.4 V min V max µA max pF max V min V max VDD = 5 V ± 5% VDD = 5 V ± 5% Typically 10 nA, VIN = 0 V to VDD V min V max ISOURCE = 8 mA VDD = 5 V ISINK = 8 mA VDD = 5 V ISOURCE = 1 mA VDD = 5 V ± 5% ISINK = 200 µA VDD = 5 V ± 5% V min V max µA max pF max – 2– REV. 0 AD7750 Parameter POWER SUPPLY VDD IDD 4.75 5.25 5.5 V min V max mA max A Version –40 C to +85 C Units Test Conditions/Comments For Specified Performance, Digital Input @ AGND or V DD 5 V – 5% 5 V + 5% Typically 3.5 mA NOTES 1 See plots in Typical Performance Graphs. 2 External current amplification/drive should be used if higher current source and sink capabilities are required, e.g., bipolar transistor. All specifications subject to change without notice. TIMING CHARACTERISTICS1, 2 Parameter t1 t2 t3 t4 3 t5 t6 3 (VDD = 5 V, AGND = 0 V, DVDD = 0 V, REFIN = REFOUT. All specifications TMIN to TMAX unless otherwise noted.) Test Conditions/Comments F1 and F2 Pulsewidth (Logic Low) Output Pulse Period. See Table I to Determine the Output Frequency Time Between F1 Falling Edge and F2 Falling Edge FOUT Pulsewidth (Logic High) FOUT Pulse Period. See Table I to Determine the Output Frequency Minimum Time Between F1 and F2 Pulse A Version 275 See Table I t2/2 90 See Table I CLKIN/4 Units ms s s ms s s NOTES 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. 2 See Figure 18. 3 The pulsewidths of F1, F2 and F OUT are not fixed for higher output frequencies. See the Digital-to-Frequency Converter (DTF) section for an explanation. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Analog Input Voltage to AGND V1+, V1–, V2+ and V 2– . . . . . . . . . . . . . . . . . . . . –6 V to +6 V Reference Input Voltage to AGND . . . . –0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . . –0.3 V to VDD + 0.3 V Digital Output Voltage to DGND . . . . . –0.3 V to V DD + 0.3 V Operating Temperature Range Commercial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65° C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C 20-Lead SOIC Package, Power Dissipation . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C 20-Lead Plastic DIP, Power Dissipation . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 102°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model AD7750AN AD7750AR Temperature Range –40°C to +85° C –40°C to +85° C Package Description 20-Lead Plastic DIP 20-Lead Wide Body SOIC Package Options N-20 R-20 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7750 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 – 3– AD7750 PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3, 4 Mnemonic VDD G1 V1(+), V1(–) 5 AGND 6, 7 V2(+), V2(–) 8 9 REFOUT REFIN 10 DGND 11 13, 12 14 FS S1, S2 ACDC 15 16 17 CLKIN CLKOUT REVP 18 FOUT 20, 19 F1, F2 Descriptions Power Supply Pin, 5 V nominal ± 5% for specifications. Gain Select, Digital Input. This input selects the gain for the Channel 1 differential input. When G1 is low, the gain is 1 and when G1 is high, the gain is 16. See Analog Inputs section. Channel 1 Differential Inputs. See the Analog Inputs section for an explanation of the maximum input signal ranges. Channel 1 has selectable gains of 1 and 16. The absolute maximum rating is ± 6 V for each pin. The recommended clamp voltage for external protection circuitry is ± 5 V. The Analog Ground reference level for Channels 1 and 2 differential input voltages. Absolute voltage range relative to DGND pin is –20 mV to +20 mV. The Analog Ground of the PCB should be connected to digital ground by connecting the AGND pin and DGND pin together at the DGND pin. Channel 2 Differential Inputs. See the Analog Inputs section for an explanation of the maximum input signal ranges. Channel 2 has a fixed gain of 2. The absolute maximum rating is ± 6 V for each pin. The recommended clamp voltage for external protection circuitry is ± 5 V. Internal Reference Output. The AD7750 can use either its own internal 2.5 V reference or an external reference. For operation with the internal reference this pin should be connected to the REFIN pin. Reference Input. The AD7750 can use either its own internal 2.5 V reference or an external reference. For operation with an external reference, a 2.5 V ± 8%, reference should be applied at this pin. For operation with an internal reference, the REFOUT pin should be connected to this input. For both internal or external reference connections, an input filtering capacitor should be connected between the REFIN pin and Analog Ground. The Ground and Substrate Supply Pin, 0 V. This is the reference ground for the digital inputs and outputs. These pins should have their own ground return on the PCB, which is joined to the Analog Ground reference at one point, i.e., the DGND pin. Frequency Select, Digital Input. This input, along with S1 and S2, selects the operating mode of the AD7750—see Table I. Mode Selection, Digital Inputs. These pins, along with FS, select the operating mode of the AD7750— see Table I. High-Pass Filter Control Digital Input. When this pin is high, the high-pass filter is switched into the signal path of Channel 1. When this pin is low, the high-pass filter is removed. Note when the filter is off there is a fixed time delay between channels; this is explained in the Functional Description section. An external clock can be provided at this pin. Alternatively, a crystal can be connected across CLKIN and CLKOUT for the clock source. The clock frequency is 3.58 MHz for specified operation. When using a crystal, it must be connected across CLKIN and CLKOUT. The CLKOUT can drive only one CMOS load when CLKIN is driven externally. Reverse Polarity, Digital Output. This output becomes active high when the polarity of the signal on Channel 1 is reversed. This output is reset to zero at power-up. This output becomes active only when there is a pulse output on F1 or F2. See Reverse Polarity Indicator section. High-Speed Frequency Output. This is also a fixed-width pulse stream that is synchronized to the AD7750 CLKIN. The frequency is proportional to the product of Channel 1 and Channel 2 or the signal on either channel, depending on the operating mode—see Table I. The output format is an active high pulse approximately 90 ms wide—see Digital-to-Frequency Conversion section. Frequency Outputs. F1 and F2 provide fixed-width pulse streams that are synchronized to the AD7750 CLKIN. The frequency is proportional to the product of Channel 1 and Channel 2—see Table I. The output format is an active low pulse approximately 275 ms wide—see Digital-to-Frequency Conversion section. –4– REV. 0 AD7750 PIN CONFIGURATION SOIC and DIP VDD 1 G1 2 V1+ 3 V1– 4 AGND 5 20 F1 19 F2 18 FOUT 17 REVP AD7750 16 CLKOUT TOP VIEW 15 CLKIN V2+ 6 (Not to Scale) V2– 7 14 ACDC REFOUT 8 REFIN 9 DGND 10 13 S1 12 S2 11 FS Typical Performance Characteristics 140 120 AS PER DATA SHEET CONDITIONS WITH GAIN = 1 120 AS PER DATA SHEET CONDITIONS WITH GAIN = 16 100 100 80 dBs 80 dBs 60 40 20 0 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 50Hz RIPPLE – V rms 0.6 0.7 0.8 0 0.01 0.02 0.03 0.04 0.05 0.06 50Hz RIPPLE – V rms 0.07 0.08 0.09 Figure 1. PSR as a Function of V DD 50 Hz Ripple Figure 3. PSR as a Function of VDD 50 Hz Ripple 0.6 0.4 0.2 0 –0.2 Degrees –0.4 –0.6 –0.8 45 46 47 48 49 50 51 52 LINE FREQUENCY – Hz 53 54 55 Figure 2. Phase Error as a Function of Line Frequency REV. 0 –5– AD7750 0.1 0.05 0.4 ERROR – % of Reading 0 ERROR – % of Reading –0.05 –0.1 –0.15 –0.2 –0.25 –0.3 0.001 VDD = 5V V2 = FULL SCALE 0.2 VDD = 5.25V 0.6 0 VDD = 5.00V –0.2 –0.4 VDD = 4.75V –0.6 100 0.01 0.1 1.0 V1 AMPLITUDE – mV rms 10 101 102 V1 AMPLITUDE – mV rms 103 Figure 4. Error as a Percentage (%) of Reading Over a Dynamic Range of 1000, Gain = 1 Figure 6. Measurement Error vs. Input Signal Level and Varying VDD with Channel 1, Gain = 1 0 –0.05 –0.1 ERROR – % of Reading ERROR – % of Reading –0.15 –0.2 –0.25 –0.3 –0.35 –0.4 –0.45 –0.5 0.0001 VDD = 5V V2 = FULL SCALE 0.8 0.6 0.4 0.2 0 –0.2 –0.4 VDD = 4.75V –0.6 VDD = 5.25V VDD = 5.00V 0.001 0.01 V1 AMPLITUDE – mV rms 0.1 10–2 10–1 100 V1 AMPLITUDE – mV rms 101 102 Figure 5. Error as a Percentage (%) of Reading Over a Dynamic Range of 1000, Gain = 16 Figure 7. Measurement Error vs. Input Signal Level and Varying VDD with Channel 1, Gain = 16 –6– REV. 0 AD7750 ANALOG INPUTS The analog inputs of the AD7750 are high impedance bipolar voltage inputs. The four voltage inputs make up two truly differential voltage input channels called V1 and V2. As with any ADC, an antialiasing filter or low-pass filter is required on the analog input. The AD7750 is designed with a unique switched capacitor architecture that allows a bipolar analog input with a single 5 V power supply. The four analog inputs (V1+, V1–, V2+, V2–) each have a voltage range from –1.0 V to +1.0 V. This is an absolute voltage range and is relative to the ground (AGND) pin. This ground is nominally at a potential of 0 V relative to the board level ground. Figure 8 shows a very simplified diagram of the analog input structure. When the analog input voltage is sampled, the switch is closed and a very small sampling capacitor is charged up to the input voltage. The resistor in the diagram can be thought of as a lumped component made up of the on resistance of various switches. R 1.4k C 2pF SAMPLING CAPACITOR In Figure 12, Channel 1 has a peak voltage on V1+ and V1– of ± 1 V. These signals are not gained (G1 = 0) and so the differential signal presented to the modulator is ± 2 V. However, Channel 2 has an associated gain of two and so care must be taken to ensure the modulator input does not exceed ± 2 V. Therefore, the maximum signal voltage that can appear on V2+ and V2– is ± 0.5 V. The difference between single-ended and complementary differential input schemes is shown in the diagram below, Figure 9. For a single-ended input scheme the V– input is held at the same potential as the AGND Pin. The maximum voltages can then be applied to the V+ input are shown in Figures 10 and 11. An example of this input scheme uses a shunt resistor to convert the line current to a voltage that is then applied to the V1+ input of the AD7750. An example of the complementary differential input scheme uses a current transformer to convert the line current to a voltage that is then applied to V1+ and V 1–. With this scheme the voltage on the V+ input is always equal to, but of opposite polarity to the voltage on V–. The maximum voltage that can be applied to the inputs of the AD7750 using this scheme is shown in Figures 12 and 13. Note that the common mode of the analog inputs must be driven. The output terminals of the CT are, therefore, referenced to ground. V+ VIN Figure 8. Equivalent Analog Input Circuit Analog Inputs Protection Circuitry The analog input section also has protection circuitry. Since the power supply rails are 0 V to 5 V, the analog inputs can no longer be clamped to the supply rails by diodes. Thus, the internal protection circuitry monitors the current paths during a fault condition and protects the device from continuous overvoltage, continuous undervoltage and ESD events. The maximum overvoltage the AD7750 analog inputs can withstand without causing irreversible damage is ± 6 V relative to AGND pin. In the case of continuous overvoltage and undervoltage the series resistance of the antialiasing filter can be used to limit input current. The total input current in the case of a fault should be limited to 10 mA. For normal operation of the AD7750 there are two further restrictions on the signal levels presented to the analog inputs. 1. The voltage on any input relative to the AGND pin must not exceed ± 1 V. 2. The differential voltage presented to the ADC (Analog Modulator) must not exceed ± 2 V. V– A CURRENT TRANSFORMER PROVIDES COMPLEMENTARY DIFFERENTIAL INPUTS TO THE AD7750 V+ SHUNT RESISTOR A CURRENT SENSE RESISTOR PROVIDES A SINGLE-ENDED INPUT TO THE AD7750 V– Figure 9. Examples of Complementary and SingleEnded Input Schemes REV. 0 –7– AD7750 1V MAX V1+ = 1V MAX X1 V1– = AGND FOUT DTF F1 2V MAX F2 V2+ = 1V MAX X2 V2– = AGND 2V ADC 1V ADC Figure 10. Maximum Input Signals with Respect to AGND for a Single-Ended Input Scheme, G1 = 0 2V MAX V1+ = 125mV MAX X16 V1– = AGND FOUT DTF 2V MAX V2+ = 1V MAX X2 V2– = AGND 2V ADC F1 F2 2V ADC Figure 11. Maximum Input Signals with Respect to AGND for a Single-Ended Input Scheme, G1 = 1 1V MAX V+ = 1V MAX X1 V– = 1V MAX 1V MAX DTF F1 1V MAX F2 V+ = 0.5V MAX X2 V– = 0.5V MAX 1V MAX 2V ADC FOUT 2V ADC Figure 12. Maximum Input Signals for a Complementary Input Scheme, G1 = 0 1V MAX V+ = 62.5V MAX X16 V– = 62.5V MAX 1V MAX DTF 1V MAX V+ = 0.5V MAX X2 V– = 0.5V MAX 1V MAX 2V ADC F1 F2 FOUT 2V ADC Figure 13. Maximum Input Signals for a Complementary Input Scheme, G1 = 1 –8– REV. 0 AD7750 DETERMINING THE OUTPUT FREQUENCIES OF THE AD7750 FOUT, F1 and F2 are the frequency outputs of the AD7750. The output frequencies of the AD7750 are a multiple of a binary fraction of the master clock frequency CLKIN. This binary fraction of the master clock is referred to as FMAX in this data sheet. FMAX can have one of two values, FMAX1 and FMAX2, depending on which mode of operation the AD7750 is in. The operating modes of the AD7750 are selected by the logic inputs FS, S2 and S1. The table below outlines the FMAX frequencies and the transfer functions for the various operating modes of the AD7750. Table I. Operating Mode Mode 0 FS 0 S2 0 S1 0 Mode Description Power Measurement Mode. Four Quandrant Multiplication (Sign and Magnitude Output). Power Measurement Mode. Two Quandrant Multiplication (Magnitude Only). Power Measurement Mode. Two Quandrant Multiplication (Magnitude Only). V1 Channel Monitor Mode on FOUT. Power Measurement Mode on F1, F2 (Sign and Magnitude Output). Power Measurement Mode. Four Quandrant Multiplication (Sign and Magnitude Output). Power Measurement Mode. Two Quandrant Multiplication (Magnitude Only). Power Measurement Mode. Two Quandrant Multiplication (Magnitude Only). V2 Channel Monitor Mode on FOUT. Power Measurement Mode on F1, F2 (Sign and Magnitude Output). F1, F21 (Hz) FMAX1 ± k.FMAX1 FOUT1 (Hz) 16.[FMAX1 ± k.FMAX1] FMAX FMAX1 = CLKIN/219 FMAX1 = 6.8 Hz FMAX1 = CLKIN/219 FMAX1 = 6.8 Hz FMAX1 = CLKIN/219 FMAX1 = 6.8 Hz FMAX1 = CLKIN/219 FMAX1 = 6.8 Hz FMAX2 = CLKIN/218 FMAX2 = 13.6 Hz FMAX2 = CLKIN/218 FMAX2 = 13.6 Hz FMAX2 = CLKIN/218 FMAX2 = 13.6 Hz FMAX2 = CLKIN/218 FMAX2 = 13.6 Hz 1 0 0 1 0 to k.FMAX1 8.[0 to k.FMAX1] 2 0 1 0 0 to k.FMAX1 16.[0 to k.FMAX1] 32 0 1 1 FMAX1 ± k.FMAX1 32.[FMAX1 ± k2.FMAX1] 4 1 0 0 FMAX2 ± k.FMAX2 16.[FMAX2 ± k.FMAX2] 5 1 0 1 0 to k.FMAX2 16.[0 to k.FMAX2] 6 1 1 0 0 to k.FMAX2 32.[0 to k.FMAX2] 72 1 1 1 FMAX2 ± k.FMAX2 16.[FMAX2 ± k2.FMAX2] NOTES 1 The variable k is proportional to the product of the rms differential input voltages on Channel 1 and Channel 2 (V 1 and V2). k = (1.32 × V1 × V2 × Gain)/V REF2 2 Applies to F OUT only. The variable k is proportional to the instantaneous differential input voltage on Channel 1 (FS = 0, S1 = 1, S0 = 1) or the instantaneous differential voltage on Channel 2 (FS = 1, S1 = 1, S0 = 1), i.e., Channel Monitor Mode. k = (0.81 × V)/V REF V = V 1 × Gain or V = V2 × 2 NOTE: V1 and V 2 here refer to the instantaneous differential voltage on Channel 1 or Channel 2, not the rms value. Mode Description (Table I) The section of Table I labeled Mode Description summarizes the functional modes of the AD7750. The AD7750 has two basic modes of operation, i.e., four and two quadrant multiplication. The diagram in Figure 14 is a graphical representation of the transfer functions for two and four quadrant multiplication. Four Quadrant Multiplication (Modes 0, 3, 4 and 7) When the AD7750 is operating in its four quadrant multiplication mode the output pulse frequency on F1, F2 and FOUT contains both sign and magnitude information. The magnitude information is indicated by the output frequency variation (k.FMAX) from a center frequency (FMAX). The sign information is indicated by the sign of the frequency variation around FMAX. For example if the output frequency is equal to FMAX – k.FMAX then the magnitude of the product is given by k.FMAX and it has a negative sign. Two Quadrant Multiplication (Modes 1, 2, 5 and 6) quadrant multiplication the magnitude information is included in the output frequency variation (k.FMAX). However, in this mode the zero power frequency is 0 Hz, so the output frequency variation is from 0 Hz to (k.FMAX) Hz. Also note that a no-load threshold and the reverse polarity indicator are implemented in these modes see No Load Threshold and Reverse Polarity Indicator sections. These modes are the most suitable for a Class 1 meter implementation. Channel Monitor Modes (Modes 3 and 7) In this mode of operation the FOUT pulse frequency does not give product information. When FS = 0, the FOUT output frequency gives sign and magnitude information about the voltage on Channel 1. When FS = 1 the FOUT output frequency gives sign and magnitude information about the voltage on Channel 2. Note the F1, F2 pulse outputs still continue to give power information. When operating in this mode the output pulse frequency only contains magnitude information. Again as in the case of four REV. 0 –9– AD7750 FOUR QUADRANT MULTIPLICATION (SIGN AND MAGNITUDE) V2(+) TWO QUADRANT MULTIPLICATION ( MAGNITUDE ONLY) V2(+) FMAX – k (–) FMAX FMAX + k (+) FMAX k FMAX (+) k FMAX (+) V1(–) 0 V1(+) V1(–) V1(+) FMAX + k (+) FMAX FMAX _ k (–) FMAX k FMAX (+) k FMAX (+) V2(–) K= (1.32 V1 V2 GAIN) V2(–) VREF2 Figure 14. Transfer Functions (Four and Two Quadrant Multiplication) Maximum Output Frequencies Table II shows the maximum output frequencies of FOUT and F1, F2 for the various operating modes of the AD7750. The table shows the maximum output frequencies for dc and ac input signals on V1 and V2. When an ac signal (sinusoidal) is applied to V1 and V2 the AD7750 produces an output frequency which is proportional to the product of the rms value of these inputs. If two ac signals with peak differential values of V1MAX and V2MAX are applied to Channels 1 and 2, respectively, then the output frequency is proportional to V1MAX/sqrt(2) × V2MAX/ sqrt(2) = (V1MAX × V2MAX)/2. If V1MAX and V2MAX are also the maximum dc input voltages then the maximum output frequencies for ac signals will always be half that of dc input signals. Example calculation of F1, F2 max for Mode 2 and Gain = 1. The maximum input voltage (dc) on Channel 1 is 2 V (V1+ = +1 V, V1– = –1 V)—see Analog Inputs section. The maximum input voltage on Channel 2 is 1 V. Using the transfer function: k = (1.32 × V1 × V2 × Gain)/V k = 0.4224 F1, F2 = k.6.8 Hz = 2.9 Hz FUNCTIONAL DESCRIPTION 2 REF reason great care must be taken when interfacing the analog inputs of the AD7750 to the transducer. This is discussed in the Applications section. HPF in Channel 1 To remove any dc offset that may be present at the output modulator 1, a user selectable high-pass IIR filter (Pin ACDC) can be introduced into the signal path. This HPF is necessary when carrying out power measurements. However, this HPF has an associated phase lead given by 90°–tan–1(f/2.25). Figure 16 shows the transfer function of the HPF in Channel 1. The Phase lead is 2.58° at 50 Hz. In order to equalize the phase difference between the two channels a fixed time delay is introduced. The time delay is set at 143 µs, which is equivalent to a phase lag of –2.58° at 50 Hz. Thus the cumulative phase shift through Channel 1 is 0° . Because the time delay is fixed, external phase compensation circuitry will be required if the line frequency differs from 50 Hz. For example with a line frequency of 60 Hz the phase lead due to the HPF is 2.148° and the phase lag due to the fixed time delay is 3.1°. This means there is a net phase lag in Channel 1 of 0.952°. This phase lag in Channel 1 can be compensated for by using a phase lag compensation circuit like the one shown in Figure 17. The phase lag compensation is placed on Channel 2 (voltage channel) to equalize the channels. The antialiasing filter associated with Channel 1 (see Applications section) produces a phase lag of 0.6° at 50 Hz; therefore, to equalize the channels, a net phase lag of (0.6° + 0.952° ) 1.552° should be in place on Channel 2. The gain trim resistor VR1 (100 Ω) produces a phase lag variation of 1.4° to 1.5° with VR2 = 0 Ω. VR2 can add an additional 0.1° phase lag (VR2 = 200 Ω). The AD7750 combines two analog-to-digital converters, a digital multiplier, digital filters and a digital-to-frequency (DTF) converter onto one low cost integrated circuit. The AD7750 is fabricated on a double poly CMOS process (0.6 µ) and retains its high accuracy by performing all multiplications and manipulations in the digital domain. The schematic in Figure 15 shows an equivalent circuit for the AD7750 signal processing chain. The first thing to notice is that the analog signals are first converted to digital signals by the two second-order sigma-delta modulators. All subsequent signal processing is carried out in the digital domain. The main source of errors in an application is therefore in the analog-to-digital conversion process. For this –10– REV. 0 AD7750 Table II. Maximum Output Frequencies Mode 0 1 2 3 4 5 6 7 G1 HPF FS S2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 S1 0 1 0 1 0 1 0 1 ACDC F1, F2 (Hz) (DC) 6.8 ± 2.9 0 to 2.9 0 to 2.9 6.8 ± 2.9 13.6 ± 5.8 0 to 5.8 0 to 5.8 13.6 ± 5.8 FOUT (Hz) (DC) 109 ± 46 0 to 23 0 to 46 218 ± 142 218 ± 92 0 to 92 0 to 184 218 ± 142 F1, F2 (Hz) (AC) 6.8 ± 1.45 0 to 1.45 0 to 1.45 6.8 ± 1.45 13.6 ± 2.9 0 to 2.9 0 to 2.9 13.6 ± 2.9 FOUT (Hz) (AC) 109 ± 23 0 to 11.5 0 to 23 218 ± 142 218 ± 46 0 to 46 0 to 92 218 ± 142 TIME DELAY 143 s (CLKIN = 3.5795MHz) 2.58 C AT 50Hz DIGITAL-TO-FREQUENCY BLOCK COUNTER/ACCUMULATOR V1+ V1– PGA ADC 1 τ LPF PHASE LEAD OF 2.58 C AT 50Hz DIGITAL MULTIPLIER CLKIN FOUT DTF F1 F2 V2+ X2 V2– ADC 2 FS S2 S1 Figure 15. Equivalent AD7750 Signal Processing Chain H(s) = sRC 1 + sRC Digital-to-Frequency Converter (DTF) C R R = 1M C = 0.0707 F Figure 16. HPF in Channel 1 R1 1M VR1 100 R3 1.1k 860:1 ATTENUTATION C1 47nF R2 33k R4 1.1k PIN 6 C3 33 F VR2 200 PIN 7 C2 33nF After they have been filtered, the outputs of the two sigma-delta modulators are fed into a digital multiplier. The output of the multiplier is then low-pass filtered to obtain the real power information. The output of the LPF enters a digital-to-frequency converter whose output frequency is now proportional to the real power. The DTF offers a range of output frequencies to suit most power measurement applications. There is also a high frequency output called FOUT , which can be used for calibration purposes. The output frequencies are determined by the logic inputs FS, S2 and S1. This is explained in the section of this data sheet called Determining the Output Frequencies of the AD7750. Figure 18 shows the waveforms of the various frequency outputs. The outputs F1 and F2 are the low frequency outputs that can be used to directly drive a stepper motor or electromechanical pulse counter. The F1 and F2 outputs provide two alternating low going pulses. The pulsewidth is set at 275 ms and the time between the falling edges of F1 and F2 is approximately half the period of F1. If, however, the period of F1 and F2 falls below 550 ms (1.81 Hz) the pulsewidth of F1 and F2 is set to half the period. For example in Mode 3, where F1 and F2 vary around 6.8 Hz, the pulsewidth would vary from 1/2.(6.8+1.45) seconds to 1/2.(6.8–1.45) seconds—see Table II. Figure 17. Phase Lag Compensation on Channel 1 for 60 Hz Line Frequency REV. 0 –11– AD7750 The high frequency FOUT output is intended to be used for communications (via IR LED) and calibration purposes. FOUT produces a 90 ms wide pulse at a frequency that is proportional to the product of Channel 1 and Channel 2 or the instantaneous voltage on Channel 1 or Channel 2. The output frequencies are given in Table I in the Determining the Output Frequencies of the AD7750 section of this data sheet. As in the case of F1 and F2, if the period of FOUT falls below 180 ms, the FOUT pulsewidth is set to half the period. For example, if the FOUT frequency is 20 Hz, the FOUT pulsewidth is 25 ms. t1 VDD F1 meter accuracy with small load currents. Hence an error of less than 1% from 4% Ib to 400% Ib will be easier to achieve. We will assume the design of a Class 1 meter. The specification (IEC1036) requires that the meter have an error of no greater than 1% over the range 4% Ib to 400% Ib (IMAX), where Ib is the basic current1. In addition, we will design a meter that accommodates signals with a crest factor of 2. The crest factor is the ratio of VPEAK/V rms. A pure sinusoidal waveform has a crest of sqrt(2) = 1.414 and an undistorted triangular waveform has a crest factor of sqrt(3) = 1.73. Using a gain of 1 on Channel 1 the maximum differential signal which can be applied to Channel 1 is ± 2 V—See Analog Input Ranges section. With a crest factor of 2 the maximum rms signal on Channel 1 is, therefore, 1 V rms (equivalent to IMAX). The smallest signal (4% Ib) appearing on Channel 1 is therefore 10 mV rms. Load Current 4% Ib Ib 400 Ib 2 400% Ib CHANNEL 1 INPUT SIGNAL – Vrms 1 t6 t2 0V VDD F2 t3 0V t4 FOUT t5 VDD 0V Channel 1 10 mV rms 250 mV rms 1 V rms Figure 18. Timing Diagram for Frequency Outputs VOLTAGE REFERENCE The AD7750 has an on-chip temperature compensated bandgap voltage reference of 2.5 V with a tolerance of ± 250 mV. The temperature drift for the reference is specified at 50 ppm/°C. It should be noted that this reference variation will cause a frequency output variation from device to device for a given set of input signals. This should not be a problem in most applications since it is a straight gain error that can easily be removed at the calibration stage. REVERSE POLARITY INDICATOR 0. 2 0. 02 4% Ib 0.01 0. 002 When the AD7750 is operated in a Magnitude Only mode of operation (i.e., Modes 1, 2, 5 and 6), and the polarity of the power changes, the logic output REVP will go high. However, the REVP pin is only activated when the there is pulse output on F1 or F2. Therefore, if the power being measured is low, it may be some time before the REVP pin goes logic high even though the polarity of the power is reversed. Once activated the REVP output will remain high until the AD7750 is powered down. APPLICATIONS INFORMATION Designing a Single Phase Class 1 Energy Meter (IEC 1036) Figure 19. Use the Upper End of the Dynamic Range of Channel 1 (Current) Calculations for a 100 PPKWHR Meter The AD7750 Product-to-Frequency Converter is designed for use in a wide range of power metering applications. In a typical power meter two parameters are measured (i.e., line voltage and current) and their product obtained. The real power is then obtained by low-pass filtering this product result. The line voltage can be measured through a resistor divider or voltage transformer, and the current can be sensed and converted to a voltage through a shunt resistor, current transformer or hall effect device. The design methodology used in the following example is to use the upper end of the current channel dynamic range, i.e., Channel 1 of the AD7750. The assumption here is that the signal on the voltage channel will remain relatively constant while the signal on the current channel will vary with load. Using the upper end of the dynamic range of Channel 1 will improve the 1 The AD7750 offers a range of maximum output frequencies— see Table I and Table II. In the Magnitude Only modes of operation the two maximum output frequencies are 1.45 Hz and 2.9 Hz. The signal on the voltage channel (Channel 2) is scaled to achieve the correct output pulse frequency for a given load (e.g., 100 PPKWHR). The relationship between the input signals and the output frequency is given by the equation: Freq = k × FMAX where k = (1.32 × V1 × V2 × Gain)/VREF2 FMAX = 6.8 Hz or 13.6 Hz depending on the mode—see Table I, Gain is the gain of Channel 1, V1 and V2 are the differential voltages on Channels 1 and 2 and VREF is the reference voltage (2.5 V ± 8%). To design a 100 PPKWHR meter with Ib = 15 A rms and a line voltage of 220 V rms the output pulse frequency with a load current of Ib is 0.0916 Hz (See Calculation 1 below). Therefore, 0.0916 Hz = k × 6.8 Hz (Mode 2) or k = 0.01347. With a load current of Ib the signal on Channel 1 (V1) is equal to 0.25 V rms (remember 400% Ib = 1 V rms) and, therefore, the signal on Channel 2 (V2) is equal to 0.255 V rms (See Calculation 2). This means that the nominal line voltage (220 V rms) needs to be attenuated by approximately 860, i.e., 220/0.255. REV. 0 See IEC 1036 2nd Edition 1996-09 Section 3.5.1.1. –12– AD7750 For 100 PPKWHR V2 is equal to 0.255 V rms or the line voltage attenuated by a factor of 860. Calculation 1 Antialiasing Components Channels 1 and 2 100 PPKWHR = 0.02777 Hz/kW. Ib of 15 A rms and line voltage of 220 V = 3.3 kΩ. Hence, the output frequency is given by 3.3 × 0.02777 Hz = 0.0916 Hz. k = (1.32 × V1 × V2 × Gain)/VREF2. 0.01347 = (1.32 × 0.25 × V2 × 1)/6.25. V2 = 0.255. Figure 21 below shows how the design equations from the previous page are implemented. Measuring the Load Current Calculation 2 The AD7750 is basically two ADCs and a digital multiplier. As with any ADC, a LPF (Low-Pass Filter) should be used on the analog inputs to avoid out of band signal being aliased into the band of interest. In the case of a Class 1 meter the band of interest lies in the range 48 Hz to 1 kHz approximately. The components R3, R4, R6, R7, C5, C6, C9 and C10 make up the LPFs on each of the four analog inputs. Note that although Channel 2 is used single ended a LPF is still required on V2–. Power Supply Circuit The load current is converted to a voltage signal for Channel 1 using a CT (Current Transformer). A 15 A rms load should produce a 250 mV rms signal on Channel 1. A CT with a turns ratio of 120 and a shunt resistor of 2 Ω. will carry out the necessary current to voltage conversion. The CT and its shunt resistance should be placed as close as possible to the AD7750. This will improve the accuracy of the meter at very small load currents. At small load currents the voltage levels on Channel 1 are in the order of 10 mV and the meter is more prone to error due to stray signal “pick up.” When measuring power the HPF in the current channel must be switched on. This is done by connecting the ACDC pin to VDD . NOTE: The voltage signals on V1+ and V1– must be referenced to ground. This can be achieved as shown in Figure 21 below, i.e., by referencing 1/2 RCT to ground or by connecting a centertap on the CT secondary to ground. Measuring the Line Voltage The AD7750 operates from a single power supply of 5 V ± 5% but still accommodates input signals in the range ± 1 V. Because the AD7750 doesn’t require dual supplies the number of external components for the power supply is reduced. One of the most important design goals for the power supply is to ensure that the ripple on the output is as low as possible. Every analog or mixed signal IC is to a greater or lesser extent susceptible to power supply variations. Power supply variations or ripple, if large enough, may affect the accuracy of the device when measuring small signals. The plot in Figure 20 shows the ripple associated with the circuit in Figure 21. The ripple is in the region of 10 mV peak to peak. 5.065 5.060 VOLTS 5.055 5.050 600 When the AD7750 is biased around the live wire as shown in Figure 21, the task of measuring the line voltage is greatly simplified. A resistor divider attenuates the line voltage and provides a single-ended input for Channel 2. The component values of the divider are chosen to give the correct rating (e.g., 100 PPKWHR) for the meter. See the design equations on the previous page. For this design an attenuation ratio of 860:1 is required. R4 LOAD 1/2 RCT 1 1/2 RCT 1 C5 C7 CT 120:1 C8 2 3 620 640 660 680 700 720 ms 740 760 780 800 TIME Figure 20. Power Supply Ripple VDD 1 20 M PULSE COUNTER 19 R8 18 17 D4 D3 D5 R3 C6 4 5 IR DIODE FOR CALIBRATION R9 R5 6 AD7750 16 C4 C3 VDD REVERSE POLARITY INDICATOR XTAL 3.57954MHz VR1 NEUTRAL PHASE R6 * C1 R1 D1 D2 MOV SOURCE C9 R7 7 TOP VIEW 15 (Not to Scale) 14 13 12 11 C10 8 9 C11 R2 VDD C2 Z1 C12 10 VDD MODE2 *BIASING AROUND THE LIVE WIRE PATENTED BY SCHLUMBERGER. Figure 21. Suggested Class 1 Meter Implementation REV. 0 –13– AD7750 Registering the Power Output The low frequency pulse outputs (F1 and F2) of the AD7750 provide the frequency output from the product-to-frequency conversion. These outputs can be used to drive a stepper motor or impulse counter. A high frequency output is available at the pin FOUT. This high frequency output is used for calibration purposes. In Mode 2 the output frequency is 16 × F1(2). With a load current of Ib the frequency at FOUT will be 1.4656 Hz (0.0916 Hz × 16 from calculations). If a higher frequency output is required, the FS pin can be set to VDD 5 V for calibration. In this case the output frequency is equal to 64 × F1 or 5.8624 Hz at Ib—see Table I. NO LOAD THRESHOLD OF THE AD7750 This is equivalent to a line current of: (37.95 µV/2 Ω ) × 120 = 2.27 mA rms or 0.5 W or (2.27 mA/15 A) × 100% = 0.015% of Ib . NOTE: The no load threshold as a percentage of Ib will be different for each value of Ib since the no load in watts is fixed: FS = 0, the no load threshold is (FMAX = 6.8 Hz) 0.5 Watts for a 100 PPKWHR meter 5 Watts for a 10 PPKWHR meter FS = 1, the no load threshold is (FMAX = 13.6 Hz) 1 Watt for a 100 PPKWHR meter 10 Watts for a 10 PPKWHR meter FMIN = 1.32 × V1 × V2 × Gain × 6.8 Hz) VREF2 1.39 × 10–5 Hz = V1 × 0.2555 × 1 × 6.8)/6.25 V1 = 37.95 µV EXTERNAL LEAD/LAG COMPENSATION Calculation 3 The AD7750 will detect when the power drops below a certain level. When the power (current) drops below a predefined threshold the AD7750 will cease to generate an output drive for the stepper motor (F1, F2). This feature of the AD7750 is intended to reproduce the behavior of Ferraris meters. A Ferraris meter will have friction associated with the wheel rotation, therefore the wheel will not rotate below a certain power level. The no load threshold is only implemented in the Magnitude Only modes (Modes 1, 2, 5 and 6—see Table I). The IEC1036 specification includes a test for this effect by requiring no output pulses during some predetermined time period. This time period is calculated as: time period = 60,000/pulses-per-minute If a meter is calibrated to 100 PPKWHR with a FOUT running 16 times faster than F1 and F2, this time period is 37.5 minutes (60,000/1,600). The IEC1036 specifications state that the no load threshold must be less than the start up current level. This is specified as 0.4% of Ib. The threshold level for a given design can be easily calculated given that the minimum output frequency of the AD7750 is 0.00048% of the maximum output frequency for a full-scale differential dc input. For example if FS = 0, the maximum output frequency for a full-scale dc input is 2.9 Hz (see Table II) and the minimum output frequency is, therefore, 1.39 × 10–5 Hz. Calculating the Threshold Power (Current) External phase compensation is often required in a power meter design to eliminate the phase errors introduced by transducers and external components. The design restriction on any external compensating network is that the network must have an overall low-pass response with a 3 dB point located somewhere between 5 kHz and 6 kHz. The corner frequency of this LPF(s) is much higher than the band of interest. The reason for this is to minimize its effect on phase variation at 50 Hz due to component tolerances. With the antialiasing filters on all channels having the same corner (–3 dB) frequency, the main contribution to phase error will be due to the CT. A phase lead in a channel is compensated by lowering the corner frequency of the antialiasing filter to increase its associated lag and therefore cancel the lead. A phase lag in a channel should be compensated by introducing extra lag in the other channel. This can be done as previously described, i.e., moving the corner frequency of the antialiasing filters. The result in this case is that the signal on both channels has the same amount of phase lag and is therefore in phase at the analog inputs to the AD7750. The recommended RC values for the antialiasing filters on the voltage and current channels (see Antialiasing Components Channels 1 and 2) are R = 1 kΩ, C = 33 nF and R = 100 Ω, C = 330 nF respectively. These values produce a phase lag of 0.6° through the filters. Varying R in the antialiasing network from 80 Ω to 100 Ω or 800 Ω to 1 kΩ produces a phase variation from 0.475° to 0.6° at 50 Hz. This allows the user to vary the lag by 0.125°. The meter used in this example is calibrated to 100 PPKWHR, has an Ib (basic current) of 15 A rms, the line voltage is 220 V rms and the turns ratio of the CT on Channel 1 is 120:1 with an 2 Ω shunt resistor. The nominal voltage on Channel 2 of the AD7750 is 255 mV rms. An FMAX of 6.8 Hz is selected by setting FS = 0. A Magnitude Only Mode (Mode 2) is selected to enable the no load threshold. The gain on Channel 1 is set to 1. The threshold power or current can be found by using the transfer function in Table I. F1, F2 = (1.32 × V1 × V2 × Gain × FMAX)/VREF2 From the transfer function V1 is calculated as 37.95 µV rms— see Calculation 3. –14– REV. 0 AD7750 Table III. Components for Suggested Class 1 Meter Implementation in Figure 21 Schematic Designator R1 R2 R3, R4, R7 R5 R6 R8, R9 VR1 C1 C2 C3, C4 C5, C6, C9, C10 C7, C11 C8, C12 Z1 D1, D2 D3 D4, D5 XTAL MOV Description 470 Ω, 5%, 1 W 1 kΩ, 5%, 1/2 W 100 Ω, 10%, 1/2 W 1 kΩ, 10%, 1/2 W 1 MΩ, 5%, 2 W 1.1 kΩ, 5%, 1/2 W 500 Ω, 10%, 1/2 W 100 Ω, 10/15 Turn 470 nF, 250 V ac 100 µF, 24 V dc 33 pF 330 nF 33 nF 10 µF, 10 V 10 nF 1N750 1N4007 LED IR LEDS 3.579545 MHz V250PA40A Comments These registers are required to form part of the antialiasing filtering on the analog inputs; they do not perform a voltage-to-current conversion. The choice of R5 determines the attenuation on the voltage channels and hence the meter rating, e.g., 100 PPKWHR. Forms part of the Gain Calibration network with R5 and VR1. This potentiometer is used to perform the Gain Calibration of the meter. Attenuation of 830 to 900—see Applications section. Forms part of the antialiasing filters on the analog inputs. Metal Oxide Varistor–Harris Semiconductor. REV. 0 –15– AD7750 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Plastic DIP (N-20) 1.060 (26.90) 0.925 (23.50) 20 1 11 10 0.280 (7.11) 0.240 (6.10) PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.070 (1.77) SEATING 0.045 (1.15) PLANE 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 20-Lead Wide Body SOIC (R-20) 0.5118 (13.00) 0.4961 (12.60) 20 11 1 10 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) 0.0291 (0.74) x 45° 0.0098 (0.25) 0.0118 (0.30) 0.0040 (0.10) 8° 0.0500 0.0192 (0.49) 0° (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE BSC 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) –16– REV. 0 PRINTED IN U.S.A. C3156–8–10/97