AD7768-1BCPZ-RL7

DC to 204 kHz, Dynamic Signal Analysis, Precision 24-Bit ADC with Power Scaling AD7768-1 Data Sheet FEATURES Power supply AVDD1 − AVSS = 5.0 V typical AVDD2 − AVSS = 2.0 V to 5.0 V typical Analog supplies can run from split supply (true bipolar) IOVDD − DGND = 1.8 V to 3.3 V typical Low power mode can run from single 3.0 V supply Pin control or SPI interface configurable Suite of diagnostic check mechanisms Temperature, interface CRC, and memory map CRC Package: 28-lead, 4 mm × 5 mm, LFCSP Temperature range: −40°C to +125°C ADC for single-channel low power, platform DAQ designs Wide bandwidth Sinc filter bandwidth range: DC to 204 kHz Low ripple FIR bandwidth range: DC to 110.8 kHz Precision ac and dc performance 108.5 dB dynamic range typical −120 dB THD ±1.1 ppm of FSR INL, ±30 µV offset error, ±30 ppm of FSR gain error Programmable ODR, filter type, and latency ODR values up to 1024 kSPS Linear phase digital filter options Low ripple FIR filter: ±0.005 dB maximum pass-band ripple, dc to 102.4 kHz Low latency sinc5 filter Low latency sinc3 filter enabling 50 Hz/60 Hz rejection Programmable FIR filter option Programmable power consumption and bandwidth Fast, highest speed 52.224 kHz bandwidth, 26.4 mW (sinc5 filter) 110.8 kHz bandwidth, 36.8 mW (FIR filter) Median, half speed: 55.4 kHz bandwidth, 19.7 mW (FIR filter) Low power, low speed: 13.9 kHz bandwidth, 6.75 mW (FIR filter) APPLICATIONS Platform ADC to serve a superset of measurements and sensor types Sound and vibration, acoustic, and material science research and development Control and hardware in loop verification Condition monitoring for predictive maintenance Electrical test and measurement Audio testing and current and voltage measurement Clinical electroencephalogram (EEG), electromyogram (EMG), and electrocardiogram (ECG) vital signs monitoring USB-, PXI-, and Ethernet-based modular DAQ Channel to channel isolated modular DAQ designs FUNCTIONAL BLOCK DIAGRAM AVDD1 REF+ REF– DGND AVDD2 REGCAPA REGCAPD IOVDD AD7768-1 SYNC_IN 1.8V LDO REFERENCE BUFFERS 1.8V LDO WIDEBAND LOW RIPPLE FILTER AIN+ POWER SCALABLE Σ-Δ ADC AIN– AVSS SINC5 LOW LATENCY FILTER SINC3 FILTER ENABLING 50Hz/60Hz REJECTION PRECHARGE BUFFERS MCLK/XTAL2 XTAL1 SYNC_OUT RESET CLKSEL ADC DATA SERIAL INTERFACE DRDY CS DOUT/RDY SDI SCLK CONTROL BLOCK MODE3 TO MODE0 (GPIO3 TO GPIO0) PIN/SPI 16481-001 ÷2 VCM Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2018–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7768-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Electromagnetic Compatibility (EMC) Testing ..................... 64 Applications ....................................................................................... 1 AD7768-1 Subsystem Layout ................................................... 65 Functional Block Diagram .............................................................. 1 Register Summary .......................................................................... 66 Revision History ............................................................................... 3 Register Details ............................................................................... 68 General Description ......................................................................... 4 Component Type Register......................................................... 68 Specifications..................................................................................... 5 Unique Product ID Registers .................................................... 68 3 V Operation.............................................................................. 10 Device Grade and Revision Register ....................................... 68 Timing Specifications ................................................................ 11 User Scratchpad Register........................................................... 68 1.8 V Timing Specifications ...................................................... 12 Device Vendor ID Registers ...................................................... 68 Absolute Maximum Ratings.......................................................... 17 Interface Format Control Register ........................................... 69 Thermal Resistance .................................................................... 17 Power and Clock Control Register........................................... 69 ESD Caution ................................................................................ 17 Analog Buffer Control Register ................................................ 70 Pin Configuration and Function Descriptions ........................... 18 VCM Control Register ............................................................... 71 Typical Performance Characteristics ........................................... 20 Conversion Source Select and Mode Control Register ......... 71 Terminology .................................................................................... 28 Digital Filter and Decimation Control Register ..................... 72 Theory of Operation ...................................................................... 29 Sinc3 Decimation Rate (MSB Register) .................................. 73 Clocking, Sampling Tree, and Power Scaling ......................... 29 Sinc3 Decimation Rate (LSB Register) .................................... 73 Noise Performance and Resolution.......................................... 30 Periodic Conversion Rate Control Register............................ 73 Core Converter ........................................................................... 32 Synchronization Modes and Reset Triggering Register ........ 74 Clocking and Clock Selection ................................................... 35 GPIO Port Control Register...................................................... 74 Digital Filtering ........................................................................... 35 GPIO Output Control Register ................................................ 75 Decimation Rate Control .......................................................... 40 GPIO Input Read Register ........................................................ 75 Antialiasing Filtering ................................................................. 40 Offset Calibration MSB Register .............................................. 75 Getting Started ............................................................................ 41 Offset Calibration MID Register .............................................. 75 Power Supplies ............................................................................ 43 Offset Calibration LSB Register ............................................... 76 Device Configuration Method ................................................. 43 Gain Calibration MSB Register ................................................ 76 Pin Control Mode Overview .................................................... 44 Gain Calibration MID Register ................................................ 76 SPI Control Overview ................................................................ 47 Gain Calibration LSB Register .................................................. 76 SPI Control Mode ....................................................................... 48 SPI Interface Diagnostic Control Register .............................. 77 Digital Interface .............................................................................. 51 ADC Diagnostic Feature Control Register ............................. 77 Data Conversion Modes ............................................................ 55 Digital Diagnostic Feature Control Register .......................... 77 Synchronization of Multiple AD7768-1 Devices.................... 56 Conversion Result Register ....................................................... 77 Additional Functionality of the AD7768-1 ............................. 58 Device Error Flags Master Register ......................................... 78 Applications Information .............................................................. 59 SPI Interface Error Register ...................................................... 78 Analog Input Recommendations ............................................. 59 ADC Diagnostics Output Register........................................... 78 Antialiasing Filter Design Considerations .............................. 60 Digital Diagnostics Output Register ........................................ 79 Recommended Interface ........................................................... 61 MCLK Diagnostic Output Register ......................................... 79 Programmable Digital Filter ..................................................... 62 Coefficient Control Register ..................................................... 79 Rev. A | Page 2 of 80 Data Sheet AD7768-1 Coefficient Data Register ...........................................................79  Ordering Guide ........................................................................... 80  Access Key Register.....................................................................79  Outline Dimensions ........................................................................80  REVISION HISTORY 5/2019—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Changes to General Description Section ....................................... 4 Change to Test Conditions/Comments for Spurious-Free Dynamic Range (SFDR) Parameters, Table 1................................. 5 Change to Test Conditions/Comments for SFDR Parameter, Table 2 ...............................................................................................10 Changes to Note 1, Figure 9 ...........................................................18 Changes to Table 7 ..........................................................................19 Changes to Figure 52 ......................................................................27 Added Figure 55 and Figure 56; Renumbered Sequentially ......27 Changes to Terminology Section ..................................................28 Changes to Noise Performance and Resolution Section ............30 Changes to Table 10 and Table 11 .................................................31 Changes to ADC Core and Signal Chain Section .......................32 Changes to Figure 67, Figure 68, and Clocking and Clock Selection Section .............................................................................35 Changes to Sinc3 Filter Section .....................................................37 Changes to Figure 77 ......................................................................41 Changes to Single-Supply Mode Section, Recommended Power Supply Configuration Section, and Figure 79 ............................. 43 Added Figure 80 .............................................................................. 43 Changes to Synchronization of Multiple AD7768-1 Devices section and Figure 95 ...................................................................... 57 Change to Recommended Driver Amplifiers Section and Table 25 ............................................................................................. 59 Change to Reg (Hex) 14, Bit 7, Table 31 and Reg (Hex) 29, Bit 3, Table 31 ................................................................................... 66 Change to Reg (Hex) 2F, Bit 3, Table 31 ....................................... 67 Changes to Bit 2 Description, Table 39 ........................................ 69 Changes to Bits[6:4] Description, Table 44 ................................. 72 Changes to Bit 7, Access, Table 48 and Bit 7, Description, Table 49 ............................................................................................. 74 Changes to Bit 3, Description, Table 58 and Bit 3, Bit Name and Description, Table 59 ...................................................................... 77 Changes to Bit 3, Bit Name and Description, Table 64 .............. 78 Update Outline Dimensions .......................................................... 80 5/2018—Revision 0: Initial Version Rev. A | Page 3 of 80 AD7768-1 Data Sheet GENERAL DESCRIPTION The AD7768-1 is a low power, high performance, Σ-Δ analogto-digital converter (ADC), with a Σ-Δ modulator and digital filter for precision conversion of both ac and dc signals. The AD7768-1 is a single-channel version of the AD7768, an 8-channel, simultaneously sampling, Σ-Δ ADC. The AD7768-1 provides a single configurable and reusable data acquisition (DAQ) footprint, which establishes a new industry standard in combined ac and dc performance and enables instrumentation and industrial system designers to design across multiple measurement variants for both isolated and nonisolated applications. The AD7768-1 achieves a 108.5 dB dynamic range when using the low ripple, finite impulse response (FIR) digital filter at 256 kSPS, giving 110.8 kHz input bandwidth, combined with ±1.1 ppm integral nonlinearity (INL), ±30 µV offset error, and ±30 ppm gain error. A wider bandwidth, up to 500 kHz Nyquist (filter −3 dB point of 204 kHz), is available using the sinc5 filter, enabling a view of signals over an extended range. The AD7768-1 offers the user the flexibility to configure and optimize for input bandwidth vs. output data rate (ODR) and vs. power dissipation. The flexibility of the AD7768-1 allows dynamic analysis of a changing input signal, making the device particularly useful in general-purpose DAQ systems. The selection of one of three available power modes allows the designer to achieve required noise targets while minimizing power consumption. The design of the AD7768-1 is unique in that it becomes a reusable and flexible platform for low power dc and high performance ac measurement modules. The AD7768-1 achieves the optimum balance of dc and ac performance with excellent power efficiency. The following three operating modes allow the user to trade off the input bandwidth vs. power budgets: • • • Fast mode offers both a sinc filter with up to 256 kSPS and 52.2 kHz of bandwidth, and 26.4 mW of power consumption, or a FIR filter with up to 256 kSPS, 110.8 kHz of bandwidth and 36.8 mW of power consumption. Median mode offers a FIR filter with up to 128 kSPS, 55.4 kHz of bandwidth and 19.7 mW of power consumption. Low power mode offers a FIR filter with up to 32 kSPS, 13.85 kHz of bandwidth and 6.75 mW of power consumption. The AD7768-1 offers extensive digital filtering capabilities that meet a wide range of system requirements. The filter options allow configuration for frequency domain measurements with tight gain error over frequency, linear phase response requirements (brick wall filter), a low latency path (sinc5 or sinc3) for use in control loop applications, and measuring dc inputs with the ability to configure the sinc3 filter to reject the line frequency of either 50 Hz or 60 Hz. All filters offer programmable decimation. A 1.024 MHz sinc5 filter path exists for users seeking an even higher ODR than is achievable using the low ripple FIR filter. This path is quantization noise limited. Therefore, it is best suited for customers requiring minimum latency for control loops or implementing custom digital filtering on an external field programmable gate array (FPGA) or digital signal processor (DSP). The filter options include the following: • • • A low ripple FIR filter with a ±0.005 dB pass-band ripple to 102.4 kHz. A low latency sinc5 filter with up to a 1.024 MHz data rate to maximize control loop responsiveness. A low latency sinc3 filter that is fully programmable, with 50 Hz/60 Hz rejection capabilities. When using the AD7768-1, embedded analog functionality within the AD7768-1 greatly reduces the design burden over the entire application range. The precharge buffer on each analog input decreases the analog input current compared to competing products, simplifying the task of an external amplifier to drive the analog input. A full buffer input on the reference reduces the input current, providing a high impedance input for the external reference device or in buffering any reference sense resistor scenarios used in ratiometric measurements. The device operates with a 5.0 V AVDD1 − AVSS supply, a 2.0 V to 5.0 V AVDD2 − AVSS supply, and a 1.8 V to 3.3 V IOVDD − DGND supply. In low power mode, the AVDD1, AVDD2, and IOVDD supplies can run from a single 3.0 V rail. The device requires an external reference. The absolute input reference (REFIN) voltage range is 1 V to AVDD1 − AVSS. The specified operating temperature range is −40°C to +125°C. The device is housed in a 4 mm × 5 mm, 28-lead LFCSP. Note that, throughout this data sheet, multifunction pins, such as XTAL2/MCLK, are referred to either by the entire pin name or by a single function of the pin, for example, MCLK, when only that function is relevant. Rev. A | Page 4 of 80 Data Sheet AD7768-1 SPECIFICATIONS AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2.0 V to 5.5 V, IOVDD = 1.7 V to 3.6 V, DGND = 0 V, AVSS = 0 V, REF+ = 4.096 V, REF− = 0 V, MCLK = 16.384 MHz, 50:50 duty cycle, analog input precharge buffers on, reference precharge on, the filter type is a low ripple FIR filter, and TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter ADC SPEED AND CODING ODR 1 Test Conditions/Comments Min Fast sinc5 Fast low ripple FIR Fast sinc3 Median sinc5 Median low ripple FIR Median sinc3 Low power sinc5 Low power low ripple FIR Low power sinc3 8 1024 8 256 0.05 256 4 512 4 128 0.025 128 1 128 1 32 0.0125 32 24-bit twos complement data, followed by eight status bits (if enabled), followed by eight cyclic redundancy check (CRC) bits (if enabled) kSPS kSPS kSPS kSPS kSPS kSPS kSPS kSPS kSPS 110 106.5 111.5 108.5 115 dB dB dB 110.5 107.5 107.3 dB dB dB Data Output Coding DYNAMIC PERFORMANCE Fast Mode Dynamic Range Signal to Noise Ratio (SNR) Signal-to-Noise-andDistortion (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Median Mode Dynamic Range SNR SINAD THD SFDR Low Power Mode Dynamic Range SNR Decimation by 32, 256 kHz ODR Shorted inputs, sinc5 filter Shorted inputs, low ripple FIR A-weighted, 1 kHz input, −60 dBFS, decimation by 128, low ripple FIR 1 kHz, −0.25 dBFS, sine input Sinc5 filter Low ripple FIR 1 kHz, −0.25 dBFS, sine input 106 105 Typ Max 1 kHz, −0.25 dBFS, sine input −120 1 kHz, −0.25 dBFS, sine input 125 dBc 111.5 108.5 dB dB 110.5 107.5 107.3 −120 125 dB dB dB dB dBc Decimation by 32, 128 kHz ODR Shorted inputs, sinc5 filter Shorted inputs, low ripple FIR 1 kHz, −0.25 dBFS, sine input Sinc5 filter Low ripple FIR 1 kHz, −0.25 dBFS, sine input 1 kHz, −0.25 dBFS, sine input 1 kHz, −0.25 dBFS, sine input Decimation by 32, 32 kHz ODR Shorted inputs, sinc5 filter Shorted inputs, low ripple FIR 1 kHz, −0.25 dBFS, sine input Sinc filter Low ripple FIR 110 106.5 106 105 −112 Unit −112 dB 110 106.5 111.5 108.5 dB dB 106 111 107.8 dB dB Rev. A | Page 5 of 80 AD7768-1 Parameter SINAD THD SFDR Intermodulation Distortion (IMD) ACCURACY No Missing Codes 2 INL Offset Error Offset Error Drift2 Gain Error Gain Drift vs. Temperature2 ANALOG INPUTS Differential Input Voltage Absolute AINx Voltage2 Analog Input Current Unbuffered Precharge Buffers On 3 Input Current Drift2 Unbuffered Precharge Buffer On EXTERNAL REFERENCE REFIN Voltage Absolute REFIN Voltage Limits Average REFIN Current Average REFIN Current Drift2 Common-Mode Rejection Data Sheet Test Conditions/Comments 1 kHz, −0.25 dBFS, sine input 1 kHz, −0.25 dBFS, sine input 1 kHz, −0.25 dBFS, sine input Frequency Input A (fa) = 9.7 kHz, Frequency Input B (fb) = 10.3 kHz Second order Third order Min 105 Low ripple FIR, sinc5 decimation > 32 Endpoint method 24 Typ 107.5 −120 125 Max −112 −125 −125 Unit dB dB dBc dB dB ±1.1 ±7 Fast mode Median mode Low power mode Fast mode Median mode Low power mode TA = 25°C, reference buffer on ±30 ±30 ±20 ±300 ±225 ±100 ±30 ±170 ±170 ±80 TA = 25°C, reference buffer off ±30 ±70 Reference buffer off ±0.25 ±0.6 Bits ppm of FSR µV µV µV nV/°C nV/°C nV/°C ppm of FSR ppm of FSR ppm/°C VREF+ AVDD1 + 0.05 V V Reference voltage (VREF) = REF+ − REF− Precharge buffers off, absolute voltage on AIN+ or AIN− Fast mode Differential component Common-mode component VREF− AVSS − 0.05 ±53 ±17 −20 µA/V µA/V µA ±12.5 ±3 nA/V/°C nA/°C Fast mode REFIN = (REF+) − (REF−) Reference unbuffered 1 AVSS − 0.05 AVDD1 − AVSS AVDD1 + 0.05 V V Reference precharge buffer on Reference buffer on Reference unbuffered Reference precharge buffer on Reference buffer on Reference unbuffered AVSS AVSS AVDD1 AVDD1 ±80 ±20 ±300 ±1.7 V V µA/V µA nA nA/V/°C 125 4 100 nA/°C nA/°C dB Reference precharge buffer on Reference buffer on Up to 10 MHz Rev. A | Page 6 of 80 Data Sheet Parameter DIGITAL FILTER RESPONSE Low Ripple FIR Filter Decimation Rate ODR Group Delay Settling Time Pass-Band Ripple 4 Pass Band Stop-Band Frequency Stop-Band Attenuation 5 Sinc5 Filter Decimation Rate ODR Group Delay Settling Time Pass Band Sinc3 Filter Decimation Rate4 ODR Group Delay Settling Time Pass Band REJECTION AC Power Supply Rejection Ratio (PSRR) AVDD1 AVDD2 IOVDD DC PSRR AVDD1 AVDD2 IOVDD Analog Input CommonMode Rejection Ratio (CMRR) DC AC Normal Mode Rejection AD7768-1 Test Conditions/Comments Min Six selectable decimation rates 32 Typ Max 1024 256 Latency Complete settling 34/ODR 68/ODR −0.005 dB −0.1 dB pass band −3 dB bandwidth Attenuation > 105 dB 0.4 × ODR 0.409 × ODR 0.433 × ODR 0.499 × ODR 105 ±0.005 Eight selectable decimation rates 8 Latency Complete settling −0.1 dB bandwidth −3 dB bandwidth 1024 1024